1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 /// NOTE: The constructor takes ownership of TLOF.
38 TargetLowering::TargetLowering(const TargetMachine &tm,
39 const TargetLoweringObjectFile *tlof)
40 : TargetLoweringBase(tm, tlof) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = isSigned;
100 Entry.isZExt = !isSigned;
101 Args.push_back(Entry);
103 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
105 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
106 TargetLowering::CallLoweringInfo CLI(DAG);
107 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
108 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
109 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
110 .setSExtResult(isSigned).setZExtResult(!isSigned);
111 return LowerCallTo(CLI);
115 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
116 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
117 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
118 SDValue &NewLHS, SDValue &NewRHS,
119 ISD::CondCode &CCCode,
121 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
122 && "Unsupported setcc type!");
124 // Expand into one or more soft-fp libcall(s).
125 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
129 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
130 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
134 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
135 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
139 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
140 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
144 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
145 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
149 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
150 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
154 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
155 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
158 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
159 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
162 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
163 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
166 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
167 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
170 // SETONE = SETOLT | SETOGT
171 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
172 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
175 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
176 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
179 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
180 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
183 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
184 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
187 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
188 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
191 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
192 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
194 default: llvm_unreachable("Do not know how to soften this setcc!");
198 // Use the target specific return value for comparions lib calls.
199 EVT RetVT = getCmpLibcallReturnType();
200 SDValue Ops[2] = { NewLHS, NewRHS };
201 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
203 NewRHS = DAG.getConstant(0, RetVT);
204 CCCode = getCmpLibcallCC(LC1);
205 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
206 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
207 getSetCCResultType(*DAG.getContext(), RetVT),
208 NewLHS, NewRHS, DAG.getCondCode(CCCode));
209 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
211 NewLHS = DAG.getNode(ISD::SETCC, dl,
212 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
213 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
214 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
219 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
220 /// current function. The returned value is a member of the
221 /// MachineJumpTableInfo::JTEntryKind enum.
222 unsigned TargetLowering::getJumpTableEncoding() const {
223 // In non-pic modes, just use the address of a block.
224 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
225 return MachineJumpTableInfo::EK_BlockAddress;
227 // In PIC mode, if the target supports a GPRel32 directive, use it.
228 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
229 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
231 // Otherwise, use a label difference.
232 return MachineJumpTableInfo::EK_LabelDifference32;
235 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
236 SelectionDAG &DAG) const {
237 // If our PIC model is GP relative, use the global offset table as the base.
238 unsigned JTEncoding = getJumpTableEncoding();
240 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
241 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
242 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
247 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
248 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
251 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
252 unsigned JTI,MCContext &Ctx) const{
253 // The normal PIC reloc base is the label at the start of the jump table.
254 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
258 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
259 // Assume that everything is safe in static mode.
260 if (getTargetMachine().getRelocationModel() == Reloc::Static)
263 // In dynamic-no-pic mode, assume that known defined values are safe.
264 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
266 !GA->getGlobal()->isDeclaration() &&
267 !GA->getGlobal()->isWeakForLinker())
270 // Otherwise assume nothing is safe.
274 //===----------------------------------------------------------------------===//
275 // Optimization Methods
276 //===----------------------------------------------------------------------===//
278 /// ShrinkDemandedConstant - Check to see if the specified operand of the
279 /// specified instruction is a constant integer. If so, check to see if there
280 /// are any bits set in the constant that are not demanded. If so, shrink the
281 /// constant and return true.
282 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
283 const APInt &Demanded) {
286 // FIXME: ISD::SELECT, ISD::SELECT_CC
287 switch (Op.getOpcode()) {
292 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
293 if (!C) return false;
295 if (Op.getOpcode() == ISD::XOR &&
296 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
299 // if we can expand it to have all bits set, do it
300 if (C->getAPIntValue().intersects(~Demanded)) {
301 EVT VT = Op.getValueType();
302 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
303 DAG.getConstant(Demanded &
306 return CombineTo(Op, New);
316 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
317 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
318 /// cast, but it could be generalized for targets with other types of
319 /// implicit widening casts.
321 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
323 const APInt &Demanded,
325 assert(Op.getNumOperands() == 2 &&
326 "ShrinkDemandedOp only supports binary operators!");
327 assert(Op.getNode()->getNumValues() == 1 &&
328 "ShrinkDemandedOp only supports nodes with one result!");
330 // Early return, as this function cannot handle vector types.
331 if (Op.getValueType().isVector())
334 // Don't do this if the node has another user, which may require the
336 if (!Op.getNode()->hasOneUse())
339 // Search for the smallest integer type with free casts to and from
340 // Op's type. For expedience, just check power-of-2 integer types.
341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
342 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
343 unsigned SmallVTBits = DemandedSize;
344 if (!isPowerOf2_32(SmallVTBits))
345 SmallVTBits = NextPowerOf2(SmallVTBits);
346 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
347 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
348 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
349 TLI.isZExtFree(SmallVT, Op.getValueType())) {
350 // We found a type with free casts.
351 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
352 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
353 Op.getNode()->getOperand(0)),
354 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
355 Op.getNode()->getOperand(1)));
356 bool NeedZext = DemandedSize > SmallVTBits;
357 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
358 dl, Op.getValueType(), X);
359 return CombineTo(Op, Z);
365 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
366 /// DemandedMask bits of the result of Op are ever used downstream. If we can
367 /// use this information to simplify Op, create a new simplified DAG node and
368 /// return true, returning the original and new nodes in Old and New. Otherwise,
369 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
370 /// the expression (used to simplify the caller). The KnownZero/One bits may
371 /// only be accurate for those bits in the DemandedMask.
372 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
373 const APInt &DemandedMask,
376 TargetLoweringOpt &TLO,
377 unsigned Depth) const {
378 unsigned BitWidth = DemandedMask.getBitWidth();
379 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
380 "Mask size mismatches value type size!");
381 APInt NewMask = DemandedMask;
384 // Don't know anything.
385 KnownZero = KnownOne = APInt(BitWidth, 0);
387 // Other users may use these bits.
388 if (!Op.getNode()->hasOneUse()) {
390 // If not at the root, Just compute the KnownZero/KnownOne bits to
391 // simplify things downstream.
392 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
395 // If this is the root being simplified, allow it to have multiple uses,
396 // just set the NewMask to all bits.
397 NewMask = APInt::getAllOnesValue(BitWidth);
398 } else if (DemandedMask == 0) {
399 // Not demanding any bits from Op.
400 if (Op.getOpcode() != ISD::UNDEF)
401 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
403 } else if (Depth == 6) { // Limit search depth.
407 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
408 switch (Op.getOpcode()) {
410 // We know all of the bits for a constant!
411 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
412 KnownZero = ~KnownOne;
413 return false; // Don't fall through, will infinitely loop.
415 // If the RHS is a constant, check to see if the LHS would be zero without
416 // using the bits from the RHS. Below, we use knowledge about the RHS to
417 // simplify the LHS, here we're using information from the LHS to simplify
419 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
420 APInt LHSZero, LHSOne;
421 // Do not increment Depth here; that can cause an infinite loop.
422 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
423 // If the LHS already has zeros where RHSC does, this and is dead.
424 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
425 return TLO.CombineTo(Op, Op.getOperand(0));
426 // If any of the set bits in the RHS are known zero on the LHS, shrink
428 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
432 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
433 KnownOne, TLO, Depth+1))
435 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
436 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
437 KnownZero2, KnownOne2, TLO, Depth+1))
439 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
441 // If all of the demanded bits are known one on one side, return the other.
442 // These bits cannot contribute to the result of the 'and'.
443 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
444 return TLO.CombineTo(Op, Op.getOperand(0));
445 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
446 return TLO.CombineTo(Op, Op.getOperand(1));
447 // If all of the demanded bits in the inputs are known zeros, return zero.
448 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
449 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
450 // If the RHS is a constant, see if we can simplify it.
451 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
453 // If the operation can be done in a smaller type, do so.
454 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
457 // Output known-1 bits are only known if set in both the LHS & RHS.
458 KnownOne &= KnownOne2;
459 // Output known-0 are known to be clear if zero in either the LHS | RHS.
460 KnownZero |= KnownZero2;
463 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
464 KnownOne, TLO, Depth+1))
466 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
467 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
468 KnownZero2, KnownOne2, TLO, Depth+1))
470 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
472 // If all of the demanded bits are known zero on one side, return the other.
473 // These bits cannot contribute to the result of the 'or'.
474 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
475 return TLO.CombineTo(Op, Op.getOperand(0));
476 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
477 return TLO.CombineTo(Op, Op.getOperand(1));
478 // If all of the potentially set bits on one side are known to be set on
479 // the other side, just use the 'other' side.
480 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
481 return TLO.CombineTo(Op, Op.getOperand(0));
482 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
483 return TLO.CombineTo(Op, Op.getOperand(1));
484 // If the RHS is a constant, see if we can simplify it.
485 if (TLO.ShrinkDemandedConstant(Op, NewMask))
487 // If the operation can be done in a smaller type, do so.
488 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
491 // Output known-0 bits are only known if clear in both the LHS & RHS.
492 KnownZero &= KnownZero2;
493 // Output known-1 are known to be set if set in either the LHS | RHS.
494 KnownOne |= KnownOne2;
497 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
498 KnownOne, TLO, Depth+1))
500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
501 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
502 KnownOne2, TLO, Depth+1))
504 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
506 // If all of the demanded bits are known zero on one side, return the other.
507 // These bits cannot contribute to the result of the 'xor'.
508 if ((KnownZero & NewMask) == NewMask)
509 return TLO.CombineTo(Op, Op.getOperand(0));
510 if ((KnownZero2 & NewMask) == NewMask)
511 return TLO.CombineTo(Op, Op.getOperand(1));
512 // If the operation can be done in a smaller type, do so.
513 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
516 // If all of the unknown bits are known to be zero on one side or the other
517 // (but not both) turn this into an *inclusive* or.
518 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
519 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
524 // Output known-0 bits are known if clear or set in both the LHS & RHS.
525 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
526 // Output known-1 are known to be set if set in only one of the LHS, RHS.
527 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
529 // If all of the demanded bits on one side are known, and all of the set
530 // bits on that side are also known to be set on the other side, turn this
531 // into an AND, as we know the bits will be cleared.
532 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
533 // NB: it is okay if more bits are known than are requested
534 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
535 if (KnownOne == KnownOne2) { // set bits are the same on both sides
536 EVT VT = Op.getValueType();
537 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
538 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
539 Op.getOperand(0), ANDC));
543 // If the RHS is a constant, see if we can simplify it.
544 // for XOR, we prefer to force bits to 1 if they will make a -1.
545 // if we can't force bits, try to shrink constant
546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
547 APInt Expanded = C->getAPIntValue() | (~NewMask);
548 // if we can expand it to have all bits set, do it
549 if (Expanded.isAllOnesValue()) {
550 if (Expanded != C->getAPIntValue()) {
551 EVT VT = Op.getValueType();
552 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
553 TLO.DAG.getConstant(Expanded, VT));
554 return TLO.CombineTo(Op, New);
556 // if it already has all the bits set, nothing to change
557 // but don't shrink either!
558 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
563 KnownZero = KnownZeroOut;
564 KnownOne = KnownOneOut;
567 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
568 KnownOne, TLO, Depth+1))
570 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
571 KnownOne2, TLO, Depth+1))
573 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
574 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
576 // If the operands are constants, see if we can simplify them.
577 if (TLO.ShrinkDemandedConstant(Op, NewMask))
580 // Only known if known in both the LHS and RHS.
581 KnownOne &= KnownOne2;
582 KnownZero &= KnownZero2;
585 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
586 KnownOne, TLO, Depth+1))
588 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
589 KnownOne2, TLO, Depth+1))
591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
592 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
594 // If the operands are constants, see if we can simplify them.
595 if (TLO.ShrinkDemandedConstant(Op, NewMask))
598 // Only known if known in both the LHS and RHS.
599 KnownOne &= KnownOne2;
600 KnownZero &= KnownZero2;
603 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
604 unsigned ShAmt = SA->getZExtValue();
605 SDValue InOp = Op.getOperand(0);
607 // If the shift count is an invalid immediate, don't do anything.
608 if (ShAmt >= BitWidth)
611 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
612 // single shift. We can do this if the bottom bits (which are shifted
613 // out) are never demanded.
614 if (InOp.getOpcode() == ISD::SRL &&
615 isa<ConstantSDNode>(InOp.getOperand(1))) {
616 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
617 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
618 unsigned Opc = ISD::SHL;
626 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
627 EVT VT = Op.getValueType();
628 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
629 InOp.getOperand(0), NewSA));
633 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
634 KnownZero, KnownOne, TLO, Depth+1))
637 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
638 // are not demanded. This will likely allow the anyext to be folded away.
639 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
640 SDValue InnerOp = InOp.getNode()->getOperand(0);
641 EVT InnerVT = InnerOp.getValueType();
642 unsigned InnerBits = InnerVT.getSizeInBits();
643 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
644 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
645 EVT ShTy = getShiftAmountTy(InnerVT);
646 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
649 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
650 TLO.DAG.getConstant(ShAmt, ShTy));
653 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
656 // Repeat the SHL optimization above in cases where an extension
657 // intervenes: (shl (anyext (shr x, c1)), c2) to
658 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
659 // aren't demanded (as above) and that the shifted upper c1 bits of
660 // x aren't demanded.
661 if (InOp.hasOneUse() &&
662 InnerOp.getOpcode() == ISD::SRL &&
663 InnerOp.hasOneUse() &&
664 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
665 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
667 if (InnerShAmt < ShAmt &&
668 InnerShAmt < InnerBits &&
669 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
670 NewMask.trunc(ShAmt) == 0) {
672 TLO.DAG.getConstant(ShAmt - InnerShAmt,
673 Op.getOperand(1).getValueType());
674 EVT VT = Op.getValueType();
675 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
676 InnerOp.getOperand(0));
677 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
683 KnownZero <<= SA->getZExtValue();
684 KnownOne <<= SA->getZExtValue();
685 // low bits known zero.
686 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
690 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691 EVT VT = Op.getValueType();
692 unsigned ShAmt = SA->getZExtValue();
693 unsigned VTSize = VT.getSizeInBits();
694 SDValue InOp = Op.getOperand(0);
696 // If the shift count is an invalid immediate, don't do anything.
697 if (ShAmt >= BitWidth)
700 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
701 // single shift. We can do this if the top bits (which are shifted out)
702 // are never demanded.
703 if (InOp.getOpcode() == ISD::SHL &&
704 isa<ConstantSDNode>(InOp.getOperand(1))) {
705 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
706 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
707 unsigned Opc = ISD::SRL;
715 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
716 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
717 InOp.getOperand(0), NewSA));
721 // Compute the new bits that are at the top now.
722 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
723 KnownZero, KnownOne, TLO, Depth+1))
725 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726 KnownZero = KnownZero.lshr(ShAmt);
727 KnownOne = KnownOne.lshr(ShAmt);
729 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
730 KnownZero |= HighBits; // High bits known zero.
734 // If this is an arithmetic shift right and only the low-bit is set, we can
735 // always convert this into a logical shr, even if the shift amount is
736 // variable. The low bit of the shift cannot be an input sign bit unless
737 // the shift amount is >= the size of the datatype, which is undefined.
739 return TLO.CombineTo(Op,
740 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
741 Op.getOperand(0), Op.getOperand(1)));
743 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
744 EVT VT = Op.getValueType();
745 unsigned ShAmt = SA->getZExtValue();
747 // If the shift count is an invalid immediate, don't do anything.
748 if (ShAmt >= BitWidth)
751 APInt InDemandedMask = (NewMask << ShAmt);
753 // If any of the demanded bits are produced by the sign extension, we also
754 // demand the input sign bit.
755 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
756 if (HighBits.intersects(NewMask))
757 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
759 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
760 KnownZero, KnownOne, TLO, Depth+1))
762 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763 KnownZero = KnownZero.lshr(ShAmt);
764 KnownOne = KnownOne.lshr(ShAmt);
766 // Handle the sign bit, adjusted to where it is now in the mask.
767 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
769 // If the input sign bit is known to be zero, or if none of the top bits
770 // are demanded, turn this into an unsigned shift right.
771 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
772 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
776 int Log2 = NewMask.exactLogBase2();
778 // The bit must come from the sign.
780 TLO.DAG.getConstant(BitWidth - 1 - Log2,
781 Op.getOperand(1).getValueType());
782 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
783 Op.getOperand(0), NewSA));
786 if (KnownOne.intersects(SignBit))
787 // New bits are known one.
788 KnownOne |= HighBits;
791 case ISD::SIGN_EXTEND_INREG: {
792 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
794 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
795 // If we only care about the highest bit, don't bother shifting right.
796 if (MsbMask == DemandedMask) {
797 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
798 SDValue InOp = Op.getOperand(0);
800 // Compute the correct shift amount type, which must be getShiftAmountTy
801 // for scalar types after legalization.
802 EVT ShiftAmtTy = Op.getValueType();
803 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
804 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
806 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
807 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
808 Op.getValueType(), InOp, ShiftAmt));
811 // Sign extension. Compute the demanded bits in the result that are not
812 // present in the input.
814 APInt::getHighBitsSet(BitWidth,
815 BitWidth - ExVT.getScalarType().getSizeInBits());
817 // If none of the extended bits are demanded, eliminate the sextinreg.
818 if ((NewBits & NewMask) == 0)
819 return TLO.CombineTo(Op, Op.getOperand(0));
822 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
823 APInt InputDemandedBits =
824 APInt::getLowBitsSet(BitWidth,
825 ExVT.getScalarType().getSizeInBits()) &
828 // Since the sign extended bits are demanded, we know that the sign
830 InputDemandedBits |= InSignBit;
832 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
833 KnownZero, KnownOne, TLO, Depth+1))
835 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
837 // If the sign bit of the input is known set or clear, then we know the
838 // top bits of the result.
840 // If the input sign bit is known zero, convert this into a zero extension.
841 if (KnownZero.intersects(InSignBit))
842 return TLO.CombineTo(Op,
843 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
845 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
847 KnownZero &= ~NewBits;
848 } else { // Input sign bit unknown
849 KnownZero &= ~NewBits;
850 KnownOne &= ~NewBits;
854 case ISD::BUILD_PAIR: {
855 EVT HalfVT = Op.getOperand(0).getValueType();
856 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
858 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
859 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
861 APInt KnownZeroLo, KnownOneLo;
862 APInt KnownZeroHi, KnownOneHi;
864 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
865 KnownOneLo, TLO, Depth + 1))
868 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
869 KnownOneHi, TLO, Depth + 1))
872 KnownZero = KnownZeroLo.zext(BitWidth) |
873 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
875 KnownOne = KnownOneLo.zext(BitWidth) |
876 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
879 case ISD::ZERO_EXTEND: {
880 unsigned OperandBitWidth =
881 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
882 APInt InMask = NewMask.trunc(OperandBitWidth);
884 // If none of the top bits are demanded, convert this into an any_extend.
886 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
887 if (!NewBits.intersects(NewMask))
888 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
892 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
893 KnownZero, KnownOne, TLO, Depth+1))
895 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
896 KnownZero = KnownZero.zext(BitWidth);
897 KnownOne = KnownOne.zext(BitWidth);
898 KnownZero |= NewBits;
901 case ISD::SIGN_EXTEND: {
902 EVT InVT = Op.getOperand(0).getValueType();
903 unsigned InBits = InVT.getScalarType().getSizeInBits();
904 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
905 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
906 APInt NewBits = ~InMask & NewMask;
908 // If none of the top bits are demanded, convert this into an any_extend.
910 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
914 // Since some of the sign extended bits are demanded, we know that the sign
916 APInt InDemandedBits = InMask & NewMask;
917 InDemandedBits |= InSignBit;
918 InDemandedBits = InDemandedBits.trunc(InBits);
920 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
921 KnownOne, TLO, Depth+1))
923 KnownZero = KnownZero.zext(BitWidth);
924 KnownOne = KnownOne.zext(BitWidth);
926 // If the sign bit is known zero, convert this to a zero extend.
927 if (KnownZero.intersects(InSignBit))
928 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
932 // If the sign bit is known one, the top bits match.
933 if (KnownOne.intersects(InSignBit)) {
935 assert((KnownZero & NewBits) == 0);
936 } else { // Otherwise, top bits aren't known.
937 assert((KnownOne & NewBits) == 0);
938 assert((KnownZero & NewBits) == 0);
942 case ISD::ANY_EXTEND: {
943 unsigned OperandBitWidth =
944 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
945 APInt InMask = NewMask.trunc(OperandBitWidth);
946 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
947 KnownZero, KnownOne, TLO, Depth+1))
949 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
950 KnownZero = KnownZero.zext(BitWidth);
951 KnownOne = KnownOne.zext(BitWidth);
954 case ISD::TRUNCATE: {
955 // Simplify the input, using demanded bit information, and compute the known
956 // zero/one bits live out.
957 unsigned OperandBitWidth =
958 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
959 APInt TruncMask = NewMask.zext(OperandBitWidth);
960 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
961 KnownZero, KnownOne, TLO, Depth+1))
963 KnownZero = KnownZero.trunc(BitWidth);
964 KnownOne = KnownOne.trunc(BitWidth);
966 // If the input is only used by this truncate, see if we can shrink it based
967 // on the known demanded bits.
968 if (Op.getOperand(0).getNode()->hasOneUse()) {
969 SDValue In = Op.getOperand(0);
970 switch (In.getOpcode()) {
973 // Shrink SRL by a constant if none of the high bits shifted in are
975 if (TLO.LegalTypes() &&
976 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
977 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
980 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
983 SDValue Shift = In.getOperand(1);
984 if (TLO.LegalTypes()) {
985 uint64_t ShVal = ShAmt->getZExtValue();
987 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
990 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
991 OperandBitWidth - BitWidth);
992 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
994 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
995 // None of the shifted in bits are needed. Add a truncate of the
996 // shift input, then shift it.
997 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1000 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1009 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1012 case ISD::AssertZext: {
1013 // AssertZext demands all of the high bits, plus any of the low bits
1014 // demanded by its users.
1015 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1016 APInt InMask = APInt::getLowBitsSet(BitWidth,
1017 VT.getSizeInBits());
1018 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1019 KnownZero, KnownOne, TLO, Depth+1))
1021 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1023 KnownZero |= ~InMask & NewMask;
1027 // If this is an FP->Int bitcast and if the sign bit is the only
1028 // thing demanded, turn this into a FGETSIGN.
1029 if (!TLO.LegalOperations() &&
1030 !Op.getValueType().isVector() &&
1031 !Op.getOperand(0).getValueType().isVector() &&
1032 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1033 Op.getOperand(0).getValueType().isFloatingPoint()) {
1034 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1035 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1036 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1037 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1038 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1039 // place. We expect the SHL to be eliminated by other optimizations.
1040 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1041 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1042 if (!OpVTLegal && OpVTSizeInBits > 32)
1043 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1044 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1045 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1046 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1055 // Add, Sub, and Mul don't demand any bits in positions beyond that
1056 // of the highest bit demanded of them.
1057 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1058 BitWidth - NewMask.countLeadingZeros());
1059 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1060 KnownOne2, TLO, Depth+1))
1062 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1063 KnownOne2, TLO, Depth+1))
1065 // See if the operation should be performed at a smaller bit width.
1066 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1071 // Just use computeKnownBits to compute output bits.
1072 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1076 // If we know the value of all of the demanded bits, return this as a
1078 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1079 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1084 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1085 /// in Mask are known to be either zero or one and return them in the
1086 /// KnownZero/KnownOne bitsets.
1087 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1090 const SelectionDAG &DAG,
1091 unsigned Depth) const {
1092 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1093 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1094 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1095 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1096 "Should use MaskedValueIsZero if you don't know whether Op"
1097 " is a target node!");
1098 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1101 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1102 /// targets that want to expose additional information about sign bits to the
1104 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1105 const SelectionDAG &,
1106 unsigned Depth) const {
1107 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1108 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1109 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1110 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1111 "Should use ComputeNumSignBits if you don't know whether Op"
1112 " is a target node!");
1116 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1117 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1118 /// determine which bit is set.
1120 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1121 // A left-shift of a constant one will have exactly one bit set, because
1122 // shifting the bit off the end is undefined.
1123 if (Val.getOpcode() == ISD::SHL)
1124 if (ConstantSDNode *C =
1125 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1126 if (C->getAPIntValue() == 1)
1129 // Similarly, a right-shift of a constant sign-bit will have exactly
1131 if (Val.getOpcode() == ISD::SRL)
1132 if (ConstantSDNode *C =
1133 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1134 if (C->getAPIntValue().isSignBit())
1137 // More could be done here, though the above checks are enough
1138 // to handle some common cases.
1140 // Fall back to computeKnownBits to catch other known cases.
1141 EVT OpVT = Val.getValueType();
1142 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1143 APInt KnownZero, KnownOne;
1144 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1145 return (KnownZero.countPopulation() == BitWidth - 1) &&
1146 (KnownOne.countPopulation() == 1);
1149 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1154 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1156 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1161 CN = BV->getConstantSplatValue();
1164 switch (getBooleanContents(IsVec)) {
1165 case UndefinedBooleanContent:
1166 return CN->getAPIntValue()[0];
1167 case ZeroOrOneBooleanContent:
1169 case ZeroOrNegativeOneBooleanContent:
1170 return CN->isAllOnesValue();
1173 llvm_unreachable("Invalid boolean contents");
1176 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1181 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1183 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1188 CN = BV->getConstantSplatValue();
1191 if (getBooleanContents(IsVec) == UndefinedBooleanContent)
1192 return !CN->getAPIntValue()[0];
1194 return CN->isNullValue();
1197 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1198 /// and cc. If it is unable to simplify it, return a null SDValue.
1200 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1201 ISD::CondCode Cond, bool foldBooleans,
1202 DAGCombinerInfo &DCI, SDLoc dl) const {
1203 SelectionDAG &DAG = DCI.DAG;
1205 // These setcc operations always fold.
1209 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1211 case ISD::SETTRUE2: {
1212 TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector());
1213 return DAG.getConstant(
1214 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1218 // Ensure that the constant occurs on the RHS, and fold constant
1220 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1221 if (isa<ConstantSDNode>(N0.getNode()) &&
1222 (DCI.isBeforeLegalizeOps() ||
1223 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1224 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1226 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1227 const APInt &C1 = N1C->getAPIntValue();
1229 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1230 // equality comparison, then we're just comparing whether X itself is
1232 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1233 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1234 N0.getOperand(1).getOpcode() == ISD::Constant) {
1236 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1237 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1238 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1239 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1240 // (srl (ctlz x), 5) == 0 -> X != 0
1241 // (srl (ctlz x), 5) != 1 -> X != 0
1244 // (srl (ctlz x), 5) != 0 -> X == 0
1245 // (srl (ctlz x), 5) == 1 -> X == 0
1248 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1249 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1255 // Look through truncs that don't change the value of a ctpop.
1256 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1257 CTPOP = N0.getOperand(0);
1259 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1260 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1261 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1262 EVT CTVT = CTPOP.getValueType();
1263 SDValue CTOp = CTPOP.getOperand(0);
1265 // (ctpop x) u< 2 -> (x & x-1) == 0
1266 // (ctpop x) u> 1 -> (x & x-1) != 0
1267 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1268 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1269 DAG.getConstant(1, CTVT));
1270 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1271 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1272 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1275 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1278 // (zext x) == C --> x == (trunc C)
1279 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1280 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1281 unsigned MinBits = N0.getValueSizeInBits();
1283 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1285 MinBits = N0->getOperand(0).getValueSizeInBits();
1286 PreZExt = N0->getOperand(0);
1287 } else if (N0->getOpcode() == ISD::AND) {
1288 // DAGCombine turns costly ZExts into ANDs
1289 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1290 if ((C->getAPIntValue()+1).isPowerOf2()) {
1291 MinBits = C->getAPIntValue().countTrailingOnes();
1292 PreZExt = N0->getOperand(0);
1294 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1296 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1297 MinBits = LN0->getMemoryVT().getSizeInBits();
1302 // Make sure we're not losing bits from the constant.
1304 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1305 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1306 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1307 // Will get folded away.
1308 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1309 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1310 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1315 // If the LHS is '(and load, const)', the RHS is 0,
1316 // the test is for equality or unsigned, and all 1 bits of the const are
1317 // in the same partial word, see if we can shorten the load.
1318 if (DCI.isBeforeLegalize() &&
1319 !ISD::isSignedIntSetCC(Cond) &&
1320 N0.getOpcode() == ISD::AND && C1 == 0 &&
1321 N0.getNode()->hasOneUse() &&
1322 isa<LoadSDNode>(N0.getOperand(0)) &&
1323 N0.getOperand(0).getNode()->hasOneUse() &&
1324 isa<ConstantSDNode>(N0.getOperand(1))) {
1325 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1327 unsigned bestWidth = 0, bestOffset = 0;
1328 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1329 unsigned origWidth = N0.getValueType().getSizeInBits();
1330 unsigned maskWidth = origWidth;
1331 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1332 // 8 bits, but have to be careful...
1333 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1334 origWidth = Lod->getMemoryVT().getSizeInBits();
1336 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1337 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1338 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1339 for (unsigned offset=0; offset<origWidth/width; offset++) {
1340 if ((newMask & Mask) == Mask) {
1341 if (!getDataLayout()->isLittleEndian())
1342 bestOffset = (origWidth/width - offset - 1) * (width/8);
1344 bestOffset = (uint64_t)offset * (width/8);
1345 bestMask = Mask.lshr(offset * (width/8) * 8);
1349 newMask = newMask << width;
1354 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1355 if (newVT.isRound()) {
1356 EVT PtrType = Lod->getOperand(1).getValueType();
1357 SDValue Ptr = Lod->getBasePtr();
1358 if (bestOffset != 0)
1359 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1360 DAG.getConstant(bestOffset, PtrType));
1361 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1362 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1363 Lod->getPointerInfo().getWithOffset(bestOffset),
1364 false, false, false, NewAlign);
1365 return DAG.getSetCC(dl, VT,
1366 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1367 DAG.getConstant(bestMask.trunc(bestWidth),
1369 DAG.getConstant(0LL, newVT), Cond);
1374 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1375 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1376 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1378 // If the comparison constant has bits in the upper part, the
1379 // zero-extended value could never match.
1380 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1381 C1.getBitWidth() - InSize))) {
1385 case ISD::SETEQ: return DAG.getConstant(0, VT);
1388 case ISD::SETNE: return DAG.getConstant(1, VT);
1391 // True if the sign bit of C1 is set.
1392 return DAG.getConstant(C1.isNegative(), VT);
1395 // True if the sign bit of C1 isn't set.
1396 return DAG.getConstant(C1.isNonNegative(), VT);
1402 // Otherwise, we can perform the comparison with the low bits.
1410 EVT newVT = N0.getOperand(0).getValueType();
1411 if (DCI.isBeforeLegalizeOps() ||
1412 (isOperationLegal(ISD::SETCC, newVT) &&
1413 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1414 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1415 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1417 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1419 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT);
1424 break; // todo, be more careful with signed comparisons
1426 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1427 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1428 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1429 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1430 EVT ExtDstTy = N0.getValueType();
1431 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1433 // If the constant doesn't fit into the number of bits for the source of
1434 // the sign extension, it is impossible for both sides to be equal.
1435 if (C1.getMinSignedBits() > ExtSrcTyBits)
1436 return DAG.getConstant(Cond == ISD::SETNE, VT);
1439 EVT Op0Ty = N0.getOperand(0).getValueType();
1440 if (Op0Ty == ExtSrcTy) {
1441 ZextOp = N0.getOperand(0);
1443 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1444 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1445 DAG.getConstant(Imm, Op0Ty));
1447 if (!DCI.isCalledByLegalizer())
1448 DCI.AddToWorklist(ZextOp.getNode());
1449 // Otherwise, make this a use of a zext.
1450 return DAG.getSetCC(dl, VT, ZextOp,
1451 DAG.getConstant(C1 & APInt::getLowBitsSet(
1456 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1457 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1458 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1459 if (N0.getOpcode() == ISD::SETCC &&
1460 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1461 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1463 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1464 // Invert the condition.
1465 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1466 CC = ISD::getSetCCInverse(CC,
1467 N0.getOperand(0).getValueType().isInteger());
1468 if (DCI.isBeforeLegalizeOps() ||
1469 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1470 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1473 if ((N0.getOpcode() == ISD::XOR ||
1474 (N0.getOpcode() == ISD::AND &&
1475 N0.getOperand(0).getOpcode() == ISD::XOR &&
1476 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1477 isa<ConstantSDNode>(N0.getOperand(1)) &&
1478 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1479 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1480 // can only do this if the top bits are known zero.
1481 unsigned BitWidth = N0.getValueSizeInBits();
1482 if (DAG.MaskedValueIsZero(N0,
1483 APInt::getHighBitsSet(BitWidth,
1485 // Okay, get the un-inverted input value.
1487 if (N0.getOpcode() == ISD::XOR)
1488 Val = N0.getOperand(0);
1490 assert(N0.getOpcode() == ISD::AND &&
1491 N0.getOperand(0).getOpcode() == ISD::XOR);
1492 // ((X^1)&1)^1 -> X & 1
1493 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1494 N0.getOperand(0).getOperand(0),
1498 return DAG.getSetCC(dl, VT, Val, N1,
1499 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1501 } else if (N1C->getAPIntValue() == 1 &&
1503 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
1505 if (Op0.getOpcode() == ISD::TRUNCATE)
1506 Op0 = Op0.getOperand(0);
1508 if ((Op0.getOpcode() == ISD::XOR) &&
1509 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1510 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1511 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1512 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1513 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1516 if (Op0.getOpcode() == ISD::AND &&
1517 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1518 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1519 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1520 if (Op0.getValueType().bitsGT(VT))
1521 Op0 = DAG.getNode(ISD::AND, dl, VT,
1522 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1523 DAG.getConstant(1, VT));
1524 else if (Op0.getValueType().bitsLT(VT))
1525 Op0 = DAG.getNode(ISD::AND, dl, VT,
1526 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1527 DAG.getConstant(1, VT));
1529 return DAG.getSetCC(dl, VT, Op0,
1530 DAG.getConstant(0, Op0.getValueType()),
1531 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1533 if (Op0.getOpcode() == ISD::AssertZext &&
1534 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1535 return DAG.getSetCC(dl, VT, Op0,
1536 DAG.getConstant(0, Op0.getValueType()),
1537 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1541 APInt MinVal, MaxVal;
1542 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1543 if (ISD::isSignedIntSetCC(Cond)) {
1544 MinVal = APInt::getSignedMinValue(OperandBitSize);
1545 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1547 MinVal = APInt::getMinValue(OperandBitSize);
1548 MaxVal = APInt::getMaxValue(OperandBitSize);
1551 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1552 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1553 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1554 // X >= C0 --> X > (C0 - 1)
1556 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1557 if ((DCI.isBeforeLegalizeOps() ||
1558 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1559 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1560 isLegalICmpImmediate(C.getSExtValue())))) {
1561 return DAG.getSetCC(dl, VT, N0,
1562 DAG.getConstant(C, N1.getValueType()),
1567 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1568 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1569 // X <= C0 --> X < (C0 + 1)
1571 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1572 if ((DCI.isBeforeLegalizeOps() ||
1573 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1574 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1575 isLegalICmpImmediate(C.getSExtValue())))) {
1576 return DAG.getSetCC(dl, VT, N0,
1577 DAG.getConstant(C, N1.getValueType()),
1582 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1583 return DAG.getConstant(0, VT); // X < MIN --> false
1584 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1585 return DAG.getConstant(1, VT); // X >= MIN --> true
1586 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1587 return DAG.getConstant(0, VT); // X > MAX --> false
1588 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1589 return DAG.getConstant(1, VT); // X <= MAX --> true
1591 // Canonicalize setgt X, Min --> setne X, Min
1592 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1593 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1594 // Canonicalize setlt X, Max --> setne X, Max
1595 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1596 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1598 // If we have setult X, 1, turn it into seteq X, 0
1599 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1600 return DAG.getSetCC(dl, VT, N0,
1601 DAG.getConstant(MinVal, N0.getValueType()),
1603 // If we have setugt X, Max-1, turn it into seteq X, Max
1604 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1605 return DAG.getSetCC(dl, VT, N0,
1606 DAG.getConstant(MaxVal, N0.getValueType()),
1609 // If we have "setcc X, C0", check to see if we can shrink the immediate
1612 // SETUGT X, SINTMAX -> SETLT X, 0
1613 if (Cond == ISD::SETUGT &&
1614 C1 == APInt::getSignedMaxValue(OperandBitSize))
1615 return DAG.getSetCC(dl, VT, N0,
1616 DAG.getConstant(0, N1.getValueType()),
1619 // SETULT X, SINTMIN -> SETGT X, -1
1620 if (Cond == ISD::SETULT &&
1621 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1622 SDValue ConstMinusOne =
1623 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1625 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1628 // Fold bit comparisons when we can.
1629 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1630 (VT == N0.getValueType() ||
1631 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1632 N0.getOpcode() == ISD::AND)
1633 if (ConstantSDNode *AndRHS =
1634 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1635 EVT ShiftTy = DCI.isBeforeLegalize() ?
1636 getPointerTy() : getShiftAmountTy(N0.getValueType());
1637 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1638 // Perform the xform if the AND RHS is a single bit.
1639 if (AndRHS->getAPIntValue().isPowerOf2()) {
1640 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1641 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1642 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1644 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1645 // (X & 8) == 8 --> (X & 8) >> 3
1646 // Perform the xform if C1 is a single bit.
1647 if (C1.isPowerOf2()) {
1648 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1649 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1650 DAG.getConstant(C1.logBase2(), ShiftTy)));
1655 if (C1.getMinSignedBits() <= 64 &&
1656 !isLegalICmpImmediate(C1.getSExtValue())) {
1657 // (X & -256) == 256 -> (X >> 8) == 1
1658 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1659 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1660 if (ConstantSDNode *AndRHS =
1661 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1662 const APInt &AndRHSC = AndRHS->getAPIntValue();
1663 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1664 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1665 EVT ShiftTy = DCI.isBeforeLegalize() ?
1666 getPointerTy() : getShiftAmountTy(N0.getValueType());
1667 EVT CmpTy = N0.getValueType();
1668 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1669 DAG.getConstant(ShiftBits, ShiftTy));
1670 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1671 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1674 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1675 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1676 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1677 // X < 0x100000000 -> (X >> 32) < 1
1678 // X >= 0x100000000 -> (X >> 32) >= 1
1679 // X <= 0x0ffffffff -> (X >> 32) < 1
1680 // X > 0x0ffffffff -> (X >> 32) >= 1
1683 ISD::CondCode NewCond = Cond;
1685 ShiftBits = C1.countTrailingOnes();
1687 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1689 ShiftBits = C1.countTrailingZeros();
1691 NewC = NewC.lshr(ShiftBits);
1692 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1693 EVT ShiftTy = DCI.isBeforeLegalize() ?
1694 getPointerTy() : getShiftAmountTy(N0.getValueType());
1695 EVT CmpTy = N0.getValueType();
1696 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1697 DAG.getConstant(ShiftBits, ShiftTy));
1698 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1699 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1705 if (isa<ConstantFPSDNode>(N0.getNode())) {
1706 // Constant fold or commute setcc.
1707 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1708 if (O.getNode()) return O;
1709 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1710 // If the RHS of an FP comparison is a constant, simplify it away in
1712 if (CFP->getValueAPF().isNaN()) {
1713 // If an operand is known to be a nan, we can fold it.
1714 switch (ISD::getUnorderedFlavor(Cond)) {
1715 default: llvm_unreachable("Unknown flavor!");
1716 case 0: // Known false.
1717 return DAG.getConstant(0, VT);
1718 case 1: // Known true.
1719 return DAG.getConstant(1, VT);
1720 case 2: // Undefined.
1721 return DAG.getUNDEF(VT);
1725 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1726 // constant if knowing that the operand is non-nan is enough. We prefer to
1727 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1729 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1730 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1732 // If the condition is not legal, see if we can find an equivalent one
1734 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1735 // If the comparison was an awkward floating-point == or != and one of
1736 // the comparison operands is infinity or negative infinity, convert the
1737 // condition to a less-awkward <= or >=.
1738 if (CFP->getValueAPF().isInfinity()) {
1739 if (CFP->getValueAPF().isNegative()) {
1740 if (Cond == ISD::SETOEQ &&
1741 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1742 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1743 if (Cond == ISD::SETUEQ &&
1744 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1745 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1746 if (Cond == ISD::SETUNE &&
1747 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1748 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1749 if (Cond == ISD::SETONE &&
1750 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1751 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1753 if (Cond == ISD::SETOEQ &&
1754 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1755 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1756 if (Cond == ISD::SETUEQ &&
1757 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1758 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1759 if (Cond == ISD::SETUNE &&
1760 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1761 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1762 if (Cond == ISD::SETONE &&
1763 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1764 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1771 // The sext(setcc()) => setcc() optimization relies on the appropriate
1772 // constant being emitted.
1774 switch (getBooleanContents(N0.getValueType().isVector())) {
1775 case UndefinedBooleanContent:
1776 case ZeroOrOneBooleanContent:
1777 EqVal = ISD::isTrueWhenEqual(Cond);
1779 case ZeroOrNegativeOneBooleanContent:
1780 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1784 // We can always fold X == X for integer setcc's.
1785 if (N0.getValueType().isInteger()) {
1786 return DAG.getConstant(EqVal, VT);
1788 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1789 if (UOF == 2) // FP operators that are undefined on NaNs.
1790 return DAG.getConstant(EqVal, VT);
1791 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1792 return DAG.getConstant(EqVal, VT);
1793 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1794 // if it is not already.
1795 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1796 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1797 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1798 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1801 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1802 N0.getValueType().isInteger()) {
1803 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1804 N0.getOpcode() == ISD::XOR) {
1805 // Simplify (X+Y) == (X+Z) --> Y == Z
1806 if (N0.getOpcode() == N1.getOpcode()) {
1807 if (N0.getOperand(0) == N1.getOperand(0))
1808 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1809 if (N0.getOperand(1) == N1.getOperand(1))
1810 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1811 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1812 // If X op Y == Y op X, try other combinations.
1813 if (N0.getOperand(0) == N1.getOperand(1))
1814 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1816 if (N0.getOperand(1) == N1.getOperand(0))
1817 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1822 // If RHS is a legal immediate value for a compare instruction, we need
1823 // to be careful about increasing register pressure needlessly.
1824 bool LegalRHSImm = false;
1826 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1827 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1828 // Turn (X+C1) == C2 --> X == C2-C1
1829 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1830 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1831 DAG.getConstant(RHSC->getAPIntValue()-
1832 LHSR->getAPIntValue(),
1833 N0.getValueType()), Cond);
1836 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1837 if (N0.getOpcode() == ISD::XOR)
1838 // If we know that all of the inverted bits are zero, don't bother
1839 // performing the inversion.
1840 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1842 DAG.getSetCC(dl, VT, N0.getOperand(0),
1843 DAG.getConstant(LHSR->getAPIntValue() ^
1844 RHSC->getAPIntValue(),
1849 // Turn (C1-X) == C2 --> X == C1-C2
1850 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1851 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1853 DAG.getSetCC(dl, VT, N0.getOperand(1),
1854 DAG.getConstant(SUBC->getAPIntValue() -
1855 RHSC->getAPIntValue(),
1861 // Could RHSC fold directly into a compare?
1862 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1863 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1866 // Simplify (X+Z) == X --> Z == 0
1867 // Don't do this if X is an immediate that can fold into a cmp
1868 // instruction and X+Z has other uses. It could be an induction variable
1869 // chain, and the transform would increase register pressure.
1870 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1871 if (N0.getOperand(0) == N1)
1872 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1873 DAG.getConstant(0, N0.getValueType()), Cond);
1874 if (N0.getOperand(1) == N1) {
1875 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1876 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1877 DAG.getConstant(0, N0.getValueType()), Cond);
1878 if (N0.getNode()->hasOneUse()) {
1879 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1880 // (Z-X) == X --> Z == X<<1
1881 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1882 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1883 if (!DCI.isCalledByLegalizer())
1884 DCI.AddToWorklist(SH.getNode());
1885 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1891 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1892 N1.getOpcode() == ISD::XOR) {
1893 // Simplify X == (X+Z) --> Z == 0
1894 if (N1.getOperand(0) == N0)
1895 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1896 DAG.getConstant(0, N1.getValueType()), Cond);
1897 if (N1.getOperand(1) == N0) {
1898 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1899 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1900 DAG.getConstant(0, N1.getValueType()), Cond);
1901 if (N1.getNode()->hasOneUse()) {
1902 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1903 // X == (Z-X) --> X<<1 == Z
1904 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1905 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1906 if (!DCI.isCalledByLegalizer())
1907 DCI.AddToWorklist(SH.getNode());
1908 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1913 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1914 // Note that where y is variable and is known to have at most
1915 // one bit set (for example, if it is z&1) we cannot do this;
1916 // the expressions are not equivalent when y==0.
1917 if (N0.getOpcode() == ISD::AND)
1918 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1919 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1920 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1921 if (DCI.isBeforeLegalizeOps() ||
1922 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1923 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1924 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1928 if (N1.getOpcode() == ISD::AND)
1929 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1930 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1931 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1932 if (DCI.isBeforeLegalizeOps() ||
1933 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1934 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1935 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1941 // Fold away ALL boolean setcc's.
1943 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1945 default: llvm_unreachable("Unknown integer setcc!");
1946 case ISD::SETEQ: // X == Y -> ~(X^Y)
1947 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1948 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1949 if (!DCI.isCalledByLegalizer())
1950 DCI.AddToWorklist(Temp.getNode());
1952 case ISD::SETNE: // X != Y --> (X^Y)
1953 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1955 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1956 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1957 Temp = DAG.getNOT(dl, N0, MVT::i1);
1958 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1959 if (!DCI.isCalledByLegalizer())
1960 DCI.AddToWorklist(Temp.getNode());
1962 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1963 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1964 Temp = DAG.getNOT(dl, N1, MVT::i1);
1965 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1966 if (!DCI.isCalledByLegalizer())
1967 DCI.AddToWorklist(Temp.getNode());
1969 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1970 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1971 Temp = DAG.getNOT(dl, N0, MVT::i1);
1972 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1973 if (!DCI.isCalledByLegalizer())
1974 DCI.AddToWorklist(Temp.getNode());
1976 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1977 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1978 Temp = DAG.getNOT(dl, N1, MVT::i1);
1979 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1982 if (VT != MVT::i1) {
1983 if (!DCI.isCalledByLegalizer())
1984 DCI.AddToWorklist(N0.getNode());
1985 // FIXME: If running after legalize, we probably can't do this.
1986 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1991 // Could not fold it.
1995 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1996 /// node is a GlobalAddress + offset.
1997 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
1998 int64_t &Offset) const {
1999 if (isa<GlobalAddressSDNode>(N)) {
2000 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2001 GA = GASD->getGlobal();
2002 Offset += GASD->getOffset();
2006 if (N->getOpcode() == ISD::ADD) {
2007 SDValue N1 = N->getOperand(0);
2008 SDValue N2 = N->getOperand(1);
2009 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2010 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2012 Offset += V->getSExtValue();
2015 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2016 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2018 Offset += V->getSExtValue();
2028 SDValue TargetLowering::
2029 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2030 // Default implementation: no optimization.
2034 //===----------------------------------------------------------------------===//
2035 // Inline Assembler Implementation Methods
2036 //===----------------------------------------------------------------------===//
2039 TargetLowering::ConstraintType
2040 TargetLowering::getConstraintType(const std::string &Constraint) const {
2041 unsigned S = Constraint.size();
2044 switch (Constraint[0]) {
2046 case 'r': return C_RegisterClass;
2048 case 'o': // offsetable
2049 case 'V': // not offsetable
2051 case 'i': // Simple Integer or Relocatable Constant
2052 case 'n': // Simple Integer
2053 case 'E': // Floating Point Constant
2054 case 'F': // Floating Point Constant
2055 case 's': // Relocatable Constant
2056 case 'p': // Address.
2057 case 'X': // Allow ANY value.
2058 case 'I': // Target registers.
2072 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2073 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2080 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2081 /// with another that has more specific requirements based on the type of the
2082 /// corresponding operand.
2083 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2084 if (ConstraintVT.isInteger())
2086 if (ConstraintVT.isFloatingPoint())
2087 return "f"; // works for many targets
2091 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2092 /// vector. If it is invalid, don't add anything to Ops.
2093 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2094 std::string &Constraint,
2095 std::vector<SDValue> &Ops,
2096 SelectionDAG &DAG) const {
2098 if (Constraint.length() > 1) return;
2100 char ConstraintLetter = Constraint[0];
2101 switch (ConstraintLetter) {
2103 case 'X': // Allows any operand; labels (basic block) use this.
2104 if (Op.getOpcode() == ISD::BasicBlock) {
2109 case 'i': // Simple Integer or Relocatable Constant
2110 case 'n': // Simple Integer
2111 case 's': { // Relocatable Constant
2112 // These operands are interested in values of the form (GV+C), where C may
2113 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2114 // is possible and fine if either GV or C are missing.
2115 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2116 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2118 // If we have "(add GV, C)", pull out GV/C
2119 if (Op.getOpcode() == ISD::ADD) {
2120 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2121 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2123 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2124 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2127 C = nullptr, GA = nullptr;
2130 // If we find a valid operand, map to the TargetXXX version so that the
2131 // value itself doesn't get selected.
2132 if (GA) { // Either &GV or &GV+C
2133 if (ConstraintLetter != 'n') {
2134 int64_t Offs = GA->getOffset();
2135 if (C) Offs += C->getZExtValue();
2136 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2137 C ? SDLoc(C) : SDLoc(),
2138 Op.getValueType(), Offs));
2142 if (C) { // just C, no GV.
2143 // Simple constants are not allowed for 's'.
2144 if (ConstraintLetter != 's') {
2145 // gcc prints these as sign extended. Sign extend value to 64 bits
2146 // now; without this it would get ZExt'd later in
2147 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2148 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2158 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2159 getRegForInlineAsmConstraint(const std::string &Constraint,
2161 if (Constraint.empty() || Constraint[0] != '{')
2162 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2163 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2165 // Remove the braces from around the name.
2166 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2168 std::pair<unsigned, const TargetRegisterClass*> R =
2169 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2171 // Figure out which register class contains this reg.
2172 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo();
2173 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2174 E = RI->regclass_end(); RCI != E; ++RCI) {
2175 const TargetRegisterClass *RC = *RCI;
2177 // If none of the value types for this register class are valid, we
2178 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2182 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2184 if (RegName.equals_lower(RI->getName(*I))) {
2185 std::pair<unsigned, const TargetRegisterClass*> S =
2186 std::make_pair(*I, RC);
2188 // If this register class has the requested value type, return it,
2189 // otherwise keep searching and return the first class found
2190 // if no other is found which explicitly has the requested type.
2191 if (RC->hasType(VT))
2202 //===----------------------------------------------------------------------===//
2203 // Constraint Selection.
2205 /// isMatchingInputConstraint - Return true of this is an input operand that is
2206 /// a matching constraint like "4".
2207 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2208 assert(!ConstraintCode.empty() && "No known constraint!");
2209 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2212 /// getMatchedOperand - If this is an input matching constraint, this method
2213 /// returns the output operand it matches.
2214 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2215 assert(!ConstraintCode.empty() && "No known constraint!");
2216 return atoi(ConstraintCode.c_str());
2220 /// ParseConstraints - Split up the constraint string from the inline
2221 /// assembly value into the specific constraints and their prefixes,
2222 /// and also tie in the associated operand values.
2223 /// If this returns an empty vector, and if the constraint string itself
2224 /// isn't empty, there was an error parsing.
2225 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2226 ImmutableCallSite CS) const {
2227 /// ConstraintOperands - Information about all of the constraints.
2228 AsmOperandInfoVector ConstraintOperands;
2229 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2230 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2232 // Do a prepass over the constraints, canonicalizing them, and building up the
2233 // ConstraintOperands list.
2234 InlineAsm::ConstraintInfoVector
2235 ConstraintInfos = IA->ParseConstraints();
2237 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2238 unsigned ResNo = 0; // ResNo - The result number of the next output.
2240 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2241 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2242 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2244 // Update multiple alternative constraint count.
2245 if (OpInfo.multipleAlternatives.size() > maCount)
2246 maCount = OpInfo.multipleAlternatives.size();
2248 OpInfo.ConstraintVT = MVT::Other;
2250 // Compute the value type for each operand.
2251 switch (OpInfo.Type) {
2252 case InlineAsm::isOutput:
2253 // Indirect outputs just consume an argument.
2254 if (OpInfo.isIndirect) {
2255 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2259 // The return value of the call is this value. As such, there is no
2260 // corresponding argument.
2261 assert(!CS.getType()->isVoidTy() &&
2263 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2264 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2266 assert(ResNo == 0 && "Asm only has one result!");
2267 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2271 case InlineAsm::isInput:
2272 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2274 case InlineAsm::isClobber:
2279 if (OpInfo.CallOperandVal) {
2280 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2281 if (OpInfo.isIndirect) {
2282 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2284 report_fatal_error("Indirect operand for inline asm not a pointer!");
2285 OpTy = PtrTy->getElementType();
2288 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2289 if (StructType *STy = dyn_cast<StructType>(OpTy))
2290 if (STy->getNumElements() == 1)
2291 OpTy = STy->getElementType(0);
2293 // If OpTy is not a single value, it may be a struct/union that we
2294 // can tile with integers.
2295 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2296 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2305 OpInfo.ConstraintVT =
2306 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2309 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2311 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2312 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2314 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2319 // If we have multiple alternative constraints, select the best alternative.
2320 if (ConstraintInfos.size()) {
2322 unsigned bestMAIndex = 0;
2323 int bestWeight = -1;
2324 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2327 // Compute the sums of the weights for each alternative, keeping track
2328 // of the best (highest weight) one so far.
2329 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2331 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2332 cIndex != eIndex; ++cIndex) {
2333 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2334 if (OpInfo.Type == InlineAsm::isClobber)
2337 // If this is an output operand with a matching input operand,
2338 // look up the matching input. If their types mismatch, e.g. one
2339 // is an integer, the other is floating point, or their sizes are
2340 // different, flag it as an maCantMatch.
2341 if (OpInfo.hasMatchingInput()) {
2342 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2343 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2344 if ((OpInfo.ConstraintVT.isInteger() !=
2345 Input.ConstraintVT.isInteger()) ||
2346 (OpInfo.ConstraintVT.getSizeInBits() !=
2347 Input.ConstraintVT.getSizeInBits())) {
2348 weightSum = -1; // Can't match.
2353 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2358 weightSum += weight;
2361 if (weightSum > bestWeight) {
2362 bestWeight = weightSum;
2363 bestMAIndex = maIndex;
2367 // Now select chosen alternative in each constraint.
2368 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2369 cIndex != eIndex; ++cIndex) {
2370 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2371 if (cInfo.Type == InlineAsm::isClobber)
2373 cInfo.selectAlternative(bestMAIndex);
2378 // Check and hook up tied operands, choose constraint code to use.
2379 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2380 cIndex != eIndex; ++cIndex) {
2381 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2383 // If this is an output operand with a matching input operand, look up the
2384 // matching input. If their types mismatch, e.g. one is an integer, the
2385 // other is floating point, or their sizes are different, flag it as an
2387 if (OpInfo.hasMatchingInput()) {
2388 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2390 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2391 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2392 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2393 OpInfo.ConstraintVT);
2394 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2395 getRegForInlineAsmConstraint(Input.ConstraintCode,
2396 Input.ConstraintVT);
2397 if ((OpInfo.ConstraintVT.isInteger() !=
2398 Input.ConstraintVT.isInteger()) ||
2399 (MatchRC.second != InputRC.second)) {
2400 report_fatal_error("Unsupported asm: input constraint"
2401 " with a matching output constraint of"
2402 " incompatible type!");
2409 return ConstraintOperands;
2413 /// getConstraintGenerality - Return an integer indicating how general CT
2415 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2417 case TargetLowering::C_Other:
2418 case TargetLowering::C_Unknown:
2420 case TargetLowering::C_Register:
2422 case TargetLowering::C_RegisterClass:
2424 case TargetLowering::C_Memory:
2427 llvm_unreachable("Invalid constraint type");
2430 /// Examine constraint type and operand type and determine a weight value.
2431 /// This object must already have been set up with the operand type
2432 /// and the current alternative constraint selected.
2433 TargetLowering::ConstraintWeight
2434 TargetLowering::getMultipleConstraintMatchWeight(
2435 AsmOperandInfo &info, int maIndex) const {
2436 InlineAsm::ConstraintCodeVector *rCodes;
2437 if (maIndex >= (int)info.multipleAlternatives.size())
2438 rCodes = &info.Codes;
2440 rCodes = &info.multipleAlternatives[maIndex].Codes;
2441 ConstraintWeight BestWeight = CW_Invalid;
2443 // Loop over the options, keeping track of the most general one.
2444 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2445 ConstraintWeight weight =
2446 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2447 if (weight > BestWeight)
2448 BestWeight = weight;
2454 /// Examine constraint type and operand type and determine a weight value.
2455 /// This object must already have been set up with the operand type
2456 /// and the current alternative constraint selected.
2457 TargetLowering::ConstraintWeight
2458 TargetLowering::getSingleConstraintMatchWeight(
2459 AsmOperandInfo &info, const char *constraint) const {
2460 ConstraintWeight weight = CW_Invalid;
2461 Value *CallOperandVal = info.CallOperandVal;
2462 // If we don't have a value, we can't do a match,
2463 // but allow it at the lowest weight.
2464 if (!CallOperandVal)
2466 // Look at the constraint type.
2467 switch (*constraint) {
2468 case 'i': // immediate integer.
2469 case 'n': // immediate integer with a known value.
2470 if (isa<ConstantInt>(CallOperandVal))
2471 weight = CW_Constant;
2473 case 's': // non-explicit intregal immediate.
2474 if (isa<GlobalValue>(CallOperandVal))
2475 weight = CW_Constant;
2477 case 'E': // immediate float if host format.
2478 case 'F': // immediate float.
2479 if (isa<ConstantFP>(CallOperandVal))
2480 weight = CW_Constant;
2482 case '<': // memory operand with autodecrement.
2483 case '>': // memory operand with autoincrement.
2484 case 'm': // memory operand.
2485 case 'o': // offsettable memory operand
2486 case 'V': // non-offsettable memory operand
2489 case 'r': // general register.
2490 case 'g': // general register, memory operand or immediate integer.
2491 // note: Clang converts "g" to "imr".
2492 if (CallOperandVal->getType()->isIntegerTy())
2493 weight = CW_Register;
2495 case 'X': // any operand.
2497 weight = CW_Default;
2503 /// ChooseConstraint - If there are multiple different constraints that we
2504 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2505 /// This is somewhat tricky: constraints fall into four classes:
2506 /// Other -> immediates and magic values
2507 /// Register -> one specific register
2508 /// RegisterClass -> a group of regs
2509 /// Memory -> memory
2510 /// Ideally, we would pick the most specific constraint possible: if we have
2511 /// something that fits into a register, we would pick it. The problem here
2512 /// is that if we have something that could either be in a register or in
2513 /// memory that use of the register could cause selection of *other*
2514 /// operands to fail: they might only succeed if we pick memory. Because of
2515 /// this the heuristic we use is:
2517 /// 1) If there is an 'other' constraint, and if the operand is valid for
2518 /// that constraint, use it. This makes us take advantage of 'i'
2519 /// constraints when available.
2520 /// 2) Otherwise, pick the most general constraint present. This prefers
2521 /// 'm' over 'r', for example.
2523 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2524 const TargetLowering &TLI,
2525 SDValue Op, SelectionDAG *DAG) {
2526 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2527 unsigned BestIdx = 0;
2528 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2529 int BestGenerality = -1;
2531 // Loop over the options, keeping track of the most general one.
2532 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2533 TargetLowering::ConstraintType CType =
2534 TLI.getConstraintType(OpInfo.Codes[i]);
2536 // If this is an 'other' constraint, see if the operand is valid for it.
2537 // For example, on X86 we might have an 'rI' constraint. If the operand
2538 // is an integer in the range [0..31] we want to use I (saving a load
2539 // of a register), otherwise we must use 'r'.
2540 if (CType == TargetLowering::C_Other && Op.getNode()) {
2541 assert(OpInfo.Codes[i].size() == 1 &&
2542 "Unhandled multi-letter 'other' constraint");
2543 std::vector<SDValue> ResultOps;
2544 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2546 if (!ResultOps.empty()) {
2553 // Things with matching constraints can only be registers, per gcc
2554 // documentation. This mainly affects "g" constraints.
2555 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2558 // This constraint letter is more general than the previous one, use it.
2559 int Generality = getConstraintGenerality(CType);
2560 if (Generality > BestGenerality) {
2563 BestGenerality = Generality;
2567 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2568 OpInfo.ConstraintType = BestType;
2571 /// ComputeConstraintToUse - Determines the constraint code and constraint
2572 /// type to use for the specific AsmOperandInfo, setting
2573 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2574 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2576 SelectionDAG *DAG) const {
2577 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2579 // Single-letter constraints ('r') are very common.
2580 if (OpInfo.Codes.size() == 1) {
2581 OpInfo.ConstraintCode = OpInfo.Codes[0];
2582 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2584 ChooseConstraint(OpInfo, *this, Op, DAG);
2587 // 'X' matches anything.
2588 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2589 // Labels and constants are handled elsewhere ('X' is the only thing
2590 // that matches labels). For Functions, the type here is the type of
2591 // the result, which is not what we want to look at; leave them alone.
2592 Value *v = OpInfo.CallOperandVal;
2593 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2594 OpInfo.CallOperandVal = v;
2598 // Otherwise, try to resolve it to something we know about by looking at
2599 // the actual operand type.
2600 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2601 OpInfo.ConstraintCode = Repl;
2602 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2607 /// \brief Given an exact SDIV by a constant, create a multiplication
2608 /// with the multiplicative inverse of the constant.
2609 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2610 SelectionDAG &DAG) const {
2611 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2612 APInt d = C->getAPIntValue();
2613 assert(d != 0 && "Division by zero!");
2615 // Shift the value upfront if it is even, so the LSB is one.
2616 unsigned ShAmt = d.countTrailingZeros();
2618 // TODO: For UDIV use SRL instead of SRA.
2619 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2620 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2625 // Calculate the multiplicative inverse, using Newton's method.
2627 while ((t = d*xn) != 1)
2628 xn *= APInt(d.getBitWidth(), 2) - t;
2630 Op2 = DAG.getConstant(xn, Op1.getValueType());
2631 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2634 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2635 /// return a DAG expression to select that will generate the same value by
2636 /// multiplying by a magic number. See:
2637 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2638 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2639 SelectionDAG &DAG, bool IsAfterLegalization,
2640 std::vector<SDNode *> *Created) const {
2641 EVT VT = N->getValueType(0);
2644 // Check to see if we can do this.
2645 // FIXME: We should be more aggressive here.
2646 if (!isTypeLegal(VT))
2649 APInt::ms magics = Divisor.magic();
2651 // Multiply the numerator (operand 0) by the magic value
2652 // FIXME: We should support doing a MUL in a wider type
2654 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2655 isOperationLegalOrCustom(ISD::MULHS, VT))
2656 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2657 DAG.getConstant(magics.m, VT));
2658 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2659 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2660 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2662 DAG.getConstant(magics.m, VT)).getNode(), 1);
2664 return SDValue(); // No mulhs or equvialent
2665 // If d > 0 and m < 0, add the numerator
2666 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2667 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2669 Created->push_back(Q.getNode());
2671 // If d < 0 and m > 0, subtract the numerator.
2672 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2673 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2675 Created->push_back(Q.getNode());
2677 // Shift right algebraic if shift value is nonzero
2679 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2680 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2682 Created->push_back(Q.getNode());
2684 // Extract the sign bit and add it to the quotient
2685 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2686 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2687 getShiftAmountTy(Q.getValueType())));
2689 Created->push_back(T.getNode());
2690 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2693 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2694 /// return a DAG expression to select that will generate the same value by
2695 /// multiplying by a magic number. See:
2696 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2697 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2698 SelectionDAG &DAG, bool IsAfterLegalization,
2699 std::vector<SDNode *> *Created) const {
2700 EVT VT = N->getValueType(0);
2703 // Check to see if we can do this.
2704 // FIXME: We should be more aggressive here.
2705 if (!isTypeLegal(VT))
2708 // FIXME: We should use a narrower constant when the upper
2709 // bits are known to be zero.
2710 APInt::mu magics = Divisor.magicu();
2712 SDValue Q = N->getOperand(0);
2714 // If the divisor is even, we can avoid using the expensive fixup by shifting
2715 // the divided value upfront.
2716 if (magics.a != 0 && !Divisor[0]) {
2717 unsigned Shift = Divisor.countTrailingZeros();
2718 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2719 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2721 Created->push_back(Q.getNode());
2723 // Get magic number for the shifted divisor.
2724 magics = Divisor.lshr(Shift).magicu(Shift);
2725 assert(magics.a == 0 && "Should use cheap fixup now");
2728 // Multiply the numerator (operand 0) by the magic value
2729 // FIXME: We should support doing a MUL in a wider type
2730 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2731 isOperationLegalOrCustom(ISD::MULHU, VT))
2732 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2733 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2734 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2735 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2736 DAG.getConstant(magics.m, VT)).getNode(), 1);
2738 return SDValue(); // No mulhu or equvialent
2740 Created->push_back(Q.getNode());
2742 if (magics.a == 0) {
2743 assert(magics.s < Divisor.getBitWidth() &&
2744 "We shouldn't generate an undefined shift!");
2745 return DAG.getNode(ISD::SRL, dl, VT, Q,
2746 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2748 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2750 Created->push_back(NPQ.getNode());
2751 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2752 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2754 Created->push_back(NPQ.getNode());
2755 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2757 Created->push_back(NPQ.getNode());
2758 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2759 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2763 bool TargetLowering::
2764 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2765 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2766 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2767 "be a constant integer");
2774 //===----------------------------------------------------------------------===//
2775 // Legalization Utilities
2776 //===----------------------------------------------------------------------===//
2778 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2779 SelectionDAG &DAG, SDValue LL, SDValue LH,
2780 SDValue RL, SDValue RH) const {
2781 EVT VT = N->getValueType(0);
2784 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2785 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2786 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2787 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2788 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2789 unsigned OuterBitSize = VT.getSizeInBits();
2790 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2791 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2792 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2794 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2795 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2796 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2798 if (!LL.getNode() && !RL.getNode() &&
2799 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2800 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2801 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2807 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2808 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2809 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2810 // The inputs are both zero-extended.
2812 // We can emit a umul_lohi.
2813 Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2814 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2815 Hi = SDValue(Lo.getNode(), 1);
2819 // We can emit a mulhu+mul.
2820 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2821 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2825 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2826 // The input values are both sign-extended.
2828 // We can emit a smul_lohi.
2829 Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2830 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2831 Hi = SDValue(Lo.getNode(), 1);
2835 // We can emit a mulhs+mul.
2836 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2837 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2842 if (!LH.getNode() && !RH.getNode() &&
2843 isOperationLegalOrCustom(ISD::SRL, VT) &&
2844 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2845 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2846 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2847 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2848 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2849 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2850 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2857 // Lo,Hi = umul LHS, RHS.
2858 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2859 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2861 Hi = UMulLOHI.getValue(1);
2862 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2863 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2864 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2865 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2869 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2870 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2871 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2872 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2873 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2874 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);