1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/MathExtras.h"
23 TargetLowering::TargetLowering(TargetMachine &tm)
24 : TM(tm), TD(TM.getTargetData()) {
25 assert(ISD::BUILTIN_OP_END <= 156 &&
26 "Fixed size array in TargetLowering is not large enough!");
27 // All operations default to being supported.
28 memset(OpActions, 0, sizeof(OpActions));
30 IsLittleEndian = TD.isLittleEndian();
31 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
32 ShiftAmtHandling = Undefined;
33 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
34 memset(TargetDAGCombineArray, 0,
35 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
36 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
37 allowUnalignedMemoryAccesses = false;
38 UseUnderscoreSetJmpLongJmp = false;
39 IntDivIsCheap = false;
40 Pow2DivIsCheap = false;
41 StackPointerRegisterToSaveRestore = 0;
42 SchedPreferenceInfo = SchedulingForLatency;
45 TargetLowering::~TargetLowering() {}
47 /// setValueTypeAction - Set the action for a particular value type. This
48 /// assumes an action has not already been set for this value type.
49 static void SetValueTypeAction(MVT::ValueType VT,
50 TargetLowering::LegalizeAction Action,
52 MVT::ValueType *TransformToType,
53 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
54 ValueTypeActions.setTypeAction(VT, Action);
55 if (Action == TargetLowering::Promote) {
56 MVT::ValueType PromoteTo;
60 unsigned LargerReg = VT+1;
61 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
63 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
64 "Nothing to promote to??");
66 PromoteTo = (MVT::ValueType)LargerReg;
69 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
70 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
71 "Can only promote from int->int or fp->fp!");
72 assert(VT < PromoteTo && "Must promote to a larger type!");
73 TransformToType[VT] = PromoteTo;
74 } else if (Action == TargetLowering::Expand) {
75 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
76 "Cannot expand this type: target must support SOME integer reg!");
77 // Expand to the next smaller integer type!
78 TransformToType[VT] = (MVT::ValueType)(VT-1);
83 /// computeRegisterProperties - Once all of the register classes are added,
84 /// this allows us to compute derived properties we expose.
85 void TargetLowering::computeRegisterProperties() {
86 assert(MVT::LAST_VALUETYPE <= 32 &&
87 "Too many value types for ValueTypeActions to hold!");
89 // Everything defaults to one.
90 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
91 NumElementsForVT[i] = 1;
93 // Find the largest integer register class.
94 unsigned LargestIntReg = MVT::i128;
95 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
96 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
98 // Every integer value type larger than this largest register takes twice as
99 // many registers to represent as the previous ValueType.
100 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
101 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
102 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
104 // Inspect all of the ValueType's possible, deciding how to process them.
105 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
106 // If we are expanding this type, expand it!
107 if (getNumElements((MVT::ValueType)IntReg) != 1)
108 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
110 else if (!isTypeLegal((MVT::ValueType)IntReg))
111 // Otherwise, if we don't have native support, we must promote to a
113 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
114 TransformToType, ValueTypeActions);
116 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
118 // If the target does not have native support for F32, promote it to F64.
119 if (!isTypeLegal(MVT::f32))
120 SetValueTypeAction(MVT::f32, Promote, *this,
121 TransformToType, ValueTypeActions);
123 TransformToType[MVT::f32] = MVT::f32;
125 // Set MVT::Vector to always be Expanded
126 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
129 // Loop over all of the legal vector value types, specifying an identity type
131 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
132 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
133 if (isTypeLegal((MVT::ValueType)i))
134 TransformToType[i] = (MVT::ValueType)i;
137 assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
138 TransformToType[MVT::f64] = MVT::f64;
141 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
145 /// getPackedTypeBreakdown - Packed types are broken down into some number of
146 /// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values
147 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
149 /// This method returns the number and type of the resultant breakdown.
151 MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
152 unsigned &NumVals) const {
153 // Figure out the right, legal destination reg to copy into.
154 unsigned NumElts = PTy->getNumElements();
155 MVT::ValueType EltTy = getValueType(PTy->getElementType());
157 unsigned NumVectorRegs = 1;
159 // Divide the input until we get to a supported size. This will always
160 // end with a scalar if the target doesn't support vectors.
161 while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
170 VT = getVectorType(EltTy, NumElts);
172 MVT::ValueType DestVT = getTypeToTransformTo(VT);
174 // Value is expanded, e.g. i64 -> i16.
175 NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
177 // Otherwise, promotion or legal types use the same number of registers as
178 // the vector decimated to the appropriate level.
179 NumVals = NumVectorRegs;
185 //===----------------------------------------------------------------------===//
186 // Optimization Methods
187 //===----------------------------------------------------------------------===//
189 /// ShrinkDemandedConstant - Check to see if the specified operand of the
190 /// specified instruction is a constant integer. If so, check to see if there
191 /// are any bits set in the constant that are not demanded. If so, shrink the
192 /// constant and return true.
193 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
195 // FIXME: ISD::SELECT, ISD::SELECT_CC
196 switch(Op.getOpcode()) {
201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
202 if ((~Demanded & C->getValue()) != 0) {
203 MVT::ValueType VT = Op.getValueType();
204 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
205 DAG.getConstant(Demanded & C->getValue(),
207 return CombineTo(Op, New);
214 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
215 /// DemandedMask bits of the result of Op are ever used downstream. If we can
216 /// use this information to simplify Op, create a new simplified DAG node and
217 /// return true, returning the original and new nodes in Old and New. Otherwise,
218 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
219 /// the expression (used to simplify the caller). The KnownZero/One bits may
220 /// only be accurate for those bits in the DemandedMask.
221 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
224 TargetLoweringOpt &TLO,
225 unsigned Depth) const {
226 KnownZero = KnownOne = 0; // Don't know anything.
227 // Other users may use these bits.
228 if (!Op.Val->hasOneUse()) {
230 // If not at the root, Just compute the KnownZero/KnownOne bits to
231 // simplify things downstream.
232 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
235 // If this is the root being simplified, allow it to have multiple uses,
236 // just set the DemandedMask to all bits.
237 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
238 } else if (DemandedMask == 0) {
239 // Not demanding any bits from Op.
240 if (Op.getOpcode() != ISD::UNDEF)
241 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
243 } else if (Depth == 6) { // Limit search depth.
247 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
248 switch (Op.getOpcode()) {
250 // We know all of the bits for a constant!
251 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
252 KnownZero = ~KnownOne & DemandedMask;
253 return false; // Don't fall through, will infinitely loop.
255 // If the RHS is a constant, check to see if the LHS would be zero without
256 // using the bits from the RHS. Below, we use knowledge about the RHS to
257 // simplify the LHS, here we're using information from the LHS to simplify
259 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
260 uint64_t LHSZero, LHSOne;
261 ComputeMaskedBits(Op.getOperand(0), DemandedMask,
262 LHSZero, LHSOne, Depth+1);
263 // If the LHS already has zeros where RHSC does, this and is dead.
264 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
265 return TLO.CombineTo(Op, Op.getOperand(0));
266 // If any of the set bits in the RHS are known zero on the LHS, shrink
268 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
272 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
273 KnownOne, TLO, Depth+1))
275 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
276 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
277 KnownZero2, KnownOne2, TLO, Depth+1))
279 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
281 // If all of the demanded bits are known one on one side, return the other.
282 // These bits cannot contribute to the result of the 'and'.
283 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
284 return TLO.CombineTo(Op, Op.getOperand(0));
285 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
286 return TLO.CombineTo(Op, Op.getOperand(1));
287 // If all of the demanded bits in the inputs are known zeros, return zero.
288 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
289 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
290 // If the RHS is a constant, see if we can simplify it.
291 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
294 // Output known-1 bits are only known if set in both the LHS & RHS.
295 KnownOne &= KnownOne2;
296 // Output known-0 are known to be clear if zero in either the LHS | RHS.
297 KnownZero |= KnownZero2;
300 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
301 KnownOne, TLO, Depth+1))
303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
304 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
305 KnownZero2, KnownOne2, TLO, Depth+1))
307 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
309 // If all of the demanded bits are known zero on one side, return the other.
310 // These bits cannot contribute to the result of the 'or'.
311 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
312 return TLO.CombineTo(Op, Op.getOperand(0));
313 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
314 return TLO.CombineTo(Op, Op.getOperand(1));
315 // If all of the potentially set bits on one side are known to be set on
316 // the other side, just use the 'other' side.
317 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
318 (DemandedMask & (~KnownZero)))
319 return TLO.CombineTo(Op, Op.getOperand(0));
320 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
321 (DemandedMask & (~KnownZero2)))
322 return TLO.CombineTo(Op, Op.getOperand(1));
323 // If the RHS is a constant, see if we can simplify it.
324 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
327 // Output known-0 bits are only known if clear in both the LHS & RHS.
328 KnownZero &= KnownZero2;
329 // Output known-1 are known to be set if set in either the LHS | RHS.
330 KnownOne |= KnownOne2;
333 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
334 KnownOne, TLO, Depth+1))
336 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
337 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
338 KnownOne2, TLO, Depth+1))
340 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
342 // If all of the demanded bits are known zero on one side, return the other.
343 // These bits cannot contribute to the result of the 'xor'.
344 if ((DemandedMask & KnownZero) == DemandedMask)
345 return TLO.CombineTo(Op, Op.getOperand(0));
346 if ((DemandedMask & KnownZero2) == DemandedMask)
347 return TLO.CombineTo(Op, Op.getOperand(1));
349 // Output known-0 bits are known if clear or set in both the LHS & RHS.
350 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
351 // Output known-1 are known to be set if set in only one of the LHS, RHS.
352 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
354 // If all of the unknown bits are known to be zero on one side or the other
355 // (but not both) turn this into an *inclusive* or.
356 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
357 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut))
358 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits)
359 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
362 // If all of the demanded bits on one side are known, and all of the set
363 // bits on that side are also known to be set on the other side, turn this
364 // into an AND, as we know the bits will be cleared.
365 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
366 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
367 if ((KnownOne & KnownOne2) == KnownOne) {
368 MVT::ValueType VT = Op.getValueType();
369 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
370 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
375 // If the RHS is a constant, see if we can simplify it.
376 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
377 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
380 KnownZero = KnownZeroOut;
381 KnownOne = KnownOneOut;
384 // If we know the result of a setcc has the top bits zero, use this info.
385 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
386 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
389 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
390 KnownOne, TLO, Depth+1))
392 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
393 KnownOne2, TLO, Depth+1))
395 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
396 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
398 // If the operands are constants, see if we can simplify them.
399 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
402 // Only known if known in both the LHS and RHS.
403 KnownOne &= KnownOne2;
404 KnownZero &= KnownZero2;
407 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
408 KnownOne, TLO, Depth+1))
410 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
411 KnownOne2, TLO, Depth+1))
413 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
414 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
416 // If the operands are constants, see if we can simplify them.
417 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
420 // Only known if known in both the LHS and RHS.
421 KnownOne &= KnownOne2;
422 KnownZero &= KnownZero2;
425 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
426 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
427 KnownZero, KnownOne, TLO, Depth+1))
429 KnownZero <<= SA->getValue();
430 KnownOne <<= SA->getValue();
431 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
435 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
436 MVT::ValueType VT = Op.getValueType();
437 unsigned ShAmt = SA->getValue();
439 // Compute the new bits that are at the top now.
440 uint64_t HighBits = (1ULL << ShAmt)-1;
441 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
442 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
444 if (SimplifyDemandedBits(Op.getOperand(0),
445 (DemandedMask << ShAmt) & TypeMask,
446 KnownZero, KnownOne, TLO, Depth+1))
448 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
449 KnownZero &= TypeMask;
450 KnownOne &= TypeMask;
453 KnownZero |= HighBits; // high bits known zero.
457 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
458 MVT::ValueType VT = Op.getValueType();
459 unsigned ShAmt = SA->getValue();
461 // Compute the new bits that are at the top now.
462 uint64_t HighBits = (1ULL << ShAmt)-1;
463 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
464 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
466 if (SimplifyDemandedBits(Op.getOperand(0),
467 (DemandedMask << ShAmt) & TypeMask,
468 KnownZero, KnownOne, TLO, Depth+1))
470 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
471 KnownZero &= TypeMask;
472 KnownOne &= TypeMask;
473 KnownZero >>= SA->getValue();
474 KnownOne >>= SA->getValue();
476 // Handle the sign bits.
477 uint64_t SignBit = MVT::getIntVTSignBit(VT);
478 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
480 // If the input sign bit is known to be zero, or if none of the top bits
481 // are demanded, turn this into an unsigned shift right.
482 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
483 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
485 } else if (KnownOne & SignBit) { // New bits are known one.
486 KnownOne |= HighBits;
490 case ISD::SIGN_EXTEND_INREG: {
491 MVT::ValueType VT = Op.getValueType();
492 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
494 // Sign extension. Compute the demanded bits in the result that are not
495 // present in the input.
496 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
498 // If none of the extended bits are demanded, eliminate the sextinreg.
500 return TLO.CombineTo(Op, Op.getOperand(0));
502 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
503 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
505 // Since the sign extended bits are demanded, we know that the sign
507 InputDemandedBits |= InSignBit;
509 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
510 KnownZero, KnownOne, TLO, Depth+1))
512 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
514 // If the sign bit of the input is known set or clear, then we know the
515 // top bits of the result.
517 // If the input sign bit is known zero, convert this into a zero extension.
518 if (KnownZero & InSignBit)
519 return TLO.CombineTo(Op,
520 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
522 if (KnownOne & InSignBit) { // Input sign bit known set
524 KnownZero &= ~NewBits;
525 } else { // Input sign bit unknown
526 KnownZero &= ~NewBits;
527 KnownOne &= ~NewBits;
534 MVT::ValueType VT = Op.getValueType();
535 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
536 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
540 case ISD::ZEXTLOAD: {
541 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
542 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
545 case ISD::ZERO_EXTEND: {
546 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
548 // If none of the top bits are demanded, convert this into an any_extend.
549 uint64_t NewBits = (~InMask) & DemandedMask;
551 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
555 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
556 KnownZero, KnownOne, TLO, Depth+1))
558 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
559 KnownZero |= NewBits;
562 case ISD::SIGN_EXTEND: {
563 MVT::ValueType InVT = Op.getOperand(0).getValueType();
564 uint64_t InMask = MVT::getIntVTBitMask(InVT);
565 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
566 uint64_t NewBits = (~InMask) & DemandedMask;
568 // If none of the top bits are demanded, convert this into an any_extend.
570 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
573 // Since some of the sign extended bits are demanded, we know that the sign
575 uint64_t InDemandedBits = DemandedMask & InMask;
576 InDemandedBits |= InSignBit;
578 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
579 KnownOne, TLO, Depth+1))
582 // If the sign bit is known zero, convert this to a zero extend.
583 if (KnownZero & InSignBit)
584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
588 // If the sign bit is known one, the top bits match.
589 if (KnownOne & InSignBit) {
591 KnownZero &= ~NewBits;
592 } else { // Otherwise, top bits aren't known.
593 KnownOne &= ~NewBits;
594 KnownZero &= ~NewBits;
598 case ISD::ANY_EXTEND: {
599 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
600 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
601 KnownZero, KnownOne, TLO, Depth+1))
603 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
606 case ISD::AssertZext: {
607 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
608 uint64_t InMask = MVT::getIntVTBitMask(VT);
609 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
610 KnownZero, KnownOne, TLO, Depth+1))
612 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
613 KnownZero |= ~InMask & DemandedMask;
618 // Just use ComputeMaskedBits to compute output bits, there are no
619 // simplifications that can be done here, and sub always demands all input
621 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
625 // If we know the value of all of the demanded bits, return this as a
627 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
628 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
633 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
634 /// this predicate to simplify operations downstream. Mask is known to be zero
635 /// for bits that V cannot have.
636 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
637 unsigned Depth) const {
638 uint64_t KnownZero, KnownOne;
639 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
640 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
641 return (KnownZero & Mask) == Mask;
644 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
645 /// known to be either zero or one and return them in the KnownZero/KnownOne
646 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
648 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
649 uint64_t &KnownZero, uint64_t &KnownOne,
650 unsigned Depth) const {
651 KnownZero = KnownOne = 0; // Don't know anything.
652 if (Depth == 6 || Mask == 0)
653 return; // Limit search depth.
655 uint64_t KnownZero2, KnownOne2;
657 switch (Op.getOpcode()) {
659 // We know all of the bits for a constant!
660 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
661 KnownZero = ~KnownOne & Mask;
664 // If either the LHS or the RHS are Zero, the result is zero.
665 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
667 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
668 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
669 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
671 // Output known-1 bits are only known if set in both the LHS & RHS.
672 KnownOne &= KnownOne2;
673 // Output known-0 are known to be clear if zero in either the LHS | RHS.
674 KnownZero |= KnownZero2;
677 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
679 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
680 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
681 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
683 // Output known-0 bits are only known if clear in both the LHS & RHS.
684 KnownZero &= KnownZero2;
685 // Output known-1 are known to be set if set in either the LHS | RHS.
686 KnownOne |= KnownOne2;
689 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
690 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
691 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
692 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
694 // Output known-0 bits are known if clear or set in both the LHS & RHS.
695 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
696 // Output known-1 are known to be set if set in only one of the LHS, RHS.
697 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
698 KnownZero = KnownZeroOut;
702 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
703 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
704 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
705 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
707 // Only known if known in both the LHS and RHS.
708 KnownOne &= KnownOne2;
709 KnownZero &= KnownZero2;
712 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
713 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
714 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
715 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
717 // Only known if known in both the LHS and RHS.
718 KnownOne &= KnownOne2;
719 KnownZero &= KnownZero2;
722 // If we know the result of a setcc has the top bits zero, use this info.
723 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
724 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
727 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
728 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
729 Mask >>= SA->getValue();
730 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
731 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
732 KnownZero <<= SA->getValue();
733 KnownOne <<= SA->getValue();
734 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
738 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
739 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
740 uint64_t HighBits = (1ULL << SA->getValue())-1;
741 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
742 Mask <<= SA->getValue();
743 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
744 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
745 KnownZero >>= SA->getValue();
746 KnownOne >>= SA->getValue();
747 KnownZero |= HighBits; // high bits known zero.
751 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
752 uint64_t HighBits = (1ULL << SA->getValue())-1;
753 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
754 Mask <<= SA->getValue();
755 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
756 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
757 KnownZero >>= SA->getValue();
758 KnownOne >>= SA->getValue();
760 // Handle the sign bits.
761 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
762 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
764 if (KnownZero & SignBit) { // New bits are known zero.
765 KnownZero |= HighBits;
766 } else if (KnownOne & SignBit) { // New bits are known one.
767 KnownOne |= HighBits;
771 case ISD::SIGN_EXTEND_INREG: {
772 MVT::ValueType VT = Op.getValueType();
773 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
775 // Sign extension. Compute the demanded bits in the result that are not
776 // present in the input.
777 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask;
779 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
780 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT);
782 // If the sign extended bits are demanded, we know that the sign
785 InputDemandedBits |= InSignBit;
787 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
788 KnownZero, KnownOne, Depth+1);
789 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
791 // If the sign bit of the input is known set or clear, then we know the
792 // top bits of the result.
793 if (KnownZero & InSignBit) { // Input sign bit known clear
794 KnownZero |= NewBits;
795 KnownOne &= ~NewBits;
796 } else if (KnownOne & InSignBit) { // Input sign bit known set
798 KnownZero &= ~NewBits;
799 } else { // Input sign bit unknown
800 KnownZero &= ~NewBits;
801 KnownOne &= ~NewBits;
808 MVT::ValueType VT = Op.getValueType();
809 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
810 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
814 case ISD::ZEXTLOAD: {
815 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
816 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
819 case ISD::ZERO_EXTEND: {
820 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
821 uint64_t NewBits = (~InMask) & Mask;
822 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
824 KnownZero |= NewBits & Mask;
825 KnownOne &= ~NewBits;
828 case ISD::SIGN_EXTEND: {
829 MVT::ValueType InVT = Op.getOperand(0).getValueType();
830 unsigned InBits = MVT::getSizeInBits(InVT);
831 uint64_t InMask = MVT::getIntVTBitMask(InVT);
832 uint64_t InSignBit = 1ULL << (InBits-1);
833 uint64_t NewBits = (~InMask) & Mask;
834 uint64_t InDemandedBits = Mask & InMask;
836 // If any of the sign extended bits are demanded, we know that the sign
839 InDemandedBits |= InSignBit;
841 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero,
843 // If the sign bit is known zero or one, the top bits match.
844 if (KnownZero & InSignBit) {
845 KnownZero |= NewBits;
846 KnownOne &= ~NewBits;
847 } else if (KnownOne & InSignBit) {
849 KnownZero &= ~NewBits;
850 } else { // Otherwise, top bits aren't known.
851 KnownOne &= ~NewBits;
852 KnownZero &= ~NewBits;
856 case ISD::ANY_EXTEND: {
857 MVT::ValueType VT = Op.getOperand(0).getValueType();
858 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT),
859 KnownZero, KnownOne, Depth+1);
862 case ISD::AssertZext: {
863 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
864 uint64_t InMask = MVT::getIntVTBitMask(VT);
865 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
867 KnownZero |= (~InMask) & Mask;
871 // If either the LHS or the RHS are Zero, the result is zero.
872 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
873 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
874 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
875 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
877 // Output known-0 bits are known if clear or set in both the low clear bits
878 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
880 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
881 CountTrailingZeros_64(~KnownZero2));
883 KnownZero = (1ULL << KnownZeroOut) - 1;
888 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
891 // We know that the top bits of C-X are clear if X contains less bits
892 // than C (i.e. no wrap-around can happen). For example, 20-X is
893 // positive if we can prove that X is >= 0 and < 16.
894 MVT::ValueType VT = CLHS->getValueType(0);
895 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
896 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
897 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
898 MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
899 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
901 // If all of the MaskV bits are known to be zero, then we know the output
902 // top bits are zero, because we now know that the output is from [0-C].
903 if ((KnownZero & MaskV) == MaskV) {
904 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
905 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
906 KnownOne = 0; // No one bits known.
908 KnownOne = KnownOne = 0; // Otherwise, nothing known.
914 // Allow the target to implement this method for its nodes.
915 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
916 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
921 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
922 /// in Mask are known to be either zero or one and return them in the
923 /// KnownZero/KnownOne bitsets.
924 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
928 unsigned Depth) const {
929 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
930 "Should use MaskedValueIsZero if you don't know whether Op"
931 " is a target node!");
936 SDOperand TargetLowering::
937 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
938 // Default implementation: no optimization.
942 //===----------------------------------------------------------------------===//
943 // Inline Assembler Implementation Methods
944 //===----------------------------------------------------------------------===//
946 TargetLowering::ConstraintType
947 TargetLowering::getConstraintType(char ConstraintLetter) const {
948 // FIXME: lots more standard ones to handle.
949 switch (ConstraintLetter) {
950 default: return C_Unknown;
951 case 'r': return C_RegisterClass;
953 case 'o': // offsetable
954 case 'V': // not offsetable
956 case 'i': // Simple Integer or Relocatable Constant
957 case 'n': // Simple Integer
958 case 's': // Relocatable Constant
959 case 'I': // Target registers.
971 bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
972 char ConstraintLetter) {
973 switch (ConstraintLetter) {
974 default: return false;
975 case 'i': // Simple Integer or Relocatable Constant
976 case 'n': // Simple Integer
977 case 's': // Relocatable Constant
978 return true; // FIXME: not right.
983 std::vector<unsigned> TargetLowering::
984 getRegClassForInlineAsmConstraint(const std::string &Constraint,
985 MVT::ValueType VT) const {
986 return std::vector<unsigned>();
990 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
991 getRegForInlineAsmConstraint(const std::string &Constraint,
992 MVT::ValueType VT) const {
993 if (Constraint[0] != '{')
994 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
995 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
997 // Remove the braces from around the name.
998 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1000 // Figure out which register class contains this reg.
1001 const MRegisterInfo *RI = TM.getRegisterInfo();
1002 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1003 E = RI->regclass_end(); RCI != E; ++RCI) {
1004 const TargetRegisterClass *RC = *RCI;
1006 // If none of the the value types for this register class are valid, we
1007 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1008 bool isLegal = false;
1009 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1011 if (isTypeLegal(*I)) {
1017 if (!isLegal) continue;
1019 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1021 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1022 return std::make_pair(*I, RC);
1026 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1029 //===----------------------------------------------------------------------===//
1030 // Loop Strength Reduction hooks
1031 //===----------------------------------------------------------------------===//
1033 /// isLegalAddressImmediate - Return true if the integer value or
1034 /// GlobalValue can be used as the offset of the target addressing mode.
1035 bool TargetLowering::isLegalAddressImmediate(int64_t V) const {
1038 bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {