1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetData.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/Support/MathExtras.h"
24 /// InitLibcallNames - Set default libcall names.
26 static void InitLibcallNames(const char **Names) {
27 Names[RTLIB::SHL_I32] = "__ashlsi3";
28 Names[RTLIB::SHL_I64] = "__ashldi3";
29 Names[RTLIB::SRL_I32] = "__lshrsi3";
30 Names[RTLIB::SRL_I64] = "__lshrdi3";
31 Names[RTLIB::SRA_I32] = "__ashrsi3";
32 Names[RTLIB::SRA_I64] = "__ashrdi3";
33 Names[RTLIB::MUL_I32] = "__mulsi3";
34 Names[RTLIB::MUL_I64] = "__muldi3";
35 Names[RTLIB::SDIV_I32] = "__divsi3";
36 Names[RTLIB::SDIV_I64] = "__divdi3";
37 Names[RTLIB::UDIV_I32] = "__udivsi3";
38 Names[RTLIB::UDIV_I64] = "__udivdi3";
39 Names[RTLIB::SREM_I32] = "__modsi3";
40 Names[RTLIB::SREM_I64] = "__moddi3";
41 Names[RTLIB::UREM_I32] = "__umodsi3";
42 Names[RTLIB::UREM_I64] = "__umoddi3";
43 Names[RTLIB::NEG_I32] = "__negsi2";
44 Names[RTLIB::NEG_I64] = "__negdi2";
45 Names[RTLIB::ADD_F32] = "__addsf3";
46 Names[RTLIB::ADD_F64] = "__adddf3";
47 Names[RTLIB::SUB_F32] = "__subsf3";
48 Names[RTLIB::SUB_F64] = "__subdf3";
49 Names[RTLIB::MUL_F32] = "__mulsf3";
50 Names[RTLIB::MUL_F64] = "__muldf3";
51 Names[RTLIB::DIV_F32] = "__divsf3";
52 Names[RTLIB::DIV_F64] = "__divdf3";
53 Names[RTLIB::REM_F32] = "fmodf";
54 Names[RTLIB::REM_F64] = "fmod";
55 Names[RTLIB::NEG_F32] = "__negsf2";
56 Names[RTLIB::NEG_F64] = "__negdf2";
57 Names[RTLIB::POWI_F32] = "__powisf2";
58 Names[RTLIB::POWI_F64] = "__powidf2";
59 Names[RTLIB::SQRT_F32] = "sqrtf";
60 Names[RTLIB::SQRT_F64] = "sqrt";
61 Names[RTLIB::SIN_F32] = "sinf";
62 Names[RTLIB::SIN_F64] = "sin";
63 Names[RTLIB::COS_F32] = "cosf";
64 Names[RTLIB::COS_F64] = "cos";
65 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
66 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
67 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
68 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
69 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
70 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
71 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
72 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
73 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
74 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
75 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
76 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
77 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
78 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
79 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
80 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
81 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
82 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
83 Names[RTLIB::OEQ_F32] = "__eqsf2";
84 Names[RTLIB::OEQ_F64] = "__eqdf2";
85 Names[RTLIB::UNE_F32] = "__nesf2";
86 Names[RTLIB::UNE_F64] = "__nedf2";
87 Names[RTLIB::OGE_F32] = "__gesf2";
88 Names[RTLIB::OGE_F64] = "__gedf2";
89 Names[RTLIB::OLT_F32] = "__ltsf2";
90 Names[RTLIB::OLT_F64] = "__ltdf2";
91 Names[RTLIB::OLE_F32] = "__lesf2";
92 Names[RTLIB::OLE_F64] = "__ledf2";
93 Names[RTLIB::OGT_F32] = "__gtsf2";
94 Names[RTLIB::OGT_F64] = "__gtdf2";
95 Names[RTLIB::UO_F32] = "__unordsf2";
96 Names[RTLIB::UO_F64] = "__unorddf2";
97 Names[RTLIB::O_F32] = "__unordsf2";
98 Names[RTLIB::O_F64] = "__unorddf2";
101 /// InitCmpLibcallCCs - Set default comparison libcall CC.
103 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
104 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
105 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
106 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
107 CCs[RTLIB::UNE_F32] = ISD::SETNE;
108 CCs[RTLIB::UNE_F64] = ISD::SETNE;
109 CCs[RTLIB::OGE_F32] = ISD::SETGE;
110 CCs[RTLIB::OGE_F64] = ISD::SETGE;
111 CCs[RTLIB::OLT_F32] = ISD::SETLT;
112 CCs[RTLIB::OLT_F64] = ISD::SETLT;
113 CCs[RTLIB::OLE_F32] = ISD::SETLE;
114 CCs[RTLIB::OLE_F64] = ISD::SETLE;
115 CCs[RTLIB::OGT_F32] = ISD::SETGT;
116 CCs[RTLIB::OGT_F64] = ISD::SETGT;
117 CCs[RTLIB::UO_F32] = ISD::SETNE;
118 CCs[RTLIB::UO_F64] = ISD::SETNE;
119 CCs[RTLIB::O_F32] = ISD::SETEQ;
120 CCs[RTLIB::O_F64] = ISD::SETEQ;
123 TargetLowering::TargetLowering(TargetMachine &tm)
124 : TM(tm), TD(TM.getTargetData()) {
125 assert(ISD::BUILTIN_OP_END <= 156 &&
126 "Fixed size array in TargetLowering is not large enough!");
127 // All operations default to being supported.
128 memset(OpActions, 0, sizeof(OpActions));
129 memset(LoadXActions, 0, sizeof(LoadXActions));
130 memset(&StoreXActions, 0, sizeof(StoreXActions));
131 // Initialize all indexed load / store to expand.
132 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
133 for (unsigned IM = (unsigned)ISD::PRE_INC;
134 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
135 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
136 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
140 IsLittleEndian = TD->isLittleEndian();
141 UsesGlobalOffsetTable = false;
142 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
143 ShiftAmtHandling = Undefined;
144 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
145 memset(TargetDAGCombineArray, 0,
146 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
147 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
148 allowUnalignedMemoryAccesses = false;
149 UseUnderscoreSetJmp = false;
150 UseUnderscoreLongJmp = false;
151 SelectIsExpensive = false;
152 IntDivIsCheap = false;
153 Pow2DivIsCheap = false;
154 StackPointerRegisterToSaveRestore = 0;
155 ExceptionPointerRegister = 0;
156 ExceptionSelectorRegister = 0;
157 SchedPreferenceInfo = SchedulingForLatency;
159 JumpBufAlignment = 0;
160 IfCvtBlockSizeLimit = 2;
162 InitLibcallNames(LibcallRoutineNames);
163 InitCmpLibcallCCs(CmpLibcallCCs);
166 TargetLowering::~TargetLowering() {}
168 /// setValueTypeAction - Set the action for a particular value type. This
169 /// assumes an action has not already been set for this value type.
170 static void SetValueTypeAction(MVT::ValueType VT,
171 TargetLowering::LegalizeAction Action,
173 MVT::ValueType *TransformToType,
174 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
175 ValueTypeActions.setTypeAction(VT, Action);
176 if (Action == TargetLowering::Promote) {
177 MVT::ValueType PromoteTo;
179 PromoteTo = MVT::f64;
181 unsigned LargerReg = VT+1;
182 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
184 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
185 "Nothing to promote to??");
187 PromoteTo = (MVT::ValueType)LargerReg;
190 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
191 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
192 "Can only promote from int->int or fp->fp!");
193 assert(VT < PromoteTo && "Must promote to a larger type!");
194 TransformToType[VT] = PromoteTo;
195 } else if (Action == TargetLowering::Expand) {
196 // f32 and f64 is each expanded to corresponding integer type of same size.
198 TransformToType[VT] = MVT::i32;
199 else if (VT == MVT::f64)
200 TransformToType[VT] = MVT::i64;
202 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
203 "Cannot expand this type: target must support SOME integer reg!");
204 // Expand to the next smaller integer type!
205 TransformToType[VT] = (MVT::ValueType)(VT-1);
211 /// computeRegisterProperties - Once all of the register classes are added,
212 /// this allows us to compute derived properties we expose.
213 void TargetLowering::computeRegisterProperties() {
214 assert(MVT::LAST_VALUETYPE <= 32 &&
215 "Too many value types for ValueTypeActions to hold!");
217 // Everything defaults to one.
218 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
219 NumRegistersForVT[i] = 1;
221 // Find the largest integer register class.
222 unsigned LargestIntReg = MVT::i128;
223 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
224 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
226 // Every integer value type larger than this largest register takes twice as
227 // many registers to represent as the previous ValueType.
228 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
229 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
230 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
232 // Inspect all of the ValueType's possible, deciding how to process them.
233 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
234 // If we are expanding this type, expand it!
235 if (getNumRegisters((MVT::ValueType)IntReg) != 1)
236 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
238 else if (!isTypeLegal((MVT::ValueType)IntReg))
239 // Otherwise, if we don't have native support, we must promote to a
241 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
242 TransformToType, ValueTypeActions);
244 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
246 // If the target does not have native f64 support, expand it to i64. We will
247 // be generating soft float library calls. If the target does not have native
248 // support for f32, promote it to f64 if it is legal. Otherwise, expand it to
250 if (isTypeLegal(MVT::f64))
251 TransformToType[MVT::f64] = MVT::f64;
253 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
254 SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
257 if (isTypeLegal(MVT::f32))
258 TransformToType[MVT::f32] = MVT::f32;
259 else if (isTypeLegal(MVT::f64))
260 SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
263 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
264 SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
268 // Set MVT::Vector to always be Expanded
269 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
272 // Loop over all of the legal vector value types, specifying an identity type
274 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
275 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
276 if (isTypeLegal((MVT::ValueType)i))
277 TransformToType[i] = (MVT::ValueType)i;
281 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
285 /// getVectorTypeBreakdown - Packed types are broken down into some number of
286 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
287 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
289 /// This method returns the number and type of the resultant breakdown.
291 unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy,
292 MVT::ValueType &PTyElementVT,
293 MVT::ValueType &PTyLegalElementVT) const {
294 // Figure out the right, legal destination reg to copy into.
295 unsigned NumElts = PTy->getNumElements();
296 MVT::ValueType EltTy = getValueType(PTy->getElementType());
298 unsigned NumVectorRegs = 1;
300 // Divide the input until we get to a supported size. This will always
301 // end with a scalar if the target doesn't support vectors.
302 while (NumElts > 1 && !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
307 MVT::ValueType VT = MVT::getVectorType(EltTy, NumElts);
308 if (!isTypeLegal(VT))
312 MVT::ValueType DestVT = getTypeToTransformTo(VT);
313 PTyLegalElementVT = DestVT;
315 // Value is expanded, e.g. i64 -> i16.
316 return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
318 // Otherwise, promotion or legal types use the same number of registers as
319 // the vector decimated to the appropriate level.
320 return NumVectorRegs;
326 //===----------------------------------------------------------------------===//
327 // Optimization Methods
328 //===----------------------------------------------------------------------===//
330 /// ShrinkDemandedConstant - Check to see if the specified operand of the
331 /// specified instruction is a constant integer. If so, check to see if there
332 /// are any bits set in the constant that are not demanded. If so, shrink the
333 /// constant and return true.
334 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
336 // FIXME: ISD::SELECT, ISD::SELECT_CC
337 switch(Op.getOpcode()) {
342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
343 if ((~Demanded & C->getValue()) != 0) {
344 MVT::ValueType VT = Op.getValueType();
345 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
346 DAG.getConstant(Demanded & C->getValue(),
348 return CombineTo(Op, New);
355 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
356 /// DemandedMask bits of the result of Op are ever used downstream. If we can
357 /// use this information to simplify Op, create a new simplified DAG node and
358 /// return true, returning the original and new nodes in Old and New. Otherwise,
359 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
360 /// the expression (used to simplify the caller). The KnownZero/One bits may
361 /// only be accurate for those bits in the DemandedMask.
362 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
365 TargetLoweringOpt &TLO,
366 unsigned Depth) const {
367 KnownZero = KnownOne = 0; // Don't know anything.
369 // The masks are not wide enough to represent this type! Should use APInt.
370 if (Op.getValueType() == MVT::i128)
373 // Other users may use these bits.
374 if (!Op.Val->hasOneUse()) {
376 // If not at the root, Just compute the KnownZero/KnownOne bits to
377 // simplify things downstream.
378 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
381 // If this is the root being simplified, allow it to have multiple uses,
382 // just set the DemandedMask to all bits.
383 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
384 } else if (DemandedMask == 0) {
385 // Not demanding any bits from Op.
386 if (Op.getOpcode() != ISD::UNDEF)
387 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
389 } else if (Depth == 6) { // Limit search depth.
393 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
394 switch (Op.getOpcode()) {
396 // We know all of the bits for a constant!
397 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
398 KnownZero = ~KnownOne & DemandedMask;
399 return false; // Don't fall through, will infinitely loop.
401 // If the RHS is a constant, check to see if the LHS would be zero without
402 // using the bits from the RHS. Below, we use knowledge about the RHS to
403 // simplify the LHS, here we're using information from the LHS to simplify
405 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
406 uint64_t LHSZero, LHSOne;
407 ComputeMaskedBits(Op.getOperand(0), DemandedMask,
408 LHSZero, LHSOne, Depth+1);
409 // If the LHS already has zeros where RHSC does, this and is dead.
410 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
411 return TLO.CombineTo(Op, Op.getOperand(0));
412 // If any of the set bits in the RHS are known zero on the LHS, shrink
414 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
418 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
419 KnownOne, TLO, Depth+1))
421 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
422 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
423 KnownZero2, KnownOne2, TLO, Depth+1))
425 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
427 // If all of the demanded bits are known one on one side, return the other.
428 // These bits cannot contribute to the result of the 'and'.
429 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
430 return TLO.CombineTo(Op, Op.getOperand(0));
431 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
432 return TLO.CombineTo(Op, Op.getOperand(1));
433 // If all of the demanded bits in the inputs are known zeros, return zero.
434 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
435 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
436 // If the RHS is a constant, see if we can simplify it.
437 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
440 // Output known-1 bits are only known if set in both the LHS & RHS.
441 KnownOne &= KnownOne2;
442 // Output known-0 are known to be clear if zero in either the LHS | RHS.
443 KnownZero |= KnownZero2;
446 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
447 KnownOne, TLO, Depth+1))
449 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
450 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
451 KnownZero2, KnownOne2, TLO, Depth+1))
453 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
455 // If all of the demanded bits are known zero on one side, return the other.
456 // These bits cannot contribute to the result of the 'or'.
457 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
458 return TLO.CombineTo(Op, Op.getOperand(0));
459 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
460 return TLO.CombineTo(Op, Op.getOperand(1));
461 // If all of the potentially set bits on one side are known to be set on
462 // the other side, just use the 'other' side.
463 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
464 (DemandedMask & (~KnownZero)))
465 return TLO.CombineTo(Op, Op.getOperand(0));
466 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
467 (DemandedMask & (~KnownZero2)))
468 return TLO.CombineTo(Op, Op.getOperand(1));
469 // If the RHS is a constant, see if we can simplify it.
470 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
473 // Output known-0 bits are only known if clear in both the LHS & RHS.
474 KnownZero &= KnownZero2;
475 // Output known-1 are known to be set if set in either the LHS | RHS.
476 KnownOne |= KnownOne2;
479 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
480 KnownOne, TLO, Depth+1))
482 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
483 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
484 KnownOne2, TLO, Depth+1))
486 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
488 // If all of the demanded bits are known zero on one side, return the other.
489 // These bits cannot contribute to the result of the 'xor'.
490 if ((DemandedMask & KnownZero) == DemandedMask)
491 return TLO.CombineTo(Op, Op.getOperand(0));
492 if ((DemandedMask & KnownZero2) == DemandedMask)
493 return TLO.CombineTo(Op, Op.getOperand(1));
495 // If all of the unknown bits are known to be zero on one side or the other
496 // (but not both) turn this into an *inclusive* or.
497 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
498 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
499 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
503 // Output known-0 bits are known if clear or set in both the LHS & RHS.
504 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
505 // Output known-1 are known to be set if set in only one of the LHS, RHS.
506 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
508 // If all of the demanded bits on one side are known, and all of the set
509 // bits on that side are also known to be set on the other side, turn this
510 // into an AND, as we know the bits will be cleared.
511 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
512 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
513 if ((KnownOne & KnownOne2) == KnownOne) {
514 MVT::ValueType VT = Op.getValueType();
515 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
516 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
521 // If the RHS is a constant, see if we can simplify it.
522 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
523 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
526 KnownZero = KnownZeroOut;
527 KnownOne = KnownOneOut;
530 // If we know the result of a setcc has the top bits zero, use this info.
531 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
532 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
535 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
536 KnownOne, TLO, Depth+1))
538 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
539 KnownOne2, TLO, Depth+1))
541 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
542 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
544 // If the operands are constants, see if we can simplify them.
545 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
548 // Only known if known in both the LHS and RHS.
549 KnownOne &= KnownOne2;
550 KnownZero &= KnownZero2;
553 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
554 KnownOne, TLO, Depth+1))
556 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
557 KnownOne2, TLO, Depth+1))
559 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
560 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
562 // If the operands are constants, see if we can simplify them.
563 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
566 // Only known if known in both the LHS and RHS.
567 KnownOne &= KnownOne2;
568 KnownZero &= KnownZero2;
571 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
572 unsigned ShAmt = SA->getValue();
573 SDOperand InOp = Op.getOperand(0);
575 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
576 // single shift. We can do this if the bottom bits (which are shifted
577 // out) are never demanded.
578 if (InOp.getOpcode() == ISD::SRL &&
579 isa<ConstantSDNode>(InOp.getOperand(1))) {
580 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
581 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
582 unsigned Opc = ISD::SHL;
590 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
591 MVT::ValueType VT = Op.getValueType();
592 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
593 InOp.getOperand(0), NewSA));
597 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
598 KnownZero, KnownOne, TLO, Depth+1))
600 KnownZero <<= SA->getValue();
601 KnownOne <<= SA->getValue();
602 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
606 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
607 MVT::ValueType VT = Op.getValueType();
608 unsigned ShAmt = SA->getValue();
609 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
610 unsigned VTSize = MVT::getSizeInBits(VT);
611 SDOperand InOp = Op.getOperand(0);
613 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
614 // single shift. We can do this if the top bits (which are shifted out)
615 // are never demanded.
616 if (InOp.getOpcode() == ISD::SHL &&
617 isa<ConstantSDNode>(InOp.getOperand(1))) {
618 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
619 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
620 unsigned Opc = ISD::SRL;
628 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
629 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
630 InOp.getOperand(0), NewSA));
634 // Compute the new bits that are at the top now.
635 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
636 KnownZero, KnownOne, TLO, Depth+1))
638 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
639 KnownZero &= TypeMask;
640 KnownOne &= TypeMask;
644 uint64_t HighBits = (1ULL << ShAmt)-1;
645 HighBits <<= VTSize - ShAmt;
646 KnownZero |= HighBits; // High bits known zero.
650 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
651 MVT::ValueType VT = Op.getValueType();
652 unsigned ShAmt = SA->getValue();
654 // Compute the new bits that are at the top now.
655 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
657 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
659 // If any of the demanded bits are produced by the sign extension, we also
660 // demand the input sign bit.
661 uint64_t HighBits = (1ULL << ShAmt)-1;
662 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
663 if (HighBits & DemandedMask)
664 InDemandedMask |= MVT::getIntVTSignBit(VT);
666 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
667 KnownZero, KnownOne, TLO, Depth+1))
669 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
670 KnownZero &= TypeMask;
671 KnownOne &= TypeMask;
675 // Handle the sign bits.
676 uint64_t SignBit = MVT::getIntVTSignBit(VT);
677 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
679 // If the input sign bit is known to be zero, or if none of the top bits
680 // are demanded, turn this into an unsigned shift right.
681 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
682 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
684 } else if (KnownOne & SignBit) { // New bits are known one.
685 KnownOne |= HighBits;
689 case ISD::SIGN_EXTEND_INREG: {
690 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
692 // Sign extension. Compute the demanded bits in the result that are not
693 // present in the input.
694 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
696 // If none of the extended bits are demanded, eliminate the sextinreg.
698 return TLO.CombineTo(Op, Op.getOperand(0));
700 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
701 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
703 // Since the sign extended bits are demanded, we know that the sign
705 InputDemandedBits |= InSignBit;
707 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
708 KnownZero, KnownOne, TLO, Depth+1))
710 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
712 // If the sign bit of the input is known set or clear, then we know the
713 // top bits of the result.
715 // If the input sign bit is known zero, convert this into a zero extension.
716 if (KnownZero & InSignBit)
717 return TLO.CombineTo(Op,
718 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
720 if (KnownOne & InSignBit) { // Input sign bit known set
722 KnownZero &= ~NewBits;
723 } else { // Input sign bit unknown
724 KnownZero &= ~NewBits;
725 KnownOne &= ~NewBits;
732 MVT::ValueType VT = Op.getValueType();
733 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
734 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
739 if (ISD::isZEXTLoad(Op.Val)) {
740 LoadSDNode *LD = cast<LoadSDNode>(Op);
741 MVT::ValueType VT = LD->getLoadedVT();
742 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
746 case ISD::ZERO_EXTEND: {
747 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
749 // If none of the top bits are demanded, convert this into an any_extend.
750 uint64_t NewBits = (~InMask) & DemandedMask;
752 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
756 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
757 KnownZero, KnownOne, TLO, Depth+1))
759 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
760 KnownZero |= NewBits;
763 case ISD::SIGN_EXTEND: {
764 MVT::ValueType InVT = Op.getOperand(0).getValueType();
765 uint64_t InMask = MVT::getIntVTBitMask(InVT);
766 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
767 uint64_t NewBits = (~InMask) & DemandedMask;
769 // If none of the top bits are demanded, convert this into an any_extend.
771 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
774 // Since some of the sign extended bits are demanded, we know that the sign
776 uint64_t InDemandedBits = DemandedMask & InMask;
777 InDemandedBits |= InSignBit;
779 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
780 KnownOne, TLO, Depth+1))
783 // If the sign bit is known zero, convert this to a zero extend.
784 if (KnownZero & InSignBit)
785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
789 // If the sign bit is known one, the top bits match.
790 if (KnownOne & InSignBit) {
792 KnownZero &= ~NewBits;
793 } else { // Otherwise, top bits aren't known.
794 KnownOne &= ~NewBits;
795 KnownZero &= ~NewBits;
799 case ISD::ANY_EXTEND: {
800 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
801 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
802 KnownZero, KnownOne, TLO, Depth+1))
804 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
807 case ISD::TRUNCATE: {
808 // Simplify the input, using demanded bit information, and compute the known
809 // zero/one bits live out.
810 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
811 KnownZero, KnownOne, TLO, Depth+1))
814 // If the input is only used by this truncate, see if we can shrink it based
815 // on the known demanded bits.
816 if (Op.getOperand(0).Val->hasOneUse()) {
817 SDOperand In = Op.getOperand(0);
818 switch (In.getOpcode()) {
821 // Shrink SRL by a constant if none of the high bits shifted in are
823 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
824 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
825 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
826 HighBits >>= ShAmt->getValue();
828 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
829 (DemandedMask & HighBits) == 0) {
830 // None of the shifted in bits are needed. Add a truncate of the
831 // shift input, then shift it.
832 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
835 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
836 NewTrunc, In.getOperand(1)));
843 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
844 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
845 KnownZero &= OutMask;
849 case ISD::AssertZext: {
850 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
851 uint64_t InMask = MVT::getIntVTBitMask(VT);
852 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
853 KnownZero, KnownOne, TLO, Depth+1))
855 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
856 KnownZero |= ~InMask & DemandedMask;
861 case ISD::INTRINSIC_WO_CHAIN:
862 case ISD::INTRINSIC_W_CHAIN:
863 case ISD::INTRINSIC_VOID:
864 // Just use ComputeMaskedBits to compute output bits.
865 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
869 // If we know the value of all of the demanded bits, return this as a
871 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
872 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
877 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
878 /// this predicate to simplify operations downstream. Mask is known to be zero
879 /// for bits that V cannot have.
880 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
881 unsigned Depth) const {
882 // The masks are not wide enough to represent this type! Should use APInt.
883 if (Op.getValueType() == MVT::i128)
886 uint64_t KnownZero, KnownOne;
887 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
888 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
889 return (KnownZero & Mask) == Mask;
892 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
893 /// known to be either zero or one and return them in the KnownZero/KnownOne
894 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
896 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
897 uint64_t &KnownZero, uint64_t &KnownOne,
898 unsigned Depth) const {
899 KnownZero = KnownOne = 0; // Don't know anything.
900 if (Depth == 6 || Mask == 0)
901 return; // Limit search depth.
903 // The masks are not wide enough to represent this type! Should use APInt.
904 if (Op.getValueType() == MVT::i128)
907 uint64_t KnownZero2, KnownOne2;
909 switch (Op.getOpcode()) {
911 // We know all of the bits for a constant!
912 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
913 KnownZero = ~KnownOne & Mask;
916 // If either the LHS or the RHS are Zero, the result is zero.
917 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
919 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
920 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
921 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
923 // Output known-1 bits are only known if set in both the LHS & RHS.
924 KnownOne &= KnownOne2;
925 // Output known-0 are known to be clear if zero in either the LHS | RHS.
926 KnownZero |= KnownZero2;
929 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
931 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
932 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
933 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
935 // Output known-0 bits are only known if clear in both the LHS & RHS.
936 KnownZero &= KnownZero2;
937 // Output known-1 are known to be set if set in either the LHS | RHS.
938 KnownOne |= KnownOne2;
941 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
942 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
943 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
944 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
946 // Output known-0 bits are known if clear or set in both the LHS & RHS.
947 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
948 // Output known-1 are known to be set if set in only one of the LHS, RHS.
949 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
950 KnownZero = KnownZeroOut;
954 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
955 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
956 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
957 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
959 // Only known if known in both the LHS and RHS.
960 KnownOne &= KnownOne2;
961 KnownZero &= KnownZero2;
964 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
965 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
966 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
967 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
969 // Only known if known in both the LHS and RHS.
970 KnownOne &= KnownOne2;
971 KnownZero &= KnownZero2;
974 // If we know the result of a setcc has the top bits zero, use this info.
975 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
976 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
979 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
980 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
981 ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(),
982 KnownZero, KnownOne, Depth+1);
983 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
984 KnownZero <<= SA->getValue();
985 KnownOne <<= SA->getValue();
986 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
990 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
991 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
992 MVT::ValueType VT = Op.getValueType();
993 unsigned ShAmt = SA->getValue();
995 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
996 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask,
997 KnownZero, KnownOne, Depth+1);
998 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
999 KnownZero &= TypeMask;
1000 KnownOne &= TypeMask;
1001 KnownZero >>= ShAmt;
1004 uint64_t HighBits = (1ULL << ShAmt)-1;
1005 HighBits <<= MVT::getSizeInBits(VT)-ShAmt;
1006 KnownZero |= HighBits; // High bits known zero.
1010 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1011 MVT::ValueType VT = Op.getValueType();
1012 unsigned ShAmt = SA->getValue();
1014 // Compute the new bits that are at the top now.
1015 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
1017 uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask;
1018 // If any of the demanded bits are produced by the sign extension, we also
1019 // demand the input sign bit.
1020 uint64_t HighBits = (1ULL << ShAmt)-1;
1021 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
1022 if (HighBits & Mask)
1023 InDemandedMask |= MVT::getIntVTSignBit(VT);
1025 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
1027 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1028 KnownZero &= TypeMask;
1029 KnownOne &= TypeMask;
1030 KnownZero >>= ShAmt;
1033 // Handle the sign bits.
1034 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1035 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
1037 if (KnownZero & SignBit) {
1038 KnownZero |= HighBits; // New bits are known zero.
1039 } else if (KnownOne & SignBit) {
1040 KnownOne |= HighBits; // New bits are known one.
1044 case ISD::SIGN_EXTEND_INREG: {
1045 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1047 // Sign extension. Compute the demanded bits in the result that are not
1048 // present in the input.
1049 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask;
1051 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
1052 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT);
1054 // If the sign extended bits are demanded, we know that the sign
1057 InputDemandedBits |= InSignBit;
1059 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
1060 KnownZero, KnownOne, Depth+1);
1061 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1063 // If the sign bit of the input is known set or clear, then we know the
1064 // top bits of the result.
1065 if (KnownZero & InSignBit) { // Input sign bit known clear
1066 KnownZero |= NewBits;
1067 KnownOne &= ~NewBits;
1068 } else if (KnownOne & InSignBit) { // Input sign bit known set
1069 KnownOne |= NewBits;
1070 KnownZero &= ~NewBits;
1071 } else { // Input sign bit unknown
1072 KnownZero &= ~NewBits;
1073 KnownOne &= ~NewBits;
1080 MVT::ValueType VT = Op.getValueType();
1081 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
1082 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
1087 if (ISD::isZEXTLoad(Op.Val)) {
1088 LoadSDNode *LD = cast<LoadSDNode>(Op);
1089 MVT::ValueType VT = LD->getLoadedVT();
1090 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
1094 case ISD::ZERO_EXTEND: {
1095 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
1096 uint64_t NewBits = (~InMask) & Mask;
1097 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1099 KnownZero |= NewBits & Mask;
1100 KnownOne &= ~NewBits;
1103 case ISD::SIGN_EXTEND: {
1104 MVT::ValueType InVT = Op.getOperand(0).getValueType();
1105 unsigned InBits = MVT::getSizeInBits(InVT);
1106 uint64_t InMask = MVT::getIntVTBitMask(InVT);
1107 uint64_t InSignBit = 1ULL << (InBits-1);
1108 uint64_t NewBits = (~InMask) & Mask;
1109 uint64_t InDemandedBits = Mask & InMask;
1111 // If any of the sign extended bits are demanded, we know that the sign
1114 InDemandedBits |= InSignBit;
1116 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1118 // If the sign bit is known zero or one, the top bits match.
1119 if (KnownZero & InSignBit) {
1120 KnownZero |= NewBits;
1121 KnownOne &= ~NewBits;
1122 } else if (KnownOne & InSignBit) {
1123 KnownOne |= NewBits;
1124 KnownZero &= ~NewBits;
1125 } else { // Otherwise, top bits aren't known.
1126 KnownOne &= ~NewBits;
1127 KnownZero &= ~NewBits;
1131 case ISD::ANY_EXTEND: {
1132 MVT::ValueType VT = Op.getOperand(0).getValueType();
1133 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT),
1134 KnownZero, KnownOne, Depth+1);
1137 case ISD::TRUNCATE: {
1138 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1139 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1140 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
1141 KnownZero &= OutMask;
1142 KnownOne &= OutMask;
1145 case ISD::AssertZext: {
1146 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1147 uint64_t InMask = MVT::getIntVTBitMask(VT);
1148 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1150 KnownZero |= (~InMask) & Mask;
1154 // If either the LHS or the RHS are Zero, the result is zero.
1155 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1156 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
1157 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1158 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1160 // Output known-0 bits are known if clear or set in both the low clear bits
1161 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
1162 // low 3 bits clear.
1163 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
1164 CountTrailingZeros_64(~KnownZero2));
1166 KnownZero = (1ULL << KnownZeroOut) - 1;
1171 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1174 // We know that the top bits of C-X are clear if X contains less bits
1175 // than C (i.e. no wrap-around can happen). For example, 20-X is
1176 // positive if we can prove that X is >= 0 and < 16.
1177 MVT::ValueType VT = CLHS->getValueType(0);
1178 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
1179 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
1180 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
1181 MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
1182 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
1184 // If all of the MaskV bits are known to be zero, then we know the output
1185 // top bits are zero, because we now know that the output is from [0-C].
1186 if ((KnownZero & MaskV) == MaskV) {
1187 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
1188 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
1189 KnownOne = 0; // No one bits known.
1191 KnownZero = KnownOne = 0; // Otherwise, nothing known.
1197 // Allow the target to implement this method for its nodes.
1198 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1199 case ISD::INTRINSIC_WO_CHAIN:
1200 case ISD::INTRINSIC_W_CHAIN:
1201 case ISD::INTRINSIC_VOID:
1202 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
1208 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1209 /// in Mask are known to be either zero or one and return them in the
1210 /// KnownZero/KnownOne bitsets.
1211 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1213 uint64_t &KnownZero,
1215 unsigned Depth) const {
1216 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1217 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1218 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1219 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1220 "Should use MaskedValueIsZero if you don't know whether Op"
1221 " is a target node!");
1226 /// ComputeNumSignBits - Return the number of times the sign bit of the
1227 /// register is replicated into the other bits. We know that at least 1 bit
1228 /// is always equal to the sign bit (itself), but other cases can give us
1229 /// information. For example, immediately after an "SRA X, 2", we know that
1230 /// the top 3 bits are all equal to each other, so we return 3.
1231 unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
1232 MVT::ValueType VT = Op.getValueType();
1233 assert(MVT::isInteger(VT) && "Invalid VT!");
1234 unsigned VTBits = MVT::getSizeInBits(VT);
1238 return 1; // Limit search depth.
1240 switch (Op.getOpcode()) {
1242 case ISD::AssertSext:
1243 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1244 return VTBits-Tmp+1;
1245 case ISD::AssertZext:
1246 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1249 case ISD::Constant: {
1250 uint64_t Val = cast<ConstantSDNode>(Op)->getValue();
1251 // If negative, invert the bits, then look at it.
1252 if (Val & MVT::getIntVTSignBit(VT))
1255 // Shift the bits so they are the leading bits in the int64_t.
1258 // Return # leading zeros. We use 'min' here in case Val was zero before
1259 // shifting. We don't want to return '64' as for an i32 "0".
1260 return std::min(VTBits, CountLeadingZeros_64(Val));
1263 case ISD::SIGN_EXTEND:
1264 Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType());
1265 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
1267 case ISD::SIGN_EXTEND_INREG:
1268 // Max of the input and what this extends.
1269 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1272 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1273 return std::max(Tmp, Tmp2);
1276 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1277 // SRA X, C -> adds C sign bits.
1278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1279 Tmp += C->getValue();
1280 if (Tmp > VTBits) Tmp = VTBits;
1284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1285 // shl destroys sign bits.
1286 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1287 if (C->getValue() >= VTBits || // Bad shift.
1288 C->getValue() >= Tmp) break; // Shifted all sign bits out.
1289 return Tmp - C->getValue();
1294 case ISD::XOR: // NOT is handled here.
1295 // Logical binary ops preserve the number of sign bits.
1296 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1297 if (Tmp == 1) return 1; // Early out.
1298 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1299 return std::min(Tmp, Tmp2);
1302 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1303 if (Tmp == 1) return 1; // Early out.
1304 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1305 return std::min(Tmp, Tmp2);
1308 // If setcc returns 0/-1, all bits are sign bits.
1309 if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult)
1314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1315 unsigned RotAmt = C->getValue() & (VTBits-1);
1317 // Handle rotate right by N like a rotate left by 32-N.
1318 if (Op.getOpcode() == ISD::ROTR)
1319 RotAmt = (VTBits-RotAmt) & (VTBits-1);
1321 // If we aren't rotating out all of the known-in sign bits, return the
1322 // number that are left. This handles rotl(sext(x), 1) for example.
1323 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1324 if (Tmp > RotAmt+1) return Tmp-RotAmt;
1328 // Add can have at most one carry bit. Thus we know that the output
1329 // is, at worst, one more bit than the inputs.
1330 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1331 if (Tmp == 1) return 1; // Early out.
1333 // Special case decrementing a value (ADD X, -1):
1334 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1335 if (CRHS->isAllOnesValue()) {
1336 uint64_t KnownZero, KnownOne;
1337 uint64_t Mask = MVT::getIntVTBitMask(VT);
1338 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1340 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1342 if ((KnownZero|1) == Mask)
1345 // If we are subtracting one from a positive number, there is no carry
1346 // out of the result.
1347 if (KnownZero & MVT::getIntVTSignBit(VT))
1351 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1352 if (Tmp2 == 1) return 1;
1353 return std::min(Tmp, Tmp2)-1;
1357 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1358 if (Tmp2 == 1) return 1;
1361 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1362 if (CLHS->getValue() == 0) {
1363 uint64_t KnownZero, KnownOne;
1364 uint64_t Mask = MVT::getIntVTBitMask(VT);
1365 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1366 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1368 if ((KnownZero|1) == Mask)
1371 // If the input is known to be positive (the sign bit is known clear),
1372 // the output of the NEG has the same number of sign bits as the input.
1373 if (KnownZero & MVT::getIntVTSignBit(VT))
1376 // Otherwise, we treat this like a SUB.
1379 // Sub can have at most one carry bit. Thus we know that the output
1380 // is, at worst, one more bit than the inputs.
1381 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1382 if (Tmp == 1) return 1; // Early out.
1383 return std::min(Tmp, Tmp2)-1;
1386 // FIXME: it's tricky to do anything useful for this, but it is an important
1387 // case for targets like X86.
1391 // Handle LOADX separately here. EXTLOAD case will fallthrough.
1392 if (Op.getOpcode() == ISD::LOAD) {
1393 LoadSDNode *LD = cast<LoadSDNode>(Op);
1394 unsigned ExtType = LD->getExtensionType();
1397 case ISD::SEXTLOAD: // '17' bits known
1398 Tmp = MVT::getSizeInBits(LD->getLoadedVT());
1399 return VTBits-Tmp+1;
1400 case ISD::ZEXTLOAD: // '16' bits known
1401 Tmp = MVT::getSizeInBits(LD->getLoadedVT());
1406 // Allow the target to implement this method for its nodes.
1407 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1408 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1409 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1410 Op.getOpcode() == ISD::INTRINSIC_VOID) {
1411 unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth);
1412 if (NumBits > 1) return NumBits;
1415 // Finally, if we can prove that the top bits of the result are 0's or 1's,
1416 // use this information.
1417 uint64_t KnownZero, KnownOne;
1418 uint64_t Mask = MVT::getIntVTBitMask(VT);
1419 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1421 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1422 if (KnownZero & SignBit) { // SignBit is 0
1424 } else if (KnownOne & SignBit) { // SignBit is 1;
1431 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
1432 // the number of identical bits in the top of the input value.
1435 // Return # leading zeros. We use 'min' here in case Val was zero before
1436 // shifting. We don't want to return '64' as for an i32 "0".
1437 return std::min(VTBits, CountLeadingZeros_64(Mask));
1442 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1443 /// targets that want to expose additional information about sign bits to the
1445 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1446 unsigned Depth) const {
1447 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1448 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1449 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1450 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1451 "Should use ComputeNumSignBits if you don't know whether Op"
1452 " is a target node!");
1457 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1458 /// and cc. If it is unable to simplify it, return a null SDOperand.
1460 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
1461 ISD::CondCode Cond, bool foldBooleans,
1462 DAGCombinerInfo &DCI) const {
1463 SelectionDAG &DAG = DCI.DAG;
1465 // These setcc operations always fold.
1469 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1471 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1474 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1475 uint64_t C1 = N1C->getValue();
1476 if (isa<ConstantSDNode>(N0.Val)) {
1477 return DAG.FoldSetCC(VT, N0, N1, Cond);
1479 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1480 // equality comparison, then we're just comparing whether X itself is
1482 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1483 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1484 N0.getOperand(1).getOpcode() == ISD::Constant) {
1485 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1486 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1487 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
1488 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1489 // (srl (ctlz x), 5) == 0 -> X != 0
1490 // (srl (ctlz x), 5) != 1 -> X != 0
1493 // (srl (ctlz x), 5) != 0 -> X == 0
1494 // (srl (ctlz x), 5) == 1 -> X == 0
1497 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
1498 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
1503 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1504 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1505 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1507 // If the comparison constant has bits in the upper part, the
1508 // zero-extended value could never match.
1509 if (C1 & (~0ULL << InSize)) {
1510 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1514 case ISD::SETEQ: return DAG.getConstant(0, VT);
1517 case ISD::SETNE: return DAG.getConstant(1, VT);
1520 // True if the sign bit of C1 is set.
1521 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
1524 // True if the sign bit of C1 isn't set.
1525 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
1531 // Otherwise, we can perform the comparison with the low bits.
1539 return DAG.getSetCC(VT, N0.getOperand(0),
1540 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1543 break; // todo, be more careful with signed comparisons
1545 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1546 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1547 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1548 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1549 MVT::ValueType ExtDstTy = N0.getValueType();
1550 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1552 // If the extended part has any inconsistent bits, it cannot ever
1553 // compare equal. In other words, they have to be all ones or all
1556 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1557 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1558 return DAG.getConstant(Cond == ISD::SETNE, VT);
1561 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1562 if (Op0Ty == ExtSrcTy) {
1563 ZextOp = N0.getOperand(0);
1565 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1566 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1567 DAG.getConstant(Imm, Op0Ty));
1569 if (!DCI.isCalledByLegalizer())
1570 DCI.AddToWorklist(ZextOp.Val);
1571 // Otherwise, make this a use of a zext.
1572 return DAG.getSetCC(VT, ZextOp,
1573 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1576 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1577 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1579 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1580 if (N0.getOpcode() == ISD::SETCC) {
1581 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1585 // Invert the condition.
1586 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1587 CC = ISD::getSetCCInverse(CC,
1588 MVT::isInteger(N0.getOperand(0).getValueType()));
1589 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1592 if ((N0.getOpcode() == ISD::XOR ||
1593 (N0.getOpcode() == ISD::AND &&
1594 N0.getOperand(0).getOpcode() == ISD::XOR &&
1595 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1596 isa<ConstantSDNode>(N0.getOperand(1)) &&
1597 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1598 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1599 // can only do this if the top bits are known zero.
1600 if (MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){
1601 // Okay, get the un-inverted input value.
1603 if (N0.getOpcode() == ISD::XOR)
1604 Val = N0.getOperand(0);
1606 assert(N0.getOpcode() == ISD::AND &&
1607 N0.getOperand(0).getOpcode() == ISD::XOR);
1608 // ((X^1)&1)^1 -> X & 1
1609 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1610 N0.getOperand(0).getOperand(0),
1613 return DAG.getSetCC(VT, Val, N1,
1614 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1619 uint64_t MinVal, MaxVal;
1620 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1621 if (ISD::isSignedIntSetCC(Cond)) {
1622 MinVal = 1ULL << (OperandBitSize-1);
1623 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1624 MaxVal = ~0ULL >> (65-OperandBitSize);
1629 MaxVal = ~0ULL >> (64-OperandBitSize);
1632 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1633 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1634 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1635 --C1; // X >= C0 --> X > (C0-1)
1636 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1637 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1640 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1641 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1642 ++C1; // X <= C0 --> X < (C0+1)
1643 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1644 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1647 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1648 return DAG.getConstant(0, VT); // X < MIN --> false
1649 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1650 return DAG.getConstant(1, VT); // X >= MIN --> true
1651 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1652 return DAG.getConstant(0, VT); // X > MAX --> false
1653 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1654 return DAG.getConstant(1, VT); // X <= MAX --> true
1656 // Canonicalize setgt X, Min --> setne X, Min
1657 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1658 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1659 // Canonicalize setlt X, Max --> setne X, Max
1660 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1661 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1663 // If we have setult X, 1, turn it into seteq X, 0
1664 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1665 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1667 // If we have setugt X, Max-1, turn it into seteq X, Max
1668 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1669 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1672 // If we have "setcc X, C0", check to see if we can shrink the immediate
1675 // SETUGT X, SINTMAX -> SETLT X, 0
1676 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1677 C1 == (~0ULL >> (65-OperandBitSize)))
1678 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1681 // FIXME: Implement the rest of these.
1683 // Fold bit comparisons when we can.
1684 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1685 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1686 if (ConstantSDNode *AndRHS =
1687 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1688 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1689 // Perform the xform if the AND RHS is a single bit.
1690 if (isPowerOf2_64(AndRHS->getValue())) {
1691 return DAG.getNode(ISD::SRL, VT, N0,
1692 DAG.getConstant(Log2_64(AndRHS->getValue()),
1693 getShiftAmountTy()));
1695 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1696 // (X & 8) == 8 --> (X & 8) >> 3
1697 // Perform the xform if C1 is a single bit.
1698 if (isPowerOf2_64(C1)) {
1699 return DAG.getNode(ISD::SRL, VT, N0,
1700 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1705 } else if (isa<ConstantSDNode>(N0.Val)) {
1706 // Ensure that the constant occurs on the RHS.
1707 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1710 if (isa<ConstantFPSDNode>(N0.Val)) {
1711 // Constant fold or commute setcc.
1712 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1713 if (O.Val) return O;
1717 // We can always fold X == X for integer setcc's.
1718 if (MVT::isInteger(N0.getValueType()))
1719 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1720 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1721 if (UOF == 2) // FP operators that are undefined on NaNs.
1722 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1723 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1724 return DAG.getConstant(UOF, VT);
1725 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1726 // if it is not already.
1727 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1728 if (NewCond != Cond)
1729 return DAG.getSetCC(VT, N0, N1, NewCond);
1732 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1733 MVT::isInteger(N0.getValueType())) {
1734 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1735 N0.getOpcode() == ISD::XOR) {
1736 // Simplify (X+Y) == (X+Z) --> Y == Z
1737 if (N0.getOpcode() == N1.getOpcode()) {
1738 if (N0.getOperand(0) == N1.getOperand(0))
1739 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1740 if (N0.getOperand(1) == N1.getOperand(1))
1741 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1742 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1743 // If X op Y == Y op X, try other combinations.
1744 if (N0.getOperand(0) == N1.getOperand(1))
1745 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1746 if (N0.getOperand(1) == N1.getOperand(0))
1747 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1751 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1752 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1753 // Turn (X+C1) == C2 --> X == C2-C1
1754 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1755 return DAG.getSetCC(VT, N0.getOperand(0),
1756 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1757 N0.getValueType()), Cond);
1760 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1761 if (N0.getOpcode() == ISD::XOR)
1762 // If we know that all of the inverted bits are zero, don't bother
1763 // performing the inversion.
1764 if (MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1765 return DAG.getSetCC(VT, N0.getOperand(0),
1766 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1767 N0.getValueType()), Cond);
1770 // Turn (C1-X) == C2 --> X == C1-C2
1771 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1772 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1773 return DAG.getSetCC(VT, N0.getOperand(1),
1774 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1775 N0.getValueType()), Cond);
1780 // Simplify (X+Z) == X --> Z == 0
1781 if (N0.getOperand(0) == N1)
1782 return DAG.getSetCC(VT, N0.getOperand(1),
1783 DAG.getConstant(0, N0.getValueType()), Cond);
1784 if (N0.getOperand(1) == N1) {
1785 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1786 return DAG.getSetCC(VT, N0.getOperand(0),
1787 DAG.getConstant(0, N0.getValueType()), Cond);
1788 else if (N0.Val->hasOneUse()) {
1789 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1790 // (Z-X) == X --> Z == X<<1
1791 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1793 DAG.getConstant(1, getShiftAmountTy()));
1794 if (!DCI.isCalledByLegalizer())
1795 DCI.AddToWorklist(SH.Val);
1796 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1801 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1802 N1.getOpcode() == ISD::XOR) {
1803 // Simplify X == (X+Z) --> Z == 0
1804 if (N1.getOperand(0) == N0) {
1805 return DAG.getSetCC(VT, N1.getOperand(1),
1806 DAG.getConstant(0, N1.getValueType()), Cond);
1807 } else if (N1.getOperand(1) == N0) {
1808 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1809 return DAG.getSetCC(VT, N1.getOperand(0),
1810 DAG.getConstant(0, N1.getValueType()), Cond);
1811 } else if (N1.Val->hasOneUse()) {
1812 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1813 // X == (Z-X) --> X<<1 == Z
1814 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1815 DAG.getConstant(1, getShiftAmountTy()));
1816 if (!DCI.isCalledByLegalizer())
1817 DCI.AddToWorklist(SH.Val);
1818 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1824 // Fold away ALL boolean setcc's.
1826 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1828 default: assert(0 && "Unknown integer setcc!");
1829 case ISD::SETEQ: // X == Y -> (X^Y)^1
1830 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1831 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1832 if (!DCI.isCalledByLegalizer())
1833 DCI.AddToWorklist(Temp.Val);
1835 case ISD::SETNE: // X != Y --> (X^Y)
1836 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1838 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1839 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1840 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1841 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1842 if (!DCI.isCalledByLegalizer())
1843 DCI.AddToWorklist(Temp.Val);
1845 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1846 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1847 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1848 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1849 if (!DCI.isCalledByLegalizer())
1850 DCI.AddToWorklist(Temp.Val);
1852 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1853 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1854 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1855 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1856 if (!DCI.isCalledByLegalizer())
1857 DCI.AddToWorklist(Temp.Val);
1859 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1860 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1861 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1862 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1865 if (VT != MVT::i1) {
1866 if (!DCI.isCalledByLegalizer())
1867 DCI.AddToWorklist(N0.Val);
1868 // FIXME: If running after legalize, we probably can't do this.
1869 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1874 // Could not fold it.
1878 SDOperand TargetLowering::
1879 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1880 // Default implementation: no optimization.
1884 //===----------------------------------------------------------------------===//
1885 // Inline Assembler Implementation Methods
1886 //===----------------------------------------------------------------------===//
1888 TargetLowering::ConstraintType
1889 TargetLowering::getConstraintType(const std::string &Constraint) const {
1890 // FIXME: lots more standard ones to handle.
1891 if (Constraint.size() == 1) {
1892 switch (Constraint[0]) {
1894 case 'r': return C_RegisterClass;
1896 case 'o': // offsetable
1897 case 'V': // not offsetable
1899 case 'i': // Simple Integer or Relocatable Constant
1900 case 'n': // Simple Integer
1901 case 's': // Relocatable Constant
1902 case 'X': // Allow ANY value.
1903 case 'I': // Target registers.
1915 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1916 Constraint[Constraint.size()-1] == '}')
1921 /// isOperandValidForConstraint - Return the specified operand (possibly
1922 /// modified) if the specified SDOperand is valid for the specified target
1923 /// constraint letter, otherwise return null.
1924 SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
1925 char ConstraintLetter,
1926 SelectionDAG &DAG) {
1927 switch (ConstraintLetter) {
1929 case 'i': // Simple Integer or Relocatable Constant
1930 case 'n': // Simple Integer
1931 case 's': // Relocatable Constant
1932 case 'X': { // Allows any operand.
1933 // These operands are interested in values of the form (GV+C), where C may
1934 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1935 // is possible and fine if either GV or C are missing.
1936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1937 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1939 // If we have "(add GV, C)", pull out GV/C
1940 if (Op.getOpcode() == ISD::ADD) {
1941 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1942 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1943 if (C == 0 || GA == 0) {
1944 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1945 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1947 if (C == 0 || GA == 0)
1951 // If we find a valid operand, map to the TargetXXX version so that the
1952 // value itself doesn't get selected.
1953 if (GA) { // Either &GV or &GV+C
1954 if (ConstraintLetter != 'n') {
1955 int64_t Offs = GA->getOffset();
1956 if (C) Offs += C->getValue();
1957 return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(),
1961 if (C) { // just C, no GV.
1962 // Simple constants are not allowed for 's'.
1963 if (ConstraintLetter != 's')
1964 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
1969 return SDOperand(0,0);
1972 std::vector<unsigned> TargetLowering::
1973 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1974 MVT::ValueType VT) const {
1975 return std::vector<unsigned>();
1979 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1980 getRegForInlineAsmConstraint(const std::string &Constraint,
1981 MVT::ValueType VT) const {
1982 if (Constraint[0] != '{')
1983 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1984 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1986 // Remove the braces from around the name.
1987 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1989 // Figure out which register class contains this reg.
1990 const MRegisterInfo *RI = TM.getRegisterInfo();
1991 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1992 E = RI->regclass_end(); RCI != E; ++RCI) {
1993 const TargetRegisterClass *RC = *RCI;
1995 // If none of the the value types for this register class are valid, we
1996 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1997 bool isLegal = false;
1998 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2000 if (isTypeLegal(*I)) {
2006 if (!isLegal) continue;
2008 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2010 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
2011 return std::make_pair(*I, RC);
2015 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2018 //===----------------------------------------------------------------------===//
2019 // Loop Strength Reduction hooks
2020 //===----------------------------------------------------------------------===//
2022 /// isLegalAddressingMode - Return true if the addressing mode represented
2023 /// by AM is legal for this target, for a load/store of the specified type.
2024 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2025 const Type *Ty) const {
2026 // The default implementation of this implements a conservative RISCy, r+r and
2029 // Allows a sign-extended 16-bit immediate field.
2030 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2033 // No global is ever allowed as a base.
2037 // Only support r+r,
2039 case 0: // "r+i" or just "i", depending on HasBaseReg.
2042 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2044 // Otherwise we have r+r or r+i.
2047 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2049 // Allow 2*r as r+r.
2056 // Magic for divide replacement
2059 int64_t m; // magic number
2060 int64_t s; // shift amount
2064 uint64_t m; // magic number
2065 int64_t a; // add indicator
2066 int64_t s; // shift amount
2069 /// magic - calculate the magic numbers required to codegen an integer sdiv as
2070 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
2072 static ms magic32(int32_t d) {
2074 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
2075 const uint32_t two31 = 0x80000000U;
2079 t = two31 + ((uint32_t)d >> 31);
2080 anc = t - 1 - t%ad; // absolute value of nc
2081 p = 31; // initialize p
2082 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
2083 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
2084 q2 = two31/ad; // initialize q2 = 2p/abs(d)
2085 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
2088 q1 = 2*q1; // update q1 = 2p/abs(nc)
2089 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
2090 if (r1 >= anc) { // must be unsigned comparison
2094 q2 = 2*q2; // update q2 = 2p/abs(d)
2095 r2 = 2*r2; // update r2 = rem(2p/abs(d))
2096 if (r2 >= ad) { // must be unsigned comparison
2101 } while (q1 < delta || (q1 == delta && r1 == 0));
2103 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
2104 if (d < 0) mag.m = -mag.m; // resulting magic number
2105 mag.s = p - 32; // resulting shift
2109 /// magicu - calculate the magic numbers required to codegen an integer udiv as
2110 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
2111 static mu magicu32(uint32_t d) {
2113 uint32_t nc, delta, q1, r1, q2, r2;
2115 magu.a = 0; // initialize "add" indicator
2117 p = 31; // initialize p
2118 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
2119 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
2120 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
2121 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
2124 if (r1 >= nc - r1 ) {
2125 q1 = 2*q1 + 1; // update q1
2126 r1 = 2*r1 - nc; // update r1
2129 q1 = 2*q1; // update q1
2130 r1 = 2*r1; // update r1
2132 if (r2 + 1 >= d - r2) {
2133 if (q2 >= 0x7FFFFFFF) magu.a = 1;
2134 q2 = 2*q2 + 1; // update q2
2135 r2 = 2*r2 + 1 - d; // update r2
2138 if (q2 >= 0x80000000) magu.a = 1;
2139 q2 = 2*q2; // update q2
2140 r2 = 2*r2 + 1; // update r2
2143 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
2144 magu.m = q2 + 1; // resulting magic number
2145 magu.s = p - 32; // resulting shift
2149 /// magic - calculate the magic numbers required to codegen an integer sdiv as
2150 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
2152 static ms magic64(int64_t d) {
2154 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
2155 const uint64_t two63 = 9223372036854775808ULL; // 2^63
2158 ad = d >= 0 ? d : -d;
2159 t = two63 + ((uint64_t)d >> 63);
2160 anc = t - 1 - t%ad; // absolute value of nc
2161 p = 63; // initialize p
2162 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
2163 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
2164 q2 = two63/ad; // initialize q2 = 2p/abs(d)
2165 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
2168 q1 = 2*q1; // update q1 = 2p/abs(nc)
2169 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
2170 if (r1 >= anc) { // must be unsigned comparison
2174 q2 = 2*q2; // update q2 = 2p/abs(d)
2175 r2 = 2*r2; // update r2 = rem(2p/abs(d))
2176 if (r2 >= ad) { // must be unsigned comparison
2181 } while (q1 < delta || (q1 == delta && r1 == 0));
2184 if (d < 0) mag.m = -mag.m; // resulting magic number
2185 mag.s = p - 64; // resulting shift
2189 /// magicu - calculate the magic numbers required to codegen an integer udiv as
2190 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
2191 static mu magicu64(uint64_t d)
2194 uint64_t nc, delta, q1, r1, q2, r2;
2196 magu.a = 0; // initialize "add" indicator
2198 p = 63; // initialize p
2199 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
2200 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
2201 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
2202 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
2205 if (r1 >= nc - r1 ) {
2206 q1 = 2*q1 + 1; // update q1
2207 r1 = 2*r1 - nc; // update r1
2210 q1 = 2*q1; // update q1
2211 r1 = 2*r1; // update r1
2213 if (r2 + 1 >= d - r2) {
2214 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
2215 q2 = 2*q2 + 1; // update q2
2216 r2 = 2*r2 + 1 - d; // update r2
2219 if (q2 >= 0x8000000000000000ull) magu.a = 1;
2220 q2 = 2*q2; // update q2
2221 r2 = 2*r2 + 1; // update r2
2224 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
2225 magu.m = q2 + 1; // resulting magic number
2226 magu.s = p - 64; // resulting shift
2230 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2231 /// return a DAG expression to select that will generate the same value by
2232 /// multiplying by a magic number. See:
2233 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2234 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2235 std::vector<SDNode*>* Created) const {
2236 MVT::ValueType VT = N->getValueType(0);
2238 // Check to see if we can do this.
2239 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2240 return SDOperand(); // BuildSDIV only operates on i32 or i64
2241 if (!isOperationLegal(ISD::MULHS, VT))
2242 return SDOperand(); // Make sure the target supports MULHS.
2244 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2245 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2247 // Multiply the numerator (operand 0) by the magic value
2248 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2249 DAG.getConstant(magics.m, VT));
2250 // If d > 0 and m < 0, add the numerator
2251 if (d > 0 && magics.m < 0) {
2252 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2254 Created->push_back(Q.Val);
2256 // If d < 0 and m > 0, subtract the numerator.
2257 if (d < 0 && magics.m > 0) {
2258 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2260 Created->push_back(Q.Val);
2262 // Shift right algebraic if shift value is nonzero
2264 Q = DAG.getNode(ISD::SRA, VT, Q,
2265 DAG.getConstant(magics.s, getShiftAmountTy()));
2267 Created->push_back(Q.Val);
2269 // Extract the sign bit and add it to the quotient
2271 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2272 getShiftAmountTy()));
2274 Created->push_back(T.Val);
2275 return DAG.getNode(ISD::ADD, VT, Q, T);
2278 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2279 /// return a DAG expression to select that will generate the same value by
2280 /// multiplying by a magic number. See:
2281 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2282 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2283 std::vector<SDNode*>* Created) const {
2284 MVT::ValueType VT = N->getValueType(0);
2286 // Check to see if we can do this.
2287 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2288 return SDOperand(); // BuildUDIV only operates on i32 or i64
2289 if (!isOperationLegal(ISD::MULHU, VT))
2290 return SDOperand(); // Make sure the target supports MULHU.
2292 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2293 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2295 // Multiply the numerator (operand 0) by the magic value
2296 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2297 DAG.getConstant(magics.m, VT));
2299 Created->push_back(Q.Val);
2301 if (magics.a == 0) {
2302 return DAG.getNode(ISD::SRL, VT, Q,
2303 DAG.getConstant(magics.s, getShiftAmountTy()));
2305 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2307 Created->push_back(NPQ.Val);
2308 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2309 DAG.getConstant(1, getShiftAmountTy()));
2311 Created->push_back(NPQ.Val);
2312 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2314 Created->push_back(NPQ.Val);
2315 return DAG.getNode(ISD::SRL, VT, NPQ,
2316 DAG.getConstant(magics.s-1, getShiftAmountTy()));