1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetData.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 /// InitLibcallNames - Set default libcall names.
28 static void InitLibcallNames(const char **Names) {
29 Names[RTLIB::SHL_I32] = "__ashlsi3";
30 Names[RTLIB::SHL_I64] = "__ashldi3";
31 Names[RTLIB::SRL_I32] = "__lshrsi3";
32 Names[RTLIB::SRL_I64] = "__lshrdi3";
33 Names[RTLIB::SRA_I32] = "__ashrsi3";
34 Names[RTLIB::SRA_I64] = "__ashrdi3";
35 Names[RTLIB::MUL_I32] = "__mulsi3";
36 Names[RTLIB::MUL_I64] = "__muldi3";
37 Names[RTLIB::SDIV_I32] = "__divsi3";
38 Names[RTLIB::SDIV_I64] = "__divdi3";
39 Names[RTLIB::UDIV_I32] = "__udivsi3";
40 Names[RTLIB::UDIV_I64] = "__udivdi3";
41 Names[RTLIB::SREM_I32] = "__modsi3";
42 Names[RTLIB::SREM_I64] = "__moddi3";
43 Names[RTLIB::UREM_I32] = "__umodsi3";
44 Names[RTLIB::UREM_I64] = "__umoddi3";
45 Names[RTLIB::NEG_I32] = "__negsi2";
46 Names[RTLIB::NEG_I64] = "__negdi2";
47 Names[RTLIB::ADD_F32] = "__addsf3";
48 Names[RTLIB::ADD_F64] = "__adddf3";
49 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
50 Names[RTLIB::SUB_F32] = "__subsf3";
51 Names[RTLIB::SUB_F64] = "__subdf3";
52 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
53 Names[RTLIB::MUL_F32] = "__mulsf3";
54 Names[RTLIB::MUL_F64] = "__muldf3";
55 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
56 Names[RTLIB::DIV_F32] = "__divsf3";
57 Names[RTLIB::DIV_F64] = "__divdf3";
58 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
59 Names[RTLIB::REM_F32] = "fmodf";
60 Names[RTLIB::REM_F64] = "fmod";
61 Names[RTLIB::REM_PPCF128] = "fmodl";
62 Names[RTLIB::NEG_F32] = "__negsf2";
63 Names[RTLIB::NEG_F64] = "__negdf2";
64 Names[RTLIB::POWI_F32] = "__powisf2";
65 Names[RTLIB::POWI_F64] = "__powidf2";
66 Names[RTLIB::POWI_F80] = "__powixf2";
67 Names[RTLIB::POWI_PPCF128] = "__powitf2";
68 Names[RTLIB::SQRT_F32] = "sqrtf";
69 Names[RTLIB::SQRT_F64] = "sqrt";
70 Names[RTLIB::SQRT_F80] = "sqrtl";
71 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
72 Names[RTLIB::SIN_F32] = "sinf";
73 Names[RTLIB::SIN_F64] = "sin";
74 Names[RTLIB::COS_F32] = "cosf";
75 Names[RTLIB::COS_F64] = "cos";
76 Names[RTLIB::POW_F32] = "powf";
77 Names[RTLIB::POW_F64] = "pow";
78 Names[RTLIB::POW_F80] = "powl";
79 Names[RTLIB::POW_PPCF128] = "powl";
80 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
81 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
82 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
83 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
84 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
85 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
86 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
87 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
88 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
89 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
90 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
91 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
92 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
93 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
94 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
95 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
96 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
97 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
98 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
99 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
100 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
101 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
102 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
103 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
104 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
105 Names[RTLIB::OEQ_F32] = "__eqsf2";
106 Names[RTLIB::OEQ_F64] = "__eqdf2";
107 Names[RTLIB::UNE_F32] = "__nesf2";
108 Names[RTLIB::UNE_F64] = "__nedf2";
109 Names[RTLIB::OGE_F32] = "__gesf2";
110 Names[RTLIB::OGE_F64] = "__gedf2";
111 Names[RTLIB::OLT_F32] = "__ltsf2";
112 Names[RTLIB::OLT_F64] = "__ltdf2";
113 Names[RTLIB::OLE_F32] = "__lesf2";
114 Names[RTLIB::OLE_F64] = "__ledf2";
115 Names[RTLIB::OGT_F32] = "__gtsf2";
116 Names[RTLIB::OGT_F64] = "__gtdf2";
117 Names[RTLIB::UO_F32] = "__unordsf2";
118 Names[RTLIB::UO_F64] = "__unorddf2";
119 Names[RTLIB::O_F32] = "__unordsf2";
120 Names[RTLIB::O_F64] = "__unorddf2";
123 /// InitCmpLibcallCCs - Set default comparison libcall CC.
125 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
126 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
127 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
128 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
129 CCs[RTLIB::UNE_F32] = ISD::SETNE;
130 CCs[RTLIB::UNE_F64] = ISD::SETNE;
131 CCs[RTLIB::OGE_F32] = ISD::SETGE;
132 CCs[RTLIB::OGE_F64] = ISD::SETGE;
133 CCs[RTLIB::OLT_F32] = ISD::SETLT;
134 CCs[RTLIB::OLT_F64] = ISD::SETLT;
135 CCs[RTLIB::OLE_F32] = ISD::SETLE;
136 CCs[RTLIB::OLE_F64] = ISD::SETLE;
137 CCs[RTLIB::OGT_F32] = ISD::SETGT;
138 CCs[RTLIB::OGT_F64] = ISD::SETGT;
139 CCs[RTLIB::UO_F32] = ISD::SETNE;
140 CCs[RTLIB::UO_F64] = ISD::SETNE;
141 CCs[RTLIB::O_F32] = ISD::SETEQ;
142 CCs[RTLIB::O_F64] = ISD::SETEQ;
145 TargetLowering::TargetLowering(TargetMachine &tm)
146 : TM(tm), TD(TM.getTargetData()) {
147 assert(ISD::BUILTIN_OP_END <= 156 &&
148 "Fixed size array in TargetLowering is not large enough!");
149 // All operations default to being supported.
150 memset(OpActions, 0, sizeof(OpActions));
151 memset(LoadXActions, 0, sizeof(LoadXActions));
152 memset(&StoreXActions, 0, sizeof(StoreXActions));
153 memset(&IndexedModeActions, 0, sizeof(IndexedModeActions));
154 memset(&ConvertActions, 0, sizeof(ConvertActions));
156 // Set all indexed load / store to expand.
157 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
158 for (unsigned IM = (unsigned)ISD::PRE_INC;
159 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
160 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
161 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
165 IsLittleEndian = TD->isLittleEndian();
166 UsesGlobalOffsetTable = false;
167 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
168 ShiftAmtHandling = Undefined;
169 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
170 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
171 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
172 allowUnalignedMemoryAccesses = false;
173 UseUnderscoreSetJmp = false;
174 UseUnderscoreLongJmp = false;
175 SelectIsExpensive = false;
176 IntDivIsCheap = false;
177 Pow2DivIsCheap = false;
178 StackPointerRegisterToSaveRestore = 0;
179 ExceptionPointerRegister = 0;
180 ExceptionSelectorRegister = 0;
181 SetCCResultContents = UndefinedSetCCResult;
182 SchedPreferenceInfo = SchedulingForLatency;
184 JumpBufAlignment = 0;
185 IfCvtBlockSizeLimit = 2;
187 InitLibcallNames(LibcallRoutineNames);
188 InitCmpLibcallCCs(CmpLibcallCCs);
190 // Tell Legalize whether the assembler supports DEBUG_LOC.
191 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile())
192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
195 TargetLowering::~TargetLowering() {}
197 /// computeRegisterProperties - Once all of the register classes are added,
198 /// this allows us to compute derived properties we expose.
199 void TargetLowering::computeRegisterProperties() {
200 assert(MVT::LAST_VALUETYPE <= 32 &&
201 "Too many value types for ValueTypeActions to hold!");
203 // Everything defaults to needing one register.
204 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
205 NumRegistersForVT[i] = 1;
206 RegisterTypeForVT[i] = TransformToType[i] = i;
208 // ...except isVoid, which doesn't need any registers.
209 NumRegistersForVT[MVT::isVoid] = 0;
211 // Find the largest integer register class.
212 unsigned LargestIntReg = MVT::i128;
213 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
214 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
216 // Every integer value type larger than this largest register takes twice as
217 // many registers to represent as the previous ValueType.
218 for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
219 MVT::isInteger(ExpandedReg); ++ExpandedReg) {
220 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
221 RegisterTypeForVT[ExpandedReg] = LargestIntReg;
222 TransformToType[ExpandedReg] = ExpandedReg - 1;
223 ValueTypeActions.setTypeAction(ExpandedReg, Expand);
226 // Inspect all of the ValueType's smaller than the largest integer
227 // register to see which ones need promotion.
228 MVT::ValueType LegalIntReg = LargestIntReg;
229 for (MVT::ValueType IntReg = LargestIntReg - 1;
230 IntReg >= MVT::i1; --IntReg) {
231 if (isTypeLegal(IntReg)) {
232 LegalIntReg = IntReg;
234 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
235 ValueTypeActions.setTypeAction(IntReg, Promote);
239 // ppcf128 type is really two f64's.
240 if (!isTypeLegal(MVT::ppcf128)) {
241 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
242 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
243 TransformToType[MVT::ppcf128] = MVT::f64;
244 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
247 // Decide how to handle f64. If the target does not have native f64 support,
248 // expand it to i64 and we will be generating soft float library calls.
249 if (!isTypeLegal(MVT::f64)) {
250 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
251 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
252 TransformToType[MVT::f64] = MVT::i64;
253 ValueTypeActions.setTypeAction(MVT::f64, Expand);
256 // Decide how to handle f32. If the target does not have native support for
257 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
258 if (!isTypeLegal(MVT::f32)) {
259 if (isTypeLegal(MVT::f64)) {
260 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
261 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
262 TransformToType[MVT::f32] = MVT::f64;
263 ValueTypeActions.setTypeAction(MVT::f32, Promote);
265 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
266 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
267 TransformToType[MVT::f32] = MVT::i32;
268 ValueTypeActions.setTypeAction(MVT::f32, Expand);
272 // Loop over all of the vector value types to see which need transformations.
273 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
274 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
275 if (!isTypeLegal(i)) {
276 MVT::ValueType IntermediateVT, RegisterVT;
277 unsigned NumIntermediates;
278 NumRegistersForVT[i] =
279 getVectorTypeBreakdown(i,
280 IntermediateVT, NumIntermediates,
282 RegisterTypeForVT[i] = RegisterVT;
283 TransformToType[i] = MVT::Other; // this isn't actually used
284 ValueTypeActions.setTypeAction(i, Expand);
289 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
293 /// getVectorTypeBreakdown - Vector types are broken down into some number of
294 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
295 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
296 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
298 /// This method returns the number of registers needed, and the VT for each
299 /// register. It also returns the VT and quantity of the intermediate values
300 /// before they are promoted/expanded.
302 unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
303 MVT::ValueType &IntermediateVT,
304 unsigned &NumIntermediates,
305 MVT::ValueType &RegisterVT) const {
306 // Figure out the right, legal destination reg to copy into.
307 unsigned NumElts = MVT::getVectorNumElements(VT);
308 MVT::ValueType EltTy = MVT::getVectorElementType(VT);
310 unsigned NumVectorRegs = 1;
312 // Divide the input until we get to a supported size. This will always
313 // end with a scalar if the target doesn't support vectors.
314 while (NumElts > 1 &&
315 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
320 NumIntermediates = NumVectorRegs;
322 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
323 if (!isTypeLegal(NewVT))
325 IntermediateVT = NewVT;
327 MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
329 if (DestVT < NewVT) {
330 // Value is expanded, e.g. i64 -> i16.
331 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
333 // Otherwise, promotion or legal types use the same number of registers as
334 // the vector decimated to the appropriate level.
335 return NumVectorRegs;
341 //===----------------------------------------------------------------------===//
342 // Optimization Methods
343 //===----------------------------------------------------------------------===//
345 /// ShrinkDemandedConstant - Check to see if the specified operand of the
346 /// specified instruction is a constant integer. If so, check to see if there
347 /// are any bits set in the constant that are not demanded. If so, shrink the
348 /// constant and return true.
349 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
351 // FIXME: ISD::SELECT, ISD::SELECT_CC
352 switch(Op.getOpcode()) {
357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
358 if ((~Demanded & C->getValue()) != 0) {
359 MVT::ValueType VT = Op.getValueType();
360 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
361 DAG.getConstant(Demanded & C->getValue(),
363 return CombineTo(Op, New);
370 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
371 /// DemandedMask bits of the result of Op are ever used downstream. If we can
372 /// use this information to simplify Op, create a new simplified DAG node and
373 /// return true, returning the original and new nodes in Old and New. Otherwise,
374 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
375 /// the expression (used to simplify the caller). The KnownZero/One bits may
376 /// only be accurate for those bits in the DemandedMask.
377 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
380 TargetLoweringOpt &TLO,
381 unsigned Depth) const {
382 KnownZero = KnownOne = 0; // Don't know anything.
384 // The masks are not wide enough to represent this type! Should use APInt.
385 if (Op.getValueType() == MVT::i128)
388 // Other users may use these bits.
389 if (!Op.Val->hasOneUse()) {
391 // If not at the root, Just compute the KnownZero/KnownOne bits to
392 // simplify things downstream.
393 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
396 // If this is the root being simplified, allow it to have multiple uses,
397 // just set the DemandedMask to all bits.
398 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
399 } else if (DemandedMask == 0) {
400 // Not demanding any bits from Op.
401 if (Op.getOpcode() != ISD::UNDEF)
402 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
404 } else if (Depth == 6) { // Limit search depth.
408 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
409 switch (Op.getOpcode()) {
411 // We know all of the bits for a constant!
412 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
413 KnownZero = ~KnownOne & DemandedMask;
414 return false; // Don't fall through, will infinitely loop.
416 // If the RHS is a constant, check to see if the LHS would be zero without
417 // using the bits from the RHS. Below, we use knowledge about the RHS to
418 // simplify the LHS, here we're using information from the LHS to simplify
420 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
421 uint64_t LHSZero, LHSOne;
422 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask,
423 LHSZero, LHSOne, Depth+1);
424 // If the LHS already has zeros where RHSC does, this and is dead.
425 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
426 return TLO.CombineTo(Op, Op.getOperand(0));
427 // If any of the set bits in the RHS are known zero on the LHS, shrink
429 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
433 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
434 KnownOne, TLO, Depth+1))
436 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
437 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
438 KnownZero2, KnownOne2, TLO, Depth+1))
440 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
442 // If all of the demanded bits are known one on one side, return the other.
443 // These bits cannot contribute to the result of the 'and'.
444 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
445 return TLO.CombineTo(Op, Op.getOperand(0));
446 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
447 return TLO.CombineTo(Op, Op.getOperand(1));
448 // If all of the demanded bits in the inputs are known zeros, return zero.
449 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
450 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
451 // If the RHS is a constant, see if we can simplify it.
452 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
455 // Output known-1 bits are only known if set in both the LHS & RHS.
456 KnownOne &= KnownOne2;
457 // Output known-0 are known to be clear if zero in either the LHS | RHS.
458 KnownZero |= KnownZero2;
461 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
462 KnownOne, TLO, Depth+1))
464 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
465 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
466 KnownZero2, KnownOne2, TLO, Depth+1))
468 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
470 // If all of the demanded bits are known zero on one side, return the other.
471 // These bits cannot contribute to the result of the 'or'.
472 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
473 return TLO.CombineTo(Op, Op.getOperand(0));
474 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
475 return TLO.CombineTo(Op, Op.getOperand(1));
476 // If all of the potentially set bits on one side are known to be set on
477 // the other side, just use the 'other' side.
478 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
479 (DemandedMask & (~KnownZero)))
480 return TLO.CombineTo(Op, Op.getOperand(0));
481 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
482 (DemandedMask & (~KnownZero2)))
483 return TLO.CombineTo(Op, Op.getOperand(1));
484 // If the RHS is a constant, see if we can simplify it.
485 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
488 // Output known-0 bits are only known if clear in both the LHS & RHS.
489 KnownZero &= KnownZero2;
490 // Output known-1 are known to be set if set in either the LHS | RHS.
491 KnownOne |= KnownOne2;
494 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
495 KnownOne, TLO, Depth+1))
497 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
498 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
499 KnownOne2, TLO, Depth+1))
501 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
503 // If all of the demanded bits are known zero on one side, return the other.
504 // These bits cannot contribute to the result of the 'xor'.
505 if ((DemandedMask & KnownZero) == DemandedMask)
506 return TLO.CombineTo(Op, Op.getOperand(0));
507 if ((DemandedMask & KnownZero2) == DemandedMask)
508 return TLO.CombineTo(Op, Op.getOperand(1));
510 // If all of the unknown bits are known to be zero on one side or the other
511 // (but not both) turn this into an *inclusive* or.
512 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
513 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
514 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
518 // Output known-0 bits are known if clear or set in both the LHS & RHS.
519 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
520 // Output known-1 are known to be set if set in only one of the LHS, RHS.
521 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
523 // If all of the demanded bits on one side are known, and all of the set
524 // bits on that side are also known to be set on the other side, turn this
525 // into an AND, as we know the bits will be cleared.
526 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
527 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
528 if ((KnownOne & KnownOne2) == KnownOne) {
529 MVT::ValueType VT = Op.getValueType();
530 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
531 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
536 // If the RHS is a constant, see if we can simplify it.
537 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
538 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
541 KnownZero = KnownZeroOut;
542 KnownOne = KnownOneOut;
545 // If we know the result of a setcc has the top bits zero, use this info.
546 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
547 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
550 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
551 KnownOne, TLO, Depth+1))
553 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
554 KnownOne2, TLO, Depth+1))
556 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
557 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
559 // If the operands are constants, see if we can simplify them.
560 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
563 // Only known if known in both the LHS and RHS.
564 KnownOne &= KnownOne2;
565 KnownZero &= KnownZero2;
568 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
569 KnownOne, TLO, Depth+1))
571 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
572 KnownOne2, TLO, Depth+1))
574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
575 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
577 // If the operands are constants, see if we can simplify them.
578 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
581 // Only known if known in both the LHS and RHS.
582 KnownOne &= KnownOne2;
583 KnownZero &= KnownZero2;
586 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
587 unsigned ShAmt = SA->getValue();
588 SDOperand InOp = Op.getOperand(0);
590 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
591 // single shift. We can do this if the bottom bits (which are shifted
592 // out) are never demanded.
593 if (InOp.getOpcode() == ISD::SRL &&
594 isa<ConstantSDNode>(InOp.getOperand(1))) {
595 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
596 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
597 unsigned Opc = ISD::SHL;
605 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
606 MVT::ValueType VT = Op.getValueType();
607 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
608 InOp.getOperand(0), NewSA));
612 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
613 KnownZero, KnownOne, TLO, Depth+1))
615 KnownZero <<= SA->getValue();
616 KnownOne <<= SA->getValue();
617 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
621 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
622 MVT::ValueType VT = Op.getValueType();
623 unsigned ShAmt = SA->getValue();
624 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
625 unsigned VTSize = MVT::getSizeInBits(VT);
626 SDOperand InOp = Op.getOperand(0);
628 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
629 // single shift. We can do this if the top bits (which are shifted out)
630 // are never demanded.
631 if (InOp.getOpcode() == ISD::SHL &&
632 isa<ConstantSDNode>(InOp.getOperand(1))) {
633 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
634 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
635 unsigned Opc = ISD::SRL;
643 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
644 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
645 InOp.getOperand(0), NewSA));
649 // Compute the new bits that are at the top now.
650 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
651 KnownZero, KnownOne, TLO, Depth+1))
653 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
654 KnownZero &= TypeMask;
655 KnownOne &= TypeMask;
659 uint64_t HighBits = (1ULL << ShAmt)-1;
660 HighBits <<= VTSize - ShAmt;
661 KnownZero |= HighBits; // High bits known zero.
665 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
666 MVT::ValueType VT = Op.getValueType();
667 unsigned ShAmt = SA->getValue();
669 // Compute the new bits that are at the top now.
670 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
672 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
674 // If any of the demanded bits are produced by the sign extension, we also
675 // demand the input sign bit.
676 uint64_t HighBits = (1ULL << ShAmt)-1;
677 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
678 if (HighBits & DemandedMask)
679 InDemandedMask |= MVT::getIntVTSignBit(VT);
681 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
682 KnownZero, KnownOne, TLO, Depth+1))
684 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
685 KnownZero &= TypeMask;
686 KnownOne &= TypeMask;
690 // Handle the sign bits.
691 uint64_t SignBit = MVT::getIntVTSignBit(VT);
692 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
694 // If the input sign bit is known to be zero, or if none of the top bits
695 // are demanded, turn this into an unsigned shift right.
696 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
697 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
699 } else if (KnownOne & SignBit) { // New bits are known one.
700 KnownOne |= HighBits;
704 case ISD::SIGN_EXTEND_INREG: {
705 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
707 // Sign extension. Compute the demanded bits in the result that are not
708 // present in the input.
709 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
711 // If none of the extended bits are demanded, eliminate the sextinreg.
713 return TLO.CombineTo(Op, Op.getOperand(0));
715 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
716 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
718 // Since the sign extended bits are demanded, we know that the sign
720 InputDemandedBits |= InSignBit;
722 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
723 KnownZero, KnownOne, TLO, Depth+1))
725 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
727 // If the sign bit of the input is known set or clear, then we know the
728 // top bits of the result.
730 // If the input sign bit is known zero, convert this into a zero extension.
731 if (KnownZero & InSignBit)
732 return TLO.CombineTo(Op,
733 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
735 if (KnownOne & InSignBit) { // Input sign bit known set
737 KnownZero &= ~NewBits;
738 } else { // Input sign bit unknown
739 KnownZero &= ~NewBits;
740 KnownOne &= ~NewBits;
747 MVT::ValueType VT = Op.getValueType();
748 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
749 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
754 if (ISD::isZEXTLoad(Op.Val)) {
755 LoadSDNode *LD = cast<LoadSDNode>(Op);
756 MVT::ValueType VT = LD->getLoadedVT();
757 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
761 case ISD::ZERO_EXTEND: {
762 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
764 // If none of the top bits are demanded, convert this into an any_extend.
765 uint64_t NewBits = (~InMask) & DemandedMask;
767 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
771 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
772 KnownZero, KnownOne, TLO, Depth+1))
774 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
775 KnownZero |= NewBits;
778 case ISD::SIGN_EXTEND: {
779 MVT::ValueType InVT = Op.getOperand(0).getValueType();
780 uint64_t InMask = MVT::getIntVTBitMask(InVT);
781 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
782 uint64_t NewBits = (~InMask) & DemandedMask;
784 // If none of the top bits are demanded, convert this into an any_extend.
786 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
789 // Since some of the sign extended bits are demanded, we know that the sign
791 uint64_t InDemandedBits = DemandedMask & InMask;
792 InDemandedBits |= InSignBit;
794 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
795 KnownOne, TLO, Depth+1))
798 // If the sign bit is known zero, convert this to a zero extend.
799 if (KnownZero & InSignBit)
800 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
804 // If the sign bit is known one, the top bits match.
805 if (KnownOne & InSignBit) {
807 KnownZero &= ~NewBits;
808 } else { // Otherwise, top bits aren't known.
809 KnownOne &= ~NewBits;
810 KnownZero &= ~NewBits;
814 case ISD::ANY_EXTEND: {
815 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
816 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
817 KnownZero, KnownOne, TLO, Depth+1))
819 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
822 case ISD::TRUNCATE: {
823 // Simplify the input, using demanded bit information, and compute the known
824 // zero/one bits live out.
825 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
826 KnownZero, KnownOne, TLO, Depth+1))
829 // If the input is only used by this truncate, see if we can shrink it based
830 // on the known demanded bits.
831 if (Op.getOperand(0).Val->hasOneUse()) {
832 SDOperand In = Op.getOperand(0);
833 switch (In.getOpcode()) {
836 // Shrink SRL by a constant if none of the high bits shifted in are
838 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
839 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
840 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
841 HighBits >>= ShAmt->getValue();
843 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
844 (DemandedMask & HighBits) == 0) {
845 // None of the shifted in bits are needed. Add a truncate of the
846 // shift input, then shift it.
847 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
850 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
851 NewTrunc, In.getOperand(1)));
858 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
859 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
860 KnownZero &= OutMask;
864 case ISD::AssertZext: {
865 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
866 uint64_t InMask = MVT::getIntVTBitMask(VT);
867 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
868 KnownZero, KnownOne, TLO, Depth+1))
870 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
871 KnownZero |= ~InMask & DemandedMask;
876 case ISD::INTRINSIC_WO_CHAIN:
877 case ISD::INTRINSIC_W_CHAIN:
878 case ISD::INTRINSIC_VOID:
879 // Just use ComputeMaskedBits to compute output bits.
880 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
884 // If we know the value of all of the demanded bits, return this as a
886 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
887 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
892 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
893 /// in Mask are known to be either zero or one and return them in the
894 /// KnownZero/KnownOne bitsets.
895 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
899 const SelectionDAG &DAG,
900 unsigned Depth) const {
901 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
902 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
903 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
904 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
905 "Should use MaskedValueIsZero if you don't know whether Op"
906 " is a target node!");
911 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
912 /// targets that want to expose additional information about sign bits to the
914 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
915 unsigned Depth) const {
916 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
917 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
918 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
919 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
920 "Should use ComputeNumSignBits if you don't know whether Op"
921 " is a target node!");
926 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
927 /// and cc. If it is unable to simplify it, return a null SDOperand.
929 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
930 ISD::CondCode Cond, bool foldBooleans,
931 DAGCombinerInfo &DCI) const {
932 SelectionDAG &DAG = DCI.DAG;
934 // These setcc operations always fold.
938 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
940 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
943 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
944 uint64_t C1 = N1C->getValue();
945 if (isa<ConstantSDNode>(N0.Val)) {
946 return DAG.FoldSetCC(VT, N0, N1, Cond);
948 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
949 // equality comparison, then we're just comparing whether X itself is
951 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
952 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
953 N0.getOperand(1).getOpcode() == ISD::Constant) {
954 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
955 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
956 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
957 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
958 // (srl (ctlz x), 5) == 0 -> X != 0
959 // (srl (ctlz x), 5) != 1 -> X != 0
962 // (srl (ctlz x), 5) != 0 -> X == 0
963 // (srl (ctlz x), 5) == 1 -> X == 0
966 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
967 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
972 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
973 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
974 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
976 // If the comparison constant has bits in the upper part, the
977 // zero-extended value could never match.
978 if (C1 & (~0ULL << InSize)) {
979 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
983 case ISD::SETEQ: return DAG.getConstant(0, VT);
986 case ISD::SETNE: return DAG.getConstant(1, VT);
989 // True if the sign bit of C1 is set.
990 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
993 // True if the sign bit of C1 isn't set.
994 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
1000 // Otherwise, we can perform the comparison with the low bits.
1008 return DAG.getSetCC(VT, N0.getOperand(0),
1009 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1012 break; // todo, be more careful with signed comparisons
1014 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1015 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1016 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1017 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1018 MVT::ValueType ExtDstTy = N0.getValueType();
1019 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1021 // If the extended part has any inconsistent bits, it cannot ever
1022 // compare equal. In other words, they have to be all ones or all
1025 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1026 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1027 return DAG.getConstant(Cond == ISD::SETNE, VT);
1030 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1031 if (Op0Ty == ExtSrcTy) {
1032 ZextOp = N0.getOperand(0);
1034 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1035 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1036 DAG.getConstant(Imm, Op0Ty));
1038 if (!DCI.isCalledByLegalizer())
1039 DCI.AddToWorklist(ZextOp.Val);
1040 // Otherwise, make this a use of a zext.
1041 return DAG.getSetCC(VT, ZextOp,
1042 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1045 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1046 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1048 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1049 if (N0.getOpcode() == ISD::SETCC) {
1050 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1054 // Invert the condition.
1055 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1056 CC = ISD::getSetCCInverse(CC,
1057 MVT::isInteger(N0.getOperand(0).getValueType()));
1058 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1061 if ((N0.getOpcode() == ISD::XOR ||
1062 (N0.getOpcode() == ISD::AND &&
1063 N0.getOperand(0).getOpcode() == ISD::XOR &&
1064 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1065 isa<ConstantSDNode>(N0.getOperand(1)) &&
1066 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1067 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1068 // can only do this if the top bits are known zero.
1069 if (DAG.MaskedValueIsZero(N0,
1070 MVT::getIntVTBitMask(N0.getValueType())-1)){
1071 // Okay, get the un-inverted input value.
1073 if (N0.getOpcode() == ISD::XOR)
1074 Val = N0.getOperand(0);
1076 assert(N0.getOpcode() == ISD::AND &&
1077 N0.getOperand(0).getOpcode() == ISD::XOR);
1078 // ((X^1)&1)^1 -> X & 1
1079 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1080 N0.getOperand(0).getOperand(0),
1083 return DAG.getSetCC(VT, Val, N1,
1084 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1089 uint64_t MinVal, MaxVal;
1090 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1091 if (ISD::isSignedIntSetCC(Cond)) {
1092 MinVal = 1ULL << (OperandBitSize-1);
1093 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1094 MaxVal = ~0ULL >> (65-OperandBitSize);
1099 MaxVal = ~0ULL >> (64-OperandBitSize);
1102 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1103 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1104 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1105 --C1; // X >= C0 --> X > (C0-1)
1106 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1107 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1110 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1111 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1112 ++C1; // X <= C0 --> X < (C0+1)
1113 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1114 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1117 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1118 return DAG.getConstant(0, VT); // X < MIN --> false
1119 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1120 return DAG.getConstant(1, VT); // X >= MIN --> true
1121 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1122 return DAG.getConstant(0, VT); // X > MAX --> false
1123 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1124 return DAG.getConstant(1, VT); // X <= MAX --> true
1126 // Canonicalize setgt X, Min --> setne X, Min
1127 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1128 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1129 // Canonicalize setlt X, Max --> setne X, Max
1130 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1131 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1133 // If we have setult X, 1, turn it into seteq X, 0
1134 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1135 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1137 // If we have setugt X, Max-1, turn it into seteq X, Max
1138 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1139 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1142 // If we have "setcc X, C0", check to see if we can shrink the immediate
1145 // SETUGT X, SINTMAX -> SETLT X, 0
1146 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1147 C1 == (~0ULL >> (65-OperandBitSize)))
1148 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1151 // FIXME: Implement the rest of these.
1153 // Fold bit comparisons when we can.
1154 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1155 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1156 if (ConstantSDNode *AndRHS =
1157 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1158 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1159 // Perform the xform if the AND RHS is a single bit.
1160 if (isPowerOf2_64(AndRHS->getValue())) {
1161 return DAG.getNode(ISD::SRL, VT, N0,
1162 DAG.getConstant(Log2_64(AndRHS->getValue()),
1163 getShiftAmountTy()));
1165 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1166 // (X & 8) == 8 --> (X & 8) >> 3
1167 // Perform the xform if C1 is a single bit.
1168 if (isPowerOf2_64(C1)) {
1169 return DAG.getNode(ISD::SRL, VT, N0,
1170 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1175 } else if (isa<ConstantSDNode>(N0.Val)) {
1176 // Ensure that the constant occurs on the RHS.
1177 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1180 if (isa<ConstantFPSDNode>(N0.Val)) {
1181 // Constant fold or commute setcc.
1182 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1183 if (O.Val) return O;
1187 // We can always fold X == X for integer setcc's.
1188 if (MVT::isInteger(N0.getValueType()))
1189 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1190 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1191 if (UOF == 2) // FP operators that are undefined on NaNs.
1192 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1193 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1194 return DAG.getConstant(UOF, VT);
1195 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1196 // if it is not already.
1197 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1198 if (NewCond != Cond)
1199 return DAG.getSetCC(VT, N0, N1, NewCond);
1202 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1203 MVT::isInteger(N0.getValueType())) {
1204 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1205 N0.getOpcode() == ISD::XOR) {
1206 // Simplify (X+Y) == (X+Z) --> Y == Z
1207 if (N0.getOpcode() == N1.getOpcode()) {
1208 if (N0.getOperand(0) == N1.getOperand(0))
1209 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1210 if (N0.getOperand(1) == N1.getOperand(1))
1211 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1212 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1213 // If X op Y == Y op X, try other combinations.
1214 if (N0.getOperand(0) == N1.getOperand(1))
1215 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1216 if (N0.getOperand(1) == N1.getOperand(0))
1217 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1221 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1222 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1223 // Turn (X+C1) == C2 --> X == C2-C1
1224 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1225 return DAG.getSetCC(VT, N0.getOperand(0),
1226 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1227 N0.getValueType()), Cond);
1230 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1231 if (N0.getOpcode() == ISD::XOR)
1232 // If we know that all of the inverted bits are zero, don't bother
1233 // performing the inversion.
1234 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1235 return DAG.getSetCC(VT, N0.getOperand(0),
1236 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1237 N0.getValueType()), Cond);
1240 // Turn (C1-X) == C2 --> X == C1-C2
1241 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1242 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1243 return DAG.getSetCC(VT, N0.getOperand(1),
1244 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1245 N0.getValueType()), Cond);
1250 // Simplify (X+Z) == X --> Z == 0
1251 if (N0.getOperand(0) == N1)
1252 return DAG.getSetCC(VT, N0.getOperand(1),
1253 DAG.getConstant(0, N0.getValueType()), Cond);
1254 if (N0.getOperand(1) == N1) {
1255 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1256 return DAG.getSetCC(VT, N0.getOperand(0),
1257 DAG.getConstant(0, N0.getValueType()), Cond);
1258 else if (N0.Val->hasOneUse()) {
1259 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1260 // (Z-X) == X --> Z == X<<1
1261 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1263 DAG.getConstant(1, getShiftAmountTy()));
1264 if (!DCI.isCalledByLegalizer())
1265 DCI.AddToWorklist(SH.Val);
1266 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1271 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1272 N1.getOpcode() == ISD::XOR) {
1273 // Simplify X == (X+Z) --> Z == 0
1274 if (N1.getOperand(0) == N0) {
1275 return DAG.getSetCC(VT, N1.getOperand(1),
1276 DAG.getConstant(0, N1.getValueType()), Cond);
1277 } else if (N1.getOperand(1) == N0) {
1278 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1279 return DAG.getSetCC(VT, N1.getOperand(0),
1280 DAG.getConstant(0, N1.getValueType()), Cond);
1281 } else if (N1.Val->hasOneUse()) {
1282 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1283 // X == (Z-X) --> X<<1 == Z
1284 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1285 DAG.getConstant(1, getShiftAmountTy()));
1286 if (!DCI.isCalledByLegalizer())
1287 DCI.AddToWorklist(SH.Val);
1288 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1294 // Fold away ALL boolean setcc's.
1296 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1298 default: assert(0 && "Unknown integer setcc!");
1299 case ISD::SETEQ: // X == Y -> (X^Y)^1
1300 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1301 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1302 if (!DCI.isCalledByLegalizer())
1303 DCI.AddToWorklist(Temp.Val);
1305 case ISD::SETNE: // X != Y --> (X^Y)
1306 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1308 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1309 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1310 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1311 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1312 if (!DCI.isCalledByLegalizer())
1313 DCI.AddToWorklist(Temp.Val);
1315 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1316 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1317 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1318 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1319 if (!DCI.isCalledByLegalizer())
1320 DCI.AddToWorklist(Temp.Val);
1322 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1323 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1324 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1325 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1326 if (!DCI.isCalledByLegalizer())
1327 DCI.AddToWorklist(Temp.Val);
1329 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1330 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1331 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1332 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1335 if (VT != MVT::i1) {
1336 if (!DCI.isCalledByLegalizer())
1337 DCI.AddToWorklist(N0.Val);
1338 // FIXME: If running after legalize, we probably can't do this.
1339 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1344 // Could not fold it.
1348 SDOperand TargetLowering::
1349 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1350 // Default implementation: no optimization.
1354 //===----------------------------------------------------------------------===//
1355 // Inline Assembler Implementation Methods
1356 //===----------------------------------------------------------------------===//
1358 TargetLowering::ConstraintType
1359 TargetLowering::getConstraintType(const std::string &Constraint) const {
1360 // FIXME: lots more standard ones to handle.
1361 if (Constraint.size() == 1) {
1362 switch (Constraint[0]) {
1364 case 'r': return C_RegisterClass;
1366 case 'o': // offsetable
1367 case 'V': // not offsetable
1369 case 'i': // Simple Integer or Relocatable Constant
1370 case 'n': // Simple Integer
1371 case 's': // Relocatable Constant
1372 case 'X': // Allow ANY value.
1373 case 'I': // Target registers.
1385 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1386 Constraint[Constraint.size()-1] == '}')
1391 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1392 /// vector. If it is invalid, don't add anything to Ops.
1393 void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
1394 char ConstraintLetter,
1395 std::vector<SDOperand> &Ops,
1396 SelectionDAG &DAG) {
1397 switch (ConstraintLetter) {
1399 case 'i': // Simple Integer or Relocatable Constant
1400 case 'n': // Simple Integer
1401 case 's': // Relocatable Constant
1402 case 'X': { // Allows any operand.
1403 // These operands are interested in values of the form (GV+C), where C may
1404 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1405 // is possible and fine if either GV or C are missing.
1406 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1407 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1409 // If we have "(add GV, C)", pull out GV/C
1410 if (Op.getOpcode() == ISD::ADD) {
1411 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1412 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1413 if (C == 0 || GA == 0) {
1414 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1415 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1417 if (C == 0 || GA == 0)
1421 // If we find a valid operand, map to the TargetXXX version so that the
1422 // value itself doesn't get selected.
1423 if (GA) { // Either &GV or &GV+C
1424 if (ConstraintLetter != 'n') {
1425 int64_t Offs = GA->getOffset();
1426 if (C) Offs += C->getValue();
1427 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1428 Op.getValueType(), Offs));
1432 if (C) { // just C, no GV.
1433 // Simple constants are not allowed for 's'.
1434 if (ConstraintLetter != 's') {
1435 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
1444 std::vector<unsigned> TargetLowering::
1445 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1446 MVT::ValueType VT) const {
1447 return std::vector<unsigned>();
1451 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1452 getRegForInlineAsmConstraint(const std::string &Constraint,
1453 MVT::ValueType VT) const {
1454 if (Constraint[0] != '{')
1455 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1456 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1458 // Remove the braces from around the name.
1459 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1461 // Figure out which register class contains this reg.
1462 const MRegisterInfo *RI = TM.getRegisterInfo();
1463 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1464 E = RI->regclass_end(); RCI != E; ++RCI) {
1465 const TargetRegisterClass *RC = *RCI;
1467 // If none of the the value types for this register class are valid, we
1468 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1469 bool isLegal = false;
1470 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1472 if (isTypeLegal(*I)) {
1478 if (!isLegal) continue;
1480 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1482 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1483 return std::make_pair(*I, RC);
1487 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1490 //===----------------------------------------------------------------------===//
1491 // Loop Strength Reduction hooks
1492 //===----------------------------------------------------------------------===//
1494 /// isLegalAddressingMode - Return true if the addressing mode represented
1495 /// by AM is legal for this target, for a load/store of the specified type.
1496 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1497 const Type *Ty) const {
1498 // The default implementation of this implements a conservative RISCy, r+r and
1501 // Allows a sign-extended 16-bit immediate field.
1502 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1505 // No global is ever allowed as a base.
1509 // Only support r+r,
1511 case 0: // "r+i" or just "i", depending on HasBaseReg.
1514 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1516 // Otherwise we have r+r or r+i.
1519 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1521 // Allow 2*r as r+r.
1528 // Magic for divide replacement
1531 int64_t m; // magic number
1532 int64_t s; // shift amount
1536 uint64_t m; // magic number
1537 int64_t a; // add indicator
1538 int64_t s; // shift amount
1541 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1542 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1544 static ms magic32(int32_t d) {
1546 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1547 const uint32_t two31 = 0x80000000U;
1551 t = two31 + ((uint32_t)d >> 31);
1552 anc = t - 1 - t%ad; // absolute value of nc
1553 p = 31; // initialize p
1554 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1555 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1556 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1557 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1560 q1 = 2*q1; // update q1 = 2p/abs(nc)
1561 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1562 if (r1 >= anc) { // must be unsigned comparison
1566 q2 = 2*q2; // update q2 = 2p/abs(d)
1567 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1568 if (r2 >= ad) { // must be unsigned comparison
1573 } while (q1 < delta || (q1 == delta && r1 == 0));
1575 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1576 if (d < 0) mag.m = -mag.m; // resulting magic number
1577 mag.s = p - 32; // resulting shift
1581 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1582 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1583 static mu magicu32(uint32_t d) {
1585 uint32_t nc, delta, q1, r1, q2, r2;
1587 magu.a = 0; // initialize "add" indicator
1589 p = 31; // initialize p
1590 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1591 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1592 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1593 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1596 if (r1 >= nc - r1 ) {
1597 q1 = 2*q1 + 1; // update q1
1598 r1 = 2*r1 - nc; // update r1
1601 q1 = 2*q1; // update q1
1602 r1 = 2*r1; // update r1
1604 if (r2 + 1 >= d - r2) {
1605 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1606 q2 = 2*q2 + 1; // update q2
1607 r2 = 2*r2 + 1 - d; // update r2
1610 if (q2 >= 0x80000000) magu.a = 1;
1611 q2 = 2*q2; // update q2
1612 r2 = 2*r2 + 1; // update r2
1615 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1616 magu.m = q2 + 1; // resulting magic number
1617 magu.s = p - 32; // resulting shift
1621 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1622 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1624 static ms magic64(int64_t d) {
1626 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1627 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1630 ad = d >= 0 ? d : -d;
1631 t = two63 + ((uint64_t)d >> 63);
1632 anc = t - 1 - t%ad; // absolute value of nc
1633 p = 63; // initialize p
1634 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1635 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1636 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1637 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1640 q1 = 2*q1; // update q1 = 2p/abs(nc)
1641 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1642 if (r1 >= anc) { // must be unsigned comparison
1646 q2 = 2*q2; // update q2 = 2p/abs(d)
1647 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1648 if (r2 >= ad) { // must be unsigned comparison
1653 } while (q1 < delta || (q1 == delta && r1 == 0));
1656 if (d < 0) mag.m = -mag.m; // resulting magic number
1657 mag.s = p - 64; // resulting shift
1661 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1662 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1663 static mu magicu64(uint64_t d)
1666 uint64_t nc, delta, q1, r1, q2, r2;
1668 magu.a = 0; // initialize "add" indicator
1670 p = 63; // initialize p
1671 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1672 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1673 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1674 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1677 if (r1 >= nc - r1 ) {
1678 q1 = 2*q1 + 1; // update q1
1679 r1 = 2*r1 - nc; // update r1
1682 q1 = 2*q1; // update q1
1683 r1 = 2*r1; // update r1
1685 if (r2 + 1 >= d - r2) {
1686 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1687 q2 = 2*q2 + 1; // update q2
1688 r2 = 2*r2 + 1 - d; // update r2
1691 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1692 q2 = 2*q2; // update q2
1693 r2 = 2*r2 + 1; // update r2
1696 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1697 magu.m = q2 + 1; // resulting magic number
1698 magu.s = p - 64; // resulting shift
1702 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1703 /// return a DAG expression to select that will generate the same value by
1704 /// multiplying by a magic number. See:
1705 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1706 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1707 std::vector<SDNode*>* Created) const {
1708 MVT::ValueType VT = N->getValueType(0);
1710 // Check to see if we can do this.
1711 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1712 return SDOperand(); // BuildSDIV only operates on i32 or i64
1714 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1715 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1717 // Multiply the numerator (operand 0) by the magic value
1719 if (isOperationLegal(ISD::MULHS, VT))
1720 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1721 DAG.getConstant(magics.m, VT));
1722 else if (isOperationLegal(ISD::SMUL_LOHI, VT))
1723 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
1725 DAG.getConstant(magics.m, VT)).Val, 1);
1727 return SDOperand(); // No mulhs or equvialent
1728 // If d > 0 and m < 0, add the numerator
1729 if (d > 0 && magics.m < 0) {
1730 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1732 Created->push_back(Q.Val);
1734 // If d < 0 and m > 0, subtract the numerator.
1735 if (d < 0 && magics.m > 0) {
1736 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1738 Created->push_back(Q.Val);
1740 // Shift right algebraic if shift value is nonzero
1742 Q = DAG.getNode(ISD::SRA, VT, Q,
1743 DAG.getConstant(magics.s, getShiftAmountTy()));
1745 Created->push_back(Q.Val);
1747 // Extract the sign bit and add it to the quotient
1749 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1750 getShiftAmountTy()));
1752 Created->push_back(T.Val);
1753 return DAG.getNode(ISD::ADD, VT, Q, T);
1756 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1757 /// return a DAG expression to select that will generate the same value by
1758 /// multiplying by a magic number. See:
1759 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1760 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1761 std::vector<SDNode*>* Created) const {
1762 MVT::ValueType VT = N->getValueType(0);
1764 // Check to see if we can do this.
1765 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1766 return SDOperand(); // BuildUDIV only operates on i32 or i64
1768 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1769 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1771 // Multiply the numerator (operand 0) by the magic value
1773 if (isOperationLegal(ISD::MULHU, VT))
1774 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1775 DAG.getConstant(magics.m, VT));
1776 else if (isOperationLegal(ISD::UMUL_LOHI, VT))
1777 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
1779 DAG.getConstant(magics.m, VT)).Val, 1);
1781 return SDOperand(); // No mulhu or equvialent
1783 Created->push_back(Q.Val);
1785 if (magics.a == 0) {
1786 return DAG.getNode(ISD::SRL, VT, Q,
1787 DAG.getConstant(magics.s, getShiftAmountTy()));
1789 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1791 Created->push_back(NPQ.Val);
1792 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1793 DAG.getConstant(1, getShiftAmountTy()));
1795 Created->push_back(NPQ.Val);
1796 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1798 Created->push_back(NPQ.Val);
1799 return DAG.getNode(ISD::SRL, VT, NPQ,
1800 DAG.getConstant(magics.s-1, getShiftAmountTy()));