1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetData.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/Support/MathExtras.h"
24 /// InitLibcallNames - Set default libcall names.
26 static void InitLibcallNames(const char **Names) {
27 Names[RTLIB::SHL_I32] = "__ashlsi3";
28 Names[RTLIB::SHL_I64] = "__ashldi3";
29 Names[RTLIB::SRL_I32] = "__lshrsi3";
30 Names[RTLIB::SRL_I64] = "__lshrdi3";
31 Names[RTLIB::SRA_I32] = "__ashrsi3";
32 Names[RTLIB::SRA_I64] = "__ashrdi3";
33 Names[RTLIB::MUL_I32] = "__mulsi3";
34 Names[RTLIB::MUL_I64] = "__muldi3";
35 Names[RTLIB::SDIV_I32] = "__divsi3";
36 Names[RTLIB::SDIV_I64] = "__divdi3";
37 Names[RTLIB::UDIV_I32] = "__udivsi3";
38 Names[RTLIB::UDIV_I64] = "__udivdi3";
39 Names[RTLIB::SREM_I32] = "__modsi3";
40 Names[RTLIB::SREM_I64] = "__moddi3";
41 Names[RTLIB::UREM_I32] = "__umodsi3";
42 Names[RTLIB::UREM_I64] = "__umoddi3";
43 Names[RTLIB::NEG_I32] = "__negsi2";
44 Names[RTLIB::NEG_I64] = "__negdi2";
45 Names[RTLIB::ADD_F32] = "__addsf3";
46 Names[RTLIB::ADD_F64] = "__adddf3";
47 Names[RTLIB::SUB_F32] = "__subsf3";
48 Names[RTLIB::SUB_F64] = "__subdf3";
49 Names[RTLIB::MUL_F32] = "__mulsf3";
50 Names[RTLIB::MUL_F64] = "__muldf3";
51 Names[RTLIB::DIV_F32] = "__divsf3";
52 Names[RTLIB::DIV_F64] = "__divdf3";
53 Names[RTLIB::REM_F32] = "fmodf";
54 Names[RTLIB::REM_F64] = "fmod";
55 Names[RTLIB::NEG_F32] = "__negsf2";
56 Names[RTLIB::NEG_F64] = "__negdf2";
57 Names[RTLIB::POWI_F32] = "__powisf2";
58 Names[RTLIB::POWI_F64] = "__powidf2";
59 Names[RTLIB::SQRT_F32] = "sqrtf";
60 Names[RTLIB::SQRT_F64] = "sqrt";
61 Names[RTLIB::SIN_F32] = "sinf";
62 Names[RTLIB::SIN_F64] = "sin";
63 Names[RTLIB::COS_F32] = "cosf";
64 Names[RTLIB::COS_F64] = "cos";
65 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
66 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
67 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
68 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
69 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
70 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
71 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
72 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
73 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
74 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
75 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
76 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
77 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
78 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
79 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
80 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
81 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
82 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
83 Names[RTLIB::OEQ_F32] = "__eqsf2";
84 Names[RTLIB::OEQ_F64] = "__eqdf2";
85 Names[RTLIB::UNE_F32] = "__nesf2";
86 Names[RTLIB::UNE_F64] = "__nedf2";
87 Names[RTLIB::OGE_F32] = "__gesf2";
88 Names[RTLIB::OGE_F64] = "__gedf2";
89 Names[RTLIB::OLT_F32] = "__ltsf2";
90 Names[RTLIB::OLT_F64] = "__ltdf2";
91 Names[RTLIB::OLE_F32] = "__lesf2";
92 Names[RTLIB::OLE_F64] = "__ledf2";
93 Names[RTLIB::OGT_F32] = "__gtsf2";
94 Names[RTLIB::OGT_F64] = "__gtdf2";
95 Names[RTLIB::UO_F32] = "__unordsf2";
96 Names[RTLIB::UO_F64] = "__unorddf2";
97 Names[RTLIB::O_F32] = "__unordsf2";
98 Names[RTLIB::O_F64] = "__unorddf2";
101 /// InitCmpLibcallCCs - Set default comparison libcall CC.
103 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
104 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
105 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
106 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
107 CCs[RTLIB::UNE_F32] = ISD::SETNE;
108 CCs[RTLIB::UNE_F64] = ISD::SETNE;
109 CCs[RTLIB::OGE_F32] = ISD::SETGE;
110 CCs[RTLIB::OGE_F64] = ISD::SETGE;
111 CCs[RTLIB::OLT_F32] = ISD::SETLT;
112 CCs[RTLIB::OLT_F64] = ISD::SETLT;
113 CCs[RTLIB::OLE_F32] = ISD::SETLE;
114 CCs[RTLIB::OLE_F64] = ISD::SETLE;
115 CCs[RTLIB::OGT_F32] = ISD::SETGT;
116 CCs[RTLIB::OGT_F64] = ISD::SETGT;
117 CCs[RTLIB::UO_F32] = ISD::SETNE;
118 CCs[RTLIB::UO_F64] = ISD::SETNE;
119 CCs[RTLIB::O_F32] = ISD::SETEQ;
120 CCs[RTLIB::O_F64] = ISD::SETEQ;
123 TargetLowering::TargetLowering(TargetMachine &tm)
124 : TM(tm), TD(TM.getTargetData()) {
125 assert(ISD::BUILTIN_OP_END <= 156 &&
126 "Fixed size array in TargetLowering is not large enough!");
127 // All operations default to being supported.
128 memset(OpActions, 0, sizeof(OpActions));
129 memset(LoadXActions, 0, sizeof(LoadXActions));
130 memset(&StoreXActions, 0, sizeof(StoreXActions));
131 // Initialize all indexed load / store to expand.
132 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
133 for (unsigned IM = (unsigned)ISD::PRE_INC;
134 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
135 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
136 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
140 IsLittleEndian = TD->isLittleEndian();
141 UsesGlobalOffsetTable = false;
142 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
143 ShiftAmtHandling = Undefined;
144 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
145 memset(TargetDAGCombineArray, 0,
146 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
147 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
148 allowUnalignedMemoryAccesses = false;
149 UseUnderscoreSetJmp = false;
150 UseUnderscoreLongJmp = false;
151 SelectIsExpensive = false;
152 IntDivIsCheap = false;
153 Pow2DivIsCheap = false;
154 StackPointerRegisterToSaveRestore = 0;
155 ExceptionPointerRegister = 0;
156 ExceptionSelectorRegister = 0;
157 SchedPreferenceInfo = SchedulingForLatency;
159 JumpBufAlignment = 0;
161 InitLibcallNames(LibcallRoutineNames);
162 InitCmpLibcallCCs(CmpLibcallCCs);
165 TargetLowering::~TargetLowering() {}
167 /// setValueTypeAction - Set the action for a particular value type. This
168 /// assumes an action has not already been set for this value type.
169 static void SetValueTypeAction(MVT::ValueType VT,
170 TargetLowering::LegalizeAction Action,
172 MVT::ValueType *TransformToType,
173 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
174 ValueTypeActions.setTypeAction(VT, Action);
175 if (Action == TargetLowering::Promote) {
176 MVT::ValueType PromoteTo;
178 PromoteTo = MVT::f64;
180 unsigned LargerReg = VT+1;
181 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
183 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
184 "Nothing to promote to??");
186 PromoteTo = (MVT::ValueType)LargerReg;
189 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
190 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
191 "Can only promote from int->int or fp->fp!");
192 assert(VT < PromoteTo && "Must promote to a larger type!");
193 TransformToType[VT] = PromoteTo;
194 } else if (Action == TargetLowering::Expand) {
195 // f32 and f64 is each expanded to corresponding integer type of same size.
197 TransformToType[VT] = MVT::i32;
198 else if (VT == MVT::f64)
199 TransformToType[VT] = MVT::i64;
201 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
202 "Cannot expand this type: target must support SOME integer reg!");
203 // Expand to the next smaller integer type!
204 TransformToType[VT] = (MVT::ValueType)(VT-1);
210 /// computeRegisterProperties - Once all of the register classes are added,
211 /// this allows us to compute derived properties we expose.
212 void TargetLowering::computeRegisterProperties() {
213 assert(MVT::LAST_VALUETYPE <= 32 &&
214 "Too many value types for ValueTypeActions to hold!");
216 // Everything defaults to one.
217 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
218 NumElementsForVT[i] = 1;
220 // Find the largest integer register class.
221 unsigned LargestIntReg = MVT::i128;
222 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
223 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
225 // Every integer value type larger than this largest register takes twice as
226 // many registers to represent as the previous ValueType.
227 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
228 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
229 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
231 // Inspect all of the ValueType's possible, deciding how to process them.
232 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
233 // If we are expanding this type, expand it!
234 if (getNumElements((MVT::ValueType)IntReg) != 1)
235 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
237 else if (!isTypeLegal((MVT::ValueType)IntReg))
238 // Otherwise, if we don't have native support, we must promote to a
240 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
241 TransformToType, ValueTypeActions);
243 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
245 // If the target does not have native F64 support, expand it to I64. We will
246 // be generating soft float library calls. If the target does not have native
247 // support for F32, promote it to F64 if it is legal. Otherwise, expand it to
249 if (isTypeLegal(MVT::f64))
250 TransformToType[MVT::f64] = MVT::f64;
252 NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64];
253 SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
256 if (isTypeLegal(MVT::f32))
257 TransformToType[MVT::f32] = MVT::f32;
258 else if (isTypeLegal(MVT::f64))
259 SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
262 NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32];
263 SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
267 // Set MVT::Vector to always be Expanded
268 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
271 // Loop over all of the legal vector value types, specifying an identity type
273 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
274 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
275 if (isTypeLegal((MVT::ValueType)i))
276 TransformToType[i] = (MVT::ValueType)i;
280 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
284 /// getVectorTypeBreakdown - Packed types are broken down into some number of
285 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32
286 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
288 /// This method returns the number and type of the resultant breakdown.
290 unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy,
291 MVT::ValueType &PTyElementVT,
292 MVT::ValueType &PTyLegalElementVT) const {
293 // Figure out the right, legal destination reg to copy into.
294 unsigned NumElts = PTy->getNumElements();
295 MVT::ValueType EltTy = getValueType(PTy->getElementType());
297 unsigned NumVectorRegs = 1;
299 // Divide the input until we get to a supported size. This will always
300 // end with a scalar if the target doesn't support vectors.
301 while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
306 MVT::ValueType VT = getVectorType(EltTy, NumElts);
307 if (!isTypeLegal(VT))
311 MVT::ValueType DestVT = getTypeToTransformTo(VT);
312 PTyLegalElementVT = DestVT;
314 // Value is expanded, e.g. i64 -> i16.
315 return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
317 // Otherwise, promotion or legal types use the same number of registers as
318 // the vector decimated to the appropriate level.
319 return NumVectorRegs;
325 //===----------------------------------------------------------------------===//
326 // Optimization Methods
327 //===----------------------------------------------------------------------===//
329 /// ShrinkDemandedConstant - Check to see if the specified operand of the
330 /// specified instruction is a constant integer. If so, check to see if there
331 /// are any bits set in the constant that are not demanded. If so, shrink the
332 /// constant and return true.
333 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
335 // FIXME: ISD::SELECT, ISD::SELECT_CC
336 switch(Op.getOpcode()) {
341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
342 if ((~Demanded & C->getValue()) != 0) {
343 MVT::ValueType VT = Op.getValueType();
344 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
345 DAG.getConstant(Demanded & C->getValue(),
347 return CombineTo(Op, New);
354 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
355 /// DemandedMask bits of the result of Op are ever used downstream. If we can
356 /// use this information to simplify Op, create a new simplified DAG node and
357 /// return true, returning the original and new nodes in Old and New. Otherwise,
358 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
359 /// the expression (used to simplify the caller). The KnownZero/One bits may
360 /// only be accurate for those bits in the DemandedMask.
361 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
364 TargetLoweringOpt &TLO,
365 unsigned Depth) const {
366 KnownZero = KnownOne = 0; // Don't know anything.
367 // Other users may use these bits.
368 if (!Op.Val->hasOneUse()) {
370 // If not at the root, Just compute the KnownZero/KnownOne bits to
371 // simplify things downstream.
372 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
375 // If this is the root being simplified, allow it to have multiple uses,
376 // just set the DemandedMask to all bits.
377 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
378 } else if (DemandedMask == 0) {
379 // Not demanding any bits from Op.
380 if (Op.getOpcode() != ISD::UNDEF)
381 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
383 } else if (Depth == 6) { // Limit search depth.
387 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
388 switch (Op.getOpcode()) {
390 // We know all of the bits for a constant!
391 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
392 KnownZero = ~KnownOne & DemandedMask;
393 return false; // Don't fall through, will infinitely loop.
395 // If the RHS is a constant, check to see if the LHS would be zero without
396 // using the bits from the RHS. Below, we use knowledge about the RHS to
397 // simplify the LHS, here we're using information from the LHS to simplify
399 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
400 uint64_t LHSZero, LHSOne;
401 ComputeMaskedBits(Op.getOperand(0), DemandedMask,
402 LHSZero, LHSOne, Depth+1);
403 // If the LHS already has zeros where RHSC does, this and is dead.
404 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
405 return TLO.CombineTo(Op, Op.getOperand(0));
406 // If any of the set bits in the RHS are known zero on the LHS, shrink
408 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
412 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
413 KnownOne, TLO, Depth+1))
415 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
416 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
417 KnownZero2, KnownOne2, TLO, Depth+1))
419 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
421 // If all of the demanded bits are known one on one side, return the other.
422 // These bits cannot contribute to the result of the 'and'.
423 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
424 return TLO.CombineTo(Op, Op.getOperand(0));
425 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
426 return TLO.CombineTo(Op, Op.getOperand(1));
427 // If all of the demanded bits in the inputs are known zeros, return zero.
428 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
429 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
430 // If the RHS is a constant, see if we can simplify it.
431 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
434 // Output known-1 bits are only known if set in both the LHS & RHS.
435 KnownOne &= KnownOne2;
436 // Output known-0 are known to be clear if zero in either the LHS | RHS.
437 KnownZero |= KnownZero2;
440 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
441 KnownOne, TLO, Depth+1))
443 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
444 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
445 KnownZero2, KnownOne2, TLO, Depth+1))
447 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
449 // If all of the demanded bits are known zero on one side, return the other.
450 // These bits cannot contribute to the result of the 'or'.
451 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
452 return TLO.CombineTo(Op, Op.getOperand(0));
453 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
454 return TLO.CombineTo(Op, Op.getOperand(1));
455 // If all of the potentially set bits on one side are known to be set on
456 // the other side, just use the 'other' side.
457 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
458 (DemandedMask & (~KnownZero)))
459 return TLO.CombineTo(Op, Op.getOperand(0));
460 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
461 (DemandedMask & (~KnownZero2)))
462 return TLO.CombineTo(Op, Op.getOperand(1));
463 // If the RHS is a constant, see if we can simplify it.
464 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
467 // Output known-0 bits are only known if clear in both the LHS & RHS.
468 KnownZero &= KnownZero2;
469 // Output known-1 are known to be set if set in either the LHS | RHS.
470 KnownOne |= KnownOne2;
473 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
474 KnownOne, TLO, Depth+1))
476 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
477 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
478 KnownOne2, TLO, Depth+1))
480 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
482 // If all of the demanded bits are known zero on one side, return the other.
483 // These bits cannot contribute to the result of the 'xor'.
484 if ((DemandedMask & KnownZero) == DemandedMask)
485 return TLO.CombineTo(Op, Op.getOperand(0));
486 if ((DemandedMask & KnownZero2) == DemandedMask)
487 return TLO.CombineTo(Op, Op.getOperand(1));
489 // If all of the unknown bits are known to be zero on one side or the other
490 // (but not both) turn this into an *inclusive* or.
491 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
492 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
493 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
497 // Output known-0 bits are known if clear or set in both the LHS & RHS.
498 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
499 // Output known-1 are known to be set if set in only one of the LHS, RHS.
500 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
502 // If all of the demanded bits on one side are known, and all of the set
503 // bits on that side are also known to be set on the other side, turn this
504 // into an AND, as we know the bits will be cleared.
505 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
506 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
507 if ((KnownOne & KnownOne2) == KnownOne) {
508 MVT::ValueType VT = Op.getValueType();
509 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
510 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
515 // If the RHS is a constant, see if we can simplify it.
516 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
517 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
520 KnownZero = KnownZeroOut;
521 KnownOne = KnownOneOut;
524 // If we know the result of a setcc has the top bits zero, use this info.
525 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
526 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
529 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
530 KnownOne, TLO, Depth+1))
532 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
533 KnownOne2, TLO, Depth+1))
535 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
536 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
538 // If the operands are constants, see if we can simplify them.
539 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
542 // Only known if known in both the LHS and RHS.
543 KnownOne &= KnownOne2;
544 KnownZero &= KnownZero2;
547 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
548 KnownOne, TLO, Depth+1))
550 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
551 KnownOne2, TLO, Depth+1))
553 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
554 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
556 // If the operands are constants, see if we can simplify them.
557 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
560 // Only known if known in both the LHS and RHS.
561 KnownOne &= KnownOne2;
562 KnownZero &= KnownZero2;
565 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
566 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
567 KnownZero, KnownOne, TLO, Depth+1))
569 KnownZero <<= SA->getValue();
570 KnownOne <<= SA->getValue();
571 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
575 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
576 MVT::ValueType VT = Op.getValueType();
577 unsigned ShAmt = SA->getValue();
579 // Compute the new bits that are at the top now.
580 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
581 if (SimplifyDemandedBits(Op.getOperand(0),
582 (DemandedMask << ShAmt) & TypeMask,
583 KnownZero, KnownOne, TLO, Depth+1))
585 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
586 KnownZero &= TypeMask;
587 KnownOne &= TypeMask;
591 uint64_t HighBits = (1ULL << ShAmt)-1;
592 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
593 KnownZero |= HighBits; // High bits known zero.
597 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
598 MVT::ValueType VT = Op.getValueType();
599 unsigned ShAmt = SA->getValue();
601 // Compute the new bits that are at the top now.
602 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
604 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
606 // If any of the demanded bits are produced by the sign extension, we also
607 // demand the input sign bit.
608 uint64_t HighBits = (1ULL << ShAmt)-1;
609 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
610 if (HighBits & DemandedMask)
611 InDemandedMask |= MVT::getIntVTSignBit(VT);
613 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
614 KnownZero, KnownOne, TLO, Depth+1))
616 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
617 KnownZero &= TypeMask;
618 KnownOne &= TypeMask;
622 // Handle the sign bits.
623 uint64_t SignBit = MVT::getIntVTSignBit(VT);
624 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
626 // If the input sign bit is known to be zero, or if none of the top bits
627 // are demanded, turn this into an unsigned shift right.
628 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
629 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
631 } else if (KnownOne & SignBit) { // New bits are known one.
632 KnownOne |= HighBits;
636 case ISD::SIGN_EXTEND_INREG: {
637 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
639 // Sign extension. Compute the demanded bits in the result that are not
640 // present in the input.
641 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
643 // If none of the extended bits are demanded, eliminate the sextinreg.
645 return TLO.CombineTo(Op, Op.getOperand(0));
647 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
648 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
650 // Since the sign extended bits are demanded, we know that the sign
652 InputDemandedBits |= InSignBit;
654 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
655 KnownZero, KnownOne, TLO, Depth+1))
657 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
659 // If the sign bit of the input is known set or clear, then we know the
660 // top bits of the result.
662 // If the input sign bit is known zero, convert this into a zero extension.
663 if (KnownZero & InSignBit)
664 return TLO.CombineTo(Op,
665 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
667 if (KnownOne & InSignBit) { // Input sign bit known set
669 KnownZero &= ~NewBits;
670 } else { // Input sign bit unknown
671 KnownZero &= ~NewBits;
672 KnownOne &= ~NewBits;
679 MVT::ValueType VT = Op.getValueType();
680 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
681 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
686 if (ISD::isZEXTLoad(Op.Val)) {
687 LoadSDNode *LD = cast<LoadSDNode>(Op);
688 MVT::ValueType VT = LD->getLoadedVT();
689 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
693 case ISD::ZERO_EXTEND: {
694 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
696 // If none of the top bits are demanded, convert this into an any_extend.
697 uint64_t NewBits = (~InMask) & DemandedMask;
699 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
703 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
704 KnownZero, KnownOne, TLO, Depth+1))
706 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
707 KnownZero |= NewBits;
710 case ISD::SIGN_EXTEND: {
711 MVT::ValueType InVT = Op.getOperand(0).getValueType();
712 uint64_t InMask = MVT::getIntVTBitMask(InVT);
713 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
714 uint64_t NewBits = (~InMask) & DemandedMask;
716 // If none of the top bits are demanded, convert this into an any_extend.
718 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
721 // Since some of the sign extended bits are demanded, we know that the sign
723 uint64_t InDemandedBits = DemandedMask & InMask;
724 InDemandedBits |= InSignBit;
726 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
727 KnownOne, TLO, Depth+1))
730 // If the sign bit is known zero, convert this to a zero extend.
731 if (KnownZero & InSignBit)
732 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
736 // If the sign bit is known one, the top bits match.
737 if (KnownOne & InSignBit) {
739 KnownZero &= ~NewBits;
740 } else { // Otherwise, top bits aren't known.
741 KnownOne &= ~NewBits;
742 KnownZero &= ~NewBits;
746 case ISD::ANY_EXTEND: {
747 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
748 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
749 KnownZero, KnownOne, TLO, Depth+1))
751 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
754 case ISD::TRUNCATE: {
755 // Simplify the input, using demanded bit information, and compute the known
756 // zero/one bits live out.
757 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
758 KnownZero, KnownOne, TLO, Depth+1))
761 // If the input is only used by this truncate, see if we can shrink it based
762 // on the known demanded bits.
763 if (Op.getOperand(0).Val->hasOneUse()) {
764 SDOperand In = Op.getOperand(0);
765 switch (In.getOpcode()) {
768 // Shrink SRL by a constant if none of the high bits shifted in are
770 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
771 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
772 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
773 HighBits >>= ShAmt->getValue();
775 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
776 (DemandedMask & HighBits) == 0) {
777 // None of the shifted in bits are needed. Add a truncate of the
778 // shift input, then shift it.
779 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
782 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
783 NewTrunc, In.getOperand(1)));
790 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
791 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
792 KnownZero &= OutMask;
796 case ISD::AssertZext: {
797 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
798 uint64_t InMask = MVT::getIntVTBitMask(VT);
799 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
800 KnownZero, KnownOne, TLO, Depth+1))
802 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
803 KnownZero |= ~InMask & DemandedMask;
808 case ISD::INTRINSIC_WO_CHAIN:
809 case ISD::INTRINSIC_W_CHAIN:
810 case ISD::INTRINSIC_VOID:
811 // Just use ComputeMaskedBits to compute output bits.
812 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
816 // If we know the value of all of the demanded bits, return this as a
818 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
819 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
824 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
825 /// this predicate to simplify operations downstream. Mask is known to be zero
826 /// for bits that V cannot have.
827 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
828 unsigned Depth) const {
829 uint64_t KnownZero, KnownOne;
830 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
831 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
832 return (KnownZero & Mask) == Mask;
835 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
836 /// known to be either zero or one and return them in the KnownZero/KnownOne
837 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
839 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
840 uint64_t &KnownZero, uint64_t &KnownOne,
841 unsigned Depth) const {
842 KnownZero = KnownOne = 0; // Don't know anything.
843 if (Depth == 6 || Mask == 0)
844 return; // Limit search depth.
846 uint64_t KnownZero2, KnownOne2;
848 switch (Op.getOpcode()) {
850 // We know all of the bits for a constant!
851 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
852 KnownZero = ~KnownOne & Mask;
855 // If either the LHS or the RHS are Zero, the result is zero.
856 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
858 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
859 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
860 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
862 // Output known-1 bits are only known if set in both the LHS & RHS.
863 KnownOne &= KnownOne2;
864 // Output known-0 are known to be clear if zero in either the LHS | RHS.
865 KnownZero |= KnownZero2;
868 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
870 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
871 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
872 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
874 // Output known-0 bits are only known if clear in both the LHS & RHS.
875 KnownZero &= KnownZero2;
876 // Output known-1 are known to be set if set in either the LHS | RHS.
877 KnownOne |= KnownOne2;
880 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
881 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
882 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
883 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
885 // Output known-0 bits are known if clear or set in both the LHS & RHS.
886 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
887 // Output known-1 are known to be set if set in only one of the LHS, RHS.
888 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
889 KnownZero = KnownZeroOut;
893 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
894 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
895 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
896 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
898 // Only known if known in both the LHS and RHS.
899 KnownOne &= KnownOne2;
900 KnownZero &= KnownZero2;
903 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
904 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
905 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
906 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
908 // Only known if known in both the LHS and RHS.
909 KnownOne &= KnownOne2;
910 KnownZero &= KnownZero2;
913 // If we know the result of a setcc has the top bits zero, use this info.
914 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
915 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
918 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
919 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
920 ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(),
921 KnownZero, KnownOne, Depth+1);
922 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
923 KnownZero <<= SA->getValue();
924 KnownOne <<= SA->getValue();
925 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
929 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
930 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
931 MVT::ValueType VT = Op.getValueType();
932 unsigned ShAmt = SA->getValue();
934 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
935 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask,
936 KnownZero, KnownOne, Depth+1);
937 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
938 KnownZero &= TypeMask;
939 KnownOne &= TypeMask;
943 uint64_t HighBits = (1ULL << ShAmt)-1;
944 HighBits <<= MVT::getSizeInBits(VT)-ShAmt;
945 KnownZero |= HighBits; // High bits known zero.
949 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
950 MVT::ValueType VT = Op.getValueType();
951 unsigned ShAmt = SA->getValue();
953 // Compute the new bits that are at the top now.
954 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
956 uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask;
957 // If any of the demanded bits are produced by the sign extension, we also
958 // demand the input sign bit.
959 uint64_t HighBits = (1ULL << ShAmt)-1;
960 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
962 InDemandedMask |= MVT::getIntVTSignBit(VT);
964 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne,
966 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
967 KnownZero &= TypeMask;
968 KnownOne &= TypeMask;
972 // Handle the sign bits.
973 uint64_t SignBit = MVT::getIntVTSignBit(VT);
974 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
976 if (KnownZero & SignBit) {
977 KnownZero |= HighBits; // New bits are known zero.
978 } else if (KnownOne & SignBit) {
979 KnownOne |= HighBits; // New bits are known one.
983 case ISD::SIGN_EXTEND_INREG: {
984 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
986 // Sign extension. Compute the demanded bits in the result that are not
987 // present in the input.
988 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask;
990 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
991 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT);
993 // If the sign extended bits are demanded, we know that the sign
996 InputDemandedBits |= InSignBit;
998 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
999 KnownZero, KnownOne, Depth+1);
1000 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1002 // If the sign bit of the input is known set or clear, then we know the
1003 // top bits of the result.
1004 if (KnownZero & InSignBit) { // Input sign bit known clear
1005 KnownZero |= NewBits;
1006 KnownOne &= ~NewBits;
1007 } else if (KnownOne & InSignBit) { // Input sign bit known set
1008 KnownOne |= NewBits;
1009 KnownZero &= ~NewBits;
1010 } else { // Input sign bit unknown
1011 KnownZero &= ~NewBits;
1012 KnownOne &= ~NewBits;
1019 MVT::ValueType VT = Op.getValueType();
1020 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
1021 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
1026 if (ISD::isZEXTLoad(Op.Val)) {
1027 LoadSDNode *LD = cast<LoadSDNode>(Op);
1028 MVT::ValueType VT = LD->getLoadedVT();
1029 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
1033 case ISD::ZERO_EXTEND: {
1034 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
1035 uint64_t NewBits = (~InMask) & Mask;
1036 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1038 KnownZero |= NewBits & Mask;
1039 KnownOne &= ~NewBits;
1042 case ISD::SIGN_EXTEND: {
1043 MVT::ValueType InVT = Op.getOperand(0).getValueType();
1044 unsigned InBits = MVT::getSizeInBits(InVT);
1045 uint64_t InMask = MVT::getIntVTBitMask(InVT);
1046 uint64_t InSignBit = 1ULL << (InBits-1);
1047 uint64_t NewBits = (~InMask) & Mask;
1048 uint64_t InDemandedBits = Mask & InMask;
1050 // If any of the sign extended bits are demanded, we know that the sign
1053 InDemandedBits |= InSignBit;
1055 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1057 // If the sign bit is known zero or one, the top bits match.
1058 if (KnownZero & InSignBit) {
1059 KnownZero |= NewBits;
1060 KnownOne &= ~NewBits;
1061 } else if (KnownOne & InSignBit) {
1062 KnownOne |= NewBits;
1063 KnownZero &= ~NewBits;
1064 } else { // Otherwise, top bits aren't known.
1065 KnownOne &= ~NewBits;
1066 KnownZero &= ~NewBits;
1070 case ISD::ANY_EXTEND: {
1071 MVT::ValueType VT = Op.getOperand(0).getValueType();
1072 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT),
1073 KnownZero, KnownOne, Depth+1);
1076 case ISD::TRUNCATE: {
1077 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1078 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1079 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
1080 KnownZero &= OutMask;
1081 KnownOne &= OutMask;
1084 case ISD::AssertZext: {
1085 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1086 uint64_t InMask = MVT::getIntVTBitMask(VT);
1087 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
1089 KnownZero |= (~InMask) & Mask;
1093 // If either the LHS or the RHS are Zero, the result is zero.
1094 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1095 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
1096 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1097 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1099 // Output known-0 bits are known if clear or set in both the low clear bits
1100 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
1101 // low 3 bits clear.
1102 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
1103 CountTrailingZeros_64(~KnownZero2));
1105 KnownZero = (1ULL << KnownZeroOut) - 1;
1110 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1113 // We know that the top bits of C-X are clear if X contains less bits
1114 // than C (i.e. no wrap-around can happen). For example, 20-X is
1115 // positive if we can prove that X is >= 0 and < 16.
1116 MVT::ValueType VT = CLHS->getValueType(0);
1117 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
1118 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
1119 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
1120 MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
1121 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
1123 // If all of the MaskV bits are known to be zero, then we know the output
1124 // top bits are zero, because we now know that the output is from [0-C].
1125 if ((KnownZero & MaskV) == MaskV) {
1126 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
1127 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
1128 KnownOne = 0; // No one bits known.
1130 KnownZero = KnownOne = 0; // Otherwise, nothing known.
1136 // Allow the target to implement this method for its nodes.
1137 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1138 case ISD::INTRINSIC_WO_CHAIN:
1139 case ISD::INTRINSIC_W_CHAIN:
1140 case ISD::INTRINSIC_VOID:
1141 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
1147 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1148 /// in Mask are known to be either zero or one and return them in the
1149 /// KnownZero/KnownOne bitsets.
1150 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1152 uint64_t &KnownZero,
1154 unsigned Depth) const {
1155 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1156 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1157 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1158 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1159 "Should use MaskedValueIsZero if you don't know whether Op"
1160 " is a target node!");
1165 /// ComputeNumSignBits - Return the number of times the sign bit of the
1166 /// register is replicated into the other bits. We know that at least 1 bit
1167 /// is always equal to the sign bit (itself), but other cases can give us
1168 /// information. For example, immediately after an "SRA X, 2", we know that
1169 /// the top 3 bits are all equal to each other, so we return 3.
1170 unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
1171 MVT::ValueType VT = Op.getValueType();
1172 assert(MVT::isInteger(VT) && "Invalid VT!");
1173 unsigned VTBits = MVT::getSizeInBits(VT);
1177 return 1; // Limit search depth.
1179 switch (Op.getOpcode()) {
1181 case ISD::AssertSext:
1182 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1183 return VTBits-Tmp+1;
1184 case ISD::AssertZext:
1185 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1188 case ISD::Constant: {
1189 uint64_t Val = cast<ConstantSDNode>(Op)->getValue();
1190 // If negative, invert the bits, then look at it.
1191 if (Val & MVT::getIntVTSignBit(VT))
1194 // Shift the bits so they are the leading bits in the int64_t.
1197 // Return # leading zeros. We use 'min' here in case Val was zero before
1198 // shifting. We don't want to return '64' as for an i32 "0".
1199 return std::min(VTBits, CountLeadingZeros_64(Val));
1202 case ISD::SIGN_EXTEND:
1203 Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType());
1204 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
1206 case ISD::SIGN_EXTEND_INREG:
1207 // Max of the input and what this extends.
1208 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1211 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1212 return std::max(Tmp, Tmp2);
1215 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1216 // SRA X, C -> adds C sign bits.
1217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1218 Tmp += C->getValue();
1219 if (Tmp > VTBits) Tmp = VTBits;
1223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1224 // shl destroys sign bits.
1225 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1226 if (C->getValue() >= VTBits || // Bad shift.
1227 C->getValue() >= Tmp) break; // Shifted all sign bits out.
1228 return Tmp - C->getValue();
1233 case ISD::XOR: // NOT is handled here.
1234 // Logical binary ops preserve the number of sign bits.
1235 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1236 if (Tmp == 1) return 1; // Early out.
1237 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1238 return std::min(Tmp, Tmp2);
1241 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1242 if (Tmp == 1) return 1; // Early out.
1243 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1244 return std::min(Tmp, Tmp2);
1247 // If setcc returns 0/-1, all bits are sign bits.
1248 if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult)
1253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1254 unsigned RotAmt = C->getValue() & (VTBits-1);
1256 // Handle rotate right by N like a rotate left by 32-N.
1257 if (Op.getOpcode() == ISD::ROTR)
1258 RotAmt = (VTBits-RotAmt) & (VTBits-1);
1260 // If we aren't rotating out all of the known-in sign bits, return the
1261 // number that are left. This handles rotl(sext(x), 1) for example.
1262 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1263 if (Tmp > RotAmt+1) return Tmp-RotAmt;
1267 // Add can have at most one carry bit. Thus we know that the output
1268 // is, at worst, one more bit than the inputs.
1269 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1270 if (Tmp == 1) return 1; // Early out.
1272 // Special case decrementing a value (ADD X, -1):
1273 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1274 if (CRHS->isAllOnesValue()) {
1275 uint64_t KnownZero, KnownOne;
1276 uint64_t Mask = MVT::getIntVTBitMask(VT);
1277 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1279 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1281 if ((KnownZero|1) == Mask)
1284 // If we are subtracting one from a positive number, there is no carry
1285 // out of the result.
1286 if (KnownZero & MVT::getIntVTSignBit(VT))
1290 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1291 if (Tmp2 == 1) return 1;
1292 return std::min(Tmp, Tmp2)-1;
1296 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1297 if (Tmp2 == 1) return 1;
1300 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
1301 if (CLHS->getValue() == 0) {
1302 uint64_t KnownZero, KnownOne;
1303 uint64_t Mask = MVT::getIntVTBitMask(VT);
1304 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
1305 // If the input is known to be 0 or 1, the output is 0/-1, which is all
1307 if ((KnownZero|1) == Mask)
1310 // If the input is known to be positive (the sign bit is known clear),
1311 // the output of the NEG has the same number of sign bits as the input.
1312 if (KnownZero & MVT::getIntVTSignBit(VT))
1315 // Otherwise, we treat this like a SUB.
1318 // Sub can have at most one carry bit. Thus we know that the output
1319 // is, at worst, one more bit than the inputs.
1320 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1321 if (Tmp == 1) return 1; // Early out.
1322 return std::min(Tmp, Tmp2)-1;
1325 // FIXME: it's tricky to do anything useful for this, but it is an important
1326 // case for targets like X86.
1330 // Handle LOADX separately here. EXTLOAD case will fallthrough.
1331 if (Op.getOpcode() == ISD::LOAD) {
1332 LoadSDNode *LD = cast<LoadSDNode>(Op);
1333 unsigned ExtType = LD->getExtensionType();
1336 case ISD::SEXTLOAD: // '17' bits known
1337 Tmp = MVT::getSizeInBits(LD->getLoadedVT());
1338 return VTBits-Tmp+1;
1339 case ISD::ZEXTLOAD: // '16' bits known
1340 Tmp = MVT::getSizeInBits(LD->getLoadedVT());
1345 // Allow the target to implement this method for its nodes.
1346 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1347 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1348 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1349 Op.getOpcode() == ISD::INTRINSIC_VOID) {
1350 unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth);
1351 if (NumBits > 1) return NumBits;
1354 // Finally, if we can prove that the top bits of the result are 0's or 1's,
1355 // use this information.
1356 uint64_t KnownZero, KnownOne;
1357 uint64_t Mask = MVT::getIntVTBitMask(VT);
1358 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
1360 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1361 if (KnownZero & SignBit) { // SignBit is 0
1363 } else if (KnownOne & SignBit) { // SignBit is 1;
1370 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine
1371 // the number of identical bits in the top of the input value.
1374 // Return # leading zeros. We use 'min' here in case Val was zero before
1375 // shifting. We don't want to return '64' as for an i32 "0".
1376 return std::min(VTBits, CountLeadingZeros_64(Mask));
1381 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1382 /// targets that want to expose additional information about sign bits to the
1384 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1385 unsigned Depth) const {
1386 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1387 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1388 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1389 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1390 "Should use ComputeNumSignBits if you don't know whether Op"
1391 " is a target node!");
1396 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1397 /// and cc. If it is unable to simplify it, return a null SDOperand.
1399 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
1400 ISD::CondCode Cond, bool foldBooleans,
1401 DAGCombinerInfo &DCI) const {
1402 SelectionDAG &DAG = DCI.DAG;
1404 // These setcc operations always fold.
1408 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1410 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1413 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1414 uint64_t C1 = N1C->getValue();
1415 if (isa<ConstantSDNode>(N0.Val)) {
1416 return DAG.FoldSetCC(VT, N0, N1, Cond);
1418 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1419 // equality comparison, then we're just comparing whether X itself is
1421 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1422 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1423 N0.getOperand(1).getOpcode() == ISD::Constant) {
1424 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1425 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1426 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
1427 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1428 // (srl (ctlz x), 5) == 0 -> X != 0
1429 // (srl (ctlz x), 5) != 1 -> X != 0
1432 // (srl (ctlz x), 5) != 0 -> X == 0
1433 // (srl (ctlz x), 5) == 1 -> X == 0
1436 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
1437 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
1442 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1443 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1444 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1446 // If the comparison constant has bits in the upper part, the
1447 // zero-extended value could never match.
1448 if (C1 & (~0ULL << InSize)) {
1449 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1453 case ISD::SETEQ: return DAG.getConstant(0, VT);
1456 case ISD::SETNE: return DAG.getConstant(1, VT);
1459 // True if the sign bit of C1 is set.
1460 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
1463 // True if the sign bit of C1 isn't set.
1464 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
1470 // Otherwise, we can perform the comparison with the low bits.
1478 return DAG.getSetCC(VT, N0.getOperand(0),
1479 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1482 break; // todo, be more careful with signed comparisons
1484 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1485 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1486 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1487 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1488 MVT::ValueType ExtDstTy = N0.getValueType();
1489 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1491 // If the extended part has any inconsistent bits, it cannot ever
1492 // compare equal. In other words, they have to be all ones or all
1495 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1496 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1497 return DAG.getConstant(Cond == ISD::SETNE, VT);
1500 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1501 if (Op0Ty == ExtSrcTy) {
1502 ZextOp = N0.getOperand(0);
1504 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1505 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1506 DAG.getConstant(Imm, Op0Ty));
1508 if (!DCI.isCalledByLegalizer())
1509 DCI.AddToWorklist(ZextOp.Val);
1510 // Otherwise, make this a use of a zext.
1511 return DAG.getSetCC(VT, ZextOp,
1512 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1515 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1516 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1518 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1519 if (N0.getOpcode() == ISD::SETCC) {
1520 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1524 // Invert the condition.
1525 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1526 CC = ISD::getSetCCInverse(CC,
1527 MVT::isInteger(N0.getOperand(0).getValueType()));
1528 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1531 if ((N0.getOpcode() == ISD::XOR ||
1532 (N0.getOpcode() == ISD::AND &&
1533 N0.getOperand(0).getOpcode() == ISD::XOR &&
1534 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1535 isa<ConstantSDNode>(N0.getOperand(1)) &&
1536 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1537 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1538 // can only do this if the top bits are known zero.
1539 if (MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){
1540 // Okay, get the un-inverted input value.
1542 if (N0.getOpcode() == ISD::XOR)
1543 Val = N0.getOperand(0);
1545 assert(N0.getOpcode() == ISD::AND &&
1546 N0.getOperand(0).getOpcode() == ISD::XOR);
1547 // ((X^1)&1)^1 -> X & 1
1548 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1549 N0.getOperand(0).getOperand(0),
1552 return DAG.getSetCC(VT, Val, N1,
1553 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1558 uint64_t MinVal, MaxVal;
1559 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1560 if (ISD::isSignedIntSetCC(Cond)) {
1561 MinVal = 1ULL << (OperandBitSize-1);
1562 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1563 MaxVal = ~0ULL >> (65-OperandBitSize);
1568 MaxVal = ~0ULL >> (64-OperandBitSize);
1571 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1572 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1573 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1574 --C1; // X >= C0 --> X > (C0-1)
1575 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1576 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1579 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1580 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1581 ++C1; // X <= C0 --> X < (C0+1)
1582 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1583 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1586 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1587 return DAG.getConstant(0, VT); // X < MIN --> false
1588 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1589 return DAG.getConstant(1, VT); // X >= MIN --> true
1590 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1591 return DAG.getConstant(0, VT); // X > MAX --> false
1592 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1593 return DAG.getConstant(1, VT); // X <= MAX --> true
1595 // Canonicalize setgt X, Min --> setne X, Min
1596 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1597 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1598 // Canonicalize setlt X, Max --> setne X, Max
1599 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1600 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1602 // If we have setult X, 1, turn it into seteq X, 0
1603 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1604 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1606 // If we have setugt X, Max-1, turn it into seteq X, Max
1607 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1608 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1611 // If we have "setcc X, C0", check to see if we can shrink the immediate
1614 // SETUGT X, SINTMAX -> SETLT X, 0
1615 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1616 C1 == (~0ULL >> (65-OperandBitSize)))
1617 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1620 // FIXME: Implement the rest of these.
1622 // Fold bit comparisons when we can.
1623 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1624 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1625 if (ConstantSDNode *AndRHS =
1626 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1627 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1628 // Perform the xform if the AND RHS is a single bit.
1629 if (isPowerOf2_64(AndRHS->getValue())) {
1630 return DAG.getNode(ISD::SRL, VT, N0,
1631 DAG.getConstant(Log2_64(AndRHS->getValue()),
1632 getShiftAmountTy()));
1634 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1635 // (X & 8) == 8 --> (X & 8) >> 3
1636 // Perform the xform if C1 is a single bit.
1637 if (isPowerOf2_64(C1)) {
1638 return DAG.getNode(ISD::SRL, VT, N0,
1639 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1644 } else if (isa<ConstantSDNode>(N0.Val)) {
1645 // Ensure that the constant occurs on the RHS.
1646 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1649 if (isa<ConstantFPSDNode>(N0.Val)) {
1650 // Constant fold or commute setcc.
1651 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1652 if (O.Val) return O;
1656 // We can always fold X == X for integer setcc's.
1657 if (MVT::isInteger(N0.getValueType()))
1658 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1659 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1660 if (UOF == 2) // FP operators that are undefined on NaNs.
1661 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1662 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1663 return DAG.getConstant(UOF, VT);
1664 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1665 // if it is not already.
1666 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1667 if (NewCond != Cond)
1668 return DAG.getSetCC(VT, N0, N1, NewCond);
1671 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1672 MVT::isInteger(N0.getValueType())) {
1673 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1674 N0.getOpcode() == ISD::XOR) {
1675 // Simplify (X+Y) == (X+Z) --> Y == Z
1676 if (N0.getOpcode() == N1.getOpcode()) {
1677 if (N0.getOperand(0) == N1.getOperand(0))
1678 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1679 if (N0.getOperand(1) == N1.getOperand(1))
1680 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1681 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1682 // If X op Y == Y op X, try other combinations.
1683 if (N0.getOperand(0) == N1.getOperand(1))
1684 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1685 if (N0.getOperand(1) == N1.getOperand(0))
1686 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1690 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1691 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1692 // Turn (X+C1) == C2 --> X == C2-C1
1693 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1694 return DAG.getSetCC(VT, N0.getOperand(0),
1695 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1696 N0.getValueType()), Cond);
1699 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1700 if (N0.getOpcode() == ISD::XOR)
1701 // If we know that all of the inverted bits are zero, don't bother
1702 // performing the inversion.
1703 if (MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1704 return DAG.getSetCC(VT, N0.getOperand(0),
1705 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1706 N0.getValueType()), Cond);
1709 // Turn (C1-X) == C2 --> X == C1-C2
1710 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1711 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1712 return DAG.getSetCC(VT, N0.getOperand(1),
1713 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1714 N0.getValueType()), Cond);
1719 // Simplify (X+Z) == X --> Z == 0
1720 if (N0.getOperand(0) == N1)
1721 return DAG.getSetCC(VT, N0.getOperand(1),
1722 DAG.getConstant(0, N0.getValueType()), Cond);
1723 if (N0.getOperand(1) == N1) {
1724 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1725 return DAG.getSetCC(VT, N0.getOperand(0),
1726 DAG.getConstant(0, N0.getValueType()), Cond);
1728 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1729 // (Z-X) == X --> Z == X<<1
1730 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1732 DAG.getConstant(1, getShiftAmountTy()));
1733 if (!DCI.isCalledByLegalizer())
1734 DCI.AddToWorklist(SH.Val);
1735 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1740 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1741 N1.getOpcode() == ISD::XOR) {
1742 // Simplify X == (X+Z) --> Z == 0
1743 if (N1.getOperand(0) == N0) {
1744 return DAG.getSetCC(VT, N1.getOperand(1),
1745 DAG.getConstant(0, N1.getValueType()), Cond);
1746 } else if (N1.getOperand(1) == N0) {
1747 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1748 return DAG.getSetCC(VT, N1.getOperand(0),
1749 DAG.getConstant(0, N1.getValueType()), Cond);
1751 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1752 // X == (Z-X) --> X<<1 == Z
1753 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1754 DAG.getConstant(1, getShiftAmountTy()));
1755 if (!DCI.isCalledByLegalizer())
1756 DCI.AddToWorklist(SH.Val);
1757 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1763 // Fold away ALL boolean setcc's.
1765 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1767 default: assert(0 && "Unknown integer setcc!");
1768 case ISD::SETEQ: // X == Y -> (X^Y)^1
1769 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1770 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1771 if (!DCI.isCalledByLegalizer())
1772 DCI.AddToWorklist(Temp.Val);
1774 case ISD::SETNE: // X != Y --> (X^Y)
1775 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1777 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1778 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1779 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1780 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1781 if (!DCI.isCalledByLegalizer())
1782 DCI.AddToWorklist(Temp.Val);
1784 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1785 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1786 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1787 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1788 if (!DCI.isCalledByLegalizer())
1789 DCI.AddToWorklist(Temp.Val);
1791 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1792 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1793 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1794 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1795 if (!DCI.isCalledByLegalizer())
1796 DCI.AddToWorklist(Temp.Val);
1798 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1799 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1800 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1801 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1804 if (VT != MVT::i1) {
1805 if (!DCI.isCalledByLegalizer())
1806 DCI.AddToWorklist(N0.Val);
1807 // FIXME: If running after legalize, we probably can't do this.
1808 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1813 // Could not fold it.
1817 SDOperand TargetLowering::
1818 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1819 // Default implementation: no optimization.
1823 //===----------------------------------------------------------------------===//
1824 // Inline Assembler Implementation Methods
1825 //===----------------------------------------------------------------------===//
1827 TargetLowering::ConstraintType
1828 TargetLowering::getConstraintType(const std::string &Constraint) const {
1829 // FIXME: lots more standard ones to handle.
1830 if (Constraint.size() == 1) {
1831 switch (Constraint[0]) {
1833 case 'r': return C_RegisterClass;
1835 case 'o': // offsetable
1836 case 'V': // not offsetable
1838 case 'i': // Simple Integer or Relocatable Constant
1839 case 'n': // Simple Integer
1840 case 's': // Relocatable Constant
1841 case 'X': // Allow ANY value.
1842 case 'I': // Target registers.
1854 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1855 Constraint[Constraint.size()-1] == '}')
1860 /// isOperandValidForConstraint - Return the specified operand (possibly
1861 /// modified) if the specified SDOperand is valid for the specified target
1862 /// constraint letter, otherwise return null.
1863 SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op,
1864 char ConstraintLetter,
1865 SelectionDAG &DAG) {
1866 switch (ConstraintLetter) {
1868 case 'i': // Simple Integer or Relocatable Constant
1869 case 'n': // Simple Integer
1870 case 's': // Relocatable Constant
1871 case 'X': // Allows any operand.
1872 // These are okay if the operand is either a global variable address or a
1873 // simple immediate value. If we have one of these, map to the TargetXXX
1874 // version so that the value itself doesn't get selected.
1875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1876 // Simple constants are not allowed for 's'.
1877 if (ConstraintLetter != 's')
1878 return DAG.getTargetConstant(C->getValue(), Op.getValueType());
1880 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
1881 if (ConstraintLetter != 'n')
1882 return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(),
1887 return SDOperand(0,0);
1890 std::vector<unsigned> TargetLowering::
1891 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1892 MVT::ValueType VT) const {
1893 return std::vector<unsigned>();
1897 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1898 getRegForInlineAsmConstraint(const std::string &Constraint,
1899 MVT::ValueType VT) const {
1900 if (Constraint[0] != '{')
1901 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1902 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1904 // Remove the braces from around the name.
1905 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1907 // Figure out which register class contains this reg.
1908 const MRegisterInfo *RI = TM.getRegisterInfo();
1909 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1910 E = RI->regclass_end(); RCI != E; ++RCI) {
1911 const TargetRegisterClass *RC = *RCI;
1913 // If none of the the value types for this register class are valid, we
1914 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1915 bool isLegal = false;
1916 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1918 if (isTypeLegal(*I)) {
1924 if (!isLegal) continue;
1926 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1928 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1929 return std::make_pair(*I, RC);
1933 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1936 //===----------------------------------------------------------------------===//
1937 // Loop Strength Reduction hooks
1938 //===----------------------------------------------------------------------===//
1940 /// isLegalAddressingMode - Return true if the addressing mode represented
1941 /// by AM is legal for this target, for a load/store of the specified type.
1942 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1943 const Type *Ty) const {
1944 // The default implementation of this implements a conservative RISCy, r+r and
1947 // Allows a sign-extended 16-bit immediate field.
1948 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1951 // No global is ever allowed as a base.
1955 // Only support r+r,
1957 case 0: // "r+i" or just "i", depending on HasBaseReg.
1960 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1962 // Otherwise we have r+r or r+i.
1965 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1967 // Allow 2*r as r+r.
1974 // Magic for divide replacement
1977 int64_t m; // magic number
1978 int64_t s; // shift amount
1982 uint64_t m; // magic number
1983 int64_t a; // add indicator
1984 int64_t s; // shift amount
1987 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1988 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1990 static ms magic32(int32_t d) {
1992 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1993 const uint32_t two31 = 0x80000000U;
1997 t = two31 + ((uint32_t)d >> 31);
1998 anc = t - 1 - t%ad; // absolute value of nc
1999 p = 31; // initialize p
2000 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
2001 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
2002 q2 = two31/ad; // initialize q2 = 2p/abs(d)
2003 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
2006 q1 = 2*q1; // update q1 = 2p/abs(nc)
2007 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
2008 if (r1 >= anc) { // must be unsigned comparison
2012 q2 = 2*q2; // update q2 = 2p/abs(d)
2013 r2 = 2*r2; // update r2 = rem(2p/abs(d))
2014 if (r2 >= ad) { // must be unsigned comparison
2019 } while (q1 < delta || (q1 == delta && r1 == 0));
2021 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
2022 if (d < 0) mag.m = -mag.m; // resulting magic number
2023 mag.s = p - 32; // resulting shift
2027 /// magicu - calculate the magic numbers required to codegen an integer udiv as
2028 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
2029 static mu magicu32(uint32_t d) {
2031 uint32_t nc, delta, q1, r1, q2, r2;
2033 magu.a = 0; // initialize "add" indicator
2035 p = 31; // initialize p
2036 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
2037 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
2038 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
2039 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
2042 if (r1 >= nc - r1 ) {
2043 q1 = 2*q1 + 1; // update q1
2044 r1 = 2*r1 - nc; // update r1
2047 q1 = 2*q1; // update q1
2048 r1 = 2*r1; // update r1
2050 if (r2 + 1 >= d - r2) {
2051 if (q2 >= 0x7FFFFFFF) magu.a = 1;
2052 q2 = 2*q2 + 1; // update q2
2053 r2 = 2*r2 + 1 - d; // update r2
2056 if (q2 >= 0x80000000) magu.a = 1;
2057 q2 = 2*q2; // update q2
2058 r2 = 2*r2 + 1; // update r2
2061 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
2062 magu.m = q2 + 1; // resulting magic number
2063 magu.s = p - 32; // resulting shift
2067 /// magic - calculate the magic numbers required to codegen an integer sdiv as
2068 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
2070 static ms magic64(int64_t d) {
2072 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
2073 const uint64_t two63 = 9223372036854775808ULL; // 2^63
2076 ad = d >= 0 ? d : -d;
2077 t = two63 + ((uint64_t)d >> 63);
2078 anc = t - 1 - t%ad; // absolute value of nc
2079 p = 63; // initialize p
2080 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
2081 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
2082 q2 = two63/ad; // initialize q2 = 2p/abs(d)
2083 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
2086 q1 = 2*q1; // update q1 = 2p/abs(nc)
2087 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
2088 if (r1 >= anc) { // must be unsigned comparison
2092 q2 = 2*q2; // update q2 = 2p/abs(d)
2093 r2 = 2*r2; // update r2 = rem(2p/abs(d))
2094 if (r2 >= ad) { // must be unsigned comparison
2099 } while (q1 < delta || (q1 == delta && r1 == 0));
2102 if (d < 0) mag.m = -mag.m; // resulting magic number
2103 mag.s = p - 64; // resulting shift
2107 /// magicu - calculate the magic numbers required to codegen an integer udiv as
2108 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
2109 static mu magicu64(uint64_t d)
2112 uint64_t nc, delta, q1, r1, q2, r2;
2114 magu.a = 0; // initialize "add" indicator
2116 p = 63; // initialize p
2117 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
2118 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
2119 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
2120 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
2123 if (r1 >= nc - r1 ) {
2124 q1 = 2*q1 + 1; // update q1
2125 r1 = 2*r1 - nc; // update r1
2128 q1 = 2*q1; // update q1
2129 r1 = 2*r1; // update r1
2131 if (r2 + 1 >= d - r2) {
2132 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
2133 q2 = 2*q2 + 1; // update q2
2134 r2 = 2*r2 + 1 - d; // update r2
2137 if (q2 >= 0x8000000000000000ull) magu.a = 1;
2138 q2 = 2*q2; // update q2
2139 r2 = 2*r2 + 1; // update r2
2142 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
2143 magu.m = q2 + 1; // resulting magic number
2144 magu.s = p - 64; // resulting shift
2148 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2149 /// return a DAG expression to select that will generate the same value by
2150 /// multiplying by a magic number. See:
2151 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2152 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2153 std::vector<SDNode*>* Created) const {
2154 MVT::ValueType VT = N->getValueType(0);
2156 // Check to see if we can do this.
2157 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2158 return SDOperand(); // BuildSDIV only operates on i32 or i64
2159 if (!isOperationLegal(ISD::MULHS, VT))
2160 return SDOperand(); // Make sure the target supports MULHS.
2162 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2163 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2165 // Multiply the numerator (operand 0) by the magic value
2166 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2167 DAG.getConstant(magics.m, VT));
2168 // If d > 0 and m < 0, add the numerator
2169 if (d > 0 && magics.m < 0) {
2170 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2172 Created->push_back(Q.Val);
2174 // If d < 0 and m > 0, subtract the numerator.
2175 if (d < 0 && magics.m > 0) {
2176 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2178 Created->push_back(Q.Val);
2180 // Shift right algebraic if shift value is nonzero
2182 Q = DAG.getNode(ISD::SRA, VT, Q,
2183 DAG.getConstant(magics.s, getShiftAmountTy()));
2185 Created->push_back(Q.Val);
2187 // Extract the sign bit and add it to the quotient
2189 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2190 getShiftAmountTy()));
2192 Created->push_back(T.Val);
2193 return DAG.getNode(ISD::ADD, VT, Q, T);
2196 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2197 /// return a DAG expression to select that will generate the same value by
2198 /// multiplying by a magic number. See:
2199 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2200 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2201 std::vector<SDNode*>* Created) const {
2202 MVT::ValueType VT = N->getValueType(0);
2204 // Check to see if we can do this.
2205 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2206 return SDOperand(); // BuildUDIV only operates on i32 or i64
2207 if (!isOperationLegal(ISD::MULHU, VT))
2208 return SDOperand(); // Make sure the target supports MULHU.
2210 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2211 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2213 // Multiply the numerator (operand 0) by the magic value
2214 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2215 DAG.getConstant(magics.m, VT));
2217 Created->push_back(Q.Val);
2219 if (magics.a == 0) {
2220 return DAG.getNode(ISD::SRL, VT, Q,
2221 DAG.getConstant(magics.s, getShiftAmountTy()));
2223 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2225 Created->push_back(NPQ.Val);
2226 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2227 DAG.getConstant(1, getShiftAmountTy()));
2229 Created->push_back(NPQ.Val);
2230 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2232 Created->push_back(NPQ.Val);
2233 return DAG.getNode(ISD::SRL, VT, NPQ,
2234 DAG.getConstant(magics.s-1, getShiftAmountTy()));