1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Target/TargetLoweringObjectFile.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
36 /// NOTE: The constructor takes ownership of TLOF.
37 TargetLowering::TargetLowering(const TargetMachine &tm,
38 const TargetLoweringObjectFile *tlof)
39 : TargetLoweringBase(tm, tlof) {}
41 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
45 /// Check whether a given call node is in tail position within its function. If
46 /// so, it sets Chain to the input chain of the tail call.
47 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
48 SDValue &Chain) const {
49 const Function *F = DAG.getMachineFunction().getFunction();
51 // Conservatively require the attributes of the call to match those of
52 // the return. Ignore noalias because it doesn't affect the call sequence.
53 AttributeSet CallerAttrs = F->getAttributes();
54 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
55 .removeAttribute(Attribute::NoAlias).hasAttributes())
58 // It's not safe to eliminate the sign / zero extension of the return value.
59 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
60 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
63 // Check if the only use is a function return node.
64 return isUsedByReturnOnly(Node, Chain);
68 /// Generate a libcall taking the given operands as arguments and returning a
69 /// result of type RetVT.
70 SDValue TargetLowering::makeLibCall(SelectionDAG &DAG,
71 RTLIB::Libcall LC, EVT RetVT,
72 const SDValue *Ops, unsigned NumOps,
73 bool isSigned, SDLoc dl) const {
74 TargetLowering::ArgListTy Args;
77 TargetLowering::ArgListEntry Entry;
78 for (unsigned i = 0; i != NumOps; ++i) {
80 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
81 Entry.isSExt = isSigned;
82 Entry.isZExt = !isSigned;
83 Args.push_back(Entry);
85 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
87 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
89 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
90 false, 0, getLibcallCallingConv(LC),
92 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
93 Callee, Args, DAG, dl);
94 std::pair<SDValue,SDValue> CallInfo = LowerCallTo(CLI);
96 return CallInfo.first;
100 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
101 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
102 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
103 SDValue &NewLHS, SDValue &NewRHS,
104 ISD::CondCode &CCCode,
106 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
107 && "Unsupported setcc type!");
109 // Expand into one or more soft-fp libcall(s).
110 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
114 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
115 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
119 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
120 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
124 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
125 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
129 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
130 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
134 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
135 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
139 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
140 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
143 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
144 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
147 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
148 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
151 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
152 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
155 // SETONE = SETOLT | SETOGT
156 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
157 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
160 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
161 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
164 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
165 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
168 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
169 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
172 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
173 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
176 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
177 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
179 default: llvm_unreachable("Do not know how to soften this setcc!");
183 // Use the target specific return value for comparions lib calls.
184 EVT RetVT = getCmpLibcallReturnType();
185 SDValue Ops[2] = { NewLHS, NewRHS };
186 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
187 NewRHS = DAG.getConstant(0, RetVT);
188 CCCode = getCmpLibcallCC(LC1);
189 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
191 getSetCCResultType(*DAG.getContext(), RetVT),
192 NewLHS, NewRHS, DAG.getCondCode(CCCode));
193 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
194 NewLHS = DAG.getNode(ISD::SETCC, dl,
195 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
196 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
197 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
202 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
203 /// current function. The returned value is a member of the
204 /// MachineJumpTableInfo::JTEntryKind enum.
205 unsigned TargetLowering::getJumpTableEncoding() const {
206 // In non-pic modes, just use the address of a block.
207 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
208 return MachineJumpTableInfo::EK_BlockAddress;
210 // In PIC mode, if the target supports a GPRel32 directive, use it.
211 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
212 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
214 // Otherwise, use a label difference.
215 return MachineJumpTableInfo::EK_LabelDifference32;
218 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
219 SelectionDAG &DAG) const {
220 // If our PIC model is GP relative, use the global offset table as the base.
221 unsigned JTEncoding = getJumpTableEncoding();
223 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
224 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
225 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
230 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
231 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
234 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
235 unsigned JTI,MCContext &Ctx) const{
236 // The normal PIC reloc base is the label at the start of the jump table.
237 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
241 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
242 // Assume that everything is safe in static mode.
243 if (getTargetMachine().getRelocationModel() == Reloc::Static)
246 // In dynamic-no-pic mode, assume that known defined values are safe.
247 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
249 !GA->getGlobal()->isDeclaration() &&
250 !GA->getGlobal()->isWeakForLinker())
253 // Otherwise assume nothing is safe.
257 //===----------------------------------------------------------------------===//
258 // Optimization Methods
259 //===----------------------------------------------------------------------===//
261 /// ShrinkDemandedConstant - Check to see if the specified operand of the
262 /// specified instruction is a constant integer. If so, check to see if there
263 /// are any bits set in the constant that are not demanded. If so, shrink the
264 /// constant and return true.
265 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
266 const APInt &Demanded) {
269 // FIXME: ISD::SELECT, ISD::SELECT_CC
270 switch (Op.getOpcode()) {
275 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
276 if (!C) return false;
278 if (Op.getOpcode() == ISD::XOR &&
279 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
282 // if we can expand it to have all bits set, do it
283 if (C->getAPIntValue().intersects(~Demanded)) {
284 EVT VT = Op.getValueType();
285 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
286 DAG.getConstant(Demanded &
289 return CombineTo(Op, New);
299 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
300 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
301 /// cast, but it could be generalized for targets with other types of
302 /// implicit widening casts.
304 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
306 const APInt &Demanded,
308 assert(Op.getNumOperands() == 2 &&
309 "ShrinkDemandedOp only supports binary operators!");
310 assert(Op.getNode()->getNumValues() == 1 &&
311 "ShrinkDemandedOp only supports nodes with one result!");
313 // Don't do this if the node has another user, which may require the
315 if (!Op.getNode()->hasOneUse())
318 // Search for the smallest integer type with free casts to and from
319 // Op's type. For expedience, just check power-of-2 integer types.
320 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
321 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
322 unsigned SmallVTBits = DemandedSize;
323 if (!isPowerOf2_32(SmallVTBits))
324 SmallVTBits = NextPowerOf2(SmallVTBits);
325 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
326 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
327 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
328 TLI.isZExtFree(SmallVT, Op.getValueType())) {
329 // We found a type with free casts.
330 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
331 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
332 Op.getNode()->getOperand(0)),
333 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
334 Op.getNode()->getOperand(1)));
335 bool NeedZext = DemandedSize > SmallVTBits;
336 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
337 dl, Op.getValueType(), X);
338 return CombineTo(Op, Z);
344 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
345 /// DemandedMask bits of the result of Op are ever used downstream. If we can
346 /// use this information to simplify Op, create a new simplified DAG node and
347 /// return true, returning the original and new nodes in Old and New. Otherwise,
348 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
349 /// the expression (used to simplify the caller). The KnownZero/One bits may
350 /// only be accurate for those bits in the DemandedMask.
351 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
352 const APInt &DemandedMask,
355 TargetLoweringOpt &TLO,
356 unsigned Depth) const {
357 unsigned BitWidth = DemandedMask.getBitWidth();
358 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
359 "Mask size mismatches value type size!");
360 APInt NewMask = DemandedMask;
363 // Don't know anything.
364 KnownZero = KnownOne = APInt(BitWidth, 0);
366 // Other users may use these bits.
367 if (!Op.getNode()->hasOneUse()) {
369 // If not at the root, Just compute the KnownZero/KnownOne bits to
370 // simplify things downstream.
371 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
374 // If this is the root being simplified, allow it to have multiple uses,
375 // just set the NewMask to all bits.
376 NewMask = APInt::getAllOnesValue(BitWidth);
377 } else if (DemandedMask == 0) {
378 // Not demanding any bits from Op.
379 if (Op.getOpcode() != ISD::UNDEF)
380 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
382 } else if (Depth == 6) { // Limit search depth.
386 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
387 switch (Op.getOpcode()) {
389 // We know all of the bits for a constant!
390 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
391 KnownZero = ~KnownOne;
392 return false; // Don't fall through, will infinitely loop.
394 // If the RHS is a constant, check to see if the LHS would be zero without
395 // using the bits from the RHS. Below, we use knowledge about the RHS to
396 // simplify the LHS, here we're using information from the LHS to simplify
398 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
399 APInt LHSZero, LHSOne;
400 // Do not increment Depth here; that can cause an infinite loop.
401 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
402 // If the LHS already has zeros where RHSC does, this and is dead.
403 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
404 return TLO.CombineTo(Op, Op.getOperand(0));
405 // If any of the set bits in the RHS are known zero on the LHS, shrink
407 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
411 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
412 KnownOne, TLO, Depth+1))
414 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
415 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
416 KnownZero2, KnownOne2, TLO, Depth+1))
418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
420 // If all of the demanded bits are known one on one side, return the other.
421 // These bits cannot contribute to the result of the 'and'.
422 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
423 return TLO.CombineTo(Op, Op.getOperand(0));
424 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
425 return TLO.CombineTo(Op, Op.getOperand(1));
426 // If all of the demanded bits in the inputs are known zeros, return zero.
427 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
428 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
429 // If the RHS is a constant, see if we can simplify it.
430 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
432 // If the operation can be done in a smaller type, do so.
433 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
436 // Output known-1 bits are only known if set in both the LHS & RHS.
437 KnownOne &= KnownOne2;
438 // Output known-0 are known to be clear if zero in either the LHS | RHS.
439 KnownZero |= KnownZero2;
442 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
443 KnownOne, TLO, Depth+1))
445 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
446 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
447 KnownZero2, KnownOne2, TLO, Depth+1))
449 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
451 // If all of the demanded bits are known zero on one side, return the other.
452 // These bits cannot contribute to the result of the 'or'.
453 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
454 return TLO.CombineTo(Op, Op.getOperand(0));
455 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
456 return TLO.CombineTo(Op, Op.getOperand(1));
457 // If all of the potentially set bits on one side are known to be set on
458 // the other side, just use the 'other' side.
459 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
460 return TLO.CombineTo(Op, Op.getOperand(0));
461 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
462 return TLO.CombineTo(Op, Op.getOperand(1));
463 // If the RHS is a constant, see if we can simplify it.
464 if (TLO.ShrinkDemandedConstant(Op, NewMask))
466 // If the operation can be done in a smaller type, do so.
467 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
470 // Output known-0 bits are only known if clear in both the LHS & RHS.
471 KnownZero &= KnownZero2;
472 // Output known-1 are known to be set if set in either the LHS | RHS.
473 KnownOne |= KnownOne2;
476 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
477 KnownOne, TLO, Depth+1))
479 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
480 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
481 KnownOne2, TLO, Depth+1))
483 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
485 // If all of the demanded bits are known zero on one side, return the other.
486 // These bits cannot contribute to the result of the 'xor'.
487 if ((KnownZero & NewMask) == NewMask)
488 return TLO.CombineTo(Op, Op.getOperand(0));
489 if ((KnownZero2 & NewMask) == NewMask)
490 return TLO.CombineTo(Op, Op.getOperand(1));
491 // If the operation can be done in a smaller type, do so.
492 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
495 // If all of the unknown bits are known to be zero on one side or the other
496 // (but not both) turn this into an *inclusive* or.
497 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
498 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
499 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
503 // Output known-0 bits are known if clear or set in both the LHS & RHS.
504 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
505 // Output known-1 are known to be set if set in only one of the LHS, RHS.
506 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
508 // If all of the demanded bits on one side are known, and all of the set
509 // bits on that side are also known to be set on the other side, turn this
510 // into an AND, as we know the bits will be cleared.
511 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
512 // NB: it is okay if more bits are known than are requested
513 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
514 if (KnownOne == KnownOne2) { // set bits are the same on both sides
515 EVT VT = Op.getValueType();
516 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
517 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
518 Op.getOperand(0), ANDC));
522 // If the RHS is a constant, see if we can simplify it.
523 // for XOR, we prefer to force bits to 1 if they will make a -1.
524 // if we can't force bits, try to shrink constant
525 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
526 APInt Expanded = C->getAPIntValue() | (~NewMask);
527 // if we can expand it to have all bits set, do it
528 if (Expanded.isAllOnesValue()) {
529 if (Expanded != C->getAPIntValue()) {
530 EVT VT = Op.getValueType();
531 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
532 TLO.DAG.getConstant(Expanded, VT));
533 return TLO.CombineTo(Op, New);
535 // if it already has all the bits set, nothing to change
536 // but don't shrink either!
537 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
542 KnownZero = KnownZeroOut;
543 KnownOne = KnownOneOut;
546 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
547 KnownOne, TLO, Depth+1))
549 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
550 KnownOne2, TLO, Depth+1))
552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
553 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
555 // If the operands are constants, see if we can simplify them.
556 if (TLO.ShrinkDemandedConstant(Op, NewMask))
559 // Only known if known in both the LHS and RHS.
560 KnownOne &= KnownOne2;
561 KnownZero &= KnownZero2;
564 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
565 KnownOne, TLO, Depth+1))
567 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
568 KnownOne2, TLO, Depth+1))
570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
573 // If the operands are constants, see if we can simplify them.
574 if (TLO.ShrinkDemandedConstant(Op, NewMask))
577 // Only known if known in both the LHS and RHS.
578 KnownOne &= KnownOne2;
579 KnownZero &= KnownZero2;
582 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
583 unsigned ShAmt = SA->getZExtValue();
584 SDValue InOp = Op.getOperand(0);
586 // If the shift count is an invalid immediate, don't do anything.
587 if (ShAmt >= BitWidth)
590 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
591 // single shift. We can do this if the bottom bits (which are shifted
592 // out) are never demanded.
593 if (InOp.getOpcode() == ISD::SRL &&
594 isa<ConstantSDNode>(InOp.getOperand(1))) {
595 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
596 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
597 unsigned Opc = ISD::SHL;
605 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
606 EVT VT = Op.getValueType();
607 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
608 InOp.getOperand(0), NewSA));
612 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
613 KnownZero, KnownOne, TLO, Depth+1))
616 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
617 // are not demanded. This will likely allow the anyext to be folded away.
618 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
619 SDValue InnerOp = InOp.getNode()->getOperand(0);
620 EVT InnerVT = InnerOp.getValueType();
621 unsigned InnerBits = InnerVT.getSizeInBits();
622 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
623 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
624 EVT ShTy = getShiftAmountTy(InnerVT);
625 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
628 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
629 TLO.DAG.getConstant(ShAmt, ShTy));
632 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
637 KnownZero <<= SA->getZExtValue();
638 KnownOne <<= SA->getZExtValue();
639 // low bits known zero.
640 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
644 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
645 EVT VT = Op.getValueType();
646 unsigned ShAmt = SA->getZExtValue();
647 unsigned VTSize = VT.getSizeInBits();
648 SDValue InOp = Op.getOperand(0);
650 // If the shift count is an invalid immediate, don't do anything.
651 if (ShAmt >= BitWidth)
654 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
655 // single shift. We can do this if the top bits (which are shifted out)
656 // are never demanded.
657 if (InOp.getOpcode() == ISD::SHL &&
658 isa<ConstantSDNode>(InOp.getOperand(1))) {
659 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
660 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
661 unsigned Opc = ISD::SRL;
669 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
670 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
671 InOp.getOperand(0), NewSA));
675 // Compute the new bits that are at the top now.
676 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
677 KnownZero, KnownOne, TLO, Depth+1))
679 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
680 KnownZero = KnownZero.lshr(ShAmt);
681 KnownOne = KnownOne.lshr(ShAmt);
683 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
684 KnownZero |= HighBits; // High bits known zero.
688 // If this is an arithmetic shift right and only the low-bit is set, we can
689 // always convert this into a logical shr, even if the shift amount is
690 // variable. The low bit of the shift cannot be an input sign bit unless
691 // the shift amount is >= the size of the datatype, which is undefined.
693 return TLO.CombineTo(Op,
694 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
695 Op.getOperand(0), Op.getOperand(1)));
697 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
698 EVT VT = Op.getValueType();
699 unsigned ShAmt = SA->getZExtValue();
701 // If the shift count is an invalid immediate, don't do anything.
702 if (ShAmt >= BitWidth)
705 APInt InDemandedMask = (NewMask << ShAmt);
707 // If any of the demanded bits are produced by the sign extension, we also
708 // demand the input sign bit.
709 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
710 if (HighBits.intersects(NewMask))
711 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
713 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
714 KnownZero, KnownOne, TLO, Depth+1))
716 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
717 KnownZero = KnownZero.lshr(ShAmt);
718 KnownOne = KnownOne.lshr(ShAmt);
720 // Handle the sign bit, adjusted to where it is now in the mask.
721 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
723 // If the input sign bit is known to be zero, or if none of the top bits
724 // are demanded, turn this into an unsigned shift right.
725 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
726 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
729 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
730 KnownOne |= HighBits;
734 case ISD::SIGN_EXTEND_INREG: {
735 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
737 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
738 // If we only care about the highest bit, don't bother shifting right.
739 if (MsbMask == DemandedMask) {
740 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
741 SDValue InOp = Op.getOperand(0);
743 // Compute the correct shift amount type, which must be getShiftAmountTy
744 // for scalar types after legalization.
745 EVT ShiftAmtTy = Op.getValueType();
746 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
747 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
749 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
750 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
751 Op.getValueType(), InOp, ShiftAmt));
754 // Sign extension. Compute the demanded bits in the result that are not
755 // present in the input.
757 APInt::getHighBitsSet(BitWidth,
758 BitWidth - ExVT.getScalarType().getSizeInBits());
760 // If none of the extended bits are demanded, eliminate the sextinreg.
761 if ((NewBits & NewMask) == 0)
762 return TLO.CombineTo(Op, Op.getOperand(0));
765 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
766 APInt InputDemandedBits =
767 APInt::getLowBitsSet(BitWidth,
768 ExVT.getScalarType().getSizeInBits()) &
771 // Since the sign extended bits are demanded, we know that the sign
773 InputDemandedBits |= InSignBit;
775 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
776 KnownZero, KnownOne, TLO, Depth+1))
778 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
780 // If the sign bit of the input is known set or clear, then we know the
781 // top bits of the result.
783 // If the input sign bit is known zero, convert this into a zero extension.
784 if (KnownZero.intersects(InSignBit))
785 return TLO.CombineTo(Op,
786 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
788 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
790 KnownZero &= ~NewBits;
791 } else { // Input sign bit unknown
792 KnownZero &= ~NewBits;
793 KnownOne &= ~NewBits;
797 case ISD::ZERO_EXTEND: {
798 unsigned OperandBitWidth =
799 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
800 APInt InMask = NewMask.trunc(OperandBitWidth);
802 // If none of the top bits are demanded, convert this into an any_extend.
804 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
805 if (!NewBits.intersects(NewMask))
806 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
810 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
811 KnownZero, KnownOne, TLO, Depth+1))
813 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
814 KnownZero = KnownZero.zext(BitWidth);
815 KnownOne = KnownOne.zext(BitWidth);
816 KnownZero |= NewBits;
819 case ISD::SIGN_EXTEND: {
820 EVT InVT = Op.getOperand(0).getValueType();
821 unsigned InBits = InVT.getScalarType().getSizeInBits();
822 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
823 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
824 APInt NewBits = ~InMask & NewMask;
826 // If none of the top bits are demanded, convert this into an any_extend.
828 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
832 // Since some of the sign extended bits are demanded, we know that the sign
834 APInt InDemandedBits = InMask & NewMask;
835 InDemandedBits |= InSignBit;
836 InDemandedBits = InDemandedBits.trunc(InBits);
838 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
839 KnownOne, TLO, Depth+1))
841 KnownZero = KnownZero.zext(BitWidth);
842 KnownOne = KnownOne.zext(BitWidth);
844 // If the sign bit is known zero, convert this to a zero extend.
845 if (KnownZero.intersects(InSignBit))
846 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
850 // If the sign bit is known one, the top bits match.
851 if (KnownOne.intersects(InSignBit)) {
853 assert((KnownZero & NewBits) == 0);
854 } else { // Otherwise, top bits aren't known.
855 assert((KnownOne & NewBits) == 0);
856 assert((KnownZero & NewBits) == 0);
860 case ISD::ANY_EXTEND: {
861 unsigned OperandBitWidth =
862 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
863 APInt InMask = NewMask.trunc(OperandBitWidth);
864 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
865 KnownZero, KnownOne, TLO, Depth+1))
867 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
868 KnownZero = KnownZero.zext(BitWidth);
869 KnownOne = KnownOne.zext(BitWidth);
872 case ISD::TRUNCATE: {
873 // Simplify the input, using demanded bit information, and compute the known
874 // zero/one bits live out.
875 unsigned OperandBitWidth =
876 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
877 APInt TruncMask = NewMask.zext(OperandBitWidth);
878 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
879 KnownZero, KnownOne, TLO, Depth+1))
881 KnownZero = KnownZero.trunc(BitWidth);
882 KnownOne = KnownOne.trunc(BitWidth);
884 // If the input is only used by this truncate, see if we can shrink it based
885 // on the known demanded bits.
886 if (Op.getOperand(0).getNode()->hasOneUse()) {
887 SDValue In = Op.getOperand(0);
888 switch (In.getOpcode()) {
891 // Shrink SRL by a constant if none of the high bits shifted in are
893 if (TLO.LegalTypes() &&
894 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
895 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
898 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
901 SDValue Shift = In.getOperand(1);
902 if (TLO.LegalTypes()) {
903 uint64_t ShVal = ShAmt->getZExtValue();
905 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
908 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
909 OperandBitWidth - BitWidth);
910 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
912 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
913 // None of the shifted in bits are needed. Add a truncate of the
914 // shift input, then shift it.
915 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
918 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
927 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
930 case ISD::AssertZext: {
931 // AssertZext demands all of the high bits, plus any of the low bits
932 // demanded by its users.
933 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
934 APInt InMask = APInt::getLowBitsSet(BitWidth,
936 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
937 KnownZero, KnownOne, TLO, Depth+1))
939 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
941 KnownZero |= ~InMask & NewMask;
945 // If this is an FP->Int bitcast and if the sign bit is the only
946 // thing demanded, turn this into a FGETSIGN.
947 if (!TLO.LegalOperations() &&
948 !Op.getValueType().isVector() &&
949 !Op.getOperand(0).getValueType().isVector() &&
950 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
951 Op.getOperand(0).getValueType().isFloatingPoint()) {
952 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
953 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
954 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
955 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
956 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
957 // place. We expect the SHL to be eliminated by other optimizations.
958 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
959 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
960 if (!OpVTLegal && OpVTSizeInBits > 32)
961 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
962 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
963 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
964 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
973 // Add, Sub, and Mul don't demand any bits in positions beyond that
974 // of the highest bit demanded of them.
975 APInt LoMask = APInt::getLowBitsSet(BitWidth,
976 BitWidth - NewMask.countLeadingZeros());
977 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
978 KnownOne2, TLO, Depth+1))
980 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
981 KnownOne2, TLO, Depth+1))
983 // See if the operation should be performed at a smaller bit width.
984 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
989 // Just use ComputeMaskedBits to compute output bits.
990 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
994 // If we know the value of all of the demanded bits, return this as a
996 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
997 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1002 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1003 /// in Mask are known to be either zero or one and return them in the
1004 /// KnownZero/KnownOne bitsets.
1005 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1008 const SelectionDAG &DAG,
1009 unsigned Depth) const {
1010 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1011 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1012 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1013 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1014 "Should use MaskedValueIsZero if you don't know whether Op"
1015 " is a target node!");
1016 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1019 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1020 /// targets that want to expose additional information about sign bits to the
1022 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1023 unsigned Depth) const {
1024 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1025 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1026 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1027 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1028 "Should use ComputeNumSignBits if you don't know whether Op"
1029 " is a target node!");
1033 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1034 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1035 /// determine which bit is set.
1037 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1038 // A left-shift of a constant one will have exactly one bit set, because
1039 // shifting the bit off the end is undefined.
1040 if (Val.getOpcode() == ISD::SHL)
1041 if (ConstantSDNode *C =
1042 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1043 if (C->getAPIntValue() == 1)
1046 // Similarly, a right-shift of a constant sign-bit will have exactly
1048 if (Val.getOpcode() == ISD::SRL)
1049 if (ConstantSDNode *C =
1050 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1051 if (C->getAPIntValue().isSignBit())
1054 // More could be done here, though the above checks are enough
1055 // to handle some common cases.
1057 // Fall back to ComputeMaskedBits to catch other known cases.
1058 EVT OpVT = Val.getValueType();
1059 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1060 APInt KnownZero, KnownOne;
1061 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1062 return (KnownZero.countPopulation() == BitWidth - 1) &&
1063 (KnownOne.countPopulation() == 1);
1066 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1067 /// and cc. If it is unable to simplify it, return a null SDValue.
1069 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1070 ISD::CondCode Cond, bool foldBooleans,
1071 DAGCombinerInfo &DCI, SDLoc dl) const {
1072 SelectionDAG &DAG = DCI.DAG;
1074 // These setcc operations always fold.
1078 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1080 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1083 // Ensure that the constant occurs on the RHS, and fold constant
1085 if (isa<ConstantSDNode>(N0.getNode()))
1086 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1088 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1089 const APInt &C1 = N1C->getAPIntValue();
1091 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1092 // equality comparison, then we're just comparing whether X itself is
1094 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1095 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1096 N0.getOperand(1).getOpcode() == ISD::Constant) {
1098 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1099 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1100 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1101 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1102 // (srl (ctlz x), 5) == 0 -> X != 0
1103 // (srl (ctlz x), 5) != 1 -> X != 0
1106 // (srl (ctlz x), 5) != 0 -> X == 0
1107 // (srl (ctlz x), 5) == 1 -> X == 0
1110 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1111 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1117 // Look through truncs that don't change the value of a ctpop.
1118 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1119 CTPOP = N0.getOperand(0);
1121 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1122 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1123 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1124 EVT CTVT = CTPOP.getValueType();
1125 SDValue CTOp = CTPOP.getOperand(0);
1127 // (ctpop x) u< 2 -> (x & x-1) == 0
1128 // (ctpop x) u> 1 -> (x & x-1) != 0
1129 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1130 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1131 DAG.getConstant(1, CTVT));
1132 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1133 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1134 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1137 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1140 // (zext x) == C --> x == (trunc C)
1141 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1142 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1143 unsigned MinBits = N0.getValueSizeInBits();
1145 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1147 MinBits = N0->getOperand(0).getValueSizeInBits();
1148 PreZExt = N0->getOperand(0);
1149 } else if (N0->getOpcode() == ISD::AND) {
1150 // DAGCombine turns costly ZExts into ANDs
1151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1152 if ((C->getAPIntValue()+1).isPowerOf2()) {
1153 MinBits = C->getAPIntValue().countTrailingOnes();
1154 PreZExt = N0->getOperand(0);
1156 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1158 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1159 MinBits = LN0->getMemoryVT().getSizeInBits();
1164 // Make sure we're not losing bits from the constant.
1166 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1167 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1168 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1169 // Will get folded away.
1170 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1171 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1172 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1177 // If the LHS is '(and load, const)', the RHS is 0,
1178 // the test is for equality or unsigned, and all 1 bits of the const are
1179 // in the same partial word, see if we can shorten the load.
1180 if (DCI.isBeforeLegalize() &&
1181 N0.getOpcode() == ISD::AND && C1 == 0 &&
1182 N0.getNode()->hasOneUse() &&
1183 isa<LoadSDNode>(N0.getOperand(0)) &&
1184 N0.getOperand(0).getNode()->hasOneUse() &&
1185 isa<ConstantSDNode>(N0.getOperand(1))) {
1186 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1188 unsigned bestWidth = 0, bestOffset = 0;
1189 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1190 unsigned origWidth = N0.getValueType().getSizeInBits();
1191 unsigned maskWidth = origWidth;
1192 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1193 // 8 bits, but have to be careful...
1194 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1195 origWidth = Lod->getMemoryVT().getSizeInBits();
1197 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1198 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1199 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1200 for (unsigned offset=0; offset<origWidth/width; offset++) {
1201 if ((newMask & Mask) == Mask) {
1202 if (!getDataLayout()->isLittleEndian())
1203 bestOffset = (origWidth/width - offset - 1) * (width/8);
1205 bestOffset = (uint64_t)offset * (width/8);
1206 bestMask = Mask.lshr(offset * (width/8) * 8);
1210 newMask = newMask << width;
1215 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1216 if (newVT.isRound()) {
1217 EVT PtrType = Lod->getOperand(1).getValueType();
1218 SDValue Ptr = Lod->getBasePtr();
1219 if (bestOffset != 0)
1220 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1221 DAG.getConstant(bestOffset, PtrType));
1222 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1223 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1224 Lod->getPointerInfo().getWithOffset(bestOffset),
1225 false, false, false, NewAlign);
1226 return DAG.getSetCC(dl, VT,
1227 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1228 DAG.getConstant(bestMask.trunc(bestWidth),
1230 DAG.getConstant(0LL, newVT), Cond);
1235 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1236 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1237 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1239 // If the comparison constant has bits in the upper part, the
1240 // zero-extended value could never match.
1241 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1242 C1.getBitWidth() - InSize))) {
1246 case ISD::SETEQ: return DAG.getConstant(0, VT);
1249 case ISD::SETNE: return DAG.getConstant(1, VT);
1252 // True if the sign bit of C1 is set.
1253 return DAG.getConstant(C1.isNegative(), VT);
1256 // True if the sign bit of C1 isn't set.
1257 return DAG.getConstant(C1.isNonNegative(), VT);
1263 // Otherwise, we can perform the comparison with the low bits.
1271 EVT newVT = N0.getOperand(0).getValueType();
1272 if (DCI.isBeforeLegalizeOps() ||
1273 (isOperationLegal(ISD::SETCC, newVT) &&
1274 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal))
1275 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1276 DAG.getConstant(C1.trunc(InSize), newVT),
1281 break; // todo, be more careful with signed comparisons
1283 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1284 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1285 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1286 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1287 EVT ExtDstTy = N0.getValueType();
1288 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1290 // If the constant doesn't fit into the number of bits for the source of
1291 // the sign extension, it is impossible for both sides to be equal.
1292 if (C1.getMinSignedBits() > ExtSrcTyBits)
1293 return DAG.getConstant(Cond == ISD::SETNE, VT);
1296 EVT Op0Ty = N0.getOperand(0).getValueType();
1297 if (Op0Ty == ExtSrcTy) {
1298 ZextOp = N0.getOperand(0);
1300 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1301 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1302 DAG.getConstant(Imm, Op0Ty));
1304 if (!DCI.isCalledByLegalizer())
1305 DCI.AddToWorklist(ZextOp.getNode());
1306 // Otherwise, make this a use of a zext.
1307 return DAG.getSetCC(dl, VT, ZextOp,
1308 DAG.getConstant(C1 & APInt::getLowBitsSet(
1313 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1314 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1315 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1316 if (N0.getOpcode() == ISD::SETCC &&
1317 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1318 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1320 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1321 // Invert the condition.
1322 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1323 CC = ISD::getSetCCInverse(CC,
1324 N0.getOperand(0).getValueType().isInteger());
1325 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1328 if ((N0.getOpcode() == ISD::XOR ||
1329 (N0.getOpcode() == ISD::AND &&
1330 N0.getOperand(0).getOpcode() == ISD::XOR &&
1331 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1332 isa<ConstantSDNode>(N0.getOperand(1)) &&
1333 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1334 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1335 // can only do this if the top bits are known zero.
1336 unsigned BitWidth = N0.getValueSizeInBits();
1337 if (DAG.MaskedValueIsZero(N0,
1338 APInt::getHighBitsSet(BitWidth,
1340 // Okay, get the un-inverted input value.
1342 if (N0.getOpcode() == ISD::XOR)
1343 Val = N0.getOperand(0);
1345 assert(N0.getOpcode() == ISD::AND &&
1346 N0.getOperand(0).getOpcode() == ISD::XOR);
1347 // ((X^1)&1)^1 -> X & 1
1348 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1349 N0.getOperand(0).getOperand(0),
1353 return DAG.getSetCC(dl, VT, Val, N1,
1354 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1356 } else if (N1C->getAPIntValue() == 1 &&
1358 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
1360 if (Op0.getOpcode() == ISD::TRUNCATE)
1361 Op0 = Op0.getOperand(0);
1363 if ((Op0.getOpcode() == ISD::XOR) &&
1364 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1365 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1366 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1367 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1368 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1371 if (Op0.getOpcode() == ISD::AND &&
1372 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1373 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1374 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1375 if (Op0.getValueType().bitsGT(VT))
1376 Op0 = DAG.getNode(ISD::AND, dl, VT,
1377 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1378 DAG.getConstant(1, VT));
1379 else if (Op0.getValueType().bitsLT(VT))
1380 Op0 = DAG.getNode(ISD::AND, dl, VT,
1381 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1382 DAG.getConstant(1, VT));
1384 return DAG.getSetCC(dl, VT, Op0,
1385 DAG.getConstant(0, Op0.getValueType()),
1386 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1388 if (Op0.getOpcode() == ISD::AssertZext &&
1389 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1390 return DAG.getSetCC(dl, VT, Op0,
1391 DAG.getConstant(0, Op0.getValueType()),
1392 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1396 APInt MinVal, MaxVal;
1397 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1398 if (ISD::isSignedIntSetCC(Cond)) {
1399 MinVal = APInt::getSignedMinValue(OperandBitSize);
1400 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1402 MinVal = APInt::getMinValue(OperandBitSize);
1403 MaxVal = APInt::getMaxValue(OperandBitSize);
1406 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1407 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1408 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1409 // X >= C0 --> X > (C0-1)
1410 return DAG.getSetCC(dl, VT, N0,
1411 DAG.getConstant(C1-1, N1.getValueType()),
1412 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1415 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1416 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1417 // X <= C0 --> X < (C0+1)
1418 return DAG.getSetCC(dl, VT, N0,
1419 DAG.getConstant(C1+1, N1.getValueType()),
1420 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1423 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1424 return DAG.getConstant(0, VT); // X < MIN --> false
1425 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1426 return DAG.getConstant(1, VT); // X >= MIN --> true
1427 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1428 return DAG.getConstant(0, VT); // X > MAX --> false
1429 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1430 return DAG.getConstant(1, VT); // X <= MAX --> true
1432 // Canonicalize setgt X, Min --> setne X, Min
1433 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1434 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1435 // Canonicalize setlt X, Max --> setne X, Max
1436 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1437 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1439 // If we have setult X, 1, turn it into seteq X, 0
1440 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1441 return DAG.getSetCC(dl, VT, N0,
1442 DAG.getConstant(MinVal, N0.getValueType()),
1444 // If we have setugt X, Max-1, turn it into seteq X, Max
1445 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1446 return DAG.getSetCC(dl, VT, N0,
1447 DAG.getConstant(MaxVal, N0.getValueType()),
1450 // If we have "setcc X, C0", check to see if we can shrink the immediate
1453 // SETUGT X, SINTMAX -> SETLT X, 0
1454 if (Cond == ISD::SETUGT &&
1455 C1 == APInt::getSignedMaxValue(OperandBitSize))
1456 return DAG.getSetCC(dl, VT, N0,
1457 DAG.getConstant(0, N1.getValueType()),
1460 // SETULT X, SINTMIN -> SETGT X, -1
1461 if (Cond == ISD::SETULT &&
1462 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1463 SDValue ConstMinusOne =
1464 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1466 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1469 // Fold bit comparisons when we can.
1470 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1471 (VT == N0.getValueType() ||
1472 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1473 N0.getOpcode() == ISD::AND)
1474 if (ConstantSDNode *AndRHS =
1475 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1476 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
1477 getPointerTy() : getShiftAmountTy(N0.getValueType());
1478 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1479 // Perform the xform if the AND RHS is a single bit.
1480 if (AndRHS->getAPIntValue().isPowerOf2()) {
1481 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1482 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1483 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1485 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1486 // (X & 8) == 8 --> (X & 8) >> 3
1487 // Perform the xform if C1 is a single bit.
1488 if (C1.isPowerOf2()) {
1489 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1490 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1491 DAG.getConstant(C1.logBase2(), ShiftTy)));
1496 if (C1.getMinSignedBits() <= 64 &&
1497 !isLegalICmpImmediate(C1.getSExtValue())) {
1498 // (X & -256) == 256 -> (X >> 8) == 1
1499 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1500 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1501 if (ConstantSDNode *AndRHS =
1502 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1503 const APInt &AndRHSC = AndRHS->getAPIntValue();
1504 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1505 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1506 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
1507 getPointerTy() : getShiftAmountTy(N0.getValueType());
1508 EVT CmpTy = N0.getValueType();
1509 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1510 DAG.getConstant(ShiftBits, ShiftTy));
1511 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1512 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1515 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1516 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1517 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1518 // X < 0x100000000 -> (X >> 32) < 1
1519 // X >= 0x100000000 -> (X >> 32) >= 1
1520 // X <= 0x0ffffffff -> (X >> 32) < 1
1521 // X > 0x0ffffffff -> (X >> 32) >= 1
1524 ISD::CondCode NewCond = Cond;
1526 ShiftBits = C1.countTrailingOnes();
1528 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1530 ShiftBits = C1.countTrailingZeros();
1532 NewC = NewC.lshr(ShiftBits);
1533 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1534 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
1535 getPointerTy() : getShiftAmountTy(N0.getValueType());
1536 EVT CmpTy = N0.getValueType();
1537 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1538 DAG.getConstant(ShiftBits, ShiftTy));
1539 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1540 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1546 if (isa<ConstantFPSDNode>(N0.getNode())) {
1547 // Constant fold or commute setcc.
1548 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1549 if (O.getNode()) return O;
1550 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1551 // If the RHS of an FP comparison is a constant, simplify it away in
1553 if (CFP->getValueAPF().isNaN()) {
1554 // If an operand is known to be a nan, we can fold it.
1555 switch (ISD::getUnorderedFlavor(Cond)) {
1556 default: llvm_unreachable("Unknown flavor!");
1557 case 0: // Known false.
1558 return DAG.getConstant(0, VT);
1559 case 1: // Known true.
1560 return DAG.getConstant(1, VT);
1561 case 2: // Undefined.
1562 return DAG.getUNDEF(VT);
1566 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1567 // constant if knowing that the operand is non-nan is enough. We prefer to
1568 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1570 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1571 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1573 // If the condition is not legal, see if we can find an equivalent one
1575 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1576 // If the comparison was an awkward floating-point == or != and one of
1577 // the comparison operands is infinity or negative infinity, convert the
1578 // condition to a less-awkward <= or >=.
1579 if (CFP->getValueAPF().isInfinity()) {
1580 if (CFP->getValueAPF().isNegative()) {
1581 if (Cond == ISD::SETOEQ &&
1582 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1583 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1584 if (Cond == ISD::SETUEQ &&
1585 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1586 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1587 if (Cond == ISD::SETUNE &&
1588 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1589 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1590 if (Cond == ISD::SETONE &&
1591 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1592 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1594 if (Cond == ISD::SETOEQ &&
1595 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1596 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1597 if (Cond == ISD::SETUEQ &&
1598 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1599 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1600 if (Cond == ISD::SETUNE &&
1601 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1602 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1603 if (Cond == ISD::SETONE &&
1604 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1605 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1612 // The sext(setcc()) => setcc() optimization relies on the appropriate
1613 // constant being emitted.
1615 switch (getBooleanContents(N0.getValueType().isVector())) {
1616 case UndefinedBooleanContent:
1617 case ZeroOrOneBooleanContent:
1618 EqVal = ISD::isTrueWhenEqual(Cond);
1620 case ZeroOrNegativeOneBooleanContent:
1621 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1625 // We can always fold X == X for integer setcc's.
1626 if (N0.getValueType().isInteger()) {
1627 return DAG.getConstant(EqVal, VT);
1629 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1630 if (UOF == 2) // FP operators that are undefined on NaNs.
1631 return DAG.getConstant(EqVal, VT);
1632 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1633 return DAG.getConstant(EqVal, VT);
1634 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1635 // if it is not already.
1636 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1637 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1638 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1639 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1642 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1643 N0.getValueType().isInteger()) {
1644 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1645 N0.getOpcode() == ISD::XOR) {
1646 // Simplify (X+Y) == (X+Z) --> Y == Z
1647 if (N0.getOpcode() == N1.getOpcode()) {
1648 if (N0.getOperand(0) == N1.getOperand(0))
1649 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1650 if (N0.getOperand(1) == N1.getOperand(1))
1651 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1652 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1653 // If X op Y == Y op X, try other combinations.
1654 if (N0.getOperand(0) == N1.getOperand(1))
1655 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1657 if (N0.getOperand(1) == N1.getOperand(0))
1658 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1663 // If RHS is a legal immediate value for a compare instruction, we need
1664 // to be careful about increasing register pressure needlessly.
1665 bool LegalRHSImm = false;
1667 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1668 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1669 // Turn (X+C1) == C2 --> X == C2-C1
1670 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1671 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1672 DAG.getConstant(RHSC->getAPIntValue()-
1673 LHSR->getAPIntValue(),
1674 N0.getValueType()), Cond);
1677 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1678 if (N0.getOpcode() == ISD::XOR)
1679 // If we know that all of the inverted bits are zero, don't bother
1680 // performing the inversion.
1681 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1683 DAG.getSetCC(dl, VT, N0.getOperand(0),
1684 DAG.getConstant(LHSR->getAPIntValue() ^
1685 RHSC->getAPIntValue(),
1690 // Turn (C1-X) == C2 --> X == C1-C2
1691 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1692 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1694 DAG.getSetCC(dl, VT, N0.getOperand(1),
1695 DAG.getConstant(SUBC->getAPIntValue() -
1696 RHSC->getAPIntValue(),
1702 // Could RHSC fold directly into a compare?
1703 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1704 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1707 // Simplify (X+Z) == X --> Z == 0
1708 // Don't do this if X is an immediate that can fold into a cmp
1709 // instruction and X+Z has other uses. It could be an induction variable
1710 // chain, and the transform would increase register pressure.
1711 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1712 if (N0.getOperand(0) == N1)
1713 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1714 DAG.getConstant(0, N0.getValueType()), Cond);
1715 if (N0.getOperand(1) == N1) {
1716 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1717 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1718 DAG.getConstant(0, N0.getValueType()), Cond);
1719 if (N0.getNode()->hasOneUse()) {
1720 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1721 // (Z-X) == X --> Z == X<<1
1722 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1723 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1724 if (!DCI.isCalledByLegalizer())
1725 DCI.AddToWorklist(SH.getNode());
1726 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1732 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1733 N1.getOpcode() == ISD::XOR) {
1734 // Simplify X == (X+Z) --> Z == 0
1735 if (N1.getOperand(0) == N0)
1736 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1737 DAG.getConstant(0, N1.getValueType()), Cond);
1738 if (N1.getOperand(1) == N0) {
1739 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1740 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1741 DAG.getConstant(0, N1.getValueType()), Cond);
1742 if (N1.getNode()->hasOneUse()) {
1743 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1744 // X == (Z-X) --> X<<1 == Z
1745 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1746 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1747 if (!DCI.isCalledByLegalizer())
1748 DCI.AddToWorklist(SH.getNode());
1749 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1754 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1755 // Note that where y is variable and is known to have at most
1756 // one bit set (for example, if it is z&1) we cannot do this;
1757 // the expressions are not equivalent when y==0.
1758 if (N0.getOpcode() == ISD::AND)
1759 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1760 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1761 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1762 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1763 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1766 if (N1.getOpcode() == ISD::AND)
1767 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1768 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1769 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1770 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1771 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1776 // Fold away ALL boolean setcc's.
1778 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1780 default: llvm_unreachable("Unknown integer setcc!");
1781 case ISD::SETEQ: // X == Y -> ~(X^Y)
1782 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1783 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1784 if (!DCI.isCalledByLegalizer())
1785 DCI.AddToWorklist(Temp.getNode());
1787 case ISD::SETNE: // X != Y --> (X^Y)
1788 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1790 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1791 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1792 Temp = DAG.getNOT(dl, N0, MVT::i1);
1793 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1794 if (!DCI.isCalledByLegalizer())
1795 DCI.AddToWorklist(Temp.getNode());
1797 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1798 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1799 Temp = DAG.getNOT(dl, N1, MVT::i1);
1800 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1801 if (!DCI.isCalledByLegalizer())
1802 DCI.AddToWorklist(Temp.getNode());
1804 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1805 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1806 Temp = DAG.getNOT(dl, N0, MVT::i1);
1807 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1808 if (!DCI.isCalledByLegalizer())
1809 DCI.AddToWorklist(Temp.getNode());
1811 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1812 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1813 Temp = DAG.getNOT(dl, N1, MVT::i1);
1814 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1817 if (VT != MVT::i1) {
1818 if (!DCI.isCalledByLegalizer())
1819 DCI.AddToWorklist(N0.getNode());
1820 // FIXME: If running after legalize, we probably can't do this.
1821 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1826 // Could not fold it.
1830 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1831 /// node is a GlobalAddress + offset.
1832 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
1833 int64_t &Offset) const {
1834 if (isa<GlobalAddressSDNode>(N)) {
1835 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
1836 GA = GASD->getGlobal();
1837 Offset += GASD->getOffset();
1841 if (N->getOpcode() == ISD::ADD) {
1842 SDValue N1 = N->getOperand(0);
1843 SDValue N2 = N->getOperand(1);
1844 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
1845 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
1847 Offset += V->getSExtValue();
1850 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
1851 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
1853 Offset += V->getSExtValue();
1863 SDValue TargetLowering::
1864 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1865 // Default implementation: no optimization.
1869 //===----------------------------------------------------------------------===//
1870 // Inline Assembler Implementation Methods
1871 //===----------------------------------------------------------------------===//
1874 TargetLowering::ConstraintType
1875 TargetLowering::getConstraintType(const std::string &Constraint) const {
1876 unsigned S = Constraint.size();
1879 switch (Constraint[0]) {
1881 case 'r': return C_RegisterClass;
1883 case 'o': // offsetable
1884 case 'V': // not offsetable
1886 case 'i': // Simple Integer or Relocatable Constant
1887 case 'n': // Simple Integer
1888 case 'E': // Floating Point Constant
1889 case 'F': // Floating Point Constant
1890 case 's': // Relocatable Constant
1891 case 'p': // Address.
1892 case 'X': // Allow ANY value.
1893 case 'I': // Target registers.
1907 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
1908 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
1915 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1916 /// with another that has more specific requirements based on the type of the
1917 /// corresponding operand.
1918 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
1919 if (ConstraintVT.isInteger())
1921 if (ConstraintVT.isFloatingPoint())
1922 return "f"; // works for many targets
1926 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1927 /// vector. If it is invalid, don't add anything to Ops.
1928 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
1929 std::string &Constraint,
1930 std::vector<SDValue> &Ops,
1931 SelectionDAG &DAG) const {
1933 if (Constraint.length() > 1) return;
1935 char ConstraintLetter = Constraint[0];
1936 switch (ConstraintLetter) {
1938 case 'X': // Allows any operand; labels (basic block) use this.
1939 if (Op.getOpcode() == ISD::BasicBlock) {
1944 case 'i': // Simple Integer or Relocatable Constant
1945 case 'n': // Simple Integer
1946 case 's': { // Relocatable Constant
1947 // These operands are interested in values of the form (GV+C), where C may
1948 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1949 // is possible and fine if either GV or C are missing.
1950 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1951 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1953 // If we have "(add GV, C)", pull out GV/C
1954 if (Op.getOpcode() == ISD::ADD) {
1955 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1956 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1957 if (C == 0 || GA == 0) {
1958 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1959 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1961 if (C == 0 || GA == 0)
1965 // If we find a valid operand, map to the TargetXXX version so that the
1966 // value itself doesn't get selected.
1967 if (GA) { // Either &GV or &GV+C
1968 if (ConstraintLetter != 'n') {
1969 int64_t Offs = GA->getOffset();
1970 if (C) Offs += C->getZExtValue();
1971 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1972 C ? SDLoc(C) : SDLoc(),
1973 Op.getValueType(), Offs));
1977 if (C) { // just C, no GV.
1978 // Simple constants are not allowed for 's'.
1979 if (ConstraintLetter != 's') {
1980 // gcc prints these as sign extended. Sign extend value to 64 bits
1981 // now; without this it would get ZExt'd later in
1982 // ScheduleDAGSDNodes::EmitNode, which is very generic.
1983 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
1993 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1994 getRegForInlineAsmConstraint(const std::string &Constraint,
1996 if (Constraint[0] != '{')
1997 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
1998 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2000 // Remove the braces from around the name.
2001 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2003 std::pair<unsigned, const TargetRegisterClass*> R =
2004 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2006 // Figure out which register class contains this reg.
2007 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo();
2008 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2009 E = RI->regclass_end(); RCI != E; ++RCI) {
2010 const TargetRegisterClass *RC = *RCI;
2012 // If none of the value types for this register class are valid, we
2013 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2017 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2019 if (RegName.equals_lower(RI->getName(*I))) {
2020 std::pair<unsigned, const TargetRegisterClass*> S =
2021 std::make_pair(*I, RC);
2023 // If this register class has the requested value type, return it,
2024 // otherwise keep searching and return the first class found
2025 // if no other is found which explicitly has the requested type.
2026 if (RC->hasType(VT))
2037 //===----------------------------------------------------------------------===//
2038 // Constraint Selection.
2040 /// isMatchingInputConstraint - Return true of this is an input operand that is
2041 /// a matching constraint like "4".
2042 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2043 assert(!ConstraintCode.empty() && "No known constraint!");
2044 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2047 /// getMatchedOperand - If this is an input matching constraint, this method
2048 /// returns the output operand it matches.
2049 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2050 assert(!ConstraintCode.empty() && "No known constraint!");
2051 return atoi(ConstraintCode.c_str());
2055 /// ParseConstraints - Split up the constraint string from the inline
2056 /// assembly value into the specific constraints and their prefixes,
2057 /// and also tie in the associated operand values.
2058 /// If this returns an empty vector, and if the constraint string itself
2059 /// isn't empty, there was an error parsing.
2060 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2061 ImmutableCallSite CS) const {
2062 /// ConstraintOperands - Information about all of the constraints.
2063 AsmOperandInfoVector ConstraintOperands;
2064 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2065 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2067 // Do a prepass over the constraints, canonicalizing them, and building up the
2068 // ConstraintOperands list.
2069 InlineAsm::ConstraintInfoVector
2070 ConstraintInfos = IA->ParseConstraints();
2072 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2073 unsigned ResNo = 0; // ResNo - The result number of the next output.
2075 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2076 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2077 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2079 // Update multiple alternative constraint count.
2080 if (OpInfo.multipleAlternatives.size() > maCount)
2081 maCount = OpInfo.multipleAlternatives.size();
2083 OpInfo.ConstraintVT = MVT::Other;
2085 // Compute the value type for each operand.
2086 switch (OpInfo.Type) {
2087 case InlineAsm::isOutput:
2088 // Indirect outputs just consume an argument.
2089 if (OpInfo.isIndirect) {
2090 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2094 // The return value of the call is this value. As such, there is no
2095 // corresponding argument.
2096 assert(!CS.getType()->isVoidTy() &&
2098 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2099 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2101 assert(ResNo == 0 && "Asm only has one result!");
2102 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2106 case InlineAsm::isInput:
2107 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2109 case InlineAsm::isClobber:
2114 if (OpInfo.CallOperandVal) {
2115 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2116 if (OpInfo.isIndirect) {
2117 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2119 report_fatal_error("Indirect operand for inline asm not a pointer!");
2120 OpTy = PtrTy->getElementType();
2123 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2124 if (StructType *STy = dyn_cast<StructType>(OpTy))
2125 if (STy->getNumElements() == 1)
2126 OpTy = STy->getElementType(0);
2128 // If OpTy is not a single value, it may be a struct/union that we
2129 // can tile with integers.
2130 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2131 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2140 OpInfo.ConstraintVT =
2141 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2144 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2145 OpInfo.ConstraintVT = MVT::getIntegerVT(
2146 8*getDataLayout()->getPointerSize(PT->getAddressSpace()));
2148 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2153 // If we have multiple alternative constraints, select the best alternative.
2154 if (ConstraintInfos.size()) {
2156 unsigned bestMAIndex = 0;
2157 int bestWeight = -1;
2158 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2161 // Compute the sums of the weights for each alternative, keeping track
2162 // of the best (highest weight) one so far.
2163 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2165 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2166 cIndex != eIndex; ++cIndex) {
2167 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2168 if (OpInfo.Type == InlineAsm::isClobber)
2171 // If this is an output operand with a matching input operand,
2172 // look up the matching input. If their types mismatch, e.g. one
2173 // is an integer, the other is floating point, or their sizes are
2174 // different, flag it as an maCantMatch.
2175 if (OpInfo.hasMatchingInput()) {
2176 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2177 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2178 if ((OpInfo.ConstraintVT.isInteger() !=
2179 Input.ConstraintVT.isInteger()) ||
2180 (OpInfo.ConstraintVT.getSizeInBits() !=
2181 Input.ConstraintVT.getSizeInBits())) {
2182 weightSum = -1; // Can't match.
2187 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2192 weightSum += weight;
2195 if (weightSum > bestWeight) {
2196 bestWeight = weightSum;
2197 bestMAIndex = maIndex;
2201 // Now select chosen alternative in each constraint.
2202 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2203 cIndex != eIndex; ++cIndex) {
2204 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2205 if (cInfo.Type == InlineAsm::isClobber)
2207 cInfo.selectAlternative(bestMAIndex);
2212 // Check and hook up tied operands, choose constraint code to use.
2213 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2214 cIndex != eIndex; ++cIndex) {
2215 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2217 // If this is an output operand with a matching input operand, look up the
2218 // matching input. If their types mismatch, e.g. one is an integer, the
2219 // other is floating point, or their sizes are different, flag it as an
2221 if (OpInfo.hasMatchingInput()) {
2222 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2224 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2225 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2226 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2227 OpInfo.ConstraintVT);
2228 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2229 getRegForInlineAsmConstraint(Input.ConstraintCode,
2230 Input.ConstraintVT);
2231 if ((OpInfo.ConstraintVT.isInteger() !=
2232 Input.ConstraintVT.isInteger()) ||
2233 (MatchRC.second != InputRC.second)) {
2234 report_fatal_error("Unsupported asm: input constraint"
2235 " with a matching output constraint of"
2236 " incompatible type!");
2243 return ConstraintOperands;
2247 /// getConstraintGenerality - Return an integer indicating how general CT
2249 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2251 case TargetLowering::C_Other:
2252 case TargetLowering::C_Unknown:
2254 case TargetLowering::C_Register:
2256 case TargetLowering::C_RegisterClass:
2258 case TargetLowering::C_Memory:
2261 llvm_unreachable("Invalid constraint type");
2264 /// Examine constraint type and operand type and determine a weight value.
2265 /// This object must already have been set up with the operand type
2266 /// and the current alternative constraint selected.
2267 TargetLowering::ConstraintWeight
2268 TargetLowering::getMultipleConstraintMatchWeight(
2269 AsmOperandInfo &info, int maIndex) const {
2270 InlineAsm::ConstraintCodeVector *rCodes;
2271 if (maIndex >= (int)info.multipleAlternatives.size())
2272 rCodes = &info.Codes;
2274 rCodes = &info.multipleAlternatives[maIndex].Codes;
2275 ConstraintWeight BestWeight = CW_Invalid;
2277 // Loop over the options, keeping track of the most general one.
2278 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2279 ConstraintWeight weight =
2280 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2281 if (weight > BestWeight)
2282 BestWeight = weight;
2288 /// Examine constraint type and operand type and determine a weight value.
2289 /// This object must already have been set up with the operand type
2290 /// and the current alternative constraint selected.
2291 TargetLowering::ConstraintWeight
2292 TargetLowering::getSingleConstraintMatchWeight(
2293 AsmOperandInfo &info, const char *constraint) const {
2294 ConstraintWeight weight = CW_Invalid;
2295 Value *CallOperandVal = info.CallOperandVal;
2296 // If we don't have a value, we can't do a match,
2297 // but allow it at the lowest weight.
2298 if (CallOperandVal == NULL)
2300 // Look at the constraint type.
2301 switch (*constraint) {
2302 case 'i': // immediate integer.
2303 case 'n': // immediate integer with a known value.
2304 if (isa<ConstantInt>(CallOperandVal))
2305 weight = CW_Constant;
2307 case 's': // non-explicit intregal immediate.
2308 if (isa<GlobalValue>(CallOperandVal))
2309 weight = CW_Constant;
2311 case 'E': // immediate float if host format.
2312 case 'F': // immediate float.
2313 if (isa<ConstantFP>(CallOperandVal))
2314 weight = CW_Constant;
2316 case '<': // memory operand with autodecrement.
2317 case '>': // memory operand with autoincrement.
2318 case 'm': // memory operand.
2319 case 'o': // offsettable memory operand
2320 case 'V': // non-offsettable memory operand
2323 case 'r': // general register.
2324 case 'g': // general register, memory operand or immediate integer.
2325 // note: Clang converts "g" to "imr".
2326 if (CallOperandVal->getType()->isIntegerTy())
2327 weight = CW_Register;
2329 case 'X': // any operand.
2331 weight = CW_Default;
2337 /// ChooseConstraint - If there are multiple different constraints that we
2338 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2339 /// This is somewhat tricky: constraints fall into four classes:
2340 /// Other -> immediates and magic values
2341 /// Register -> one specific register
2342 /// RegisterClass -> a group of regs
2343 /// Memory -> memory
2344 /// Ideally, we would pick the most specific constraint possible: if we have
2345 /// something that fits into a register, we would pick it. The problem here
2346 /// is that if we have something that could either be in a register or in
2347 /// memory that use of the register could cause selection of *other*
2348 /// operands to fail: they might only succeed if we pick memory. Because of
2349 /// this the heuristic we use is:
2351 /// 1) If there is an 'other' constraint, and if the operand is valid for
2352 /// that constraint, use it. This makes us take advantage of 'i'
2353 /// constraints when available.
2354 /// 2) Otherwise, pick the most general constraint present. This prefers
2355 /// 'm' over 'r', for example.
2357 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2358 const TargetLowering &TLI,
2359 SDValue Op, SelectionDAG *DAG) {
2360 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2361 unsigned BestIdx = 0;
2362 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2363 int BestGenerality = -1;
2365 // Loop over the options, keeping track of the most general one.
2366 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2367 TargetLowering::ConstraintType CType =
2368 TLI.getConstraintType(OpInfo.Codes[i]);
2370 // If this is an 'other' constraint, see if the operand is valid for it.
2371 // For example, on X86 we might have an 'rI' constraint. If the operand
2372 // is an integer in the range [0..31] we want to use I (saving a load
2373 // of a register), otherwise we must use 'r'.
2374 if (CType == TargetLowering::C_Other && Op.getNode()) {
2375 assert(OpInfo.Codes[i].size() == 1 &&
2376 "Unhandled multi-letter 'other' constraint");
2377 std::vector<SDValue> ResultOps;
2378 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2380 if (!ResultOps.empty()) {
2387 // Things with matching constraints can only be registers, per gcc
2388 // documentation. This mainly affects "g" constraints.
2389 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2392 // This constraint letter is more general than the previous one, use it.
2393 int Generality = getConstraintGenerality(CType);
2394 if (Generality > BestGenerality) {
2397 BestGenerality = Generality;
2401 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2402 OpInfo.ConstraintType = BestType;
2405 /// ComputeConstraintToUse - Determines the constraint code and constraint
2406 /// type to use for the specific AsmOperandInfo, setting
2407 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2408 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2410 SelectionDAG *DAG) const {
2411 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2413 // Single-letter constraints ('r') are very common.
2414 if (OpInfo.Codes.size() == 1) {
2415 OpInfo.ConstraintCode = OpInfo.Codes[0];
2416 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2418 ChooseConstraint(OpInfo, *this, Op, DAG);
2421 // 'X' matches anything.
2422 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2423 // Labels and constants are handled elsewhere ('X' is the only thing
2424 // that matches labels). For Functions, the type here is the type of
2425 // the result, which is not what we want to look at; leave them alone.
2426 Value *v = OpInfo.CallOperandVal;
2427 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2428 OpInfo.CallOperandVal = v;
2432 // Otherwise, try to resolve it to something we know about by looking at
2433 // the actual operand type.
2434 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2435 OpInfo.ConstraintCode = Repl;
2436 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2441 /// \brief Given an exact SDIV by a constant, create a multiplication
2442 /// with the multiplicative inverse of the constant.
2443 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2444 SelectionDAG &DAG) const {
2445 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2446 APInt d = C->getAPIntValue();
2447 assert(d != 0 && "Division by zero!");
2449 // Shift the value upfront if it is even, so the LSB is one.
2450 unsigned ShAmt = d.countTrailingZeros();
2452 // TODO: For UDIV use SRL instead of SRA.
2453 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2454 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
2458 // Calculate the multiplicative inverse, using Newton's method.
2460 while ((t = d*xn) != 1)
2461 xn *= APInt(d.getBitWidth(), 2) - t;
2463 Op2 = DAG.getConstant(xn, Op1.getValueType());
2464 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2467 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2468 /// return a DAG expression to select that will generate the same value by
2469 /// multiplying by a magic number. See:
2470 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2471 SDValue TargetLowering::
2472 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2473 std::vector<SDNode*> *Created) const {
2474 EVT VT = N->getValueType(0);
2477 // Check to see if we can do this.
2478 // FIXME: We should be more aggressive here.
2479 if (!isTypeLegal(VT))
2482 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2483 APInt::ms magics = d.magic();
2485 // Multiply the numerator (operand 0) by the magic value
2486 // FIXME: We should support doing a MUL in a wider type
2488 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2489 isOperationLegalOrCustom(ISD::MULHS, VT))
2490 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2491 DAG.getConstant(magics.m, VT));
2492 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2493 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2494 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2496 DAG.getConstant(magics.m, VT)).getNode(), 1);
2498 return SDValue(); // No mulhs or equvialent
2499 // If d > 0 and m < 0, add the numerator
2500 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2501 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2503 Created->push_back(Q.getNode());
2505 // If d < 0 and m > 0, subtract the numerator.
2506 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2507 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2509 Created->push_back(Q.getNode());
2511 // Shift right algebraic if shift value is nonzero
2513 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2514 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2516 Created->push_back(Q.getNode());
2518 // Extract the sign bit and add it to the quotient
2520 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2521 getShiftAmountTy(Q.getValueType())));
2523 Created->push_back(T.getNode());
2524 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2527 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2528 /// return a DAG expression to select that will generate the same value by
2529 /// multiplying by a magic number. See:
2530 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2531 SDValue TargetLowering::
2532 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2533 std::vector<SDNode*> *Created) const {
2534 EVT VT = N->getValueType(0);
2537 // Check to see if we can do this.
2538 // FIXME: We should be more aggressive here.
2539 if (!isTypeLegal(VT))
2542 // FIXME: We should use a narrower constant when the upper
2543 // bits are known to be zero.
2544 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2545 APInt::mu magics = N1C.magicu();
2547 SDValue Q = N->getOperand(0);
2549 // If the divisor is even, we can avoid using the expensive fixup by shifting
2550 // the divided value upfront.
2551 if (magics.a != 0 && !N1C[0]) {
2552 unsigned Shift = N1C.countTrailingZeros();
2553 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2554 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2556 Created->push_back(Q.getNode());
2558 // Get magic number for the shifted divisor.
2559 magics = N1C.lshr(Shift).magicu(Shift);
2560 assert(magics.a == 0 && "Should use cheap fixup now");
2563 // Multiply the numerator (operand 0) by the magic value
2564 // FIXME: We should support doing a MUL in a wider type
2565 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2566 isOperationLegalOrCustom(ISD::MULHU, VT))
2567 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2568 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2569 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2570 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2571 DAG.getConstant(magics.m, VT)).getNode(), 1);
2573 return SDValue(); // No mulhu or equvialent
2575 Created->push_back(Q.getNode());
2577 if (magics.a == 0) {
2578 assert(magics.s < N1C.getBitWidth() &&
2579 "We shouldn't generate an undefined shift!");
2580 return DAG.getNode(ISD::SRL, dl, VT, Q,
2581 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2583 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2585 Created->push_back(NPQ.getNode());
2586 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2587 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2589 Created->push_back(NPQ.getNode());
2590 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2592 Created->push_back(NPQ.getNode());
2593 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2594 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));