1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtarget.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
34 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
45 return TLSModel::GeneralDynamic;
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
50 return TLSModel::InitialExec;
55 /// InitLibcallNames - Set default libcall names.
57 static void InitLibcallNames(const char **Names) {
58 Names[RTLIB::SHL_I16] = "__ashlhi3";
59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
61 Names[RTLIB::SHL_I128] = "__ashlti3";
62 Names[RTLIB::SRL_I16] = "__lshrhi3";
63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
65 Names[RTLIB::SRL_I128] = "__lshrti3";
66 Names[RTLIB::SRA_I16] = "__ashrhi3";
67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
69 Names[RTLIB::SRA_I128] = "__ashrti3";
70 Names[RTLIB::MUL_I8] = "__mulqi3";
71 Names[RTLIB::MUL_I16] = "__mulhi3";
72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
74 Names[RTLIB::MUL_I128] = "__multi3";
75 Names[RTLIB::SDIV_I8] = "__divqi3";
76 Names[RTLIB::SDIV_I16] = "__divhi3";
77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
79 Names[RTLIB::SDIV_I128] = "__divti3";
80 Names[RTLIB::UDIV_I8] = "__udivqi3";
81 Names[RTLIB::UDIV_I16] = "__udivhi3";
82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
84 Names[RTLIB::UDIV_I128] = "__udivti3";
85 Names[RTLIB::SREM_I8] = "__modqi3";
86 Names[RTLIB::SREM_I16] = "__modhi3";
87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
89 Names[RTLIB::SREM_I128] = "__modti3";
90 Names[RTLIB::UREM_I8] = "__umodqi3";
91 Names[RTLIB::UREM_I16] = "__umodhi3";
92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
94 Names[RTLIB::UREM_I128] = "__umodti3";
95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
99 Names[RTLIB::ADD_F80] = "__addxf3";
100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
103 Names[RTLIB::SUB_F80] = "__subxf3";
104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
107 Names[RTLIB::MUL_F80] = "__mulxf3";
108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
111 Names[RTLIB::DIV_F80] = "__divxf3";
112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
115 Names[RTLIB::REM_F80] = "fmodl";
116 Names[RTLIB::REM_PPCF128] = "fmodl";
117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
177 Names[RTLIB::COPYSIGN_F32] = "copysignf";
178 Names[RTLIB::COPYSIGN_F64] = "copysign";
179 Names[RTLIB::COPYSIGN_F80] = "copysignl";
180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
245 Names[RTLIB::OEQ_F32] = "__eqsf2";
246 Names[RTLIB::OEQ_F64] = "__eqdf2";
247 Names[RTLIB::UNE_F32] = "__nesf2";
248 Names[RTLIB::UNE_F64] = "__nedf2";
249 Names[RTLIB::OGE_F32] = "__gesf2";
250 Names[RTLIB::OGE_F64] = "__gedf2";
251 Names[RTLIB::OLT_F32] = "__ltsf2";
252 Names[RTLIB::OLT_F64] = "__ltdf2";
253 Names[RTLIB::OLE_F32] = "__lesf2";
254 Names[RTLIB::OLE_F64] = "__ledf2";
255 Names[RTLIB::OGT_F32] = "__gtsf2";
256 Names[RTLIB::OGT_F64] = "__gtdf2";
257 Names[RTLIB::UO_F32] = "__unordsf2";
258 Names[RTLIB::UO_F64] = "__unorddf2";
259 Names[RTLIB::O_F32] = "__unordsf2";
260 Names[RTLIB::O_F64] = "__unorddf2";
261 Names[RTLIB::MEMCPY] = "memcpy";
262 Names[RTLIB::MEMMOVE] = "memmove";
263 Names[RTLIB::MEMSET] = "memset";
264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
267 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
269 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
270 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
271 CCs[i] = CallingConv::C;
275 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
276 /// UNKNOWN_LIBCALL if there is none.
277 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
278 if (OpVT == MVT::f32) {
279 if (RetVT == MVT::f64)
280 return FPEXT_F32_F64;
283 return UNKNOWN_LIBCALL;
286 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
287 /// UNKNOWN_LIBCALL if there is none.
288 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
289 if (RetVT == MVT::f32) {
290 if (OpVT == MVT::f64)
291 return FPROUND_F64_F32;
292 if (OpVT == MVT::f80)
293 return FPROUND_F80_F32;
294 if (OpVT == MVT::ppcf128)
295 return FPROUND_PPCF128_F32;
296 } else if (RetVT == MVT::f64) {
297 if (OpVT == MVT::f80)
298 return FPROUND_F80_F64;
299 if (OpVT == MVT::ppcf128)
300 return FPROUND_PPCF128_F64;
303 return UNKNOWN_LIBCALL;
306 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
307 /// UNKNOWN_LIBCALL if there is none.
308 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
309 if (OpVT == MVT::f32) {
310 if (RetVT == MVT::i8)
311 return FPTOSINT_F32_I8;
312 if (RetVT == MVT::i16)
313 return FPTOSINT_F32_I16;
314 if (RetVT == MVT::i32)
315 return FPTOSINT_F32_I32;
316 if (RetVT == MVT::i64)
317 return FPTOSINT_F32_I64;
318 if (RetVT == MVT::i128)
319 return FPTOSINT_F32_I128;
320 } else if (OpVT == MVT::f64) {
321 if (RetVT == MVT::i8)
322 return FPTOSINT_F64_I8;
323 if (RetVT == MVT::i16)
324 return FPTOSINT_F64_I16;
325 if (RetVT == MVT::i32)
326 return FPTOSINT_F64_I32;
327 if (RetVT == MVT::i64)
328 return FPTOSINT_F64_I64;
329 if (RetVT == MVT::i128)
330 return FPTOSINT_F64_I128;
331 } else if (OpVT == MVT::f80) {
332 if (RetVT == MVT::i32)
333 return FPTOSINT_F80_I32;
334 if (RetVT == MVT::i64)
335 return FPTOSINT_F80_I64;
336 if (RetVT == MVT::i128)
337 return FPTOSINT_F80_I128;
338 } else if (OpVT == MVT::ppcf128) {
339 if (RetVT == MVT::i32)
340 return FPTOSINT_PPCF128_I32;
341 if (RetVT == MVT::i64)
342 return FPTOSINT_PPCF128_I64;
343 if (RetVT == MVT::i128)
344 return FPTOSINT_PPCF128_I128;
346 return UNKNOWN_LIBCALL;
349 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
350 /// UNKNOWN_LIBCALL if there is none.
351 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
352 if (OpVT == MVT::f32) {
353 if (RetVT == MVT::i8)
354 return FPTOUINT_F32_I8;
355 if (RetVT == MVT::i16)
356 return FPTOUINT_F32_I16;
357 if (RetVT == MVT::i32)
358 return FPTOUINT_F32_I32;
359 if (RetVT == MVT::i64)
360 return FPTOUINT_F32_I64;
361 if (RetVT == MVT::i128)
362 return FPTOUINT_F32_I128;
363 } else if (OpVT == MVT::f64) {
364 if (RetVT == MVT::i8)
365 return FPTOUINT_F64_I8;
366 if (RetVT == MVT::i16)
367 return FPTOUINT_F64_I16;
368 if (RetVT == MVT::i32)
369 return FPTOUINT_F64_I32;
370 if (RetVT == MVT::i64)
371 return FPTOUINT_F64_I64;
372 if (RetVT == MVT::i128)
373 return FPTOUINT_F64_I128;
374 } else if (OpVT == MVT::f80) {
375 if (RetVT == MVT::i32)
376 return FPTOUINT_F80_I32;
377 if (RetVT == MVT::i64)
378 return FPTOUINT_F80_I64;
379 if (RetVT == MVT::i128)
380 return FPTOUINT_F80_I128;
381 } else if (OpVT == MVT::ppcf128) {
382 if (RetVT == MVT::i32)
383 return FPTOUINT_PPCF128_I32;
384 if (RetVT == MVT::i64)
385 return FPTOUINT_PPCF128_I64;
386 if (RetVT == MVT::i128)
387 return FPTOUINT_PPCF128_I128;
389 return UNKNOWN_LIBCALL;
392 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
393 /// UNKNOWN_LIBCALL if there is none.
394 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
395 if (OpVT == MVT::i32) {
396 if (RetVT == MVT::f32)
397 return SINTTOFP_I32_F32;
398 else if (RetVT == MVT::f64)
399 return SINTTOFP_I32_F64;
400 else if (RetVT == MVT::f80)
401 return SINTTOFP_I32_F80;
402 else if (RetVT == MVT::ppcf128)
403 return SINTTOFP_I32_PPCF128;
404 } else if (OpVT == MVT::i64) {
405 if (RetVT == MVT::f32)
406 return SINTTOFP_I64_F32;
407 else if (RetVT == MVT::f64)
408 return SINTTOFP_I64_F64;
409 else if (RetVT == MVT::f80)
410 return SINTTOFP_I64_F80;
411 else if (RetVT == MVT::ppcf128)
412 return SINTTOFP_I64_PPCF128;
413 } else if (OpVT == MVT::i128) {
414 if (RetVT == MVT::f32)
415 return SINTTOFP_I128_F32;
416 else if (RetVT == MVT::f64)
417 return SINTTOFP_I128_F64;
418 else if (RetVT == MVT::f80)
419 return SINTTOFP_I128_F80;
420 else if (RetVT == MVT::ppcf128)
421 return SINTTOFP_I128_PPCF128;
423 return UNKNOWN_LIBCALL;
426 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
427 /// UNKNOWN_LIBCALL if there is none.
428 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
429 if (OpVT == MVT::i32) {
430 if (RetVT == MVT::f32)
431 return UINTTOFP_I32_F32;
432 else if (RetVT == MVT::f64)
433 return UINTTOFP_I32_F64;
434 else if (RetVT == MVT::f80)
435 return UINTTOFP_I32_F80;
436 else if (RetVT == MVT::ppcf128)
437 return UINTTOFP_I32_PPCF128;
438 } else if (OpVT == MVT::i64) {
439 if (RetVT == MVT::f32)
440 return UINTTOFP_I64_F32;
441 else if (RetVT == MVT::f64)
442 return UINTTOFP_I64_F64;
443 else if (RetVT == MVT::f80)
444 return UINTTOFP_I64_F80;
445 else if (RetVT == MVT::ppcf128)
446 return UINTTOFP_I64_PPCF128;
447 } else if (OpVT == MVT::i128) {
448 if (RetVT == MVT::f32)
449 return UINTTOFP_I128_F32;
450 else if (RetVT == MVT::f64)
451 return UINTTOFP_I128_F64;
452 else if (RetVT == MVT::f80)
453 return UINTTOFP_I128_F80;
454 else if (RetVT == MVT::ppcf128)
455 return UINTTOFP_I128_PPCF128;
457 return UNKNOWN_LIBCALL;
460 /// InitCmpLibcallCCs - Set default comparison libcall CC.
462 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
463 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
464 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
465 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
466 CCs[RTLIB::UNE_F32] = ISD::SETNE;
467 CCs[RTLIB::UNE_F64] = ISD::SETNE;
468 CCs[RTLIB::OGE_F32] = ISD::SETGE;
469 CCs[RTLIB::OGE_F64] = ISD::SETGE;
470 CCs[RTLIB::OLT_F32] = ISD::SETLT;
471 CCs[RTLIB::OLT_F64] = ISD::SETLT;
472 CCs[RTLIB::OLE_F32] = ISD::SETLE;
473 CCs[RTLIB::OLE_F64] = ISD::SETLE;
474 CCs[RTLIB::OGT_F32] = ISD::SETGT;
475 CCs[RTLIB::OGT_F64] = ISD::SETGT;
476 CCs[RTLIB::UO_F32] = ISD::SETNE;
477 CCs[RTLIB::UO_F64] = ISD::SETNE;
478 CCs[RTLIB::O_F32] = ISD::SETEQ;
479 CCs[RTLIB::O_F64] = ISD::SETEQ;
482 /// NOTE: The constructor takes ownership of TLOF.
483 TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
484 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
485 // All operations default to being supported.
486 memset(OpActions, 0, sizeof(OpActions));
487 memset(LoadExtActions, 0, sizeof(LoadExtActions));
488 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
489 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
490 memset(CondCodeActions, 0, sizeof(CondCodeActions));
492 // Set default actions for various operations.
493 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
494 // Default all indexed load / store to expand.
495 for (unsigned IM = (unsigned)ISD::PRE_INC;
496 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
497 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
498 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
501 // These operations default to expand.
502 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
503 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
506 // Most targets ignore the @llvm.prefetch intrinsic.
507 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
509 // ConstantFP nodes default to expand. Targets can either change this to
510 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
511 // to optimize expansions for certain constants.
512 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
513 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
514 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
516 // These library functions default to expand.
517 setOperationAction(ISD::FLOG , MVT::f64, Expand);
518 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
519 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
520 setOperationAction(ISD::FEXP , MVT::f64, Expand);
521 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
522 setOperationAction(ISD::FLOG , MVT::f32, Expand);
523 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
524 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
525 setOperationAction(ISD::FEXP , MVT::f32, Expand);
526 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
528 // Default ISD::TRAP to expand (which turns it into abort).
529 setOperationAction(ISD::TRAP, MVT::Other, Expand);
531 IsLittleEndian = TD->isLittleEndian();
532 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
533 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
534 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
535 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
536 benefitFromCodePlacementOpt = false;
537 UseUnderscoreSetJmp = false;
538 UseUnderscoreLongJmp = false;
539 SelectIsExpensive = false;
540 IntDivIsCheap = false;
541 Pow2DivIsCheap = false;
542 StackPointerRegisterToSaveRestore = 0;
543 ExceptionPointerRegister = 0;
544 ExceptionSelectorRegister = 0;
545 BooleanContents = UndefinedBooleanContent;
546 SchedPreferenceInfo = SchedulingForLatency;
548 JumpBufAlignment = 0;
549 IfCvtBlockSizeLimit = 2;
550 IfCvtDupBlockSizeLimit = 0;
551 PrefLoopAlignment = 0;
553 InitLibcallNames(LibcallRoutineNames);
554 InitCmpLibcallCCs(CmpLibcallCCs);
555 InitLibcallCallingConvs(LibcallCallingConvs);
558 TargetLowering::~TargetLowering() {
562 /// canOpTrap - Returns true if the operation can trap for the value type.
563 /// VT must be a legal type.
564 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
565 assert(isTypeLegal(VT));
580 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
581 unsigned &NumIntermediates,
583 TargetLowering* TLI) {
584 // Figure out the right, legal destination reg to copy into.
585 unsigned NumElts = VT.getVectorNumElements();
586 MVT EltTy = VT.getVectorElementType();
588 unsigned NumVectorRegs = 1;
590 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
591 // could break down into LHS/RHS like LegalizeDAG does.
592 if (!isPowerOf2_32(NumElts)) {
593 NumVectorRegs = NumElts;
597 // Divide the input until we get to a supported size. This will always
598 // end with a scalar if the target doesn't support vectors.
599 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
604 NumIntermediates = NumVectorRegs;
606 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
607 if (!TLI->isTypeLegal(NewVT))
609 IntermediateVT = NewVT;
611 EVT DestVT = TLI->getRegisterType(NewVT);
613 if (EVT(DestVT).bitsLT(NewVT)) {
614 // Value is expanded, e.g. i64 -> i16.
615 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
617 // Otherwise, promotion or legal types use the same number of registers as
618 // the vector decimated to the appropriate level.
619 return NumVectorRegs;
625 /// computeRegisterProperties - Once all of the register classes are added,
626 /// this allows us to compute derived properties we expose.
627 void TargetLowering::computeRegisterProperties() {
628 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
629 "Too many value types for ValueTypeActions to hold!");
631 // Everything defaults to needing one register.
632 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
633 NumRegistersForVT[i] = 1;
634 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
636 // ...except isVoid, which doesn't need any registers.
637 NumRegistersForVT[MVT::isVoid] = 0;
639 // Find the largest integer register class.
640 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
641 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
642 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
644 // Every integer value type larger than this largest register takes twice as
645 // many registers to represent as the previous ValueType.
646 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
647 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
648 if (!ExpandedVT.isInteger())
650 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
651 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
652 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
653 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
656 // Inspect all of the ValueType's smaller than the largest integer
657 // register to see which ones need promotion.
658 unsigned LegalIntReg = LargestIntReg;
659 for (unsigned IntReg = LargestIntReg - 1;
660 IntReg >= (unsigned)MVT::i1; --IntReg) {
661 EVT IVT = (MVT::SimpleValueType)IntReg;
662 if (isTypeLegal(IVT)) {
663 LegalIntReg = IntReg;
665 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
666 (MVT::SimpleValueType)LegalIntReg;
667 ValueTypeActions.setTypeAction(IVT, Promote);
671 // ppcf128 type is really two f64's.
672 if (!isTypeLegal(MVT::ppcf128)) {
673 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
674 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
675 TransformToType[MVT::ppcf128] = MVT::f64;
676 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
679 // Decide how to handle f64. If the target does not have native f64 support,
680 // expand it to i64 and we will be generating soft float library calls.
681 if (!isTypeLegal(MVT::f64)) {
682 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
683 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
684 TransformToType[MVT::f64] = MVT::i64;
685 ValueTypeActions.setTypeAction(MVT::f64, Expand);
688 // Decide how to handle f32. If the target does not have native support for
689 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
690 if (!isTypeLegal(MVT::f32)) {
691 if (isTypeLegal(MVT::f64)) {
692 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
693 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
694 TransformToType[MVT::f32] = MVT::f64;
695 ValueTypeActions.setTypeAction(MVT::f32, Promote);
697 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
698 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
699 TransformToType[MVT::f32] = MVT::i32;
700 ValueTypeActions.setTypeAction(MVT::f32, Expand);
704 // Loop over all of the vector value types to see which need transformations.
705 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
706 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
707 MVT VT = (MVT::SimpleValueType)i;
708 if (!isTypeLegal(VT)) {
711 unsigned NumIntermediates;
712 NumRegistersForVT[i] =
713 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
715 RegisterTypeForVT[i] = RegisterVT;
717 // Determine if there is a legal wider type.
718 bool IsLegalWiderType = false;
719 EVT EltVT = VT.getVectorElementType();
720 unsigned NElts = VT.getVectorNumElements();
721 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
722 EVT SVT = (MVT::SimpleValueType)nVT;
723 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
724 SVT.getVectorNumElements() > NElts && NElts != 1) {
725 TransformToType[i] = SVT;
726 ValueTypeActions.setTypeAction(VT, Promote);
727 IsLegalWiderType = true;
731 if (!IsLegalWiderType) {
732 EVT NVT = VT.getPow2VectorType();
734 // Type is already a power of 2. The default action is to split.
735 TransformToType[i] = MVT::Other;
736 ValueTypeActions.setTypeAction(VT, Expand);
738 TransformToType[i] = NVT;
739 ValueTypeActions.setTypeAction(VT, Promote);
746 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
751 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
752 return PointerTy.SimpleTy;
755 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
756 return MVT::i32; // return the default value
759 /// getVectorTypeBreakdown - Vector types are broken down into some number of
760 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
761 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
762 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
764 /// This method returns the number of registers needed, and the VT for each
765 /// register. It also returns the VT and quantity of the intermediate values
766 /// before they are promoted/expanded.
768 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
770 unsigned &NumIntermediates,
771 EVT &RegisterVT) const {
772 // Figure out the right, legal destination reg to copy into.
773 unsigned NumElts = VT.getVectorNumElements();
774 EVT EltTy = VT.getVectorElementType();
776 unsigned NumVectorRegs = 1;
778 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
779 // could break down into LHS/RHS like LegalizeDAG does.
780 if (!isPowerOf2_32(NumElts)) {
781 NumVectorRegs = NumElts;
785 // Divide the input until we get to a supported size. This will always
786 // end with a scalar if the target doesn't support vectors.
787 while (NumElts > 1 && !isTypeLegal(
788 EVT::getVectorVT(Context, EltTy, NumElts))) {
793 NumIntermediates = NumVectorRegs;
795 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
796 if (!isTypeLegal(NewVT))
798 IntermediateVT = NewVT;
800 EVT DestVT = getRegisterType(Context, NewVT);
802 if (DestVT.bitsLT(NewVT)) {
803 // Value is expanded, e.g. i64 -> i16.
804 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
806 // Otherwise, promotion or legal types use the same number of registers as
807 // the vector decimated to the appropriate level.
808 return NumVectorRegs;
814 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
815 /// function arguments in the caller parameter area. This is the actual
816 /// alignment, not its logarithm.
817 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
818 return TD->getCallFrameTypeAlignment(Ty);
821 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
822 /// current function. The returned value is a member of the
823 /// MachineJumpTableInfo::JTEntryKind enum.
824 unsigned TargetLowering::getJumpTableEncoding() const {
825 // In non-pic modes, just use the address of a block.
826 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
827 return MachineJumpTableInfo::EK_BlockAddress;
829 // In PIC mode, if the target supports a GPRel32 directive, use it.
830 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
831 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
833 // Otherwise, use a label difference.
834 return MachineJumpTableInfo::EK_LabelDifference32;
837 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
838 SelectionDAG &DAG) const {
839 // If our PIC model is GP relative, use the global offset table as the base.
840 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
841 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
845 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
846 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
849 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
850 unsigned JTI,MCContext &Ctx) const{
851 // The normal PIC reloc base is the label at the start of the jump table.
852 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
856 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
857 // Assume that everything is safe in static mode.
858 if (getTargetMachine().getRelocationModel() == Reloc::Static)
861 // In dynamic-no-pic mode, assume that known defined values are safe.
862 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
864 !GA->getGlobal()->isDeclaration() &&
865 !GA->getGlobal()->isWeakForLinker())
868 // Otherwise assume nothing is safe.
872 //===----------------------------------------------------------------------===//
873 // Optimization Methods
874 //===----------------------------------------------------------------------===//
876 /// ShrinkDemandedConstant - Check to see if the specified operand of the
877 /// specified instruction is a constant integer. If so, check to see if there
878 /// are any bits set in the constant that are not demanded. If so, shrink the
879 /// constant and return true.
880 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
881 const APInt &Demanded) {
882 DebugLoc dl = Op.getDebugLoc();
884 // FIXME: ISD::SELECT, ISD::SELECT_CC
885 switch (Op.getOpcode()) {
890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
891 if (!C) return false;
893 if (Op.getOpcode() == ISD::XOR &&
894 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
897 // if we can expand it to have all bits set, do it
898 if (C->getAPIntValue().intersects(~Demanded)) {
899 EVT VT = Op.getValueType();
900 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
901 DAG.getConstant(Demanded &
904 return CombineTo(Op, New);
914 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
915 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
916 /// cast, but it could be generalized for targets with other types of
917 /// implicit widening casts.
919 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
921 const APInt &Demanded,
923 assert(Op.getNumOperands() == 2 &&
924 "ShrinkDemandedOp only supports binary operators!");
925 assert(Op.getNode()->getNumValues() == 1 &&
926 "ShrinkDemandedOp only supports nodes with one result!");
928 // Don't do this if the node has another user, which may require the
930 if (!Op.getNode()->hasOneUse())
933 // Search for the smallest integer type with free casts to and from
934 // Op's type. For expedience, just check power-of-2 integer types.
935 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
936 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
937 if (!isPowerOf2_32(SmallVTBits))
938 SmallVTBits = NextPowerOf2(SmallVTBits);
939 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
940 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
941 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
942 TLI.isZExtFree(SmallVT, Op.getValueType())) {
943 // We found a type with free casts.
944 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
945 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
946 Op.getNode()->getOperand(0)),
947 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
948 Op.getNode()->getOperand(1)));
949 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
950 return CombineTo(Op, Z);
956 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
957 /// DemandedMask bits of the result of Op are ever used downstream. If we can
958 /// use this information to simplify Op, create a new simplified DAG node and
959 /// return true, returning the original and new nodes in Old and New. Otherwise,
960 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
961 /// the expression (used to simplify the caller). The KnownZero/One bits may
962 /// only be accurate for those bits in the DemandedMask.
963 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
964 const APInt &DemandedMask,
967 TargetLoweringOpt &TLO,
968 unsigned Depth) const {
969 unsigned BitWidth = DemandedMask.getBitWidth();
970 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
971 "Mask size mismatches value type size!");
972 APInt NewMask = DemandedMask;
973 DebugLoc dl = Op.getDebugLoc();
975 // Don't know anything.
976 KnownZero = KnownOne = APInt(BitWidth, 0);
978 // Other users may use these bits.
979 if (!Op.getNode()->hasOneUse()) {
981 // If not at the root, Just compute the KnownZero/KnownOne bits to
982 // simplify things downstream.
983 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
986 // If this is the root being simplified, allow it to have multiple uses,
987 // just set the NewMask to all bits.
988 NewMask = APInt::getAllOnesValue(BitWidth);
989 } else if (DemandedMask == 0) {
990 // Not demanding any bits from Op.
991 if (Op.getOpcode() != ISD::UNDEF)
992 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
994 } else if (Depth == 6) { // Limit search depth.
998 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
999 switch (Op.getOpcode()) {
1001 // We know all of the bits for a constant!
1002 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1003 KnownZero = ~KnownOne & NewMask;
1004 return false; // Don't fall through, will infinitely loop.
1006 // If the RHS is a constant, check to see if the LHS would be zero without
1007 // using the bits from the RHS. Below, we use knowledge about the RHS to
1008 // simplify the LHS, here we're using information from the LHS to simplify
1010 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1011 APInt LHSZero, LHSOne;
1012 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
1013 LHSZero, LHSOne, Depth+1);
1014 // If the LHS already has zeros where RHSC does, this and is dead.
1015 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1016 return TLO.CombineTo(Op, Op.getOperand(0));
1017 // If any of the set bits in the RHS are known zero on the LHS, shrink
1019 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1023 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1024 KnownOne, TLO, Depth+1))
1026 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1027 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1028 KnownZero2, KnownOne2, TLO, Depth+1))
1030 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1032 // If all of the demanded bits are known one on one side, return the other.
1033 // These bits cannot contribute to the result of the 'and'.
1034 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1035 return TLO.CombineTo(Op, Op.getOperand(0));
1036 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1037 return TLO.CombineTo(Op, Op.getOperand(1));
1038 // If all of the demanded bits in the inputs are known zeros, return zero.
1039 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1040 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1041 // If the RHS is a constant, see if we can simplify it.
1042 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1044 // If the operation can be done in a smaller type, do so.
1045 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1048 // Output known-1 bits are only known if set in both the LHS & RHS.
1049 KnownOne &= KnownOne2;
1050 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1051 KnownZero |= KnownZero2;
1054 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1055 KnownOne, TLO, Depth+1))
1057 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1058 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1059 KnownZero2, KnownOne2, TLO, Depth+1))
1061 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1063 // If all of the demanded bits are known zero on one side, return the other.
1064 // These bits cannot contribute to the result of the 'or'.
1065 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1066 return TLO.CombineTo(Op, Op.getOperand(0));
1067 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1068 return TLO.CombineTo(Op, Op.getOperand(1));
1069 // If all of the potentially set bits on one side are known to be set on
1070 // the other side, just use the 'other' side.
1071 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1072 return TLO.CombineTo(Op, Op.getOperand(0));
1073 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1074 return TLO.CombineTo(Op, Op.getOperand(1));
1075 // If the RHS is a constant, see if we can simplify it.
1076 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1078 // If the operation can be done in a smaller type, do so.
1079 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1082 // Output known-0 bits are only known if clear in both the LHS & RHS.
1083 KnownZero &= KnownZero2;
1084 // Output known-1 are known to be set if set in either the LHS | RHS.
1085 KnownOne |= KnownOne2;
1088 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1089 KnownOne, TLO, Depth+1))
1091 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1092 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1093 KnownOne2, TLO, Depth+1))
1095 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1097 // If all of the demanded bits are known zero on one side, return the other.
1098 // These bits cannot contribute to the result of the 'xor'.
1099 if ((KnownZero & NewMask) == NewMask)
1100 return TLO.CombineTo(Op, Op.getOperand(0));
1101 if ((KnownZero2 & NewMask) == NewMask)
1102 return TLO.CombineTo(Op, Op.getOperand(1));
1103 // If the operation can be done in a smaller type, do so.
1104 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1107 // If all of the unknown bits are known to be zero on one side or the other
1108 // (but not both) turn this into an *inclusive* or.
1109 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1110 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1111 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1115 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1116 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1117 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1118 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1120 // If all of the demanded bits on one side are known, and all of the set
1121 // bits on that side are also known to be set on the other side, turn this
1122 // into an AND, as we know the bits will be cleared.
1123 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1124 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1125 if ((KnownOne & KnownOne2) == KnownOne) {
1126 EVT VT = Op.getValueType();
1127 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1128 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1129 Op.getOperand(0), ANDC));
1133 // If the RHS is a constant, see if we can simplify it.
1134 // for XOR, we prefer to force bits to 1 if they will make a -1.
1135 // if we can't force bits, try to shrink constant
1136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1137 APInt Expanded = C->getAPIntValue() | (~NewMask);
1138 // if we can expand it to have all bits set, do it
1139 if (Expanded.isAllOnesValue()) {
1140 if (Expanded != C->getAPIntValue()) {
1141 EVT VT = Op.getValueType();
1142 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1143 TLO.DAG.getConstant(Expanded, VT));
1144 return TLO.CombineTo(Op, New);
1146 // if it already has all the bits set, nothing to change
1147 // but don't shrink either!
1148 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1153 KnownZero = KnownZeroOut;
1154 KnownOne = KnownOneOut;
1157 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1158 KnownOne, TLO, Depth+1))
1160 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1161 KnownOne2, TLO, Depth+1))
1163 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1164 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1166 // If the operands are constants, see if we can simplify them.
1167 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1170 // Only known if known in both the LHS and RHS.
1171 KnownOne &= KnownOne2;
1172 KnownZero &= KnownZero2;
1174 case ISD::SELECT_CC:
1175 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1176 KnownOne, TLO, Depth+1))
1178 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1179 KnownOne2, TLO, Depth+1))
1181 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1182 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1184 // If the operands are constants, see if we can simplify them.
1185 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1188 // Only known if known in both the LHS and RHS.
1189 KnownOne &= KnownOne2;
1190 KnownZero &= KnownZero2;
1193 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1194 unsigned ShAmt = SA->getZExtValue();
1195 SDValue InOp = Op.getOperand(0);
1197 // If the shift count is an invalid immediate, don't do anything.
1198 if (ShAmt >= BitWidth)
1201 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1202 // single shift. We can do this if the bottom bits (which are shifted
1203 // out) are never demanded.
1204 if (InOp.getOpcode() == ISD::SRL &&
1205 isa<ConstantSDNode>(InOp.getOperand(1))) {
1206 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1207 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1208 unsigned Opc = ISD::SHL;
1209 int Diff = ShAmt-C1;
1216 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1217 EVT VT = Op.getValueType();
1218 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1219 InOp.getOperand(0), NewSA));
1223 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1224 KnownZero, KnownOne, TLO, Depth+1))
1226 KnownZero <<= SA->getZExtValue();
1227 KnownOne <<= SA->getZExtValue();
1228 // low bits known zero.
1229 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1233 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1234 EVT VT = Op.getValueType();
1235 unsigned ShAmt = SA->getZExtValue();
1236 unsigned VTSize = VT.getSizeInBits();
1237 SDValue InOp = Op.getOperand(0);
1239 // If the shift count is an invalid immediate, don't do anything.
1240 if (ShAmt >= BitWidth)
1243 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1244 // single shift. We can do this if the top bits (which are shifted out)
1245 // are never demanded.
1246 if (InOp.getOpcode() == ISD::SHL &&
1247 isa<ConstantSDNode>(InOp.getOperand(1))) {
1248 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1249 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1250 unsigned Opc = ISD::SRL;
1251 int Diff = ShAmt-C1;
1258 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1259 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1260 InOp.getOperand(0), NewSA));
1264 // Compute the new bits that are at the top now.
1265 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1266 KnownZero, KnownOne, TLO, Depth+1))
1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1269 KnownZero = KnownZero.lshr(ShAmt);
1270 KnownOne = KnownOne.lshr(ShAmt);
1272 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1273 KnownZero |= HighBits; // High bits known zero.
1277 // If this is an arithmetic shift right and only the low-bit is set, we can
1278 // always convert this into a logical shr, even if the shift amount is
1279 // variable. The low bit of the shift cannot be an input sign bit unless
1280 // the shift amount is >= the size of the datatype, which is undefined.
1281 if (DemandedMask == 1)
1282 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1283 Op.getOperand(0), Op.getOperand(1)));
1285 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1286 EVT VT = Op.getValueType();
1287 unsigned ShAmt = SA->getZExtValue();
1289 // If the shift count is an invalid immediate, don't do anything.
1290 if (ShAmt >= BitWidth)
1293 APInt InDemandedMask = (NewMask << ShAmt);
1295 // If any of the demanded bits are produced by the sign extension, we also
1296 // demand the input sign bit.
1297 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1298 if (HighBits.intersects(NewMask))
1299 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1301 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1302 KnownZero, KnownOne, TLO, Depth+1))
1304 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1305 KnownZero = KnownZero.lshr(ShAmt);
1306 KnownOne = KnownOne.lshr(ShAmt);
1308 // Handle the sign bit, adjusted to where it is now in the mask.
1309 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1311 // If the input sign bit is known to be zero, or if none of the top bits
1312 // are demanded, turn this into an unsigned shift right.
1313 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1314 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1317 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1318 KnownOne |= HighBits;
1322 case ISD::SIGN_EXTEND_INREG: {
1323 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1325 // Sign extension. Compute the demanded bits in the result that are not
1326 // present in the input.
1328 APInt::getHighBitsSet(BitWidth,
1329 BitWidth - EVT.getScalarType().getSizeInBits()) &
1332 // If none of the extended bits are demanded, eliminate the sextinreg.
1334 return TLO.CombineTo(Op, Op.getOperand(0));
1336 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1337 InSignBit.zext(BitWidth);
1338 APInt InputDemandedBits =
1339 APInt::getLowBitsSet(BitWidth,
1340 EVT.getScalarType().getSizeInBits()) &
1343 // Since the sign extended bits are demanded, we know that the sign
1345 InputDemandedBits |= InSignBit;
1347 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1348 KnownZero, KnownOne, TLO, Depth+1))
1350 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1352 // If the sign bit of the input is known set or clear, then we know the
1353 // top bits of the result.
1355 // If the input sign bit is known zero, convert this into a zero extension.
1356 if (KnownZero.intersects(InSignBit))
1357 return TLO.CombineTo(Op,
1358 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1360 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1361 KnownOne |= NewBits;
1362 KnownZero &= ~NewBits;
1363 } else { // Input sign bit unknown
1364 KnownZero &= ~NewBits;
1365 KnownOne &= ~NewBits;
1369 case ISD::ZERO_EXTEND: {
1370 unsigned OperandBitWidth =
1371 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1372 APInt InMask = NewMask;
1373 InMask.trunc(OperandBitWidth);
1375 // If none of the top bits are demanded, convert this into an any_extend.
1377 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1378 if (!NewBits.intersects(NewMask))
1379 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1383 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1384 KnownZero, KnownOne, TLO, Depth+1))
1386 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1387 KnownZero.zext(BitWidth);
1388 KnownOne.zext(BitWidth);
1389 KnownZero |= NewBits;
1392 case ISD::SIGN_EXTEND: {
1393 EVT InVT = Op.getOperand(0).getValueType();
1394 unsigned InBits = InVT.getScalarType().getSizeInBits();
1395 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1396 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1397 APInt NewBits = ~InMask & NewMask;
1399 // If none of the top bits are demanded, convert this into an any_extend.
1401 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1405 // Since some of the sign extended bits are demanded, we know that the sign
1407 APInt InDemandedBits = InMask & NewMask;
1408 InDemandedBits |= InSignBit;
1409 InDemandedBits.trunc(InBits);
1411 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1412 KnownOne, TLO, Depth+1))
1414 KnownZero.zext(BitWidth);
1415 KnownOne.zext(BitWidth);
1417 // If the sign bit is known zero, convert this to a zero extend.
1418 if (KnownZero.intersects(InSignBit))
1419 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1423 // If the sign bit is known one, the top bits match.
1424 if (KnownOne.intersects(InSignBit)) {
1425 KnownOne |= NewBits;
1426 KnownZero &= ~NewBits;
1427 } else { // Otherwise, top bits aren't known.
1428 KnownOne &= ~NewBits;
1429 KnownZero &= ~NewBits;
1433 case ISD::ANY_EXTEND: {
1434 unsigned OperandBitWidth =
1435 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1436 APInt InMask = NewMask;
1437 InMask.trunc(OperandBitWidth);
1438 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1439 KnownZero, KnownOne, TLO, Depth+1))
1441 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1442 KnownZero.zext(BitWidth);
1443 KnownOne.zext(BitWidth);
1446 case ISD::TRUNCATE: {
1447 // Simplify the input, using demanded bit information, and compute the known
1448 // zero/one bits live out.
1449 unsigned OperandBitWidth =
1450 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1451 APInt TruncMask = NewMask;
1452 TruncMask.zext(OperandBitWidth);
1453 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1454 KnownZero, KnownOne, TLO, Depth+1))
1456 KnownZero.trunc(BitWidth);
1457 KnownOne.trunc(BitWidth);
1459 // If the input is only used by this truncate, see if we can shrink it based
1460 // on the known demanded bits.
1461 if (Op.getOperand(0).getNode()->hasOneUse()) {
1462 SDValue In = Op.getOperand(0);
1463 switch (In.getOpcode()) {
1466 // Shrink SRL by a constant if none of the high bits shifted in are
1468 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1469 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1470 OperandBitWidth - BitWidth);
1471 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1472 HighBits.trunc(BitWidth);
1474 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1475 // None of the shifted in bits are needed. Add a truncate of the
1476 // shift input, then shift it.
1477 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1480 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1490 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1493 case ISD::AssertZext: {
1494 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1495 APInt InMask = APInt::getLowBitsSet(BitWidth,
1496 VT.getSizeInBits());
1497 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1498 KnownZero, KnownOne, TLO, Depth+1))
1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1501 KnownZero |= ~InMask & NewMask;
1504 case ISD::BIT_CONVERT:
1506 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1507 // is demanded, turn this into a FGETSIGN.
1508 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1509 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1510 !MVT::isVector(Op.getOperand(0).getValueType())) {
1511 // Only do this xform if FGETSIGN is valid or if before legalize.
1512 if (!TLO.AfterLegalize ||
1513 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1514 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1515 // place. We expect the SHL to be eliminated by other optimizations.
1516 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1518 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1519 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1529 // Add, Sub, and Mul don't demand any bits in positions beyond that
1530 // of the highest bit demanded of them.
1531 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1532 BitWidth - NewMask.countLeadingZeros());
1533 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1534 KnownOne2, TLO, Depth+1))
1536 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1537 KnownOne2, TLO, Depth+1))
1539 // See if the operation should be performed at a smaller bit width.
1540 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1545 // Just use ComputeMaskedBits to compute output bits.
1546 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1550 // If we know the value of all of the demanded bits, return this as a
1552 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1553 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1558 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1559 /// in Mask are known to be either zero or one and return them in the
1560 /// KnownZero/KnownOne bitsets.
1561 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1565 const SelectionDAG &DAG,
1566 unsigned Depth) const {
1567 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1568 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1569 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1570 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1571 "Should use MaskedValueIsZero if you don't know whether Op"
1572 " is a target node!");
1573 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1576 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1577 /// targets that want to expose additional information about sign bits to the
1579 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1580 unsigned Depth) const {
1581 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1582 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1583 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1584 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1585 "Should use ComputeNumSignBits if you don't know whether Op"
1586 " is a target node!");
1590 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1591 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1592 /// determine which bit is set.
1594 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1595 // A left-shift of a constant one will have exactly one bit set, because
1596 // shifting the bit off the end is undefined.
1597 if (Val.getOpcode() == ISD::SHL)
1598 if (ConstantSDNode *C =
1599 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1600 if (C->getAPIntValue() == 1)
1603 // Similarly, a right-shift of a constant sign-bit will have exactly
1605 if (Val.getOpcode() == ISD::SRL)
1606 if (ConstantSDNode *C =
1607 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1608 if (C->getAPIntValue().isSignBit())
1611 // More could be done here, though the above checks are enough
1612 // to handle some common cases.
1614 // Fall back to ComputeMaskedBits to catch other known cases.
1615 EVT OpVT = Val.getValueType();
1616 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1617 APInt Mask = APInt::getAllOnesValue(BitWidth);
1618 APInt KnownZero, KnownOne;
1619 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1620 return (KnownZero.countPopulation() == BitWidth - 1) &&
1621 (KnownOne.countPopulation() == 1);
1624 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1625 /// and cc. If it is unable to simplify it, return a null SDValue.
1627 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1628 ISD::CondCode Cond, bool foldBooleans,
1629 DAGCombinerInfo &DCI, DebugLoc dl) const {
1630 SelectionDAG &DAG = DCI.DAG;
1631 LLVMContext &Context = *DAG.getContext();
1633 // These setcc operations always fold.
1637 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1639 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1642 if (isa<ConstantSDNode>(N0.getNode())) {
1643 // Ensure that the constant occurs on the RHS, and fold constant
1645 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1648 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1649 const APInt &C1 = N1C->getAPIntValue();
1651 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1652 // equality comparison, then we're just comparing whether X itself is
1654 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1655 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1656 N0.getOperand(1).getOpcode() == ISD::Constant) {
1658 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1659 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1660 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1661 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1662 // (srl (ctlz x), 5) == 0 -> X != 0
1663 // (srl (ctlz x), 5) != 1 -> X != 0
1666 // (srl (ctlz x), 5) != 0 -> X == 0
1667 // (srl (ctlz x), 5) == 1 -> X == 0
1670 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1671 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1676 // If the LHS is '(and load, const)', the RHS is 0,
1677 // the test is for equality or unsigned, and all 1 bits of the const are
1678 // in the same partial word, see if we can shorten the load.
1679 if (DCI.isBeforeLegalize() &&
1680 N0.getOpcode() == ISD::AND && C1 == 0 &&
1681 N0.getNode()->hasOneUse() &&
1682 isa<LoadSDNode>(N0.getOperand(0)) &&
1683 N0.getOperand(0).getNode()->hasOneUse() &&
1684 isa<ConstantSDNode>(N0.getOperand(1))) {
1685 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1687 unsigned bestWidth = 0, bestOffset = 0;
1688 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1689 unsigned origWidth = N0.getValueType().getSizeInBits();
1690 unsigned maskWidth = origWidth;
1691 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1692 // 8 bits, but have to be careful...
1693 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1694 origWidth = Lod->getMemoryVT().getSizeInBits();
1696 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1697 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1698 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1699 for (unsigned offset=0; offset<origWidth/width; offset++) {
1700 if ((newMask & Mask) == Mask) {
1701 if (!TD->isLittleEndian())
1702 bestOffset = (origWidth/width - offset - 1) * (width/8);
1704 bestOffset = (uint64_t)offset * (width/8);
1705 bestMask = Mask.lshr(offset * (width/8) * 8);
1709 newMask = newMask << width;
1714 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1715 if (newVT.isRound()) {
1716 EVT PtrType = Lod->getOperand(1).getValueType();
1717 SDValue Ptr = Lod->getBasePtr();
1718 if (bestOffset != 0)
1719 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1720 DAG.getConstant(bestOffset, PtrType));
1721 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1722 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1724 Lod->getSrcValueOffset() + bestOffset,
1725 false, false, NewAlign);
1726 return DAG.getSetCC(dl, VT,
1727 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1728 DAG.getConstant(bestMask.trunc(bestWidth),
1730 DAG.getConstant(0LL, newVT), Cond);
1735 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1736 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1737 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1739 // If the comparison constant has bits in the upper part, the
1740 // zero-extended value could never match.
1741 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1742 C1.getBitWidth() - InSize))) {
1746 case ISD::SETEQ: return DAG.getConstant(0, VT);
1749 case ISD::SETNE: return DAG.getConstant(1, VT);
1752 // True if the sign bit of C1 is set.
1753 return DAG.getConstant(C1.isNegative(), VT);
1756 // True if the sign bit of C1 isn't set.
1757 return DAG.getConstant(C1.isNonNegative(), VT);
1763 // Otherwise, we can perform the comparison with the low bits.
1771 EVT newVT = N0.getOperand(0).getValueType();
1772 if (DCI.isBeforeLegalizeOps() ||
1773 (isOperationLegal(ISD::SETCC, newVT) &&
1774 getCondCodeAction(Cond, newVT)==Legal))
1775 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1776 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1781 break; // todo, be more careful with signed comparisons
1783 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1784 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1785 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1786 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1787 EVT ExtDstTy = N0.getValueType();
1788 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1790 // If the extended part has any inconsistent bits, it cannot ever
1791 // compare equal. In other words, they have to be all ones or all
1794 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1795 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1796 return DAG.getConstant(Cond == ISD::SETNE, VT);
1799 EVT Op0Ty = N0.getOperand(0).getValueType();
1800 if (Op0Ty == ExtSrcTy) {
1801 ZextOp = N0.getOperand(0);
1803 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1804 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1805 DAG.getConstant(Imm, Op0Ty));
1807 if (!DCI.isCalledByLegalizer())
1808 DCI.AddToWorklist(ZextOp.getNode());
1809 // Otherwise, make this a use of a zext.
1810 return DAG.getSetCC(dl, VT, ZextOp,
1811 DAG.getConstant(C1 & APInt::getLowBitsSet(
1816 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1817 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1818 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1819 if (N0.getOpcode() == ISD::SETCC &&
1820 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1821 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1823 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1824 // Invert the condition.
1825 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1826 CC = ISD::getSetCCInverse(CC,
1827 N0.getOperand(0).getValueType().isInteger());
1828 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1831 if ((N0.getOpcode() == ISD::XOR ||
1832 (N0.getOpcode() == ISD::AND &&
1833 N0.getOperand(0).getOpcode() == ISD::XOR &&
1834 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1835 isa<ConstantSDNode>(N0.getOperand(1)) &&
1836 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1837 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1838 // can only do this if the top bits are known zero.
1839 unsigned BitWidth = N0.getValueSizeInBits();
1840 if (DAG.MaskedValueIsZero(N0,
1841 APInt::getHighBitsSet(BitWidth,
1843 // Okay, get the un-inverted input value.
1845 if (N0.getOpcode() == ISD::XOR)
1846 Val = N0.getOperand(0);
1848 assert(N0.getOpcode() == ISD::AND &&
1849 N0.getOperand(0).getOpcode() == ISD::XOR);
1850 // ((X^1)&1)^1 -> X & 1
1851 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1852 N0.getOperand(0).getOperand(0),
1856 return DAG.getSetCC(dl, VT, Val, N1,
1857 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1859 } else if (N1C->getAPIntValue() == 1 &&
1861 getBooleanContents() == ZeroOrOneBooleanContent)) {
1863 if (Op0.getOpcode() == ISD::TRUNCATE)
1864 Op0 = Op0.getOperand(0);
1866 if ((Op0.getOpcode() == ISD::XOR) &&
1867 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1868 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1869 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1870 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1871 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1873 } else if (Op0.getOpcode() == ISD::AND &&
1874 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1875 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1876 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1877 if (Op0.getValueType() != VT)
1878 Op0 = DAG.getNode(ISD::AND, dl, VT,
1879 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1880 DAG.getConstant(1, VT));
1881 return DAG.getSetCC(dl, VT, Op0,
1882 DAG.getConstant(0, Op0.getValueType()),
1883 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1888 APInt MinVal, MaxVal;
1889 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1890 if (ISD::isSignedIntSetCC(Cond)) {
1891 MinVal = APInt::getSignedMinValue(OperandBitSize);
1892 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1894 MinVal = APInt::getMinValue(OperandBitSize);
1895 MaxVal = APInt::getMaxValue(OperandBitSize);
1898 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1899 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1900 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1901 // X >= C0 --> X > (C0-1)
1902 return DAG.getSetCC(dl, VT, N0,
1903 DAG.getConstant(C1-1, N1.getValueType()),
1904 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1907 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1908 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1909 // X <= C0 --> X < (C0+1)
1910 return DAG.getSetCC(dl, VT, N0,
1911 DAG.getConstant(C1+1, N1.getValueType()),
1912 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1915 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1916 return DAG.getConstant(0, VT); // X < MIN --> false
1917 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1918 return DAG.getConstant(1, VT); // X >= MIN --> true
1919 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1920 return DAG.getConstant(0, VT); // X > MAX --> false
1921 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1922 return DAG.getConstant(1, VT); // X <= MAX --> true
1924 // Canonicalize setgt X, Min --> setne X, Min
1925 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1926 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1927 // Canonicalize setlt X, Max --> setne X, Max
1928 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1929 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1931 // If we have setult X, 1, turn it into seteq X, 0
1932 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1933 return DAG.getSetCC(dl, VT, N0,
1934 DAG.getConstant(MinVal, N0.getValueType()),
1936 // If we have setugt X, Max-1, turn it into seteq X, Max
1937 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1938 return DAG.getSetCC(dl, VT, N0,
1939 DAG.getConstant(MaxVal, N0.getValueType()),
1942 // If we have "setcc X, C0", check to see if we can shrink the immediate
1945 // SETUGT X, SINTMAX -> SETLT X, 0
1946 if (Cond == ISD::SETUGT &&
1947 C1 == APInt::getSignedMaxValue(OperandBitSize))
1948 return DAG.getSetCC(dl, VT, N0,
1949 DAG.getConstant(0, N1.getValueType()),
1952 // SETULT X, SINTMIN -> SETGT X, -1
1953 if (Cond == ISD::SETULT &&
1954 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1955 SDValue ConstMinusOne =
1956 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1958 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1961 // Fold bit comparisons when we can.
1962 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1963 (VT == N0.getValueType() ||
1964 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1965 N0.getOpcode() == ISD::AND)
1966 if (ConstantSDNode *AndRHS =
1967 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1968 EVT ShiftTy = DCI.isBeforeLegalize() ?
1969 getPointerTy() : getShiftAmountTy();
1970 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1971 // Perform the xform if the AND RHS is a single bit.
1972 if (AndRHS->getAPIntValue().isPowerOf2()) {
1973 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1974 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1975 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1977 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1978 // (X & 8) == 8 --> (X & 8) >> 3
1979 // Perform the xform if C1 is a single bit.
1980 if (C1.isPowerOf2()) {
1981 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1982 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1983 DAG.getConstant(C1.logBase2(), ShiftTy)));
1989 if (isa<ConstantFPSDNode>(N0.getNode())) {
1990 // Constant fold or commute setcc.
1991 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1992 if (O.getNode()) return O;
1993 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1994 // If the RHS of an FP comparison is a constant, simplify it away in
1996 if (CFP->getValueAPF().isNaN()) {
1997 // If an operand is known to be a nan, we can fold it.
1998 switch (ISD::getUnorderedFlavor(Cond)) {
1999 default: llvm_unreachable("Unknown flavor!");
2000 case 0: // Known false.
2001 return DAG.getConstant(0, VT);
2002 case 1: // Known true.
2003 return DAG.getConstant(1, VT);
2004 case 2: // Undefined.
2005 return DAG.getUNDEF(VT);
2009 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2010 // constant if knowing that the operand is non-nan is enough. We prefer to
2011 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2013 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2014 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2016 // If the condition is not legal, see if we can find an equivalent one
2018 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2019 // If the comparison was an awkward floating-point == or != and one of
2020 // the comparison operands is infinity or negative infinity, convert the
2021 // condition to a less-awkward <= or >=.
2022 if (CFP->getValueAPF().isInfinity()) {
2023 if (CFP->getValueAPF().isNegative()) {
2024 if (Cond == ISD::SETOEQ &&
2025 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2026 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2027 if (Cond == ISD::SETUEQ &&
2028 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2029 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2030 if (Cond == ISD::SETUNE &&
2031 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2032 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2033 if (Cond == ISD::SETONE &&
2034 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2035 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2037 if (Cond == ISD::SETOEQ &&
2038 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2039 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2040 if (Cond == ISD::SETUEQ &&
2041 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2042 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2043 if (Cond == ISD::SETUNE &&
2044 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2045 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2046 if (Cond == ISD::SETONE &&
2047 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2048 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2055 // We can always fold X == X for integer setcc's.
2056 if (N0.getValueType().isInteger())
2057 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2058 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2059 if (UOF == 2) // FP operators that are undefined on NaNs.
2060 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2061 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2062 return DAG.getConstant(UOF, VT);
2063 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2064 // if it is not already.
2065 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2066 if (NewCond != Cond)
2067 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2070 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2071 N0.getValueType().isInteger()) {
2072 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2073 N0.getOpcode() == ISD::XOR) {
2074 // Simplify (X+Y) == (X+Z) --> Y == Z
2075 if (N0.getOpcode() == N1.getOpcode()) {
2076 if (N0.getOperand(0) == N1.getOperand(0))
2077 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2078 if (N0.getOperand(1) == N1.getOperand(1))
2079 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2080 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2081 // If X op Y == Y op X, try other combinations.
2082 if (N0.getOperand(0) == N1.getOperand(1))
2083 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2085 if (N0.getOperand(1) == N1.getOperand(0))
2086 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2091 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2092 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2093 // Turn (X+C1) == C2 --> X == C2-C1
2094 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2095 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2096 DAG.getConstant(RHSC->getAPIntValue()-
2097 LHSR->getAPIntValue(),
2098 N0.getValueType()), Cond);
2101 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2102 if (N0.getOpcode() == ISD::XOR)
2103 // If we know that all of the inverted bits are zero, don't bother
2104 // performing the inversion.
2105 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2107 DAG.getSetCC(dl, VT, N0.getOperand(0),
2108 DAG.getConstant(LHSR->getAPIntValue() ^
2109 RHSC->getAPIntValue(),
2114 // Turn (C1-X) == C2 --> X == C1-C2
2115 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2116 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2118 DAG.getSetCC(dl, VT, N0.getOperand(1),
2119 DAG.getConstant(SUBC->getAPIntValue() -
2120 RHSC->getAPIntValue(),
2127 // Simplify (X+Z) == X --> Z == 0
2128 if (N0.getOperand(0) == N1)
2129 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2130 DAG.getConstant(0, N0.getValueType()), Cond);
2131 if (N0.getOperand(1) == N1) {
2132 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2133 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2134 DAG.getConstant(0, N0.getValueType()), Cond);
2135 else if (N0.getNode()->hasOneUse()) {
2136 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2137 // (Z-X) == X --> Z == X<<1
2138 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2140 DAG.getConstant(1, getShiftAmountTy()));
2141 if (!DCI.isCalledByLegalizer())
2142 DCI.AddToWorklist(SH.getNode());
2143 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2148 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2149 N1.getOpcode() == ISD::XOR) {
2150 // Simplify X == (X+Z) --> Z == 0
2151 if (N1.getOperand(0) == N0) {
2152 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2153 DAG.getConstant(0, N1.getValueType()), Cond);
2154 } else if (N1.getOperand(1) == N0) {
2155 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2156 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2157 DAG.getConstant(0, N1.getValueType()), Cond);
2158 } else if (N1.getNode()->hasOneUse()) {
2159 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2160 // X == (Z-X) --> X<<1 == Z
2161 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2162 DAG.getConstant(1, getShiftAmountTy()));
2163 if (!DCI.isCalledByLegalizer())
2164 DCI.AddToWorklist(SH.getNode());
2165 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2170 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2171 // Note that where y is variable and is known to have at most
2172 // one bit set (for example, if it is z&1) we cannot do this;
2173 // the expressions are not equivalent when y==0.
2174 if (N0.getOpcode() == ISD::AND)
2175 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2176 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2177 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2178 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2179 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2182 if (N1.getOpcode() == ISD::AND)
2183 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2184 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2185 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2186 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2187 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2192 // Fold away ALL boolean setcc's.
2194 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2196 default: llvm_unreachable("Unknown integer setcc!");
2197 case ISD::SETEQ: // X == Y -> ~(X^Y)
2198 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2199 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2200 if (!DCI.isCalledByLegalizer())
2201 DCI.AddToWorklist(Temp.getNode());
2203 case ISD::SETNE: // X != Y --> (X^Y)
2204 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2206 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2207 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2208 Temp = DAG.getNOT(dl, N0, MVT::i1);
2209 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2210 if (!DCI.isCalledByLegalizer())
2211 DCI.AddToWorklist(Temp.getNode());
2213 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2214 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2215 Temp = DAG.getNOT(dl, N1, MVT::i1);
2216 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2217 if (!DCI.isCalledByLegalizer())
2218 DCI.AddToWorklist(Temp.getNode());
2220 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2221 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2222 Temp = DAG.getNOT(dl, N0, MVT::i1);
2223 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2224 if (!DCI.isCalledByLegalizer())
2225 DCI.AddToWorklist(Temp.getNode());
2227 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2228 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2229 Temp = DAG.getNOT(dl, N1, MVT::i1);
2230 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2233 if (VT != MVT::i1) {
2234 if (!DCI.isCalledByLegalizer())
2235 DCI.AddToWorklist(N0.getNode());
2236 // FIXME: If running after legalize, we probably can't do this.
2237 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2242 // Could not fold it.
2246 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2247 /// node is a GlobalAddress + offset.
2248 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2249 int64_t &Offset) const {
2250 if (isa<GlobalAddressSDNode>(N)) {
2251 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2252 GA = GASD->getGlobal();
2253 Offset += GASD->getOffset();
2257 if (N->getOpcode() == ISD::ADD) {
2258 SDValue N1 = N->getOperand(0);
2259 SDValue N2 = N->getOperand(1);
2260 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2261 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2263 Offset += V->getSExtValue();
2266 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2267 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2269 Offset += V->getSExtValue();
2278 SDValue TargetLowering::
2279 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2280 // Default implementation: no optimization.
2284 //===----------------------------------------------------------------------===//
2285 // Inline Assembler Implementation Methods
2286 //===----------------------------------------------------------------------===//
2289 TargetLowering::ConstraintType
2290 TargetLowering::getConstraintType(const std::string &Constraint) const {
2291 // FIXME: lots more standard ones to handle.
2292 if (Constraint.size() == 1) {
2293 switch (Constraint[0]) {
2295 case 'r': return C_RegisterClass;
2297 case 'o': // offsetable
2298 case 'V': // not offsetable
2300 case 'i': // Simple Integer or Relocatable Constant
2301 case 'n': // Simple Integer
2302 case 's': // Relocatable Constant
2303 case 'X': // Allow ANY value.
2304 case 'I': // Target registers.
2316 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2317 Constraint[Constraint.size()-1] == '}')
2322 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2323 /// with another that has more specific requirements based on the type of the
2324 /// corresponding operand.
2325 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2326 if (ConstraintVT.isInteger())
2328 if (ConstraintVT.isFloatingPoint())
2329 return "f"; // works for many targets
2333 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2334 /// vector. If it is invalid, don't add anything to Ops.
2335 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2336 char ConstraintLetter,
2338 std::vector<SDValue> &Ops,
2339 SelectionDAG &DAG) const {
2340 switch (ConstraintLetter) {
2342 case 'X': // Allows any operand; labels (basic block) use this.
2343 if (Op.getOpcode() == ISD::BasicBlock) {
2348 case 'i': // Simple Integer or Relocatable Constant
2349 case 'n': // Simple Integer
2350 case 's': { // Relocatable Constant
2351 // These operands are interested in values of the form (GV+C), where C may
2352 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2353 // is possible and fine if either GV or C are missing.
2354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2355 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2357 // If we have "(add GV, C)", pull out GV/C
2358 if (Op.getOpcode() == ISD::ADD) {
2359 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2360 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2361 if (C == 0 || GA == 0) {
2362 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2363 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2365 if (C == 0 || GA == 0)
2369 // If we find a valid operand, map to the TargetXXX version so that the
2370 // value itself doesn't get selected.
2371 if (GA) { // Either &GV or &GV+C
2372 if (ConstraintLetter != 'n') {
2373 int64_t Offs = GA->getOffset();
2374 if (C) Offs += C->getZExtValue();
2375 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2376 Op.getValueType(), Offs));
2380 if (C) { // just C, no GV.
2381 // Simple constants are not allowed for 's'.
2382 if (ConstraintLetter != 's') {
2383 // gcc prints these as sign extended. Sign extend value to 64 bits
2384 // now; without this it would get ZExt'd later in
2385 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2386 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2396 std::vector<unsigned> TargetLowering::
2397 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2399 return std::vector<unsigned>();
2403 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2404 getRegForInlineAsmConstraint(const std::string &Constraint,
2406 if (Constraint[0] != '{')
2407 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2408 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2410 // Remove the braces from around the name.
2411 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2413 // Figure out which register class contains this reg.
2414 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2415 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2416 E = RI->regclass_end(); RCI != E; ++RCI) {
2417 const TargetRegisterClass *RC = *RCI;
2419 // If none of the value types for this register class are valid, we
2420 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2421 bool isLegal = false;
2422 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2424 if (isTypeLegal(*I)) {
2430 if (!isLegal) continue;
2432 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2434 if (RegName.equals_lower(RI->getName(*I)))
2435 return std::make_pair(*I, RC);
2439 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2442 //===----------------------------------------------------------------------===//
2443 // Constraint Selection.
2445 /// isMatchingInputConstraint - Return true of this is an input operand that is
2446 /// a matching constraint like "4".
2447 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2448 assert(!ConstraintCode.empty() && "No known constraint!");
2449 return isdigit(ConstraintCode[0]);
2452 /// getMatchedOperand - If this is an input matching constraint, this method
2453 /// returns the output operand it matches.
2454 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2455 assert(!ConstraintCode.empty() && "No known constraint!");
2456 return atoi(ConstraintCode.c_str());
2460 /// getConstraintGenerality - Return an integer indicating how general CT
2462 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2464 default: llvm_unreachable("Unknown constraint type!");
2465 case TargetLowering::C_Other:
2466 case TargetLowering::C_Unknown:
2468 case TargetLowering::C_Register:
2470 case TargetLowering::C_RegisterClass:
2472 case TargetLowering::C_Memory:
2477 /// ChooseConstraint - If there are multiple different constraints that we
2478 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2479 /// This is somewhat tricky: constraints fall into four classes:
2480 /// Other -> immediates and magic values
2481 /// Register -> one specific register
2482 /// RegisterClass -> a group of regs
2483 /// Memory -> memory
2484 /// Ideally, we would pick the most specific constraint possible: if we have
2485 /// something that fits into a register, we would pick it. The problem here
2486 /// is that if we have something that could either be in a register or in
2487 /// memory that use of the register could cause selection of *other*
2488 /// operands to fail: they might only succeed if we pick memory. Because of
2489 /// this the heuristic we use is:
2491 /// 1) If there is an 'other' constraint, and if the operand is valid for
2492 /// that constraint, use it. This makes us take advantage of 'i'
2493 /// constraints when available.
2494 /// 2) Otherwise, pick the most general constraint present. This prefers
2495 /// 'm' over 'r', for example.
2497 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2498 bool hasMemory, const TargetLowering &TLI,
2499 SDValue Op, SelectionDAG *DAG) {
2500 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2501 unsigned BestIdx = 0;
2502 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2503 int BestGenerality = -1;
2505 // Loop over the options, keeping track of the most general one.
2506 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2507 TargetLowering::ConstraintType CType =
2508 TLI.getConstraintType(OpInfo.Codes[i]);
2510 // If this is an 'other' constraint, see if the operand is valid for it.
2511 // For example, on X86 we might have an 'rI' constraint. If the operand
2512 // is an integer in the range [0..31] we want to use I (saving a load
2513 // of a register), otherwise we must use 'r'.
2514 if (CType == TargetLowering::C_Other && Op.getNode()) {
2515 assert(OpInfo.Codes[i].size() == 1 &&
2516 "Unhandled multi-letter 'other' constraint");
2517 std::vector<SDValue> ResultOps;
2518 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2520 if (!ResultOps.empty()) {
2527 // This constraint letter is more general than the previous one, use it.
2528 int Generality = getConstraintGenerality(CType);
2529 if (Generality > BestGenerality) {
2532 BestGenerality = Generality;
2536 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2537 OpInfo.ConstraintType = BestType;
2540 /// ComputeConstraintToUse - Determines the constraint code and constraint
2541 /// type to use for the specific AsmOperandInfo, setting
2542 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2543 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2546 SelectionDAG *DAG) const {
2547 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2549 // Single-letter constraints ('r') are very common.
2550 if (OpInfo.Codes.size() == 1) {
2551 OpInfo.ConstraintCode = OpInfo.Codes[0];
2552 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2554 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2557 // 'X' matches anything.
2558 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2559 // Labels and constants are handled elsewhere ('X' is the only thing
2560 // that matches labels). For Functions, the type here is the type of
2561 // the result, which is not what we want to look at; leave them alone.
2562 Value *v = OpInfo.CallOperandVal;
2563 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2564 OpInfo.CallOperandVal = v;
2568 // Otherwise, try to resolve it to something we know about by looking at
2569 // the actual operand type.
2570 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2571 OpInfo.ConstraintCode = Repl;
2572 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2577 //===----------------------------------------------------------------------===//
2578 // Loop Strength Reduction hooks
2579 //===----------------------------------------------------------------------===//
2581 /// isLegalAddressingMode - Return true if the addressing mode represented
2582 /// by AM is legal for this target, for a load/store of the specified type.
2583 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2584 const Type *Ty) const {
2585 // The default implementation of this implements a conservative RISCy, r+r and
2588 // Allows a sign-extended 16-bit immediate field.
2589 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2592 // No global is ever allowed as a base.
2596 // Only support r+r,
2598 case 0: // "r+i" or just "i", depending on HasBaseReg.
2601 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2603 // Otherwise we have r+r or r+i.
2606 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2608 // Allow 2*r as r+r.
2615 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2616 /// return a DAG expression to select that will generate the same value by
2617 /// multiplying by a magic number. See:
2618 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2619 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2620 std::vector<SDNode*>* Created) const {
2621 EVT VT = N->getValueType(0);
2622 DebugLoc dl= N->getDebugLoc();
2624 // Check to see if we can do this.
2625 // FIXME: We should be more aggressive here.
2626 if (!isTypeLegal(VT))
2629 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2630 APInt::ms magics = d.magic();
2632 // Multiply the numerator (operand 0) by the magic value
2633 // FIXME: We should support doing a MUL in a wider type
2635 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2636 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2637 DAG.getConstant(magics.m, VT));
2638 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2639 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2641 DAG.getConstant(magics.m, VT)).getNode(), 1);
2643 return SDValue(); // No mulhs or equvialent
2644 // If d > 0 and m < 0, add the numerator
2645 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2646 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2648 Created->push_back(Q.getNode());
2650 // If d < 0 and m > 0, subtract the numerator.
2651 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2652 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2654 Created->push_back(Q.getNode());
2656 // Shift right algebraic if shift value is nonzero
2658 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2659 DAG.getConstant(magics.s, getShiftAmountTy()));
2661 Created->push_back(Q.getNode());
2663 // Extract the sign bit and add it to the quotient
2665 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2666 getShiftAmountTy()));
2668 Created->push_back(T.getNode());
2669 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2672 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2673 /// return a DAG expression to select that will generate the same value by
2674 /// multiplying by a magic number. See:
2675 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2676 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2677 std::vector<SDNode*>* Created) const {
2678 EVT VT = N->getValueType(0);
2679 DebugLoc dl = N->getDebugLoc();
2681 // Check to see if we can do this.
2682 // FIXME: We should be more aggressive here.
2683 if (!isTypeLegal(VT))
2686 // FIXME: We should use a narrower constant when the upper
2687 // bits are known to be zero.
2688 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2689 APInt::mu magics = N1C->getAPIntValue().magicu();
2691 // Multiply the numerator (operand 0) by the magic value
2692 // FIXME: We should support doing a MUL in a wider type
2694 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2695 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2696 DAG.getConstant(magics.m, VT));
2697 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2698 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2700 DAG.getConstant(magics.m, VT)).getNode(), 1);
2702 return SDValue(); // No mulhu or equvialent
2704 Created->push_back(Q.getNode());
2706 if (magics.a == 0) {
2707 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2708 "We shouldn't generate an undefined shift!");
2709 return DAG.getNode(ISD::SRL, dl, VT, Q,
2710 DAG.getConstant(magics.s, getShiftAmountTy()));
2712 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2714 Created->push_back(NPQ.getNode());
2715 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2716 DAG.getConstant(1, getShiftAmountTy()));
2718 Created->push_back(NPQ.getNode());
2719 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2721 Created->push_back(NPQ.getNode());
2722 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2723 DAG.getConstant(magics.s-1, getShiftAmountTy()));