1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 /// NOTE: The constructor takes ownership of TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm,
40 const TargetLoweringObjectFile *tlof)
41 : TargetLoweringBase(tm, tlof) {}
43 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
47 /// Check whether a given call node is in tail position within its function. If
48 /// so, it sets Chain to the input chain of the tail call.
49 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
50 SDValue &Chain) const {
51 const Function *F = DAG.getMachineFunction().getFunction();
53 // Conservatively require the attributes of the call to match those of
54 // the return. Ignore noalias because it doesn't affect the call sequence.
55 AttributeSet CallerAttrs = F->getAttributes();
56 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
57 .removeAttribute(Attribute::NoAlias).hasAttributes())
60 // It's not safe to eliminate the sign / zero extension of the return value.
61 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
62 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
65 // Check if the only use is a function return node.
66 return isUsedByReturnOnly(Node, Chain);
69 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
70 /// and called function attributes.
71 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
73 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
74 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
75 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
76 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
77 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
78 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
79 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
80 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
81 Alignment = CS->getParamAlignment(AttrIdx);
84 /// Generate a libcall taking the given operands as arguments and returning a
85 /// result of type RetVT.
86 std::pair<SDValue, SDValue>
87 TargetLowering::makeLibCall(SelectionDAG &DAG,
88 RTLIB::Libcall LC, EVT RetVT,
89 const SDValue *Ops, unsigned NumOps,
90 bool isSigned, SDLoc dl,
92 bool isReturnValueUsed) const {
93 TargetLowering::ArgListTy Args;
96 TargetLowering::ArgListEntry Entry;
97 for (unsigned i = 0; i != NumOps; ++i) {
99 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
100 Entry.isSExt = isSigned;
101 Entry.isZExt = !isSigned;
102 Args.push_back(Entry);
104 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
106 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
107 TargetLowering::CallLoweringInfo CLI(DAG);
108 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
109 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
110 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
111 .setSExtResult(isSigned).setZExtResult(!isSigned);
112 return LowerCallTo(CLI);
116 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
117 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
118 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
119 SDValue &NewLHS, SDValue &NewRHS,
120 ISD::CondCode &CCCode,
122 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
123 && "Unsupported setcc type!");
125 // Expand into one or more soft-fp libcall(s).
126 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
130 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
135 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
140 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
145 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
150 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
155 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
159 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
163 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
164 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
167 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
171 // SETONE = SETOLT | SETOGT
172 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
176 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
180 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
184 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
188 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
192 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
195 default: llvm_unreachable("Do not know how to soften this setcc!");
199 // Use the target specific return value for comparions lib calls.
200 EVT RetVT = getCmpLibcallReturnType();
201 SDValue Ops[2] = { NewLHS, NewRHS };
202 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
204 NewRHS = DAG.getConstant(0, RetVT);
205 CCCode = getCmpLibcallCC(LC1);
206 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
207 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
208 getSetCCResultType(*DAG.getContext(), RetVT),
209 NewLHS, NewRHS, DAG.getCondCode(CCCode));
210 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
212 NewLHS = DAG.getNode(ISD::SETCC, dl,
213 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
214 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
215 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
220 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
221 /// current function. The returned value is a member of the
222 /// MachineJumpTableInfo::JTEntryKind enum.
223 unsigned TargetLowering::getJumpTableEncoding() const {
224 // In non-pic modes, just use the address of a block.
225 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
226 return MachineJumpTableInfo::EK_BlockAddress;
228 // In PIC mode, if the target supports a GPRel32 directive, use it.
229 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
230 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
232 // Otherwise, use a label difference.
233 return MachineJumpTableInfo::EK_LabelDifference32;
236 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
237 SelectionDAG &DAG) const {
238 // If our PIC model is GP relative, use the global offset table as the base.
239 unsigned JTEncoding = getJumpTableEncoding();
241 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
243 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
248 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
249 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
252 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
253 unsigned JTI,MCContext &Ctx) const{
254 // The normal PIC reloc base is the label at the start of the jump table.
255 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
259 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
260 // Assume that everything is safe in static mode.
261 if (getTargetMachine().getRelocationModel() == Reloc::Static)
264 // In dynamic-no-pic mode, assume that known defined values are safe.
265 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
267 !GA->getGlobal()->isDeclaration() &&
268 !GA->getGlobal()->isWeakForLinker())
271 // Otherwise assume nothing is safe.
275 //===----------------------------------------------------------------------===//
276 // Optimization Methods
277 //===----------------------------------------------------------------------===//
279 /// ShrinkDemandedConstant - Check to see if the specified operand of the
280 /// specified instruction is a constant integer. If so, check to see if there
281 /// are any bits set in the constant that are not demanded. If so, shrink the
282 /// constant and return true.
283 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
284 const APInt &Demanded) {
287 // FIXME: ISD::SELECT, ISD::SELECT_CC
288 switch (Op.getOpcode()) {
293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
294 if (!C) return false;
296 if (Op.getOpcode() == ISD::XOR &&
297 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
300 // if we can expand it to have all bits set, do it
301 if (C->getAPIntValue().intersects(~Demanded)) {
302 EVT VT = Op.getValueType();
303 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
304 DAG.getConstant(Demanded &
307 return CombineTo(Op, New);
317 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
318 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
319 /// cast, but it could be generalized for targets with other types of
320 /// implicit widening casts.
322 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
324 const APInt &Demanded,
326 assert(Op.getNumOperands() == 2 &&
327 "ShrinkDemandedOp only supports binary operators!");
328 assert(Op.getNode()->getNumValues() == 1 &&
329 "ShrinkDemandedOp only supports nodes with one result!");
331 // Early return, as this function cannot handle vector types.
332 if (Op.getValueType().isVector())
335 // Don't do this if the node has another user, which may require the
337 if (!Op.getNode()->hasOneUse())
340 // Search for the smallest integer type with free casts to and from
341 // Op's type. For expedience, just check power-of-2 integer types.
342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
343 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
344 unsigned SmallVTBits = DemandedSize;
345 if (!isPowerOf2_32(SmallVTBits))
346 SmallVTBits = NextPowerOf2(SmallVTBits);
347 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
348 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
349 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
350 TLI.isZExtFree(SmallVT, Op.getValueType())) {
351 // We found a type with free casts.
352 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
353 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
354 Op.getNode()->getOperand(0)),
355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
356 Op.getNode()->getOperand(1)));
357 bool NeedZext = DemandedSize > SmallVTBits;
358 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
359 dl, Op.getValueType(), X);
360 return CombineTo(Op, Z);
366 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
367 /// DemandedMask bits of the result of Op are ever used downstream. If we can
368 /// use this information to simplify Op, create a new simplified DAG node and
369 /// return true, returning the original and new nodes in Old and New. Otherwise,
370 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
371 /// the expression (used to simplify the caller). The KnownZero/One bits may
372 /// only be accurate for those bits in the DemandedMask.
373 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
374 const APInt &DemandedMask,
377 TargetLoweringOpt &TLO,
378 unsigned Depth) const {
379 unsigned BitWidth = DemandedMask.getBitWidth();
380 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
381 "Mask size mismatches value type size!");
382 APInt NewMask = DemandedMask;
385 // Don't know anything.
386 KnownZero = KnownOne = APInt(BitWidth, 0);
388 // Other users may use these bits.
389 if (!Op.getNode()->hasOneUse()) {
391 // If not at the root, Just compute the KnownZero/KnownOne bits to
392 // simplify things downstream.
393 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
396 // If this is the root being simplified, allow it to have multiple uses,
397 // just set the NewMask to all bits.
398 NewMask = APInt::getAllOnesValue(BitWidth);
399 } else if (DemandedMask == 0) {
400 // Not demanding any bits from Op.
401 if (Op.getOpcode() != ISD::UNDEF)
402 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
404 } else if (Depth == 6) { // Limit search depth.
408 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
409 switch (Op.getOpcode()) {
411 // We know all of the bits for a constant!
412 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
413 KnownZero = ~KnownOne;
414 return false; // Don't fall through, will infinitely loop.
416 // If the RHS is a constant, check to see if the LHS would be zero without
417 // using the bits from the RHS. Below, we use knowledge about the RHS to
418 // simplify the LHS, here we're using information from the LHS to simplify
420 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
421 APInt LHSZero, LHSOne;
422 // Do not increment Depth here; that can cause an infinite loop.
423 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
424 // If the LHS already has zeros where RHSC does, this and is dead.
425 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
426 return TLO.CombineTo(Op, Op.getOperand(0));
427 // If any of the set bits in the RHS are known zero on the LHS, shrink
429 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
433 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
434 KnownOne, TLO, Depth+1))
436 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
437 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
438 KnownZero2, KnownOne2, TLO, Depth+1))
440 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
442 // If all of the demanded bits are known one on one side, return the other.
443 // These bits cannot contribute to the result of the 'and'.
444 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
445 return TLO.CombineTo(Op, Op.getOperand(0));
446 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
447 return TLO.CombineTo(Op, Op.getOperand(1));
448 // If all of the demanded bits in the inputs are known zeros, return zero.
449 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
450 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
451 // If the RHS is a constant, see if we can simplify it.
452 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
454 // If the operation can be done in a smaller type, do so.
455 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
458 // Output known-1 bits are only known if set in both the LHS & RHS.
459 KnownOne &= KnownOne2;
460 // Output known-0 are known to be clear if zero in either the LHS | RHS.
461 KnownZero |= KnownZero2;
464 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
465 KnownOne, TLO, Depth+1))
467 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
468 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
469 KnownZero2, KnownOne2, TLO, Depth+1))
471 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
473 // If all of the demanded bits are known zero on one side, return the other.
474 // These bits cannot contribute to the result of the 'or'.
475 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
476 return TLO.CombineTo(Op, Op.getOperand(0));
477 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(1));
479 // If all of the potentially set bits on one side are known to be set on
480 // the other side, just use the 'other' side.
481 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
482 return TLO.CombineTo(Op, Op.getOperand(0));
483 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
484 return TLO.CombineTo(Op, Op.getOperand(1));
485 // If the RHS is a constant, see if we can simplify it.
486 if (TLO.ShrinkDemandedConstant(Op, NewMask))
488 // If the operation can be done in a smaller type, do so.
489 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
492 // Output known-0 bits are only known if clear in both the LHS & RHS.
493 KnownZero &= KnownZero2;
494 // Output known-1 are known to be set if set in either the LHS | RHS.
495 KnownOne |= KnownOne2;
498 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
499 KnownOne, TLO, Depth+1))
501 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
502 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
503 KnownOne2, TLO, Depth+1))
505 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
507 // If all of the demanded bits are known zero on one side, return the other.
508 // These bits cannot contribute to the result of the 'xor'.
509 if ((KnownZero & NewMask) == NewMask)
510 return TLO.CombineTo(Op, Op.getOperand(0));
511 if ((KnownZero2 & NewMask) == NewMask)
512 return TLO.CombineTo(Op, Op.getOperand(1));
513 // If the operation can be done in a smaller type, do so.
514 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
517 // If all of the unknown bits are known to be zero on one side or the other
518 // (but not both) turn this into an *inclusive* or.
519 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
520 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
521 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
525 // Output known-0 bits are known if clear or set in both the LHS & RHS.
526 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
527 // Output known-1 are known to be set if set in only one of the LHS, RHS.
528 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
530 // If all of the demanded bits on one side are known, and all of the set
531 // bits on that side are also known to be set on the other side, turn this
532 // into an AND, as we know the bits will be cleared.
533 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
534 // NB: it is okay if more bits are known than are requested
535 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
536 if (KnownOne == KnownOne2) { // set bits are the same on both sides
537 EVT VT = Op.getValueType();
538 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
539 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
540 Op.getOperand(0), ANDC));
544 // If the RHS is a constant, see if we can simplify it.
545 // for XOR, we prefer to force bits to 1 if they will make a -1.
546 // if we can't force bits, try to shrink constant
547 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
548 APInt Expanded = C->getAPIntValue() | (~NewMask);
549 // if we can expand it to have all bits set, do it
550 if (Expanded.isAllOnesValue()) {
551 if (Expanded != C->getAPIntValue()) {
552 EVT VT = Op.getValueType();
553 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
554 TLO.DAG.getConstant(Expanded, VT));
555 return TLO.CombineTo(Op, New);
557 // if it already has all the bits set, nothing to change
558 // but don't shrink either!
559 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
564 KnownZero = KnownZeroOut;
565 KnownOne = KnownOneOut;
568 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
569 KnownOne, TLO, Depth+1))
571 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
572 KnownOne2, TLO, Depth+1))
574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
575 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
577 // If the operands are constants, see if we can simplify them.
578 if (TLO.ShrinkDemandedConstant(Op, NewMask))
581 // Only known if known in both the LHS and RHS.
582 KnownOne &= KnownOne2;
583 KnownZero &= KnownZero2;
586 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
587 KnownOne, TLO, Depth+1))
589 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
590 KnownOne2, TLO, Depth+1))
592 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
593 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
595 // If the operands are constants, see if we can simplify them.
596 if (TLO.ShrinkDemandedConstant(Op, NewMask))
599 // Only known if known in both the LHS and RHS.
600 KnownOne &= KnownOne2;
601 KnownZero &= KnownZero2;
604 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
605 unsigned ShAmt = SA->getZExtValue();
606 SDValue InOp = Op.getOperand(0);
608 // If the shift count is an invalid immediate, don't do anything.
609 if (ShAmt >= BitWidth)
612 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
613 // single shift. We can do this if the bottom bits (which are shifted
614 // out) are never demanded.
615 if (InOp.getOpcode() == ISD::SRL &&
616 isa<ConstantSDNode>(InOp.getOperand(1))) {
617 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
618 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
619 unsigned Opc = ISD::SHL;
627 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
628 EVT VT = Op.getValueType();
629 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
630 InOp.getOperand(0), NewSA));
634 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
635 KnownZero, KnownOne, TLO, Depth+1))
638 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
639 // are not demanded. This will likely allow the anyext to be folded away.
640 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
641 SDValue InnerOp = InOp.getNode()->getOperand(0);
642 EVT InnerVT = InnerOp.getValueType();
643 unsigned InnerBits = InnerVT.getSizeInBits();
644 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
645 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
646 EVT ShTy = getShiftAmountTy(InnerVT);
647 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
650 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
651 TLO.DAG.getConstant(ShAmt, ShTy));
654 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
657 // Repeat the SHL optimization above in cases where an extension
658 // intervenes: (shl (anyext (shr x, c1)), c2) to
659 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
660 // aren't demanded (as above) and that the shifted upper c1 bits of
661 // x aren't demanded.
662 if (InOp.hasOneUse() &&
663 InnerOp.getOpcode() == ISD::SRL &&
664 InnerOp.hasOneUse() &&
665 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
666 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
668 if (InnerShAmt < ShAmt &&
669 InnerShAmt < InnerBits &&
670 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
671 NewMask.trunc(ShAmt) == 0) {
673 TLO.DAG.getConstant(ShAmt - InnerShAmt,
674 Op.getOperand(1).getValueType());
675 EVT VT = Op.getValueType();
676 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
677 InnerOp.getOperand(0));
678 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
684 KnownZero <<= SA->getZExtValue();
685 KnownOne <<= SA->getZExtValue();
686 // low bits known zero.
687 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
691 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
692 EVT VT = Op.getValueType();
693 unsigned ShAmt = SA->getZExtValue();
694 unsigned VTSize = VT.getSizeInBits();
695 SDValue InOp = Op.getOperand(0);
697 // If the shift count is an invalid immediate, don't do anything.
698 if (ShAmt >= BitWidth)
701 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
702 // single shift. We can do this if the top bits (which are shifted out)
703 // are never demanded.
704 if (InOp.getOpcode() == ISD::SHL &&
705 isa<ConstantSDNode>(InOp.getOperand(1))) {
706 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
707 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
708 unsigned Opc = ISD::SRL;
716 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
717 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
718 InOp.getOperand(0), NewSA));
722 // Compute the new bits that are at the top now.
723 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
724 KnownZero, KnownOne, TLO, Depth+1))
726 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
727 KnownZero = KnownZero.lshr(ShAmt);
728 KnownOne = KnownOne.lshr(ShAmt);
730 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
731 KnownZero |= HighBits; // High bits known zero.
735 // If this is an arithmetic shift right and only the low-bit is set, we can
736 // always convert this into a logical shr, even if the shift amount is
737 // variable. The low bit of the shift cannot be an input sign bit unless
738 // the shift amount is >= the size of the datatype, which is undefined.
740 return TLO.CombineTo(Op,
741 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
742 Op.getOperand(0), Op.getOperand(1)));
744 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
745 EVT VT = Op.getValueType();
746 unsigned ShAmt = SA->getZExtValue();
748 // If the shift count is an invalid immediate, don't do anything.
749 if (ShAmt >= BitWidth)
752 APInt InDemandedMask = (NewMask << ShAmt);
754 // If any of the demanded bits are produced by the sign extension, we also
755 // demand the input sign bit.
756 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
757 if (HighBits.intersects(NewMask))
758 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
760 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
761 KnownZero, KnownOne, TLO, Depth+1))
763 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
764 KnownZero = KnownZero.lshr(ShAmt);
765 KnownOne = KnownOne.lshr(ShAmt);
767 // Handle the sign bit, adjusted to where it is now in the mask.
768 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
770 // If the input sign bit is known to be zero, or if none of the top bits
771 // are demanded, turn this into an unsigned shift right.
772 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
773 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
777 int Log2 = NewMask.exactLogBase2();
779 // The bit must come from the sign.
781 TLO.DAG.getConstant(BitWidth - 1 - Log2,
782 Op.getOperand(1).getValueType());
783 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
784 Op.getOperand(0), NewSA));
787 if (KnownOne.intersects(SignBit))
788 // New bits are known one.
789 KnownOne |= HighBits;
792 case ISD::SIGN_EXTEND_INREG: {
793 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
795 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
796 // If we only care about the highest bit, don't bother shifting right.
797 if (MsbMask == DemandedMask) {
798 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
799 SDValue InOp = Op.getOperand(0);
801 // Compute the correct shift amount type, which must be getShiftAmountTy
802 // for scalar types after legalization.
803 EVT ShiftAmtTy = Op.getValueType();
804 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
805 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
807 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
808 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
809 Op.getValueType(), InOp, ShiftAmt));
812 // Sign extension. Compute the demanded bits in the result that are not
813 // present in the input.
815 APInt::getHighBitsSet(BitWidth,
816 BitWidth - ExVT.getScalarType().getSizeInBits());
818 // If none of the extended bits are demanded, eliminate the sextinreg.
819 if ((NewBits & NewMask) == 0)
820 return TLO.CombineTo(Op, Op.getOperand(0));
823 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
824 APInt InputDemandedBits =
825 APInt::getLowBitsSet(BitWidth,
826 ExVT.getScalarType().getSizeInBits()) &
829 // Since the sign extended bits are demanded, we know that the sign
831 InputDemandedBits |= InSignBit;
833 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
834 KnownZero, KnownOne, TLO, Depth+1))
836 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
838 // If the sign bit of the input is known set or clear, then we know the
839 // top bits of the result.
841 // If the input sign bit is known zero, convert this into a zero extension.
842 if (KnownZero.intersects(InSignBit))
843 return TLO.CombineTo(Op,
844 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
846 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
848 KnownZero &= ~NewBits;
849 } else { // Input sign bit unknown
850 KnownZero &= ~NewBits;
851 KnownOne &= ~NewBits;
855 case ISD::BUILD_PAIR: {
856 EVT HalfVT = Op.getOperand(0).getValueType();
857 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
859 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
860 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
862 APInt KnownZeroLo, KnownOneLo;
863 APInt KnownZeroHi, KnownOneHi;
865 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
866 KnownOneLo, TLO, Depth + 1))
869 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
870 KnownOneHi, TLO, Depth + 1))
873 KnownZero = KnownZeroLo.zext(BitWidth) |
874 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
876 KnownOne = KnownOneLo.zext(BitWidth) |
877 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
880 case ISD::ZERO_EXTEND: {
881 unsigned OperandBitWidth =
882 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
883 APInt InMask = NewMask.trunc(OperandBitWidth);
885 // If none of the top bits are demanded, convert this into an any_extend.
887 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
888 if (!NewBits.intersects(NewMask))
889 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
893 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
894 KnownZero, KnownOne, TLO, Depth+1))
896 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
897 KnownZero = KnownZero.zext(BitWidth);
898 KnownOne = KnownOne.zext(BitWidth);
899 KnownZero |= NewBits;
902 case ISD::SIGN_EXTEND: {
903 EVT InVT = Op.getOperand(0).getValueType();
904 unsigned InBits = InVT.getScalarType().getSizeInBits();
905 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
906 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
907 APInt NewBits = ~InMask & NewMask;
909 // If none of the top bits are demanded, convert this into an any_extend.
911 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
915 // Since some of the sign extended bits are demanded, we know that the sign
917 APInt InDemandedBits = InMask & NewMask;
918 InDemandedBits |= InSignBit;
919 InDemandedBits = InDemandedBits.trunc(InBits);
921 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
922 KnownOne, TLO, Depth+1))
924 KnownZero = KnownZero.zext(BitWidth);
925 KnownOne = KnownOne.zext(BitWidth);
927 // If the sign bit is known zero, convert this to a zero extend.
928 if (KnownZero.intersects(InSignBit))
929 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
933 // If the sign bit is known one, the top bits match.
934 if (KnownOne.intersects(InSignBit)) {
936 assert((KnownZero & NewBits) == 0);
937 } else { // Otherwise, top bits aren't known.
938 assert((KnownOne & NewBits) == 0);
939 assert((KnownZero & NewBits) == 0);
943 case ISD::ANY_EXTEND: {
944 unsigned OperandBitWidth =
945 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
946 APInt InMask = NewMask.trunc(OperandBitWidth);
947 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
948 KnownZero, KnownOne, TLO, Depth+1))
950 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
951 KnownZero = KnownZero.zext(BitWidth);
952 KnownOne = KnownOne.zext(BitWidth);
955 case ISD::TRUNCATE: {
956 // Simplify the input, using demanded bit information, and compute the known
957 // zero/one bits live out.
958 unsigned OperandBitWidth =
959 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
960 APInt TruncMask = NewMask.zext(OperandBitWidth);
961 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
962 KnownZero, KnownOne, TLO, Depth+1))
964 KnownZero = KnownZero.trunc(BitWidth);
965 KnownOne = KnownOne.trunc(BitWidth);
967 // If the input is only used by this truncate, see if we can shrink it based
968 // on the known demanded bits.
969 if (Op.getOperand(0).getNode()->hasOneUse()) {
970 SDValue In = Op.getOperand(0);
971 switch (In.getOpcode()) {
974 // Shrink SRL by a constant if none of the high bits shifted in are
976 if (TLO.LegalTypes() &&
977 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
978 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
981 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
984 SDValue Shift = In.getOperand(1);
985 if (TLO.LegalTypes()) {
986 uint64_t ShVal = ShAmt->getZExtValue();
988 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
991 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
992 OperandBitWidth - BitWidth);
993 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
995 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
996 // None of the shifted in bits are needed. Add a truncate of the
997 // shift input, then shift it.
998 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1001 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1010 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1013 case ISD::AssertZext: {
1014 // AssertZext demands all of the high bits, plus any of the low bits
1015 // demanded by its users.
1016 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1017 APInt InMask = APInt::getLowBitsSet(BitWidth,
1018 VT.getSizeInBits());
1019 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1020 KnownZero, KnownOne, TLO, Depth+1))
1022 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1024 KnownZero |= ~InMask & NewMask;
1028 // If this is an FP->Int bitcast and if the sign bit is the only
1029 // thing demanded, turn this into a FGETSIGN.
1030 if (!TLO.LegalOperations() &&
1031 !Op.getValueType().isVector() &&
1032 !Op.getOperand(0).getValueType().isVector() &&
1033 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1034 Op.getOperand(0).getValueType().isFloatingPoint()) {
1035 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1036 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1037 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1038 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1039 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1040 // place. We expect the SHL to be eliminated by other optimizations.
1041 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1042 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1043 if (!OpVTLegal && OpVTSizeInBits > 32)
1044 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1045 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1046 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1047 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1056 // Add, Sub, and Mul don't demand any bits in positions beyond that
1057 // of the highest bit demanded of them.
1058 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1059 BitWidth - NewMask.countLeadingZeros());
1060 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1061 KnownOne2, TLO, Depth+1))
1063 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1064 KnownOne2, TLO, Depth+1))
1066 // See if the operation should be performed at a smaller bit width.
1067 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1072 // Just use computeKnownBits to compute output bits.
1073 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1077 // If we know the value of all of the demanded bits, return this as a
1079 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1080 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1085 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1086 /// in Mask are known to be either zero or one and return them in the
1087 /// KnownZero/KnownOne bitsets.
1088 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1091 const SelectionDAG &DAG,
1092 unsigned Depth) const {
1093 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1094 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1095 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1096 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1097 "Should use MaskedValueIsZero if you don't know whether Op"
1098 " is a target node!");
1099 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1102 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1103 /// targets that want to expose additional information about sign bits to the
1105 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1106 const SelectionDAG &,
1107 unsigned Depth) const {
1108 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1109 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1110 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1111 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1112 "Should use ComputeNumSignBits if you don't know whether Op"
1113 " is a target node!");
1117 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1118 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1119 /// determine which bit is set.
1121 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1122 // A left-shift of a constant one will have exactly one bit set, because
1123 // shifting the bit off the end is undefined.
1124 if (Val.getOpcode() == ISD::SHL)
1125 if (ConstantSDNode *C =
1126 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1127 if (C->getAPIntValue() == 1)
1130 // Similarly, a right-shift of a constant sign-bit will have exactly
1132 if (Val.getOpcode() == ISD::SRL)
1133 if (ConstantSDNode *C =
1134 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1135 if (C->getAPIntValue().isSignBit())
1138 // More could be done here, though the above checks are enough
1139 // to handle some common cases.
1141 // Fall back to computeKnownBits to catch other known cases.
1142 EVT OpVT = Val.getValueType();
1143 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1144 APInt KnownZero, KnownOne;
1145 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1146 return (KnownZero.countPopulation() == BitWidth - 1) &&
1147 (KnownOne.countPopulation() == 1);
1150 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1154 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1156 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1160 BitVector UndefElements;
1161 CN = BV->getConstantSplatNode(&UndefElements);
1162 // Only interested in constant splats, and we don't try to handle undef
1163 // elements in identifying boolean constants.
1164 if (!CN || UndefElements.none())
1168 switch (getBooleanContents(N->getValueType(0))) {
1169 case UndefinedBooleanContent:
1170 return CN->getAPIntValue()[0];
1171 case ZeroOrOneBooleanContent:
1173 case ZeroOrNegativeOneBooleanContent:
1174 return CN->isAllOnesValue();
1177 llvm_unreachable("Invalid boolean contents");
1180 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1184 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1186 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1190 BitVector UndefElements;
1191 CN = BV->getConstantSplatNode(&UndefElements);
1192 // Only interested in constant splats, and we don't try to handle undef
1193 // elements in identifying boolean constants.
1194 if (!CN || UndefElements.none())
1198 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1199 return !CN->getAPIntValue()[0];
1201 return CN->isNullValue();
1204 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1205 /// and cc. If it is unable to simplify it, return a null SDValue.
1207 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1208 ISD::CondCode Cond, bool foldBooleans,
1209 DAGCombinerInfo &DCI, SDLoc dl) const {
1210 SelectionDAG &DAG = DCI.DAG;
1212 // These setcc operations always fold.
1216 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1218 case ISD::SETTRUE2: {
1219 TargetLowering::BooleanContent Cnt =
1220 getBooleanContents(N0->getValueType(0));
1221 return DAG.getConstant(
1222 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1226 // Ensure that the constant occurs on the RHS, and fold constant
1228 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1229 if (isa<ConstantSDNode>(N0.getNode()) &&
1230 (DCI.isBeforeLegalizeOps() ||
1231 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1232 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1234 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1235 const APInt &C1 = N1C->getAPIntValue();
1237 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1238 // equality comparison, then we're just comparing whether X itself is
1240 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1241 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1242 N0.getOperand(1).getOpcode() == ISD::Constant) {
1244 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1245 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1246 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1247 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1248 // (srl (ctlz x), 5) == 0 -> X != 0
1249 // (srl (ctlz x), 5) != 1 -> X != 0
1252 // (srl (ctlz x), 5) != 0 -> X == 0
1253 // (srl (ctlz x), 5) == 1 -> X == 0
1256 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1257 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1263 // Look through truncs that don't change the value of a ctpop.
1264 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1265 CTPOP = N0.getOperand(0);
1267 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1268 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1269 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1270 EVT CTVT = CTPOP.getValueType();
1271 SDValue CTOp = CTPOP.getOperand(0);
1273 // (ctpop x) u< 2 -> (x & x-1) == 0
1274 // (ctpop x) u> 1 -> (x & x-1) != 0
1275 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1276 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1277 DAG.getConstant(1, CTVT));
1278 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1279 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1280 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1283 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1286 // (zext x) == C --> x == (trunc C)
1287 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1288 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1289 unsigned MinBits = N0.getValueSizeInBits();
1291 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1293 MinBits = N0->getOperand(0).getValueSizeInBits();
1294 PreZExt = N0->getOperand(0);
1295 } else if (N0->getOpcode() == ISD::AND) {
1296 // DAGCombine turns costly ZExts into ANDs
1297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1298 if ((C->getAPIntValue()+1).isPowerOf2()) {
1299 MinBits = C->getAPIntValue().countTrailingOnes();
1300 PreZExt = N0->getOperand(0);
1302 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1304 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1305 MinBits = LN0->getMemoryVT().getSizeInBits();
1310 // Make sure we're not losing bits from the constant.
1312 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1313 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1314 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1315 // Will get folded away.
1316 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1317 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1318 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1323 // If the LHS is '(and load, const)', the RHS is 0,
1324 // the test is for equality or unsigned, and all 1 bits of the const are
1325 // in the same partial word, see if we can shorten the load.
1326 if (DCI.isBeforeLegalize() &&
1327 !ISD::isSignedIntSetCC(Cond) &&
1328 N0.getOpcode() == ISD::AND && C1 == 0 &&
1329 N0.getNode()->hasOneUse() &&
1330 isa<LoadSDNode>(N0.getOperand(0)) &&
1331 N0.getOperand(0).getNode()->hasOneUse() &&
1332 isa<ConstantSDNode>(N0.getOperand(1))) {
1333 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1335 unsigned bestWidth = 0, bestOffset = 0;
1336 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1337 unsigned origWidth = N0.getValueType().getSizeInBits();
1338 unsigned maskWidth = origWidth;
1339 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1340 // 8 bits, but have to be careful...
1341 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1342 origWidth = Lod->getMemoryVT().getSizeInBits();
1344 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1345 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1346 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1347 for (unsigned offset=0; offset<origWidth/width; offset++) {
1348 if ((newMask & Mask) == Mask) {
1349 if (!getDataLayout()->isLittleEndian())
1350 bestOffset = (origWidth/width - offset - 1) * (width/8);
1352 bestOffset = (uint64_t)offset * (width/8);
1353 bestMask = Mask.lshr(offset * (width/8) * 8);
1357 newMask = newMask << width;
1362 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1363 if (newVT.isRound()) {
1364 EVT PtrType = Lod->getOperand(1).getValueType();
1365 SDValue Ptr = Lod->getBasePtr();
1366 if (bestOffset != 0)
1367 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1368 DAG.getConstant(bestOffset, PtrType));
1369 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1370 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1371 Lod->getPointerInfo().getWithOffset(bestOffset),
1372 false, false, false, NewAlign);
1373 return DAG.getSetCC(dl, VT,
1374 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1375 DAG.getConstant(bestMask.trunc(bestWidth),
1377 DAG.getConstant(0LL, newVT), Cond);
1382 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1383 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1384 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1386 // If the comparison constant has bits in the upper part, the
1387 // zero-extended value could never match.
1388 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1389 C1.getBitWidth() - InSize))) {
1393 case ISD::SETEQ: return DAG.getConstant(0, VT);
1396 case ISD::SETNE: return DAG.getConstant(1, VT);
1399 // True if the sign bit of C1 is set.
1400 return DAG.getConstant(C1.isNegative(), VT);
1403 // True if the sign bit of C1 isn't set.
1404 return DAG.getConstant(C1.isNonNegative(), VT);
1410 // Otherwise, we can perform the comparison with the low bits.
1418 EVT newVT = N0.getOperand(0).getValueType();
1419 if (DCI.isBeforeLegalizeOps() ||
1420 (isOperationLegal(ISD::SETCC, newVT) &&
1421 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1422 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1423 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1425 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1427 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1432 break; // todo, be more careful with signed comparisons
1434 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1435 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1436 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1437 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1438 EVT ExtDstTy = N0.getValueType();
1439 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1441 // If the constant doesn't fit into the number of bits for the source of
1442 // the sign extension, it is impossible for both sides to be equal.
1443 if (C1.getMinSignedBits() > ExtSrcTyBits)
1444 return DAG.getConstant(Cond == ISD::SETNE, VT);
1447 EVT Op0Ty = N0.getOperand(0).getValueType();
1448 if (Op0Ty == ExtSrcTy) {
1449 ZextOp = N0.getOperand(0);
1451 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1452 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1453 DAG.getConstant(Imm, Op0Ty));
1455 if (!DCI.isCalledByLegalizer())
1456 DCI.AddToWorklist(ZextOp.getNode());
1457 // Otherwise, make this a use of a zext.
1458 return DAG.getSetCC(dl, VT, ZextOp,
1459 DAG.getConstant(C1 & APInt::getLowBitsSet(
1464 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1465 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1466 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1467 if (N0.getOpcode() == ISD::SETCC &&
1468 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1469 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1471 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1472 // Invert the condition.
1473 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1474 CC = ISD::getSetCCInverse(CC,
1475 N0.getOperand(0).getValueType().isInteger());
1476 if (DCI.isBeforeLegalizeOps() ||
1477 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1478 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1481 if ((N0.getOpcode() == ISD::XOR ||
1482 (N0.getOpcode() == ISD::AND &&
1483 N0.getOperand(0).getOpcode() == ISD::XOR &&
1484 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1485 isa<ConstantSDNode>(N0.getOperand(1)) &&
1486 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1487 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1488 // can only do this if the top bits are known zero.
1489 unsigned BitWidth = N0.getValueSizeInBits();
1490 if (DAG.MaskedValueIsZero(N0,
1491 APInt::getHighBitsSet(BitWidth,
1493 // Okay, get the un-inverted input value.
1495 if (N0.getOpcode() == ISD::XOR)
1496 Val = N0.getOperand(0);
1498 assert(N0.getOpcode() == ISD::AND &&
1499 N0.getOperand(0).getOpcode() == ISD::XOR);
1500 // ((X^1)&1)^1 -> X & 1
1501 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1502 N0.getOperand(0).getOperand(0),
1506 return DAG.getSetCC(dl, VT, Val, N1,
1507 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1509 } else if (N1C->getAPIntValue() == 1 &&
1511 getBooleanContents(N0->getValueType(0)) ==
1512 ZeroOrOneBooleanContent)) {
1514 if (Op0.getOpcode() == ISD::TRUNCATE)
1515 Op0 = Op0.getOperand(0);
1517 if ((Op0.getOpcode() == ISD::XOR) &&
1518 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1519 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1520 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1521 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1522 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1525 if (Op0.getOpcode() == ISD::AND &&
1526 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1527 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1528 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1529 if (Op0.getValueType().bitsGT(VT))
1530 Op0 = DAG.getNode(ISD::AND, dl, VT,
1531 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1532 DAG.getConstant(1, VT));
1533 else if (Op0.getValueType().bitsLT(VT))
1534 Op0 = DAG.getNode(ISD::AND, dl, VT,
1535 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1536 DAG.getConstant(1, VT));
1538 return DAG.getSetCC(dl, VT, Op0,
1539 DAG.getConstant(0, Op0.getValueType()),
1540 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1542 if (Op0.getOpcode() == ISD::AssertZext &&
1543 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1544 return DAG.getSetCC(dl, VT, Op0,
1545 DAG.getConstant(0, Op0.getValueType()),
1546 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1550 APInt MinVal, MaxVal;
1551 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1552 if (ISD::isSignedIntSetCC(Cond)) {
1553 MinVal = APInt::getSignedMinValue(OperandBitSize);
1554 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1556 MinVal = APInt::getMinValue(OperandBitSize);
1557 MaxVal = APInt::getMaxValue(OperandBitSize);
1560 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1561 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1562 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1563 // X >= C0 --> X > (C0 - 1)
1565 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1566 if ((DCI.isBeforeLegalizeOps() ||
1567 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1568 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1569 isLegalICmpImmediate(C.getSExtValue())))) {
1570 return DAG.getSetCC(dl, VT, N0,
1571 DAG.getConstant(C, N1.getValueType()),
1576 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1577 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1578 // X <= C0 --> X < (C0 + 1)
1580 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1581 if ((DCI.isBeforeLegalizeOps() ||
1582 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1583 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1584 isLegalICmpImmediate(C.getSExtValue())))) {
1585 return DAG.getSetCC(dl, VT, N0,
1586 DAG.getConstant(C, N1.getValueType()),
1591 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1592 return DAG.getConstant(0, VT); // X < MIN --> false
1593 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1594 return DAG.getConstant(1, VT); // X >= MIN --> true
1595 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1596 return DAG.getConstant(0, VT); // X > MAX --> false
1597 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1598 return DAG.getConstant(1, VT); // X <= MAX --> true
1600 // Canonicalize setgt X, Min --> setne X, Min
1601 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1602 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1603 // Canonicalize setlt X, Max --> setne X, Max
1604 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1605 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1607 // If we have setult X, 1, turn it into seteq X, 0
1608 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1609 return DAG.getSetCC(dl, VT, N0,
1610 DAG.getConstant(MinVal, N0.getValueType()),
1612 // If we have setugt X, Max-1, turn it into seteq X, Max
1613 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1614 return DAG.getSetCC(dl, VT, N0,
1615 DAG.getConstant(MaxVal, N0.getValueType()),
1618 // If we have "setcc X, C0", check to see if we can shrink the immediate
1621 // SETUGT X, SINTMAX -> SETLT X, 0
1622 if (Cond == ISD::SETUGT &&
1623 C1 == APInt::getSignedMaxValue(OperandBitSize))
1624 return DAG.getSetCC(dl, VT, N0,
1625 DAG.getConstant(0, N1.getValueType()),
1628 // SETULT X, SINTMIN -> SETGT X, -1
1629 if (Cond == ISD::SETULT &&
1630 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1631 SDValue ConstMinusOne =
1632 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1634 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1637 // Fold bit comparisons when we can.
1638 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1639 (VT == N0.getValueType() ||
1640 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1641 N0.getOpcode() == ISD::AND)
1642 if (ConstantSDNode *AndRHS =
1643 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1644 EVT ShiftTy = DCI.isBeforeLegalize() ?
1645 getPointerTy() : getShiftAmountTy(N0.getValueType());
1646 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1647 // Perform the xform if the AND RHS is a single bit.
1648 if (AndRHS->getAPIntValue().isPowerOf2()) {
1649 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1650 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1651 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1653 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1654 // (X & 8) == 8 --> (X & 8) >> 3
1655 // Perform the xform if C1 is a single bit.
1656 if (C1.isPowerOf2()) {
1657 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1658 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1659 DAG.getConstant(C1.logBase2(), ShiftTy)));
1664 if (C1.getMinSignedBits() <= 64 &&
1665 !isLegalICmpImmediate(C1.getSExtValue())) {
1666 // (X & -256) == 256 -> (X >> 8) == 1
1667 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1668 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1669 if (ConstantSDNode *AndRHS =
1670 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1671 const APInt &AndRHSC = AndRHS->getAPIntValue();
1672 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1673 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1674 EVT ShiftTy = DCI.isBeforeLegalize() ?
1675 getPointerTy() : getShiftAmountTy(N0.getValueType());
1676 EVT CmpTy = N0.getValueType();
1677 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1678 DAG.getConstant(ShiftBits, ShiftTy));
1679 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1680 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1683 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1684 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1685 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1686 // X < 0x100000000 -> (X >> 32) < 1
1687 // X >= 0x100000000 -> (X >> 32) >= 1
1688 // X <= 0x0ffffffff -> (X >> 32) < 1
1689 // X > 0x0ffffffff -> (X >> 32) >= 1
1692 ISD::CondCode NewCond = Cond;
1694 ShiftBits = C1.countTrailingOnes();
1696 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1698 ShiftBits = C1.countTrailingZeros();
1700 NewC = NewC.lshr(ShiftBits);
1701 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1702 EVT ShiftTy = DCI.isBeforeLegalize() ?
1703 getPointerTy() : getShiftAmountTy(N0.getValueType());
1704 EVT CmpTy = N0.getValueType();
1705 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1706 DAG.getConstant(ShiftBits, ShiftTy));
1707 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1708 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1714 if (isa<ConstantFPSDNode>(N0.getNode())) {
1715 // Constant fold or commute setcc.
1716 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1717 if (O.getNode()) return O;
1718 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1719 // If the RHS of an FP comparison is a constant, simplify it away in
1721 if (CFP->getValueAPF().isNaN()) {
1722 // If an operand is known to be a nan, we can fold it.
1723 switch (ISD::getUnorderedFlavor(Cond)) {
1724 default: llvm_unreachable("Unknown flavor!");
1725 case 0: // Known false.
1726 return DAG.getConstant(0, VT);
1727 case 1: // Known true.
1728 return DAG.getConstant(1, VT);
1729 case 2: // Undefined.
1730 return DAG.getUNDEF(VT);
1734 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1735 // constant if knowing that the operand is non-nan is enough. We prefer to
1736 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1738 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1739 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1741 // If the condition is not legal, see if we can find an equivalent one
1743 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1744 // If the comparison was an awkward floating-point == or != and one of
1745 // the comparison operands is infinity or negative infinity, convert the
1746 // condition to a less-awkward <= or >=.
1747 if (CFP->getValueAPF().isInfinity()) {
1748 if (CFP->getValueAPF().isNegative()) {
1749 if (Cond == ISD::SETOEQ &&
1750 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1751 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1752 if (Cond == ISD::SETUEQ &&
1753 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1754 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1755 if (Cond == ISD::SETUNE &&
1756 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1757 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1758 if (Cond == ISD::SETONE &&
1759 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1760 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1762 if (Cond == ISD::SETOEQ &&
1763 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1764 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1765 if (Cond == ISD::SETUEQ &&
1766 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1767 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1768 if (Cond == ISD::SETUNE &&
1769 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1770 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1771 if (Cond == ISD::SETONE &&
1772 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1773 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1780 // The sext(setcc()) => setcc() optimization relies on the appropriate
1781 // constant being emitted.
1783 switch (getBooleanContents(N0.getValueType())) {
1784 case UndefinedBooleanContent:
1785 case ZeroOrOneBooleanContent:
1786 EqVal = ISD::isTrueWhenEqual(Cond);
1788 case ZeroOrNegativeOneBooleanContent:
1789 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1793 // We can always fold X == X for integer setcc's.
1794 if (N0.getValueType().isInteger()) {
1795 return DAG.getConstant(EqVal, VT);
1797 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1798 if (UOF == 2) // FP operators that are undefined on NaNs.
1799 return DAG.getConstant(EqVal, VT);
1800 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1801 return DAG.getConstant(EqVal, VT);
1802 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1803 // if it is not already.
1804 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1805 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1806 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1807 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1810 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1811 N0.getValueType().isInteger()) {
1812 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1813 N0.getOpcode() == ISD::XOR) {
1814 // Simplify (X+Y) == (X+Z) --> Y == Z
1815 if (N0.getOpcode() == N1.getOpcode()) {
1816 if (N0.getOperand(0) == N1.getOperand(0))
1817 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1818 if (N0.getOperand(1) == N1.getOperand(1))
1819 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1820 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1821 // If X op Y == Y op X, try other combinations.
1822 if (N0.getOperand(0) == N1.getOperand(1))
1823 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1825 if (N0.getOperand(1) == N1.getOperand(0))
1826 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1831 // If RHS is a legal immediate value for a compare instruction, we need
1832 // to be careful about increasing register pressure needlessly.
1833 bool LegalRHSImm = false;
1835 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1836 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1837 // Turn (X+C1) == C2 --> X == C2-C1
1838 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1839 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1840 DAG.getConstant(RHSC->getAPIntValue()-
1841 LHSR->getAPIntValue(),
1842 N0.getValueType()), Cond);
1845 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1846 if (N0.getOpcode() == ISD::XOR)
1847 // If we know that all of the inverted bits are zero, don't bother
1848 // performing the inversion.
1849 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1851 DAG.getSetCC(dl, VT, N0.getOperand(0),
1852 DAG.getConstant(LHSR->getAPIntValue() ^
1853 RHSC->getAPIntValue(),
1858 // Turn (C1-X) == C2 --> X == C1-C2
1859 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1860 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1862 DAG.getSetCC(dl, VT, N0.getOperand(1),
1863 DAG.getConstant(SUBC->getAPIntValue() -
1864 RHSC->getAPIntValue(),
1870 // Could RHSC fold directly into a compare?
1871 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1872 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1875 // Simplify (X+Z) == X --> Z == 0
1876 // Don't do this if X is an immediate that can fold into a cmp
1877 // instruction and X+Z has other uses. It could be an induction variable
1878 // chain, and the transform would increase register pressure.
1879 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1880 if (N0.getOperand(0) == N1)
1881 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1882 DAG.getConstant(0, N0.getValueType()), Cond);
1883 if (N0.getOperand(1) == N1) {
1884 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1885 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1886 DAG.getConstant(0, N0.getValueType()), Cond);
1887 if (N0.getNode()->hasOneUse()) {
1888 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1889 // (Z-X) == X --> Z == X<<1
1890 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1891 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1892 if (!DCI.isCalledByLegalizer())
1893 DCI.AddToWorklist(SH.getNode());
1894 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1900 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1901 N1.getOpcode() == ISD::XOR) {
1902 // Simplify X == (X+Z) --> Z == 0
1903 if (N1.getOperand(0) == N0)
1904 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1905 DAG.getConstant(0, N1.getValueType()), Cond);
1906 if (N1.getOperand(1) == N0) {
1907 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1908 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1909 DAG.getConstant(0, N1.getValueType()), Cond);
1910 if (N1.getNode()->hasOneUse()) {
1911 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1912 // X == (Z-X) --> X<<1 == Z
1913 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1914 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1915 if (!DCI.isCalledByLegalizer())
1916 DCI.AddToWorklist(SH.getNode());
1917 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1922 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1923 // Note that where y is variable and is known to have at most
1924 // one bit set (for example, if it is z&1) we cannot do this;
1925 // the expressions are not equivalent when y==0.
1926 if (N0.getOpcode() == ISD::AND)
1927 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1928 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1929 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1930 if (DCI.isBeforeLegalizeOps() ||
1931 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1932 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1933 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1937 if (N1.getOpcode() == ISD::AND)
1938 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1939 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1940 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1941 if (DCI.isBeforeLegalizeOps() ||
1942 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1943 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1944 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1950 // Fold away ALL boolean setcc's.
1952 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1954 default: llvm_unreachable("Unknown integer setcc!");
1955 case ISD::SETEQ: // X == Y -> ~(X^Y)
1956 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1957 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1958 if (!DCI.isCalledByLegalizer())
1959 DCI.AddToWorklist(Temp.getNode());
1961 case ISD::SETNE: // X != Y --> (X^Y)
1962 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1964 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1965 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1966 Temp = DAG.getNOT(dl, N0, MVT::i1);
1967 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1968 if (!DCI.isCalledByLegalizer())
1969 DCI.AddToWorklist(Temp.getNode());
1971 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1972 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1973 Temp = DAG.getNOT(dl, N1, MVT::i1);
1974 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1975 if (!DCI.isCalledByLegalizer())
1976 DCI.AddToWorklist(Temp.getNode());
1978 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1979 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1980 Temp = DAG.getNOT(dl, N0, MVT::i1);
1981 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1982 if (!DCI.isCalledByLegalizer())
1983 DCI.AddToWorklist(Temp.getNode());
1985 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1986 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1987 Temp = DAG.getNOT(dl, N1, MVT::i1);
1988 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1991 if (VT != MVT::i1) {
1992 if (!DCI.isCalledByLegalizer())
1993 DCI.AddToWorklist(N0.getNode());
1994 // FIXME: If running after legalize, we probably can't do this.
1995 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2000 // Could not fold it.
2004 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2005 /// node is a GlobalAddress + offset.
2006 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2007 int64_t &Offset) const {
2008 if (isa<GlobalAddressSDNode>(N)) {
2009 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2010 GA = GASD->getGlobal();
2011 Offset += GASD->getOffset();
2015 if (N->getOpcode() == ISD::ADD) {
2016 SDValue N1 = N->getOperand(0);
2017 SDValue N2 = N->getOperand(1);
2018 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2019 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2021 Offset += V->getSExtValue();
2024 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2025 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2027 Offset += V->getSExtValue();
2037 SDValue TargetLowering::
2038 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2039 // Default implementation: no optimization.
2043 //===----------------------------------------------------------------------===//
2044 // Inline Assembler Implementation Methods
2045 //===----------------------------------------------------------------------===//
2048 TargetLowering::ConstraintType
2049 TargetLowering::getConstraintType(const std::string &Constraint) const {
2050 unsigned S = Constraint.size();
2053 switch (Constraint[0]) {
2055 case 'r': return C_RegisterClass;
2057 case 'o': // offsetable
2058 case 'V': // not offsetable
2060 case 'i': // Simple Integer or Relocatable Constant
2061 case 'n': // Simple Integer
2062 case 'E': // Floating Point Constant
2063 case 'F': // Floating Point Constant
2064 case 's': // Relocatable Constant
2065 case 'p': // Address.
2066 case 'X': // Allow ANY value.
2067 case 'I': // Target registers.
2081 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2082 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2089 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2090 /// with another that has more specific requirements based on the type of the
2091 /// corresponding operand.
2092 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2093 if (ConstraintVT.isInteger())
2095 if (ConstraintVT.isFloatingPoint())
2096 return "f"; // works for many targets
2100 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2101 /// vector. If it is invalid, don't add anything to Ops.
2102 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2103 std::string &Constraint,
2104 std::vector<SDValue> &Ops,
2105 SelectionDAG &DAG) const {
2107 if (Constraint.length() > 1) return;
2109 char ConstraintLetter = Constraint[0];
2110 switch (ConstraintLetter) {
2112 case 'X': // Allows any operand; labels (basic block) use this.
2113 if (Op.getOpcode() == ISD::BasicBlock) {
2118 case 'i': // Simple Integer or Relocatable Constant
2119 case 'n': // Simple Integer
2120 case 's': { // Relocatable Constant
2121 // These operands are interested in values of the form (GV+C), where C may
2122 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2123 // is possible and fine if either GV or C are missing.
2124 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2125 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2127 // If we have "(add GV, C)", pull out GV/C
2128 if (Op.getOpcode() == ISD::ADD) {
2129 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2130 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2132 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2133 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2136 C = nullptr, GA = nullptr;
2139 // If we find a valid operand, map to the TargetXXX version so that the
2140 // value itself doesn't get selected.
2141 if (GA) { // Either &GV or &GV+C
2142 if (ConstraintLetter != 'n') {
2143 int64_t Offs = GA->getOffset();
2144 if (C) Offs += C->getZExtValue();
2145 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2146 C ? SDLoc(C) : SDLoc(),
2147 Op.getValueType(), Offs));
2151 if (C) { // just C, no GV.
2152 // Simple constants are not allowed for 's'.
2153 if (ConstraintLetter != 's') {
2154 // gcc prints these as sign extended. Sign extend value to 64 bits
2155 // now; without this it would get ZExt'd later in
2156 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2157 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2167 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2168 getRegForInlineAsmConstraint(const std::string &Constraint,
2170 if (Constraint.empty() || Constraint[0] != '{')
2171 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2172 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2174 // Remove the braces from around the name.
2175 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2177 std::pair<unsigned, const TargetRegisterClass*> R =
2178 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2180 // Figure out which register class contains this reg.
2181 const TargetRegisterInfo *RI =
2182 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2183 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2184 E = RI->regclass_end(); RCI != E; ++RCI) {
2185 const TargetRegisterClass *RC = *RCI;
2187 // If none of the value types for this register class are valid, we
2188 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2192 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2194 if (RegName.equals_lower(RI->getName(*I))) {
2195 std::pair<unsigned, const TargetRegisterClass*> S =
2196 std::make_pair(*I, RC);
2198 // If this register class has the requested value type, return it,
2199 // otherwise keep searching and return the first class found
2200 // if no other is found which explicitly has the requested type.
2201 if (RC->hasType(VT))
2212 //===----------------------------------------------------------------------===//
2213 // Constraint Selection.
2215 /// isMatchingInputConstraint - Return true of this is an input operand that is
2216 /// a matching constraint like "4".
2217 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2218 assert(!ConstraintCode.empty() && "No known constraint!");
2219 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2222 /// getMatchedOperand - If this is an input matching constraint, this method
2223 /// returns the output operand it matches.
2224 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2225 assert(!ConstraintCode.empty() && "No known constraint!");
2226 return atoi(ConstraintCode.c_str());
2230 /// ParseConstraints - Split up the constraint string from the inline
2231 /// assembly value into the specific constraints and their prefixes,
2232 /// and also tie in the associated operand values.
2233 /// If this returns an empty vector, and if the constraint string itself
2234 /// isn't empty, there was an error parsing.
2235 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2236 ImmutableCallSite CS) const {
2237 /// ConstraintOperands - Information about all of the constraints.
2238 AsmOperandInfoVector ConstraintOperands;
2239 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2240 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2242 // Do a prepass over the constraints, canonicalizing them, and building up the
2243 // ConstraintOperands list.
2244 InlineAsm::ConstraintInfoVector
2245 ConstraintInfos = IA->ParseConstraints();
2247 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2248 unsigned ResNo = 0; // ResNo - The result number of the next output.
2250 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2251 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2252 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2254 // Update multiple alternative constraint count.
2255 if (OpInfo.multipleAlternatives.size() > maCount)
2256 maCount = OpInfo.multipleAlternatives.size();
2258 OpInfo.ConstraintVT = MVT::Other;
2260 // Compute the value type for each operand.
2261 switch (OpInfo.Type) {
2262 case InlineAsm::isOutput:
2263 // Indirect outputs just consume an argument.
2264 if (OpInfo.isIndirect) {
2265 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2269 // The return value of the call is this value. As such, there is no
2270 // corresponding argument.
2271 assert(!CS.getType()->isVoidTy() &&
2273 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2274 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2276 assert(ResNo == 0 && "Asm only has one result!");
2277 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2281 case InlineAsm::isInput:
2282 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2284 case InlineAsm::isClobber:
2289 if (OpInfo.CallOperandVal) {
2290 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2291 if (OpInfo.isIndirect) {
2292 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2294 report_fatal_error("Indirect operand for inline asm not a pointer!");
2295 OpTy = PtrTy->getElementType();
2298 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2299 if (StructType *STy = dyn_cast<StructType>(OpTy))
2300 if (STy->getNumElements() == 1)
2301 OpTy = STy->getElementType(0);
2303 // If OpTy is not a single value, it may be a struct/union that we
2304 // can tile with integers.
2305 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2306 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2315 OpInfo.ConstraintVT =
2316 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2319 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2321 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2322 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2324 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2329 // If we have multiple alternative constraints, select the best alternative.
2330 if (ConstraintInfos.size()) {
2332 unsigned bestMAIndex = 0;
2333 int bestWeight = -1;
2334 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2337 // Compute the sums of the weights for each alternative, keeping track
2338 // of the best (highest weight) one so far.
2339 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2341 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2342 cIndex != eIndex; ++cIndex) {
2343 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2344 if (OpInfo.Type == InlineAsm::isClobber)
2347 // If this is an output operand with a matching input operand,
2348 // look up the matching input. If their types mismatch, e.g. one
2349 // is an integer, the other is floating point, or their sizes are
2350 // different, flag it as an maCantMatch.
2351 if (OpInfo.hasMatchingInput()) {
2352 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2353 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2354 if ((OpInfo.ConstraintVT.isInteger() !=
2355 Input.ConstraintVT.isInteger()) ||
2356 (OpInfo.ConstraintVT.getSizeInBits() !=
2357 Input.ConstraintVT.getSizeInBits())) {
2358 weightSum = -1; // Can't match.
2363 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2368 weightSum += weight;
2371 if (weightSum > bestWeight) {
2372 bestWeight = weightSum;
2373 bestMAIndex = maIndex;
2377 // Now select chosen alternative in each constraint.
2378 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2379 cIndex != eIndex; ++cIndex) {
2380 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2381 if (cInfo.Type == InlineAsm::isClobber)
2383 cInfo.selectAlternative(bestMAIndex);
2388 // Check and hook up tied operands, choose constraint code to use.
2389 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2390 cIndex != eIndex; ++cIndex) {
2391 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2393 // If this is an output operand with a matching input operand, look up the
2394 // matching input. If their types mismatch, e.g. one is an integer, the
2395 // other is floating point, or their sizes are different, flag it as an
2397 if (OpInfo.hasMatchingInput()) {
2398 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2400 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2401 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2402 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2403 OpInfo.ConstraintVT);
2404 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2405 getRegForInlineAsmConstraint(Input.ConstraintCode,
2406 Input.ConstraintVT);
2407 if ((OpInfo.ConstraintVT.isInteger() !=
2408 Input.ConstraintVT.isInteger()) ||
2409 (MatchRC.second != InputRC.second)) {
2410 report_fatal_error("Unsupported asm: input constraint"
2411 " with a matching output constraint of"
2412 " incompatible type!");
2419 return ConstraintOperands;
2423 /// getConstraintGenerality - Return an integer indicating how general CT
2425 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2427 case TargetLowering::C_Other:
2428 case TargetLowering::C_Unknown:
2430 case TargetLowering::C_Register:
2432 case TargetLowering::C_RegisterClass:
2434 case TargetLowering::C_Memory:
2437 llvm_unreachable("Invalid constraint type");
2440 /// Examine constraint type and operand type and determine a weight value.
2441 /// This object must already have been set up with the operand type
2442 /// and the current alternative constraint selected.
2443 TargetLowering::ConstraintWeight
2444 TargetLowering::getMultipleConstraintMatchWeight(
2445 AsmOperandInfo &info, int maIndex) const {
2446 InlineAsm::ConstraintCodeVector *rCodes;
2447 if (maIndex >= (int)info.multipleAlternatives.size())
2448 rCodes = &info.Codes;
2450 rCodes = &info.multipleAlternatives[maIndex].Codes;
2451 ConstraintWeight BestWeight = CW_Invalid;
2453 // Loop over the options, keeping track of the most general one.
2454 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2455 ConstraintWeight weight =
2456 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2457 if (weight > BestWeight)
2458 BestWeight = weight;
2464 /// Examine constraint type and operand type and determine a weight value.
2465 /// This object must already have been set up with the operand type
2466 /// and the current alternative constraint selected.
2467 TargetLowering::ConstraintWeight
2468 TargetLowering::getSingleConstraintMatchWeight(
2469 AsmOperandInfo &info, const char *constraint) const {
2470 ConstraintWeight weight = CW_Invalid;
2471 Value *CallOperandVal = info.CallOperandVal;
2472 // If we don't have a value, we can't do a match,
2473 // but allow it at the lowest weight.
2474 if (!CallOperandVal)
2476 // Look at the constraint type.
2477 switch (*constraint) {
2478 case 'i': // immediate integer.
2479 case 'n': // immediate integer with a known value.
2480 if (isa<ConstantInt>(CallOperandVal))
2481 weight = CW_Constant;
2483 case 's': // non-explicit intregal immediate.
2484 if (isa<GlobalValue>(CallOperandVal))
2485 weight = CW_Constant;
2487 case 'E': // immediate float if host format.
2488 case 'F': // immediate float.
2489 if (isa<ConstantFP>(CallOperandVal))
2490 weight = CW_Constant;
2492 case '<': // memory operand with autodecrement.
2493 case '>': // memory operand with autoincrement.
2494 case 'm': // memory operand.
2495 case 'o': // offsettable memory operand
2496 case 'V': // non-offsettable memory operand
2499 case 'r': // general register.
2500 case 'g': // general register, memory operand or immediate integer.
2501 // note: Clang converts "g" to "imr".
2502 if (CallOperandVal->getType()->isIntegerTy())
2503 weight = CW_Register;
2505 case 'X': // any operand.
2507 weight = CW_Default;
2513 /// ChooseConstraint - If there are multiple different constraints that we
2514 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2515 /// This is somewhat tricky: constraints fall into four classes:
2516 /// Other -> immediates and magic values
2517 /// Register -> one specific register
2518 /// RegisterClass -> a group of regs
2519 /// Memory -> memory
2520 /// Ideally, we would pick the most specific constraint possible: if we have
2521 /// something that fits into a register, we would pick it. The problem here
2522 /// is that if we have something that could either be in a register or in
2523 /// memory that use of the register could cause selection of *other*
2524 /// operands to fail: they might only succeed if we pick memory. Because of
2525 /// this the heuristic we use is:
2527 /// 1) If there is an 'other' constraint, and if the operand is valid for
2528 /// that constraint, use it. This makes us take advantage of 'i'
2529 /// constraints when available.
2530 /// 2) Otherwise, pick the most general constraint present. This prefers
2531 /// 'm' over 'r', for example.
2533 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2534 const TargetLowering &TLI,
2535 SDValue Op, SelectionDAG *DAG) {
2536 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2537 unsigned BestIdx = 0;
2538 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2539 int BestGenerality = -1;
2541 // Loop over the options, keeping track of the most general one.
2542 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2543 TargetLowering::ConstraintType CType =
2544 TLI.getConstraintType(OpInfo.Codes[i]);
2546 // If this is an 'other' constraint, see if the operand is valid for it.
2547 // For example, on X86 we might have an 'rI' constraint. If the operand
2548 // is an integer in the range [0..31] we want to use I (saving a load
2549 // of a register), otherwise we must use 'r'.
2550 if (CType == TargetLowering::C_Other && Op.getNode()) {
2551 assert(OpInfo.Codes[i].size() == 1 &&
2552 "Unhandled multi-letter 'other' constraint");
2553 std::vector<SDValue> ResultOps;
2554 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2556 if (!ResultOps.empty()) {
2563 // Things with matching constraints can only be registers, per gcc
2564 // documentation. This mainly affects "g" constraints.
2565 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2568 // This constraint letter is more general than the previous one, use it.
2569 int Generality = getConstraintGenerality(CType);
2570 if (Generality > BestGenerality) {
2573 BestGenerality = Generality;
2577 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2578 OpInfo.ConstraintType = BestType;
2581 /// ComputeConstraintToUse - Determines the constraint code and constraint
2582 /// type to use for the specific AsmOperandInfo, setting
2583 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2584 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2586 SelectionDAG *DAG) const {
2587 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2589 // Single-letter constraints ('r') are very common.
2590 if (OpInfo.Codes.size() == 1) {
2591 OpInfo.ConstraintCode = OpInfo.Codes[0];
2592 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2594 ChooseConstraint(OpInfo, *this, Op, DAG);
2597 // 'X' matches anything.
2598 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2599 // Labels and constants are handled elsewhere ('X' is the only thing
2600 // that matches labels). For Functions, the type here is the type of
2601 // the result, which is not what we want to look at; leave them alone.
2602 Value *v = OpInfo.CallOperandVal;
2603 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2604 OpInfo.CallOperandVal = v;
2608 // Otherwise, try to resolve it to something we know about by looking at
2609 // the actual operand type.
2610 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2611 OpInfo.ConstraintCode = Repl;
2612 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2617 /// \brief Given an exact SDIV by a constant, create a multiplication
2618 /// with the multiplicative inverse of the constant.
2619 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2620 SelectionDAG &DAG) const {
2621 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2622 APInt d = C->getAPIntValue();
2623 assert(d != 0 && "Division by zero!");
2625 // Shift the value upfront if it is even, so the LSB is one.
2626 unsigned ShAmt = d.countTrailingZeros();
2628 // TODO: For UDIV use SRL instead of SRA.
2629 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2630 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2635 // Calculate the multiplicative inverse, using Newton's method.
2637 while ((t = d*xn) != 1)
2638 xn *= APInt(d.getBitWidth(), 2) - t;
2640 Op2 = DAG.getConstant(xn, Op1.getValueType());
2641 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2644 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2645 /// return a DAG expression to select that will generate the same value by
2646 /// multiplying by a magic number.
2647 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2648 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2649 SelectionDAG &DAG, bool IsAfterLegalization,
2650 std::vector<SDNode *> *Created) const {
2651 assert(Created && "No vector to hold sdiv ops.");
2653 EVT VT = N->getValueType(0);
2656 // Check to see if we can do this.
2657 // FIXME: We should be more aggressive here.
2658 if (!isTypeLegal(VT))
2661 APInt::ms magics = Divisor.magic();
2663 // Multiply the numerator (operand 0) by the magic value
2664 // FIXME: We should support doing a MUL in a wider type
2666 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2667 isOperationLegalOrCustom(ISD::MULHS, VT))
2668 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2669 DAG.getConstant(magics.m, VT));
2670 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2671 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2672 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2674 DAG.getConstant(magics.m, VT)).getNode(), 1);
2676 return SDValue(); // No mulhs or equvialent
2677 // If d > 0 and m < 0, add the numerator
2678 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2679 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2680 Created->push_back(Q.getNode());
2682 // If d < 0 and m > 0, subtract the numerator.
2683 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2684 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2685 Created->push_back(Q.getNode());
2687 // Shift right algebraic if shift value is nonzero
2689 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2690 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2691 Created->push_back(Q.getNode());
2693 // Extract the sign bit and add it to the quotient
2694 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2695 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2696 getShiftAmountTy(Q.getValueType())));
2697 Created->push_back(T.getNode());
2698 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2701 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2702 /// return a DAG expression to select that will generate the same value by
2703 /// multiplying by a magic number.
2704 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2705 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2706 SelectionDAG &DAG, bool IsAfterLegalization,
2707 std::vector<SDNode *> *Created) const {
2708 assert(Created && "No vector to hold udiv ops.");
2710 EVT VT = N->getValueType(0);
2713 // Check to see if we can do this.
2714 // FIXME: We should be more aggressive here.
2715 if (!isTypeLegal(VT))
2718 // FIXME: We should use a narrower constant when the upper
2719 // bits are known to be zero.
2720 APInt::mu magics = Divisor.magicu();
2722 SDValue Q = N->getOperand(0);
2724 // If the divisor is even, we can avoid using the expensive fixup by shifting
2725 // the divided value upfront.
2726 if (magics.a != 0 && !Divisor[0]) {
2727 unsigned Shift = Divisor.countTrailingZeros();
2728 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2729 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2730 Created->push_back(Q.getNode());
2732 // Get magic number for the shifted divisor.
2733 magics = Divisor.lshr(Shift).magicu(Shift);
2734 assert(magics.a == 0 && "Should use cheap fixup now");
2737 // Multiply the numerator (operand 0) by the magic value
2738 // FIXME: We should support doing a MUL in a wider type
2739 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2740 isOperationLegalOrCustom(ISD::MULHU, VT))
2741 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2742 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2743 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2744 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2745 DAG.getConstant(magics.m, VT)).getNode(), 1);
2747 return SDValue(); // No mulhu or equvialent
2749 Created->push_back(Q.getNode());
2751 if (magics.a == 0) {
2752 assert(magics.s < Divisor.getBitWidth() &&
2753 "We shouldn't generate an undefined shift!");
2754 return DAG.getNode(ISD::SRL, dl, VT, Q,
2755 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2757 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2758 Created->push_back(NPQ.getNode());
2759 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2760 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2761 Created->push_back(NPQ.getNode());
2762 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2763 Created->push_back(NPQ.getNode());
2764 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2765 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2769 bool TargetLowering::
2770 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2771 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2772 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2773 "be a constant integer");
2780 //===----------------------------------------------------------------------===//
2781 // Legalization Utilities
2782 //===----------------------------------------------------------------------===//
2784 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2785 SelectionDAG &DAG, SDValue LL, SDValue LH,
2786 SDValue RL, SDValue RH) const {
2787 EVT VT = N->getValueType(0);
2790 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2791 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2792 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2793 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2794 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2795 unsigned OuterBitSize = VT.getSizeInBits();
2796 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2797 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2798 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2800 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2801 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2802 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2804 if (!LL.getNode() && !RL.getNode() &&
2805 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2806 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2807 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2813 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2814 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2815 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2816 // The inputs are both zero-extended.
2818 // We can emit a umul_lohi.
2819 Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2820 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2821 Hi = SDValue(Lo.getNode(), 1);
2825 // We can emit a mulhu+mul.
2826 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2827 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2831 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2832 // The input values are both sign-extended.
2834 // We can emit a smul_lohi.
2835 Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2836 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2837 Hi = SDValue(Lo.getNode(), 1);
2841 // We can emit a mulhs+mul.
2842 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2843 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2848 if (!LH.getNode() && !RH.getNode() &&
2849 isOperationLegalOrCustom(ISD::SRL, VT) &&
2850 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2851 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2852 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2853 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2854 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2855 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2856 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2863 // Lo,Hi = umul LHS, RHS.
2864 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2865 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2867 Hi = UMulLOHI.getValue(1);
2868 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2869 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2870 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2871 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2875 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2876 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2877 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2878 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2879 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2880 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2887 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2888 SelectionDAG &DAG) const {
2889 EVT VT = Node->getOperand(0).getValueType();
2890 EVT NVT = Node->getValueType(0);
2891 SDLoc dl(SDValue(Node, 0));
2893 // FIXME: Only f32 to i64 conversions are supported.
2894 if (VT != MVT::f32 || NVT != MVT::i64)
2897 // Expand f32 -> i64 conversion
2898 // This algorithm comes from compiler-rt's implementation of fixsfdi:
2899 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2900 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2901 VT.getSizeInBits());
2902 SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2903 SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2904 SDValue Bias = DAG.getConstant(127, IntVT);
2905 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2907 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2908 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2910 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2912 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2913 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2914 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2915 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2917 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2918 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2919 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2920 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2922 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2923 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2924 DAG.getConstant(0x00800000, IntVT));
2926 R = DAG.getZExtOrTrunc(R, dl, NVT);
2929 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2930 DAG.getNode(ISD::SHL, dl, NVT, R,
2932 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2933 dl, getShiftAmountTy(IntVT))),
2934 DAG.getNode(ISD::SRL, dl, NVT, R,
2936 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2937 dl, getShiftAmountTy(IntVT))),
2940 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2941 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2944 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2945 DAG.getConstant(0, NVT), Ret, ISD::SETLT);