1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtarget.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
34 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
45 return TLSModel::GeneralDynamic;
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
50 return TLSModel::InitialExec;
55 /// InitLibcallNames - Set default libcall names.
57 static void InitLibcallNames(const char **Names) {
58 Names[RTLIB::SHL_I16] = "__ashlhi3";
59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
61 Names[RTLIB::SHL_I128] = "__ashlti3";
62 Names[RTLIB::SRL_I16] = "__lshrhi3";
63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
65 Names[RTLIB::SRL_I128] = "__lshrti3";
66 Names[RTLIB::SRA_I16] = "__ashrhi3";
67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
69 Names[RTLIB::SRA_I128] = "__ashrti3";
70 Names[RTLIB::MUL_I8] = "__mulqi3";
71 Names[RTLIB::MUL_I16] = "__mulhi3";
72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
74 Names[RTLIB::MUL_I128] = "__multi3";
75 Names[RTLIB::SDIV_I8] = "__divqi3";
76 Names[RTLIB::SDIV_I16] = "__divhi3";
77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
79 Names[RTLIB::SDIV_I128] = "__divti3";
80 Names[RTLIB::UDIV_I8] = "__udivqi3";
81 Names[RTLIB::UDIV_I16] = "__udivhi3";
82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
84 Names[RTLIB::UDIV_I128] = "__udivti3";
85 Names[RTLIB::SREM_I8] = "__modqi3";
86 Names[RTLIB::SREM_I16] = "__modhi3";
87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
89 Names[RTLIB::SREM_I128] = "__modti3";
90 Names[RTLIB::UREM_I8] = "__umodqi3";
91 Names[RTLIB::UREM_I16] = "__umodhi3";
92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
94 Names[RTLIB::UREM_I128] = "__umodti3";
95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
99 Names[RTLIB::ADD_F80] = "__addxf3";
100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
103 Names[RTLIB::SUB_F80] = "__subxf3";
104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
107 Names[RTLIB::MUL_F80] = "__mulxf3";
108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
111 Names[RTLIB::DIV_F80] = "__divxf3";
112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
115 Names[RTLIB::REM_F80] = "fmodl";
116 Names[RTLIB::REM_PPCF128] = "fmodl";
117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
177 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
178 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
179 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
180 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
181 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
182 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
183 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
184 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
185 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
186 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
187 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
188 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
189 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
190 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
191 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
192 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
193 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
194 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
195 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
196 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
197 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
198 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
199 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
200 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
201 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
202 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
203 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
204 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
205 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
206 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
207 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
208 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
209 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
210 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
211 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
212 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
213 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
214 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
215 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
216 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
217 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
218 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
219 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
220 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
221 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
222 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
223 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
224 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
225 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
226 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
227 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
228 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
229 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
230 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
231 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
232 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
233 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
234 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
235 Names[RTLIB::OEQ_F32] = "__eqsf2";
236 Names[RTLIB::OEQ_F64] = "__eqdf2";
237 Names[RTLIB::UNE_F32] = "__nesf2";
238 Names[RTLIB::UNE_F64] = "__nedf2";
239 Names[RTLIB::OGE_F32] = "__gesf2";
240 Names[RTLIB::OGE_F64] = "__gedf2";
241 Names[RTLIB::OLT_F32] = "__ltsf2";
242 Names[RTLIB::OLT_F64] = "__ltdf2";
243 Names[RTLIB::OLE_F32] = "__lesf2";
244 Names[RTLIB::OLE_F64] = "__ledf2";
245 Names[RTLIB::OGT_F32] = "__gtsf2";
246 Names[RTLIB::OGT_F64] = "__gtdf2";
247 Names[RTLIB::UO_F32] = "__unordsf2";
248 Names[RTLIB::UO_F64] = "__unorddf2";
249 Names[RTLIB::O_F32] = "__unordsf2";
250 Names[RTLIB::O_F64] = "__unorddf2";
251 Names[RTLIB::MEMCPY] = "memcpy";
252 Names[RTLIB::MEMMOVE] = "memmove";
253 Names[RTLIB::MEMSET] = "memset";
254 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
257 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
259 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
260 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
261 CCs[i] = CallingConv::C;
265 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
266 /// UNKNOWN_LIBCALL if there is none.
267 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
268 if (OpVT == MVT::f32) {
269 if (RetVT == MVT::f64)
270 return FPEXT_F32_F64;
272 return UNKNOWN_LIBCALL;
275 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
276 /// UNKNOWN_LIBCALL if there is none.
277 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
278 if (RetVT == MVT::f32) {
279 if (OpVT == MVT::f64)
280 return FPROUND_F64_F32;
281 if (OpVT == MVT::f80)
282 return FPROUND_F80_F32;
283 if (OpVT == MVT::ppcf128)
284 return FPROUND_PPCF128_F32;
285 } else if (RetVT == MVT::f64) {
286 if (OpVT == MVT::f80)
287 return FPROUND_F80_F64;
288 if (OpVT == MVT::ppcf128)
289 return FPROUND_PPCF128_F64;
291 return UNKNOWN_LIBCALL;
294 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
295 /// UNKNOWN_LIBCALL if there is none.
296 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
297 if (OpVT == MVT::f32) {
298 if (RetVT == MVT::i8)
299 return FPTOSINT_F32_I8;
300 if (RetVT == MVT::i16)
301 return FPTOSINT_F32_I16;
302 if (RetVT == MVT::i32)
303 return FPTOSINT_F32_I32;
304 if (RetVT == MVT::i64)
305 return FPTOSINT_F32_I64;
306 if (RetVT == MVT::i128)
307 return FPTOSINT_F32_I128;
308 } else if (OpVT == MVT::f64) {
309 if (RetVT == MVT::i32)
310 return FPTOSINT_F64_I32;
311 if (RetVT == MVT::i64)
312 return FPTOSINT_F64_I64;
313 if (RetVT == MVT::i128)
314 return FPTOSINT_F64_I128;
315 } else if (OpVT == MVT::f80) {
316 if (RetVT == MVT::i32)
317 return FPTOSINT_F80_I32;
318 if (RetVT == MVT::i64)
319 return FPTOSINT_F80_I64;
320 if (RetVT == MVT::i128)
321 return FPTOSINT_F80_I128;
322 } else if (OpVT == MVT::ppcf128) {
323 if (RetVT == MVT::i32)
324 return FPTOSINT_PPCF128_I32;
325 if (RetVT == MVT::i64)
326 return FPTOSINT_PPCF128_I64;
327 if (RetVT == MVT::i128)
328 return FPTOSINT_PPCF128_I128;
330 return UNKNOWN_LIBCALL;
333 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
334 /// UNKNOWN_LIBCALL if there is none.
335 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
336 if (OpVT == MVT::f32) {
337 if (RetVT == MVT::i8)
338 return FPTOUINT_F32_I8;
339 if (RetVT == MVT::i16)
340 return FPTOUINT_F32_I16;
341 if (RetVT == MVT::i32)
342 return FPTOUINT_F32_I32;
343 if (RetVT == MVT::i64)
344 return FPTOUINT_F32_I64;
345 if (RetVT == MVT::i128)
346 return FPTOUINT_F32_I128;
347 } else if (OpVT == MVT::f64) {
348 if (RetVT == MVT::i32)
349 return FPTOUINT_F64_I32;
350 if (RetVT == MVT::i64)
351 return FPTOUINT_F64_I64;
352 if (RetVT == MVT::i128)
353 return FPTOUINT_F64_I128;
354 } else if (OpVT == MVT::f80) {
355 if (RetVT == MVT::i32)
356 return FPTOUINT_F80_I32;
357 if (RetVT == MVT::i64)
358 return FPTOUINT_F80_I64;
359 if (RetVT == MVT::i128)
360 return FPTOUINT_F80_I128;
361 } else if (OpVT == MVT::ppcf128) {
362 if (RetVT == MVT::i32)
363 return FPTOUINT_PPCF128_I32;
364 if (RetVT == MVT::i64)
365 return FPTOUINT_PPCF128_I64;
366 if (RetVT == MVT::i128)
367 return FPTOUINT_PPCF128_I128;
369 return UNKNOWN_LIBCALL;
372 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
373 /// UNKNOWN_LIBCALL if there is none.
374 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
375 if (OpVT == MVT::i32) {
376 if (RetVT == MVT::f32)
377 return SINTTOFP_I32_F32;
378 else if (RetVT == MVT::f64)
379 return SINTTOFP_I32_F64;
380 else if (RetVT == MVT::f80)
381 return SINTTOFP_I32_F80;
382 else if (RetVT == MVT::ppcf128)
383 return SINTTOFP_I32_PPCF128;
384 } else if (OpVT == MVT::i64) {
385 if (RetVT == MVT::f32)
386 return SINTTOFP_I64_F32;
387 else if (RetVT == MVT::f64)
388 return SINTTOFP_I64_F64;
389 else if (RetVT == MVT::f80)
390 return SINTTOFP_I64_F80;
391 else if (RetVT == MVT::ppcf128)
392 return SINTTOFP_I64_PPCF128;
393 } else if (OpVT == MVT::i128) {
394 if (RetVT == MVT::f32)
395 return SINTTOFP_I128_F32;
396 else if (RetVT == MVT::f64)
397 return SINTTOFP_I128_F64;
398 else if (RetVT == MVT::f80)
399 return SINTTOFP_I128_F80;
400 else if (RetVT == MVT::ppcf128)
401 return SINTTOFP_I128_PPCF128;
403 return UNKNOWN_LIBCALL;
406 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
407 /// UNKNOWN_LIBCALL if there is none.
408 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
409 if (OpVT == MVT::i32) {
410 if (RetVT == MVT::f32)
411 return UINTTOFP_I32_F32;
412 else if (RetVT == MVT::f64)
413 return UINTTOFP_I32_F64;
414 else if (RetVT == MVT::f80)
415 return UINTTOFP_I32_F80;
416 else if (RetVT == MVT::ppcf128)
417 return UINTTOFP_I32_PPCF128;
418 } else if (OpVT == MVT::i64) {
419 if (RetVT == MVT::f32)
420 return UINTTOFP_I64_F32;
421 else if (RetVT == MVT::f64)
422 return UINTTOFP_I64_F64;
423 else if (RetVT == MVT::f80)
424 return UINTTOFP_I64_F80;
425 else if (RetVT == MVT::ppcf128)
426 return UINTTOFP_I64_PPCF128;
427 } else if (OpVT == MVT::i128) {
428 if (RetVT == MVT::f32)
429 return UINTTOFP_I128_F32;
430 else if (RetVT == MVT::f64)
431 return UINTTOFP_I128_F64;
432 else if (RetVT == MVT::f80)
433 return UINTTOFP_I128_F80;
434 else if (RetVT == MVT::ppcf128)
435 return UINTTOFP_I128_PPCF128;
437 return UNKNOWN_LIBCALL;
440 /// InitCmpLibcallCCs - Set default comparison libcall CC.
442 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
443 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
444 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
445 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
446 CCs[RTLIB::UNE_F32] = ISD::SETNE;
447 CCs[RTLIB::UNE_F64] = ISD::SETNE;
448 CCs[RTLIB::OGE_F32] = ISD::SETGE;
449 CCs[RTLIB::OGE_F64] = ISD::SETGE;
450 CCs[RTLIB::OLT_F32] = ISD::SETLT;
451 CCs[RTLIB::OLT_F64] = ISD::SETLT;
452 CCs[RTLIB::OLE_F32] = ISD::SETLE;
453 CCs[RTLIB::OLE_F64] = ISD::SETLE;
454 CCs[RTLIB::OGT_F32] = ISD::SETGT;
455 CCs[RTLIB::OGT_F64] = ISD::SETGT;
456 CCs[RTLIB::UO_F32] = ISD::SETNE;
457 CCs[RTLIB::UO_F64] = ISD::SETNE;
458 CCs[RTLIB::O_F32] = ISD::SETEQ;
459 CCs[RTLIB::O_F64] = ISD::SETEQ;
462 /// NOTE: The constructor takes ownership of TLOF.
463 TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
464 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
465 // All operations default to being supported.
466 memset(OpActions, 0, sizeof(OpActions));
467 memset(LoadExtActions, 0, sizeof(LoadExtActions));
468 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
469 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
470 memset(ConvertActions, 0, sizeof(ConvertActions));
471 memset(CondCodeActions, 0, sizeof(CondCodeActions));
473 // Set default actions for various operations.
474 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
475 // Default all indexed load / store to expand.
476 for (unsigned IM = (unsigned)ISD::PRE_INC;
477 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
478 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
479 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
482 // These operations default to expand.
483 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
484 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
487 // Most targets ignore the @llvm.prefetch intrinsic.
488 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
490 // ConstantFP nodes default to expand. Targets can either change this to
491 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
492 // to optimize expansions for certain constants.
493 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
494 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
495 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
497 // These library functions default to expand.
498 setOperationAction(ISD::FLOG , MVT::f64, Expand);
499 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
500 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
501 setOperationAction(ISD::FEXP , MVT::f64, Expand);
502 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
503 setOperationAction(ISD::FLOG , MVT::f32, Expand);
504 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
505 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
506 setOperationAction(ISD::FEXP , MVT::f32, Expand);
507 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
509 // Default ISD::TRAP to expand (which turns it into abort).
510 setOperationAction(ISD::TRAP, MVT::Other, Expand);
512 IsLittleEndian = TD->isLittleEndian();
513 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
514 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
515 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
516 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
517 benefitFromCodePlacementOpt = false;
518 UseUnderscoreSetJmp = false;
519 UseUnderscoreLongJmp = false;
520 SelectIsExpensive = false;
521 IntDivIsCheap = false;
522 Pow2DivIsCheap = false;
523 StackPointerRegisterToSaveRestore = 0;
524 ExceptionPointerRegister = 0;
525 ExceptionSelectorRegister = 0;
526 BooleanContents = UndefinedBooleanContent;
527 SchedPreferenceInfo = SchedulingForLatency;
529 JumpBufAlignment = 0;
530 IfCvtBlockSizeLimit = 2;
531 IfCvtDupBlockSizeLimit = 0;
532 PrefLoopAlignment = 0;
534 InitLibcallNames(LibcallRoutineNames);
535 InitCmpLibcallCCs(CmpLibcallCCs);
536 InitLibcallCallingConvs(LibcallCallingConvs);
539 TargetLowering::~TargetLowering() {
543 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
544 unsigned &NumIntermediates,
546 TargetLowering* TLI) {
547 // Figure out the right, legal destination reg to copy into.
548 unsigned NumElts = VT.getVectorNumElements();
549 MVT EltTy = VT.getVectorElementType();
551 unsigned NumVectorRegs = 1;
553 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
554 // could break down into LHS/RHS like LegalizeDAG does.
555 if (!isPowerOf2_32(NumElts)) {
556 NumVectorRegs = NumElts;
560 // Divide the input until we get to a supported size. This will always
561 // end with a scalar if the target doesn't support vectors.
562 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
567 NumIntermediates = NumVectorRegs;
569 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
570 if (!TLI->isTypeLegal(NewVT))
572 IntermediateVT = NewVT;
574 EVT DestVT = TLI->getRegisterType(NewVT);
576 if (EVT(DestVT).bitsLT(NewVT)) {
577 // Value is expanded, e.g. i64 -> i16.
578 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
580 // Otherwise, promotion or legal types use the same number of registers as
581 // the vector decimated to the appropriate level.
582 return NumVectorRegs;
588 /// computeRegisterProperties - Once all of the register classes are added,
589 /// this allows us to compute derived properties we expose.
590 void TargetLowering::computeRegisterProperties() {
591 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
592 "Too many value types for ValueTypeActions to hold!");
594 // Everything defaults to needing one register.
595 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
596 NumRegistersForVT[i] = 1;
597 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
599 // ...except isVoid, which doesn't need any registers.
600 NumRegistersForVT[MVT::isVoid] = 0;
602 // Find the largest integer register class.
603 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
604 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
605 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
607 // Every integer value type larger than this largest register takes twice as
608 // many registers to represent as the previous ValueType.
609 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
610 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
611 if (!ExpandedVT.isInteger())
613 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
614 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
615 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
616 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
619 // Inspect all of the ValueType's smaller than the largest integer
620 // register to see which ones need promotion.
621 unsigned LegalIntReg = LargestIntReg;
622 for (unsigned IntReg = LargestIntReg - 1;
623 IntReg >= (unsigned)MVT::i1; --IntReg) {
624 EVT IVT = (MVT::SimpleValueType)IntReg;
625 if (isTypeLegal(IVT)) {
626 LegalIntReg = IntReg;
628 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
629 (MVT::SimpleValueType)LegalIntReg;
630 ValueTypeActions.setTypeAction(IVT, Promote);
634 // ppcf128 type is really two f64's.
635 if (!isTypeLegal(MVT::ppcf128)) {
636 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
637 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
638 TransformToType[MVT::ppcf128] = MVT::f64;
639 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
642 // Decide how to handle f64. If the target does not have native f64 support,
643 // expand it to i64 and we will be generating soft float library calls.
644 if (!isTypeLegal(MVT::f64)) {
645 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
646 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
647 TransformToType[MVT::f64] = MVT::i64;
648 ValueTypeActions.setTypeAction(MVT::f64, Expand);
651 // Decide how to handle f32. If the target does not have native support for
652 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
653 if (!isTypeLegal(MVT::f32)) {
654 if (isTypeLegal(MVT::f64)) {
655 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
656 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
657 TransformToType[MVT::f32] = MVT::f64;
658 ValueTypeActions.setTypeAction(MVT::f32, Promote);
660 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
661 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
662 TransformToType[MVT::f32] = MVT::i32;
663 ValueTypeActions.setTypeAction(MVT::f32, Expand);
667 // Loop over all of the vector value types to see which need transformations.
668 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
669 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
670 MVT VT = (MVT::SimpleValueType)i;
671 if (!isTypeLegal(VT)) {
674 unsigned NumIntermediates;
675 NumRegistersForVT[i] =
676 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
678 RegisterTypeForVT[i] = RegisterVT;
680 // Determine if there is a legal wider type.
681 bool IsLegalWiderType = false;
682 EVT EltVT = VT.getVectorElementType();
683 unsigned NElts = VT.getVectorNumElements();
684 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
685 EVT SVT = (MVT::SimpleValueType)nVT;
686 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
687 SVT.getVectorNumElements() > NElts && NElts != 1) {
688 TransformToType[i] = SVT;
689 ValueTypeActions.setTypeAction(VT, Promote);
690 IsLegalWiderType = true;
694 if (!IsLegalWiderType) {
695 EVT NVT = VT.getPow2VectorType();
697 // Type is already a power of 2. The default action is to split.
698 TransformToType[i] = MVT::Other;
699 ValueTypeActions.setTypeAction(VT, Expand);
701 TransformToType[i] = NVT;
702 ValueTypeActions.setTypeAction(VT, Promote);
709 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
714 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
715 return PointerTy.SimpleTy;
718 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
719 return MVT::i32; // return the default value
722 /// getVectorTypeBreakdown - Vector types are broken down into some number of
723 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
724 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
725 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
727 /// This method returns the number of registers needed, and the VT for each
728 /// register. It also returns the VT and quantity of the intermediate values
729 /// before they are promoted/expanded.
731 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
733 unsigned &NumIntermediates,
734 EVT &RegisterVT) const {
735 // Figure out the right, legal destination reg to copy into.
736 unsigned NumElts = VT.getVectorNumElements();
737 EVT EltTy = VT.getVectorElementType();
739 unsigned NumVectorRegs = 1;
741 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
742 // could break down into LHS/RHS like LegalizeDAG does.
743 if (!isPowerOf2_32(NumElts)) {
744 NumVectorRegs = NumElts;
748 // Divide the input until we get to a supported size. This will always
749 // end with a scalar if the target doesn't support vectors.
750 while (NumElts > 1 && !isTypeLegal(
751 EVT::getVectorVT(Context, EltTy, NumElts))) {
756 NumIntermediates = NumVectorRegs;
758 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
759 if (!isTypeLegal(NewVT))
761 IntermediateVT = NewVT;
763 EVT DestVT = getRegisterType(Context, NewVT);
765 if (DestVT.bitsLT(NewVT)) {
766 // Value is expanded, e.g. i64 -> i16.
767 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
769 // Otherwise, promotion or legal types use the same number of registers as
770 // the vector decimated to the appropriate level.
771 return NumVectorRegs;
777 /// getWidenVectorType: given a vector type, returns the type to widen to
778 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
779 /// If there is no vector type that we want to widen to, returns MVT::Other
780 /// When and where to widen is target dependent based on the cost of
781 /// scalarizing vs using the wider vector type.
782 EVT TargetLowering::getWidenVectorType(EVT VT) const {
783 assert(VT.isVector());
787 // Default is not to widen until moved to LegalizeTypes
791 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
792 /// function arguments in the caller parameter area. This is the actual
793 /// alignment, not its logarithm.
794 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
795 return TD->getCallFrameTypeAlignment(Ty);
798 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
799 /// current function. The returned value is a member of the
800 /// MachineJumpTableInfo::JTEntryKind enum.
801 unsigned TargetLowering::getJumpTableEncoding() const {
802 // In non-pic modes, just use the address of a block.
803 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
804 return MachineJumpTableInfo::EK_BlockAddress;
806 // In PIC mode, if the target supports a GPRel32 directive, use it.
807 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
808 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
810 // Otherwise, use a label difference.
811 return MachineJumpTableInfo::EK_LabelDifference32;
814 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
815 SelectionDAG &DAG) const {
816 // If our PIC model is GP relative, use the global offset table as the base.
817 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
818 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
822 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
823 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
826 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
827 unsigned JTI,MCContext &Ctx) const{
828 // The normal PIC reloc base is the label at the start of the jump table.
829 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
833 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
834 // Assume that everything is safe in static mode.
835 if (getTargetMachine().getRelocationModel() == Reloc::Static)
838 // In dynamic-no-pic mode, assume that known defined values are safe.
839 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
841 !GA->getGlobal()->isDeclaration() &&
842 !GA->getGlobal()->isWeakForLinker())
845 // Otherwise assume nothing is safe.
849 //===----------------------------------------------------------------------===//
850 // Optimization Methods
851 //===----------------------------------------------------------------------===//
853 /// ShrinkDemandedConstant - Check to see if the specified operand of the
854 /// specified instruction is a constant integer. If so, check to see if there
855 /// are any bits set in the constant that are not demanded. If so, shrink the
856 /// constant and return true.
857 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
858 const APInt &Demanded) {
859 DebugLoc dl = Op.getDebugLoc();
861 // FIXME: ISD::SELECT, ISD::SELECT_CC
862 switch (Op.getOpcode()) {
867 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
868 if (!C) return false;
870 if (Op.getOpcode() == ISD::XOR &&
871 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
874 // if we can expand it to have all bits set, do it
875 if (C->getAPIntValue().intersects(~Demanded)) {
876 EVT VT = Op.getValueType();
877 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
878 DAG.getConstant(Demanded &
881 return CombineTo(Op, New);
891 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
892 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
893 /// cast, but it could be generalized for targets with other types of
894 /// implicit widening casts.
896 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
898 const APInt &Demanded,
900 assert(Op.getNumOperands() == 2 &&
901 "ShrinkDemandedOp only supports binary operators!");
902 assert(Op.getNode()->getNumValues() == 1 &&
903 "ShrinkDemandedOp only supports nodes with one result!");
905 // Don't do this if the node has another user, which may require the
907 if (!Op.getNode()->hasOneUse())
910 // Search for the smallest integer type with free casts to and from
911 // Op's type. For expedience, just check power-of-2 integer types.
912 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
913 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
914 if (!isPowerOf2_32(SmallVTBits))
915 SmallVTBits = NextPowerOf2(SmallVTBits);
916 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
917 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
918 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
919 TLI.isZExtFree(SmallVT, Op.getValueType())) {
920 // We found a type with free casts.
921 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
922 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
923 Op.getNode()->getOperand(0)),
924 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
925 Op.getNode()->getOperand(1)));
926 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
927 return CombineTo(Op, Z);
933 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
934 /// DemandedMask bits of the result of Op are ever used downstream. If we can
935 /// use this information to simplify Op, create a new simplified DAG node and
936 /// return true, returning the original and new nodes in Old and New. Otherwise,
937 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
938 /// the expression (used to simplify the caller). The KnownZero/One bits may
939 /// only be accurate for those bits in the DemandedMask.
940 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
941 const APInt &DemandedMask,
944 TargetLoweringOpt &TLO,
945 unsigned Depth) const {
946 unsigned BitWidth = DemandedMask.getBitWidth();
947 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
948 "Mask size mismatches value type size!");
949 APInt NewMask = DemandedMask;
950 DebugLoc dl = Op.getDebugLoc();
952 // Don't know anything.
953 KnownZero = KnownOne = APInt(BitWidth, 0);
955 // Other users may use these bits.
956 if (!Op.getNode()->hasOneUse()) {
958 // If not at the root, Just compute the KnownZero/KnownOne bits to
959 // simplify things downstream.
960 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
963 // If this is the root being simplified, allow it to have multiple uses,
964 // just set the NewMask to all bits.
965 NewMask = APInt::getAllOnesValue(BitWidth);
966 } else if (DemandedMask == 0) {
967 // Not demanding any bits from Op.
968 if (Op.getOpcode() != ISD::UNDEF)
969 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
971 } else if (Depth == 6) { // Limit search depth.
975 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
976 switch (Op.getOpcode()) {
978 // We know all of the bits for a constant!
979 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
980 KnownZero = ~KnownOne & NewMask;
981 return false; // Don't fall through, will infinitely loop.
983 // If the RHS is a constant, check to see if the LHS would be zero without
984 // using the bits from the RHS. Below, we use knowledge about the RHS to
985 // simplify the LHS, here we're using information from the LHS to simplify
987 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
988 APInt LHSZero, LHSOne;
989 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
990 LHSZero, LHSOne, Depth+1);
991 // If the LHS already has zeros where RHSC does, this and is dead.
992 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
993 return TLO.CombineTo(Op, Op.getOperand(0));
994 // If any of the set bits in the RHS are known zero on the LHS, shrink
996 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1000 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1001 KnownOne, TLO, Depth+1))
1003 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1004 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1005 KnownZero2, KnownOne2, TLO, Depth+1))
1007 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1009 // If all of the demanded bits are known one on one side, return the other.
1010 // These bits cannot contribute to the result of the 'and'.
1011 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1012 return TLO.CombineTo(Op, Op.getOperand(0));
1013 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1014 return TLO.CombineTo(Op, Op.getOperand(1));
1015 // If all of the demanded bits in the inputs are known zeros, return zero.
1016 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1017 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1018 // If the RHS is a constant, see if we can simplify it.
1019 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1021 // If the operation can be done in a smaller type, do so.
1022 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1025 // Output known-1 bits are only known if set in both the LHS & RHS.
1026 KnownOne &= KnownOne2;
1027 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1028 KnownZero |= KnownZero2;
1031 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1032 KnownOne, TLO, Depth+1))
1034 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1035 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1036 KnownZero2, KnownOne2, TLO, Depth+1))
1038 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1040 // If all of the demanded bits are known zero on one side, return the other.
1041 // These bits cannot contribute to the result of the 'or'.
1042 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1043 return TLO.CombineTo(Op, Op.getOperand(0));
1044 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1045 return TLO.CombineTo(Op, Op.getOperand(1));
1046 // If all of the potentially set bits on one side are known to be set on
1047 // the other side, just use the 'other' side.
1048 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1049 return TLO.CombineTo(Op, Op.getOperand(0));
1050 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1051 return TLO.CombineTo(Op, Op.getOperand(1));
1052 // If the RHS is a constant, see if we can simplify it.
1053 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1055 // If the operation can be done in a smaller type, do so.
1056 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1059 // Output known-0 bits are only known if clear in both the LHS & RHS.
1060 KnownZero &= KnownZero2;
1061 // Output known-1 are known to be set if set in either the LHS | RHS.
1062 KnownOne |= KnownOne2;
1065 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1066 KnownOne, TLO, Depth+1))
1068 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1069 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1070 KnownOne2, TLO, Depth+1))
1072 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1074 // If all of the demanded bits are known zero on one side, return the other.
1075 // These bits cannot contribute to the result of the 'xor'.
1076 if ((KnownZero & NewMask) == NewMask)
1077 return TLO.CombineTo(Op, Op.getOperand(0));
1078 if ((KnownZero2 & NewMask) == NewMask)
1079 return TLO.CombineTo(Op, Op.getOperand(1));
1080 // If the operation can be done in a smaller type, do so.
1081 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1084 // If all of the unknown bits are known to be zero on one side or the other
1085 // (but not both) turn this into an *inclusive* or.
1086 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1087 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1088 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1092 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1093 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1094 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1095 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1097 // If all of the demanded bits on one side are known, and all of the set
1098 // bits on that side are also known to be set on the other side, turn this
1099 // into an AND, as we know the bits will be cleared.
1100 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1101 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1102 if ((KnownOne & KnownOne2) == KnownOne) {
1103 EVT VT = Op.getValueType();
1104 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1105 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1106 Op.getOperand(0), ANDC));
1110 // If the RHS is a constant, see if we can simplify it.
1111 // for XOR, we prefer to force bits to 1 if they will make a -1.
1112 // if we can't force bits, try to shrink constant
1113 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1114 APInt Expanded = C->getAPIntValue() | (~NewMask);
1115 // if we can expand it to have all bits set, do it
1116 if (Expanded.isAllOnesValue()) {
1117 if (Expanded != C->getAPIntValue()) {
1118 EVT VT = Op.getValueType();
1119 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1120 TLO.DAG.getConstant(Expanded, VT));
1121 return TLO.CombineTo(Op, New);
1123 // if it already has all the bits set, nothing to change
1124 // but don't shrink either!
1125 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1130 KnownZero = KnownZeroOut;
1131 KnownOne = KnownOneOut;
1134 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1135 KnownOne, TLO, Depth+1))
1137 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1138 KnownOne2, TLO, Depth+1))
1140 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1141 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1143 // If the operands are constants, see if we can simplify them.
1144 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1147 // Only known if known in both the LHS and RHS.
1148 KnownOne &= KnownOne2;
1149 KnownZero &= KnownZero2;
1151 case ISD::SELECT_CC:
1152 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1153 KnownOne, TLO, Depth+1))
1155 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1156 KnownOne2, TLO, Depth+1))
1158 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1159 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1161 // If the operands are constants, see if we can simplify them.
1162 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1165 // Only known if known in both the LHS and RHS.
1166 KnownOne &= KnownOne2;
1167 KnownZero &= KnownZero2;
1170 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1171 unsigned ShAmt = SA->getZExtValue();
1172 SDValue InOp = Op.getOperand(0);
1174 // If the shift count is an invalid immediate, don't do anything.
1175 if (ShAmt >= BitWidth)
1178 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1179 // single shift. We can do this if the bottom bits (which are shifted
1180 // out) are never demanded.
1181 if (InOp.getOpcode() == ISD::SRL &&
1182 isa<ConstantSDNode>(InOp.getOperand(1))) {
1183 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1184 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1185 unsigned Opc = ISD::SHL;
1186 int Diff = ShAmt-C1;
1193 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1194 EVT VT = Op.getValueType();
1195 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1196 InOp.getOperand(0), NewSA));
1200 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1201 KnownZero, KnownOne, TLO, Depth+1))
1203 KnownZero <<= SA->getZExtValue();
1204 KnownOne <<= SA->getZExtValue();
1205 // low bits known zero.
1206 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1210 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1211 EVT VT = Op.getValueType();
1212 unsigned ShAmt = SA->getZExtValue();
1213 unsigned VTSize = VT.getSizeInBits();
1214 SDValue InOp = Op.getOperand(0);
1216 // If the shift count is an invalid immediate, don't do anything.
1217 if (ShAmt >= BitWidth)
1220 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1221 // single shift. We can do this if the top bits (which are shifted out)
1222 // are never demanded.
1223 if (InOp.getOpcode() == ISD::SHL &&
1224 isa<ConstantSDNode>(InOp.getOperand(1))) {
1225 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1226 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1227 unsigned Opc = ISD::SRL;
1228 int Diff = ShAmt-C1;
1235 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1236 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1237 InOp.getOperand(0), NewSA));
1241 // Compute the new bits that are at the top now.
1242 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1243 KnownZero, KnownOne, TLO, Depth+1))
1245 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1246 KnownZero = KnownZero.lshr(ShAmt);
1247 KnownOne = KnownOne.lshr(ShAmt);
1249 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1250 KnownZero |= HighBits; // High bits known zero.
1254 // If this is an arithmetic shift right and only the low-bit is set, we can
1255 // always convert this into a logical shr, even if the shift amount is
1256 // variable. The low bit of the shift cannot be an input sign bit unless
1257 // the shift amount is >= the size of the datatype, which is undefined.
1258 if (DemandedMask == 1)
1259 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1260 Op.getOperand(0), Op.getOperand(1)));
1262 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1263 EVT VT = Op.getValueType();
1264 unsigned ShAmt = SA->getZExtValue();
1266 // If the shift count is an invalid immediate, don't do anything.
1267 if (ShAmt >= BitWidth)
1270 APInt InDemandedMask = (NewMask << ShAmt);
1272 // If any of the demanded bits are produced by the sign extension, we also
1273 // demand the input sign bit.
1274 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1275 if (HighBits.intersects(NewMask))
1276 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1278 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1279 KnownZero, KnownOne, TLO, Depth+1))
1281 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1282 KnownZero = KnownZero.lshr(ShAmt);
1283 KnownOne = KnownOne.lshr(ShAmt);
1285 // Handle the sign bit, adjusted to where it is now in the mask.
1286 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1288 // If the input sign bit is known to be zero, or if none of the top bits
1289 // are demanded, turn this into an unsigned shift right.
1290 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1291 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1294 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1295 KnownOne |= HighBits;
1299 case ISD::SIGN_EXTEND_INREG: {
1300 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1302 // Sign extension. Compute the demanded bits in the result that are not
1303 // present in the input.
1305 APInt::getHighBitsSet(BitWidth,
1306 BitWidth - EVT.getScalarType().getSizeInBits()) &
1309 // If none of the extended bits are demanded, eliminate the sextinreg.
1311 return TLO.CombineTo(Op, Op.getOperand(0));
1313 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1314 InSignBit.zext(BitWidth);
1315 APInt InputDemandedBits =
1316 APInt::getLowBitsSet(BitWidth,
1317 EVT.getScalarType().getSizeInBits()) &
1320 // Since the sign extended bits are demanded, we know that the sign
1322 InputDemandedBits |= InSignBit;
1324 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1325 KnownZero, KnownOne, TLO, Depth+1))
1327 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1329 // If the sign bit of the input is known set or clear, then we know the
1330 // top bits of the result.
1332 // If the input sign bit is known zero, convert this into a zero extension.
1333 if (KnownZero.intersects(InSignBit))
1334 return TLO.CombineTo(Op,
1335 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1337 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1338 KnownOne |= NewBits;
1339 KnownZero &= ~NewBits;
1340 } else { // Input sign bit unknown
1341 KnownZero &= ~NewBits;
1342 KnownOne &= ~NewBits;
1346 case ISD::ZERO_EXTEND: {
1347 unsigned OperandBitWidth =
1348 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1349 APInt InMask = NewMask;
1350 InMask.trunc(OperandBitWidth);
1352 // If none of the top bits are demanded, convert this into an any_extend.
1354 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1355 if (!NewBits.intersects(NewMask))
1356 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1360 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1361 KnownZero, KnownOne, TLO, Depth+1))
1363 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1364 KnownZero.zext(BitWidth);
1365 KnownOne.zext(BitWidth);
1366 KnownZero |= NewBits;
1369 case ISD::SIGN_EXTEND: {
1370 EVT InVT = Op.getOperand(0).getValueType();
1371 unsigned InBits = InVT.getScalarType().getSizeInBits();
1372 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1373 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1374 APInt NewBits = ~InMask & NewMask;
1376 // If none of the top bits are demanded, convert this into an any_extend.
1378 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1382 // Since some of the sign extended bits are demanded, we know that the sign
1384 APInt InDemandedBits = InMask & NewMask;
1385 InDemandedBits |= InSignBit;
1386 InDemandedBits.trunc(InBits);
1388 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1389 KnownOne, TLO, Depth+1))
1391 KnownZero.zext(BitWidth);
1392 KnownOne.zext(BitWidth);
1394 // If the sign bit is known zero, convert this to a zero extend.
1395 if (KnownZero.intersects(InSignBit))
1396 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1400 // If the sign bit is known one, the top bits match.
1401 if (KnownOne.intersects(InSignBit)) {
1402 KnownOne |= NewBits;
1403 KnownZero &= ~NewBits;
1404 } else { // Otherwise, top bits aren't known.
1405 KnownOne &= ~NewBits;
1406 KnownZero &= ~NewBits;
1410 case ISD::ANY_EXTEND: {
1411 unsigned OperandBitWidth =
1412 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1413 APInt InMask = NewMask;
1414 InMask.trunc(OperandBitWidth);
1415 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1416 KnownZero, KnownOne, TLO, Depth+1))
1418 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1419 KnownZero.zext(BitWidth);
1420 KnownOne.zext(BitWidth);
1423 case ISD::TRUNCATE: {
1424 // Simplify the input, using demanded bit information, and compute the known
1425 // zero/one bits live out.
1426 APInt TruncMask = NewMask;
1427 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1428 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1429 KnownZero, KnownOne, TLO, Depth+1))
1431 KnownZero.trunc(BitWidth);
1432 KnownOne.trunc(BitWidth);
1434 // If the input is only used by this truncate, see if we can shrink it based
1435 // on the known demanded bits.
1436 if (Op.getOperand(0).getNode()->hasOneUse()) {
1437 SDValue In = Op.getOperand(0);
1438 unsigned InBitWidth = In.getValueSizeInBits();
1439 switch (In.getOpcode()) {
1442 // Shrink SRL by a constant if none of the high bits shifted in are
1444 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1445 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1446 InBitWidth - BitWidth);
1447 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1448 HighBits.trunc(BitWidth);
1450 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1451 // None of the shifted in bits are needed. Add a truncate of the
1452 // shift input, then shift it.
1453 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1456 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1466 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1469 case ISD::AssertZext: {
1470 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1471 APInt InMask = APInt::getLowBitsSet(BitWidth,
1472 VT.getSizeInBits());
1473 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1474 KnownZero, KnownOne, TLO, Depth+1))
1476 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1477 KnownZero |= ~InMask & NewMask;
1480 case ISD::BIT_CONVERT:
1482 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1483 // is demanded, turn this into a FGETSIGN.
1484 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1485 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1486 !MVT::isVector(Op.getOperand(0).getValueType())) {
1487 // Only do this xform if FGETSIGN is valid or if before legalize.
1488 if (!TLO.AfterLegalize ||
1489 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1490 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1491 // place. We expect the SHL to be eliminated by other optimizations.
1492 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1494 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1495 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1496 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1505 // Add, Sub, and Mul don't demand any bits in positions beyond that
1506 // of the highest bit demanded of them.
1507 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1508 BitWidth - NewMask.countLeadingZeros());
1509 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1510 KnownOne2, TLO, Depth+1))
1512 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1513 KnownOne2, TLO, Depth+1))
1515 // See if the operation should be performed at a smaller bit width.
1516 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1521 // Just use ComputeMaskedBits to compute output bits.
1522 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1526 // If we know the value of all of the demanded bits, return this as a
1528 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1529 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1534 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1535 /// in Mask are known to be either zero or one and return them in the
1536 /// KnownZero/KnownOne bitsets.
1537 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1541 const SelectionDAG &DAG,
1542 unsigned Depth) const {
1543 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1544 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1545 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1546 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1547 "Should use MaskedValueIsZero if you don't know whether Op"
1548 " is a target node!");
1549 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1552 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1553 /// targets that want to expose additional information about sign bits to the
1555 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1556 unsigned Depth) const {
1557 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1558 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1559 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1560 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1561 "Should use ComputeNumSignBits if you don't know whether Op"
1562 " is a target node!");
1566 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1567 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1568 /// determine which bit is set.
1570 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1571 // A left-shift of a constant one will have exactly one bit set, because
1572 // shifting the bit off the end is undefined.
1573 if (Val.getOpcode() == ISD::SHL)
1574 if (ConstantSDNode *C =
1575 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1576 if (C->getAPIntValue() == 1)
1579 // Similarly, a right-shift of a constant sign-bit will have exactly
1581 if (Val.getOpcode() == ISD::SRL)
1582 if (ConstantSDNode *C =
1583 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1584 if (C->getAPIntValue().isSignBit())
1587 // More could be done here, though the above checks are enough
1588 // to handle some common cases.
1590 // Fall back to ComputeMaskedBits to catch other known cases.
1591 EVT OpVT = Val.getValueType();
1592 unsigned BitWidth = OpVT.getSizeInBits();
1593 APInt Mask = APInt::getAllOnesValue(BitWidth);
1594 APInt KnownZero, KnownOne;
1595 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1596 return (KnownZero.countPopulation() == BitWidth - 1) &&
1597 (KnownOne.countPopulation() == 1);
1600 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1601 /// and cc. If it is unable to simplify it, return a null SDValue.
1603 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1604 ISD::CondCode Cond, bool foldBooleans,
1605 DAGCombinerInfo &DCI, DebugLoc dl) const {
1606 SelectionDAG &DAG = DCI.DAG;
1607 LLVMContext &Context = *DAG.getContext();
1609 // These setcc operations always fold.
1613 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1615 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1618 if (isa<ConstantSDNode>(N0.getNode())) {
1619 // Ensure that the constant occurs on the RHS, and fold constant
1621 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1624 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1625 const APInt &C1 = N1C->getAPIntValue();
1627 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1628 // equality comparison, then we're just comparing whether X itself is
1630 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1631 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1632 N0.getOperand(1).getOpcode() == ISD::Constant) {
1634 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1635 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1636 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1637 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1638 // (srl (ctlz x), 5) == 0 -> X != 0
1639 // (srl (ctlz x), 5) != 1 -> X != 0
1642 // (srl (ctlz x), 5) != 0 -> X == 0
1643 // (srl (ctlz x), 5) == 1 -> X == 0
1646 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1647 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1652 // If the LHS is '(and load, const)', the RHS is 0,
1653 // the test is for equality or unsigned, and all 1 bits of the const are
1654 // in the same partial word, see if we can shorten the load.
1655 if (DCI.isBeforeLegalize() &&
1656 N0.getOpcode() == ISD::AND && C1 == 0 &&
1657 N0.getNode()->hasOneUse() &&
1658 isa<LoadSDNode>(N0.getOperand(0)) &&
1659 N0.getOperand(0).getNode()->hasOneUse() &&
1660 isa<ConstantSDNode>(N0.getOperand(1))) {
1661 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1663 unsigned bestWidth = 0, bestOffset = 0;
1664 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1665 unsigned origWidth = N0.getValueType().getSizeInBits();
1666 unsigned maskWidth = origWidth;
1667 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1668 // 8 bits, but have to be careful...
1669 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1670 origWidth = Lod->getMemoryVT().getSizeInBits();
1672 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1673 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1674 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1675 for (unsigned offset=0; offset<origWidth/width; offset++) {
1676 if ((newMask & Mask) == Mask) {
1677 if (!TD->isLittleEndian())
1678 bestOffset = (origWidth/width - offset - 1) * (width/8);
1680 bestOffset = (uint64_t)offset * (width/8);
1681 bestMask = Mask.lshr(offset * (width/8) * 8);
1685 newMask = newMask << width;
1690 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1691 if (newVT.isRound()) {
1692 EVT PtrType = Lod->getOperand(1).getValueType();
1693 SDValue Ptr = Lod->getBasePtr();
1694 if (bestOffset != 0)
1695 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1696 DAG.getConstant(bestOffset, PtrType));
1697 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1698 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1700 Lod->getSrcValueOffset() + bestOffset,
1702 return DAG.getSetCC(dl, VT,
1703 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1704 DAG.getConstant(bestMask.trunc(bestWidth),
1706 DAG.getConstant(0LL, newVT), Cond);
1711 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1712 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1713 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1715 // If the comparison constant has bits in the upper part, the
1716 // zero-extended value could never match.
1717 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1718 C1.getBitWidth() - InSize))) {
1722 case ISD::SETEQ: return DAG.getConstant(0, VT);
1725 case ISD::SETNE: return DAG.getConstant(1, VT);
1728 // True if the sign bit of C1 is set.
1729 return DAG.getConstant(C1.isNegative(), VT);
1732 // True if the sign bit of C1 isn't set.
1733 return DAG.getConstant(C1.isNonNegative(), VT);
1739 // Otherwise, we can perform the comparison with the low bits.
1747 EVT newVT = N0.getOperand(0).getValueType();
1748 if (DCI.isBeforeLegalizeOps() ||
1749 (isOperationLegal(ISD::SETCC, newVT) &&
1750 getCondCodeAction(Cond, newVT)==Legal))
1751 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1752 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1757 break; // todo, be more careful with signed comparisons
1759 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1760 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1761 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1762 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1763 EVT ExtDstTy = N0.getValueType();
1764 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1766 // If the extended part has any inconsistent bits, it cannot ever
1767 // compare equal. In other words, they have to be all ones or all
1770 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1771 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1772 return DAG.getConstant(Cond == ISD::SETNE, VT);
1775 EVT Op0Ty = N0.getOperand(0).getValueType();
1776 if (Op0Ty == ExtSrcTy) {
1777 ZextOp = N0.getOperand(0);
1779 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1780 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1781 DAG.getConstant(Imm, Op0Ty));
1783 if (!DCI.isCalledByLegalizer())
1784 DCI.AddToWorklist(ZextOp.getNode());
1785 // Otherwise, make this a use of a zext.
1786 return DAG.getSetCC(dl, VT, ZextOp,
1787 DAG.getConstant(C1 & APInt::getLowBitsSet(
1792 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1793 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1795 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1796 if (N0.getOpcode() == ISD::SETCC) {
1797 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1801 // Invert the condition.
1802 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1803 CC = ISD::getSetCCInverse(CC,
1804 N0.getOperand(0).getValueType().isInteger());
1805 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1808 if ((N0.getOpcode() == ISD::XOR ||
1809 (N0.getOpcode() == ISD::AND &&
1810 N0.getOperand(0).getOpcode() == ISD::XOR &&
1811 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1812 isa<ConstantSDNode>(N0.getOperand(1)) &&
1813 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1814 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1815 // can only do this if the top bits are known zero.
1816 unsigned BitWidth = N0.getValueSizeInBits();
1817 if (DAG.MaskedValueIsZero(N0,
1818 APInt::getHighBitsSet(BitWidth,
1820 // Okay, get the un-inverted input value.
1822 if (N0.getOpcode() == ISD::XOR)
1823 Val = N0.getOperand(0);
1825 assert(N0.getOpcode() == ISD::AND &&
1826 N0.getOperand(0).getOpcode() == ISD::XOR);
1827 // ((X^1)&1)^1 -> X & 1
1828 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1829 N0.getOperand(0).getOperand(0),
1832 return DAG.getSetCC(dl, VT, Val, N1,
1833 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1838 APInt MinVal, MaxVal;
1839 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1840 if (ISD::isSignedIntSetCC(Cond)) {
1841 MinVal = APInt::getSignedMinValue(OperandBitSize);
1842 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1844 MinVal = APInt::getMinValue(OperandBitSize);
1845 MaxVal = APInt::getMaxValue(OperandBitSize);
1848 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1849 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1850 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1851 // X >= C0 --> X > (C0-1)
1852 return DAG.getSetCC(dl, VT, N0,
1853 DAG.getConstant(C1-1, N1.getValueType()),
1854 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1857 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1858 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1859 // X <= C0 --> X < (C0+1)
1860 return DAG.getSetCC(dl, VT, N0,
1861 DAG.getConstant(C1+1, N1.getValueType()),
1862 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1865 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1866 return DAG.getConstant(0, VT); // X < MIN --> false
1867 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1868 return DAG.getConstant(1, VT); // X >= MIN --> true
1869 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1870 return DAG.getConstant(0, VT); // X > MAX --> false
1871 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1872 return DAG.getConstant(1, VT); // X <= MAX --> true
1874 // Canonicalize setgt X, Min --> setne X, Min
1875 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1876 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1877 // Canonicalize setlt X, Max --> setne X, Max
1878 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1879 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1881 // If we have setult X, 1, turn it into seteq X, 0
1882 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1883 return DAG.getSetCC(dl, VT, N0,
1884 DAG.getConstant(MinVal, N0.getValueType()),
1886 // If we have setugt X, Max-1, turn it into seteq X, Max
1887 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1888 return DAG.getSetCC(dl, VT, N0,
1889 DAG.getConstant(MaxVal, N0.getValueType()),
1892 // If we have "setcc X, C0", check to see if we can shrink the immediate
1895 // SETUGT X, SINTMAX -> SETLT X, 0
1896 if (Cond == ISD::SETUGT &&
1897 C1 == APInt::getSignedMaxValue(OperandBitSize))
1898 return DAG.getSetCC(dl, VT, N0,
1899 DAG.getConstant(0, N1.getValueType()),
1902 // SETULT X, SINTMIN -> SETGT X, -1
1903 if (Cond == ISD::SETULT &&
1904 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1905 SDValue ConstMinusOne =
1906 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1908 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1911 // Fold bit comparisons when we can.
1912 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1913 (VT == N0.getValueType() ||
1914 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1915 N0.getOpcode() == ISD::AND)
1916 if (ConstantSDNode *AndRHS =
1917 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1918 EVT ShiftTy = DCI.isBeforeLegalize() ?
1919 getPointerTy() : getShiftAmountTy();
1920 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1921 // Perform the xform if the AND RHS is a single bit.
1922 if (AndRHS->getAPIntValue().isPowerOf2()) {
1923 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1924 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1925 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1927 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1928 // (X & 8) == 8 --> (X & 8) >> 3
1929 // Perform the xform if C1 is a single bit.
1930 if (C1.isPowerOf2()) {
1931 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1932 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1933 DAG.getConstant(C1.logBase2(), ShiftTy)));
1939 if (isa<ConstantFPSDNode>(N0.getNode())) {
1940 // Constant fold or commute setcc.
1941 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1942 if (O.getNode()) return O;
1943 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1944 // If the RHS of an FP comparison is a constant, simplify it away in
1946 if (CFP->getValueAPF().isNaN()) {
1947 // If an operand is known to be a nan, we can fold it.
1948 switch (ISD::getUnorderedFlavor(Cond)) {
1949 default: llvm_unreachable("Unknown flavor!");
1950 case 0: // Known false.
1951 return DAG.getConstant(0, VT);
1952 case 1: // Known true.
1953 return DAG.getConstant(1, VT);
1954 case 2: // Undefined.
1955 return DAG.getUNDEF(VT);
1959 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1960 // constant if knowing that the operand is non-nan is enough. We prefer to
1961 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1963 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1964 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1966 // If the condition is not legal, see if we can find an equivalent one
1968 if (!isCondCodeLegal(Cond, N0.getValueType())) {
1969 // If the comparison was an awkward floating-point == or != and one of
1970 // the comparison operands is infinity or negative infinity, convert the
1971 // condition to a less-awkward <= or >=.
1972 if (CFP->getValueAPF().isInfinity()) {
1973 if (CFP->getValueAPF().isNegative()) {
1974 if (Cond == ISD::SETOEQ &&
1975 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1976 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1977 if (Cond == ISD::SETUEQ &&
1978 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1979 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1980 if (Cond == ISD::SETUNE &&
1981 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1982 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1983 if (Cond == ISD::SETONE &&
1984 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1985 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1987 if (Cond == ISD::SETOEQ &&
1988 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1989 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1990 if (Cond == ISD::SETUEQ &&
1991 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1992 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1993 if (Cond == ISD::SETUNE &&
1994 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1995 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1996 if (Cond == ISD::SETONE &&
1997 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1998 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2005 // We can always fold X == X for integer setcc's.
2006 if (N0.getValueType().isInteger())
2007 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2008 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2009 if (UOF == 2) // FP operators that are undefined on NaNs.
2010 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2011 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2012 return DAG.getConstant(UOF, VT);
2013 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2014 // if it is not already.
2015 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2016 if (NewCond != Cond)
2017 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2020 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2021 N0.getValueType().isInteger()) {
2022 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2023 N0.getOpcode() == ISD::XOR) {
2024 // Simplify (X+Y) == (X+Z) --> Y == Z
2025 if (N0.getOpcode() == N1.getOpcode()) {
2026 if (N0.getOperand(0) == N1.getOperand(0))
2027 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2028 if (N0.getOperand(1) == N1.getOperand(1))
2029 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2030 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2031 // If X op Y == Y op X, try other combinations.
2032 if (N0.getOperand(0) == N1.getOperand(1))
2033 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2035 if (N0.getOperand(1) == N1.getOperand(0))
2036 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2041 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2042 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2043 // Turn (X+C1) == C2 --> X == C2-C1
2044 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2045 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2046 DAG.getConstant(RHSC->getAPIntValue()-
2047 LHSR->getAPIntValue(),
2048 N0.getValueType()), Cond);
2051 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2052 if (N0.getOpcode() == ISD::XOR)
2053 // If we know that all of the inverted bits are zero, don't bother
2054 // performing the inversion.
2055 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2057 DAG.getSetCC(dl, VT, N0.getOperand(0),
2058 DAG.getConstant(LHSR->getAPIntValue() ^
2059 RHSC->getAPIntValue(),
2064 // Turn (C1-X) == C2 --> X == C1-C2
2065 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2066 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2068 DAG.getSetCC(dl, VT, N0.getOperand(1),
2069 DAG.getConstant(SUBC->getAPIntValue() -
2070 RHSC->getAPIntValue(),
2077 // Simplify (X+Z) == X --> Z == 0
2078 if (N0.getOperand(0) == N1)
2079 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2080 DAG.getConstant(0, N0.getValueType()), Cond);
2081 if (N0.getOperand(1) == N1) {
2082 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2083 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2084 DAG.getConstant(0, N0.getValueType()), Cond);
2085 else if (N0.getNode()->hasOneUse()) {
2086 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2087 // (Z-X) == X --> Z == X<<1
2088 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2090 DAG.getConstant(1, getShiftAmountTy()));
2091 if (!DCI.isCalledByLegalizer())
2092 DCI.AddToWorklist(SH.getNode());
2093 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2098 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2099 N1.getOpcode() == ISD::XOR) {
2100 // Simplify X == (X+Z) --> Z == 0
2101 if (N1.getOperand(0) == N0) {
2102 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2103 DAG.getConstant(0, N1.getValueType()), Cond);
2104 } else if (N1.getOperand(1) == N0) {
2105 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2106 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2107 DAG.getConstant(0, N1.getValueType()), Cond);
2108 } else if (N1.getNode()->hasOneUse()) {
2109 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2110 // X == (Z-X) --> X<<1 == Z
2111 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2112 DAG.getConstant(1, getShiftAmountTy()));
2113 if (!DCI.isCalledByLegalizer())
2114 DCI.AddToWorklist(SH.getNode());
2115 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2120 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2121 // Note that where y is variable and is known to have at most
2122 // one bit set (for example, if it is z&1) we cannot do this;
2123 // the expressions are not equivalent when y==0.
2124 if (N0.getOpcode() == ISD::AND)
2125 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2126 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2127 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2128 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2129 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2132 if (N1.getOpcode() == ISD::AND)
2133 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2134 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2135 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2136 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2137 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2142 // Fold away ALL boolean setcc's.
2144 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2146 default: llvm_unreachable("Unknown integer setcc!");
2147 case ISD::SETEQ: // X == Y -> ~(X^Y)
2148 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2149 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2150 if (!DCI.isCalledByLegalizer())
2151 DCI.AddToWorklist(Temp.getNode());
2153 case ISD::SETNE: // X != Y --> (X^Y)
2154 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2156 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2157 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2158 Temp = DAG.getNOT(dl, N0, MVT::i1);
2159 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2160 if (!DCI.isCalledByLegalizer())
2161 DCI.AddToWorklist(Temp.getNode());
2163 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2164 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2165 Temp = DAG.getNOT(dl, N1, MVT::i1);
2166 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2167 if (!DCI.isCalledByLegalizer())
2168 DCI.AddToWorklist(Temp.getNode());
2170 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2171 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2172 Temp = DAG.getNOT(dl, N0, MVT::i1);
2173 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2174 if (!DCI.isCalledByLegalizer())
2175 DCI.AddToWorklist(Temp.getNode());
2177 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2178 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2179 Temp = DAG.getNOT(dl, N1, MVT::i1);
2180 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2183 if (VT != MVT::i1) {
2184 if (!DCI.isCalledByLegalizer())
2185 DCI.AddToWorklist(N0.getNode());
2186 // FIXME: If running after legalize, we probably can't do this.
2187 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2192 // Could not fold it.
2196 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2197 /// node is a GlobalAddress + offset.
2198 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2199 int64_t &Offset) const {
2200 if (isa<GlobalAddressSDNode>(N)) {
2201 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2202 GA = GASD->getGlobal();
2203 Offset += GASD->getOffset();
2207 if (N->getOpcode() == ISD::ADD) {
2208 SDValue N1 = N->getOperand(0);
2209 SDValue N2 = N->getOperand(1);
2210 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2211 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2213 Offset += V->getSExtValue();
2216 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2217 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2219 Offset += V->getSExtValue();
2228 SDValue TargetLowering::
2229 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2230 // Default implementation: no optimization.
2234 //===----------------------------------------------------------------------===//
2235 // Inline Assembler Implementation Methods
2236 //===----------------------------------------------------------------------===//
2239 TargetLowering::ConstraintType
2240 TargetLowering::getConstraintType(const std::string &Constraint) const {
2241 // FIXME: lots more standard ones to handle.
2242 if (Constraint.size() == 1) {
2243 switch (Constraint[0]) {
2245 case 'r': return C_RegisterClass;
2247 case 'o': // offsetable
2248 case 'V': // not offsetable
2250 case 'i': // Simple Integer or Relocatable Constant
2251 case 'n': // Simple Integer
2252 case 's': // Relocatable Constant
2253 case 'X': // Allow ANY value.
2254 case 'I': // Target registers.
2266 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2267 Constraint[Constraint.size()-1] == '}')
2272 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2273 /// with another that has more specific requirements based on the type of the
2274 /// corresponding operand.
2275 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2276 if (ConstraintVT.isInteger())
2278 if (ConstraintVT.isFloatingPoint())
2279 return "f"; // works for many targets
2283 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2284 /// vector. If it is invalid, don't add anything to Ops.
2285 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2286 char ConstraintLetter,
2288 std::vector<SDValue> &Ops,
2289 SelectionDAG &DAG) const {
2290 switch (ConstraintLetter) {
2292 case 'X': // Allows any operand; labels (basic block) use this.
2293 if (Op.getOpcode() == ISD::BasicBlock) {
2298 case 'i': // Simple Integer or Relocatable Constant
2299 case 'n': // Simple Integer
2300 case 's': { // Relocatable Constant
2301 // These operands are interested in values of the form (GV+C), where C may
2302 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2303 // is possible and fine if either GV or C are missing.
2304 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2305 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2307 // If we have "(add GV, C)", pull out GV/C
2308 if (Op.getOpcode() == ISD::ADD) {
2309 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2310 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2311 if (C == 0 || GA == 0) {
2312 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2313 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2315 if (C == 0 || GA == 0)
2319 // If we find a valid operand, map to the TargetXXX version so that the
2320 // value itself doesn't get selected.
2321 if (GA) { // Either &GV or &GV+C
2322 if (ConstraintLetter != 'n') {
2323 int64_t Offs = GA->getOffset();
2324 if (C) Offs += C->getZExtValue();
2325 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2326 Op.getValueType(), Offs));
2330 if (C) { // just C, no GV.
2331 // Simple constants are not allowed for 's'.
2332 if (ConstraintLetter != 's') {
2333 // gcc prints these as sign extended. Sign extend value to 64 bits
2334 // now; without this it would get ZExt'd later in
2335 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2336 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2346 std::vector<unsigned> TargetLowering::
2347 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2349 return std::vector<unsigned>();
2353 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2354 getRegForInlineAsmConstraint(const std::string &Constraint,
2356 if (Constraint[0] != '{')
2357 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2358 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2360 // Remove the braces from around the name.
2361 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2363 // Figure out which register class contains this reg.
2364 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2365 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2366 E = RI->regclass_end(); RCI != E; ++RCI) {
2367 const TargetRegisterClass *RC = *RCI;
2369 // If none of the the value types for this register class are valid, we
2370 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2371 bool isLegal = false;
2372 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2374 if (isTypeLegal(*I)) {
2380 if (!isLegal) continue;
2382 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2384 if (RegName.equals_lower(RI->getName(*I)))
2385 return std::make_pair(*I, RC);
2389 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2392 //===----------------------------------------------------------------------===//
2393 // Constraint Selection.
2395 /// isMatchingInputConstraint - Return true of this is an input operand that is
2396 /// a matching constraint like "4".
2397 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2398 assert(!ConstraintCode.empty() && "No known constraint!");
2399 return isdigit(ConstraintCode[0]);
2402 /// getMatchedOperand - If this is an input matching constraint, this method
2403 /// returns the output operand it matches.
2404 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2405 assert(!ConstraintCode.empty() && "No known constraint!");
2406 return atoi(ConstraintCode.c_str());
2410 /// getConstraintGenerality - Return an integer indicating how general CT
2412 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2414 default: llvm_unreachable("Unknown constraint type!");
2415 case TargetLowering::C_Other:
2416 case TargetLowering::C_Unknown:
2418 case TargetLowering::C_Register:
2420 case TargetLowering::C_RegisterClass:
2422 case TargetLowering::C_Memory:
2427 /// ChooseConstraint - If there are multiple different constraints that we
2428 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2429 /// This is somewhat tricky: constraints fall into four classes:
2430 /// Other -> immediates and magic values
2431 /// Register -> one specific register
2432 /// RegisterClass -> a group of regs
2433 /// Memory -> memory
2434 /// Ideally, we would pick the most specific constraint possible: if we have
2435 /// something that fits into a register, we would pick it. The problem here
2436 /// is that if we have something that could either be in a register or in
2437 /// memory that use of the register could cause selection of *other*
2438 /// operands to fail: they might only succeed if we pick memory. Because of
2439 /// this the heuristic we use is:
2441 /// 1) If there is an 'other' constraint, and if the operand is valid for
2442 /// that constraint, use it. This makes us take advantage of 'i'
2443 /// constraints when available.
2444 /// 2) Otherwise, pick the most general constraint present. This prefers
2445 /// 'm' over 'r', for example.
2447 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2448 bool hasMemory, const TargetLowering &TLI,
2449 SDValue Op, SelectionDAG *DAG) {
2450 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2451 unsigned BestIdx = 0;
2452 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2453 int BestGenerality = -1;
2455 // Loop over the options, keeping track of the most general one.
2456 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2457 TargetLowering::ConstraintType CType =
2458 TLI.getConstraintType(OpInfo.Codes[i]);
2460 // If this is an 'other' constraint, see if the operand is valid for it.
2461 // For example, on X86 we might have an 'rI' constraint. If the operand
2462 // is an integer in the range [0..31] we want to use I (saving a load
2463 // of a register), otherwise we must use 'r'.
2464 if (CType == TargetLowering::C_Other && Op.getNode()) {
2465 assert(OpInfo.Codes[i].size() == 1 &&
2466 "Unhandled multi-letter 'other' constraint");
2467 std::vector<SDValue> ResultOps;
2468 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2470 if (!ResultOps.empty()) {
2477 // This constraint letter is more general than the previous one, use it.
2478 int Generality = getConstraintGenerality(CType);
2479 if (Generality > BestGenerality) {
2482 BestGenerality = Generality;
2486 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2487 OpInfo.ConstraintType = BestType;
2490 /// ComputeConstraintToUse - Determines the constraint code and constraint
2491 /// type to use for the specific AsmOperandInfo, setting
2492 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2493 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2496 SelectionDAG *DAG) const {
2497 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2499 // Single-letter constraints ('r') are very common.
2500 if (OpInfo.Codes.size() == 1) {
2501 OpInfo.ConstraintCode = OpInfo.Codes[0];
2502 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2504 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2507 // 'X' matches anything.
2508 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2509 // Labels and constants are handled elsewhere ('X' is the only thing
2510 // that matches labels). For Functions, the type here is the type of
2511 // the result, which is not what we want to look at; leave them alone.
2512 Value *v = OpInfo.CallOperandVal;
2513 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2514 OpInfo.CallOperandVal = v;
2518 // Otherwise, try to resolve it to something we know about by looking at
2519 // the actual operand type.
2520 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2521 OpInfo.ConstraintCode = Repl;
2522 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2527 //===----------------------------------------------------------------------===//
2528 // Loop Strength Reduction hooks
2529 //===----------------------------------------------------------------------===//
2531 /// isLegalAddressingMode - Return true if the addressing mode represented
2532 /// by AM is legal for this target, for a load/store of the specified type.
2533 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2534 const Type *Ty) const {
2535 // The default implementation of this implements a conservative RISCy, r+r and
2538 // Allows a sign-extended 16-bit immediate field.
2539 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2542 // No global is ever allowed as a base.
2546 // Only support r+r,
2548 case 0: // "r+i" or just "i", depending on HasBaseReg.
2551 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2553 // Otherwise we have r+r or r+i.
2556 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2558 // Allow 2*r as r+r.
2565 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2566 /// return a DAG expression to select that will generate the same value by
2567 /// multiplying by a magic number. See:
2568 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2569 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2570 std::vector<SDNode*>* Created) const {
2571 EVT VT = N->getValueType(0);
2572 DebugLoc dl= N->getDebugLoc();
2574 // Check to see if we can do this.
2575 // FIXME: We should be more aggressive here.
2576 if (!isTypeLegal(VT))
2579 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2580 APInt::ms magics = d.magic();
2582 // Multiply the numerator (operand 0) by the magic value
2583 // FIXME: We should support doing a MUL in a wider type
2585 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2586 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2587 DAG.getConstant(magics.m, VT));
2588 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2589 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2591 DAG.getConstant(magics.m, VT)).getNode(), 1);
2593 return SDValue(); // No mulhs or equvialent
2594 // If d > 0 and m < 0, add the numerator
2595 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2596 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2598 Created->push_back(Q.getNode());
2600 // If d < 0 and m > 0, subtract the numerator.
2601 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2602 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2604 Created->push_back(Q.getNode());
2606 // Shift right algebraic if shift value is nonzero
2608 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2609 DAG.getConstant(magics.s, getShiftAmountTy()));
2611 Created->push_back(Q.getNode());
2613 // Extract the sign bit and add it to the quotient
2615 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2616 getShiftAmountTy()));
2618 Created->push_back(T.getNode());
2619 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2622 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2623 /// return a DAG expression to select that will generate the same value by
2624 /// multiplying by a magic number. See:
2625 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2626 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2627 std::vector<SDNode*>* Created) const {
2628 EVT VT = N->getValueType(0);
2629 DebugLoc dl = N->getDebugLoc();
2631 // Check to see if we can do this.
2632 // FIXME: We should be more aggressive here.
2633 if (!isTypeLegal(VT))
2636 // FIXME: We should use a narrower constant when the upper
2637 // bits are known to be zero.
2638 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2639 APInt::mu magics = N1C->getAPIntValue().magicu();
2641 // Multiply the numerator (operand 0) by the magic value
2642 // FIXME: We should support doing a MUL in a wider type
2644 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2645 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2646 DAG.getConstant(magics.m, VT));
2647 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2648 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2650 DAG.getConstant(magics.m, VT)).getNode(), 1);
2652 return SDValue(); // No mulhu or equvialent
2654 Created->push_back(Q.getNode());
2656 if (magics.a == 0) {
2657 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2658 "We shouldn't generate an undefined shift!");
2659 return DAG.getNode(ISD::SRL, dl, VT, Q,
2660 DAG.getConstant(magics.s, getShiftAmountTy()));
2662 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2664 Created->push_back(NPQ.getNode());
2665 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2666 DAG.getConstant(1, getShiftAmountTy()));
2668 Created->push_back(NPQ.getNode());
2669 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2671 Created->push_back(NPQ.getNode());
2672 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2673 DAG.getConstant(magics.s-1, getShiftAmountTy()));