1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40 : TargetLoweringBase(tm) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
101 Args.push_back(Entry);
103 if (LC == RTLIB::UNKNOWN_LIBCALL)
104 report_fatal_error("Unsupported library call operation!");
105 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
107 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
108 TargetLowering::CallLoweringInfo CLI(DAG);
109 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
110 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
111 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
112 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
113 .setSExtResult(signExtend).setZExtResult(!signExtend);
114 return LowerCallTo(CLI);
118 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
119 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
120 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
121 SDValue &NewLHS, SDValue &NewRHS,
122 ISD::CondCode &CCCode,
124 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
125 && "Unsupported setcc type!");
127 // Expand into one or more soft-fp libcall(s).
128 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
132 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
133 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
137 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
138 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
143 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
147 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
148 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
152 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
153 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
157 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
158 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
161 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
162 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
165 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
166 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
169 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
170 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
173 // SETONE = SETOLT | SETOGT
174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
175 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
178 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
179 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
182 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
183 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
186 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
187 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
190 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
191 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
194 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
195 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
197 default: llvm_unreachable("Do not know how to soften this setcc!");
201 // Use the target specific return value for comparions lib calls.
202 EVT RetVT = getCmpLibcallReturnType();
203 SDValue Ops[2] = { NewLHS, NewRHS };
204 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
206 NewRHS = DAG.getConstant(0, dl, RetVT);
207 CCCode = getCmpLibcallCC(LC1);
208 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
209 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
210 getSetCCResultType(*DAG.getContext(), RetVT),
211 NewLHS, NewRHS, DAG.getCondCode(CCCode));
212 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
214 NewLHS = DAG.getNode(ISD::SETCC, dl,
215 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
216 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
217 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
222 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
223 /// current function. The returned value is a member of the
224 /// MachineJumpTableInfo::JTEntryKind enum.
225 unsigned TargetLowering::getJumpTableEncoding() const {
226 // In non-pic modes, just use the address of a block.
227 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
228 return MachineJumpTableInfo::EK_BlockAddress;
230 // In PIC mode, if the target supports a GPRel32 directive, use it.
231 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
232 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
234 // Otherwise, use a label difference.
235 return MachineJumpTableInfo::EK_LabelDifference32;
238 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
239 SelectionDAG &DAG) const {
240 // If our PIC model is GP relative, use the global offset table as the base.
241 unsigned JTEncoding = getJumpTableEncoding();
243 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
244 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
245 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
250 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
251 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
254 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
255 unsigned JTI,MCContext &Ctx) const{
256 // The normal PIC reloc base is the label at the start of the jump table.
257 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
261 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
262 // Assume that everything is safe in static mode.
263 if (getTargetMachine().getRelocationModel() == Reloc::Static)
266 // In dynamic-no-pic mode, assume that known defined values are safe.
267 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
269 !GA->getGlobal()->isDeclaration() &&
270 !GA->getGlobal()->isWeakForLinker())
273 // Otherwise assume nothing is safe.
277 //===----------------------------------------------------------------------===//
278 // Optimization Methods
279 //===----------------------------------------------------------------------===//
281 /// ShrinkDemandedConstant - Check to see if the specified operand of the
282 /// specified instruction is a constant integer. If so, check to see if there
283 /// are any bits set in the constant that are not demanded. If so, shrink the
284 /// constant and return true.
285 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
286 const APInt &Demanded) {
289 // FIXME: ISD::SELECT, ISD::SELECT_CC
290 switch (Op.getOpcode()) {
295 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
296 if (!C) return false;
298 if (Op.getOpcode() == ISD::XOR &&
299 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
302 // if we can expand it to have all bits set, do it
303 if (C->getAPIntValue().intersects(~Demanded)) {
304 EVT VT = Op.getValueType();
305 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
306 DAG.getConstant(Demanded &
309 return CombineTo(Op, New);
319 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
320 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
321 /// cast, but it could be generalized for targets with other types of
322 /// implicit widening casts.
324 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
326 const APInt &Demanded,
328 assert(Op.getNumOperands() == 2 &&
329 "ShrinkDemandedOp only supports binary operators!");
330 assert(Op.getNode()->getNumValues() == 1 &&
331 "ShrinkDemandedOp only supports nodes with one result!");
333 // Early return, as this function cannot handle vector types.
334 if (Op.getValueType().isVector())
337 // Don't do this if the node has another user, which may require the
339 if (!Op.getNode()->hasOneUse())
342 // Search for the smallest integer type with free casts to and from
343 // Op's type. For expedience, just check power-of-2 integer types.
344 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
345 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
346 unsigned SmallVTBits = DemandedSize;
347 if (!isPowerOf2_32(SmallVTBits))
348 SmallVTBits = NextPowerOf2(SmallVTBits);
349 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
350 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
351 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
352 TLI.isZExtFree(SmallVT, Op.getValueType())) {
353 // We found a type with free casts.
354 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
356 Op.getNode()->getOperand(0)),
357 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
358 Op.getNode()->getOperand(1)));
359 bool NeedZext = DemandedSize > SmallVTBits;
360 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
361 dl, Op.getValueType(), X);
362 return CombineTo(Op, Z);
368 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
369 /// DemandedMask bits of the result of Op are ever used downstream. If we can
370 /// use this information to simplify Op, create a new simplified DAG node and
371 /// return true, returning the original and new nodes in Old and New. Otherwise,
372 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
373 /// the expression (used to simplify the caller). The KnownZero/One bits may
374 /// only be accurate for those bits in the DemandedMask.
375 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
376 const APInt &DemandedMask,
379 TargetLoweringOpt &TLO,
380 unsigned Depth) const {
381 unsigned BitWidth = DemandedMask.getBitWidth();
382 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
383 "Mask size mismatches value type size!");
384 APInt NewMask = DemandedMask;
387 // Don't know anything.
388 KnownZero = KnownOne = APInt(BitWidth, 0);
390 // Other users may use these bits.
391 if (!Op.getNode()->hasOneUse()) {
393 // If not at the root, Just compute the KnownZero/KnownOne bits to
394 // simplify things downstream.
395 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
398 // If this is the root being simplified, allow it to have multiple uses,
399 // just set the NewMask to all bits.
400 NewMask = APInt::getAllOnesValue(BitWidth);
401 } else if (DemandedMask == 0) {
402 // Not demanding any bits from Op.
403 if (Op.getOpcode() != ISD::UNDEF)
404 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
406 } else if (Depth == 6) { // Limit search depth.
410 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
411 switch (Op.getOpcode()) {
413 // We know all of the bits for a constant!
414 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
415 KnownZero = ~KnownOne;
416 return false; // Don't fall through, will infinitely loop.
418 // If the RHS is a constant, check to see if the LHS would be zero without
419 // using the bits from the RHS. Below, we use knowledge about the RHS to
420 // simplify the LHS, here we're using information from the LHS to simplify
422 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
423 APInt LHSZero, LHSOne;
424 // Do not increment Depth here; that can cause an infinite loop.
425 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
426 // If the LHS already has zeros where RHSC does, this and is dead.
427 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
428 return TLO.CombineTo(Op, Op.getOperand(0));
429 // If any of the set bits in the RHS are known zero on the LHS, shrink
431 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
435 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
436 KnownOne, TLO, Depth+1))
438 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
439 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
440 KnownZero2, KnownOne2, TLO, Depth+1))
442 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
444 // If all of the demanded bits are known one on one side, return the other.
445 // These bits cannot contribute to the result of the 'and'.
446 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
447 return TLO.CombineTo(Op, Op.getOperand(0));
448 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
449 return TLO.CombineTo(Op, Op.getOperand(1));
450 // If all of the demanded bits in the inputs are known zeros, return zero.
451 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
452 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
453 // If the RHS is a constant, see if we can simplify it.
454 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
456 // If the operation can be done in a smaller type, do so.
457 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
460 // Output known-1 bits are only known if set in both the LHS & RHS.
461 KnownOne &= KnownOne2;
462 // Output known-0 are known to be clear if zero in either the LHS | RHS.
463 KnownZero |= KnownZero2;
466 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
467 KnownOne, TLO, Depth+1))
469 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
470 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
471 KnownZero2, KnownOne2, TLO, Depth+1))
473 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
475 // If all of the demanded bits are known zero on one side, return the other.
476 // These bits cannot contribute to the result of the 'or'.
477 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(0));
479 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
480 return TLO.CombineTo(Op, Op.getOperand(1));
481 // If all of the potentially set bits on one side are known to be set on
482 // the other side, just use the 'other' side.
483 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
484 return TLO.CombineTo(Op, Op.getOperand(0));
485 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
486 return TLO.CombineTo(Op, Op.getOperand(1));
487 // If the RHS is a constant, see if we can simplify it.
488 if (TLO.ShrinkDemandedConstant(Op, NewMask))
490 // If the operation can be done in a smaller type, do so.
491 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
494 // Output known-0 bits are only known if clear in both the LHS & RHS.
495 KnownZero &= KnownZero2;
496 // Output known-1 are known to be set if set in either the LHS | RHS.
497 KnownOne |= KnownOne2;
500 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
501 KnownOne, TLO, Depth+1))
503 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
504 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
505 KnownOne2, TLO, Depth+1))
507 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
509 // If all of the demanded bits are known zero on one side, return the other.
510 // These bits cannot contribute to the result of the 'xor'.
511 if ((KnownZero & NewMask) == NewMask)
512 return TLO.CombineTo(Op, Op.getOperand(0));
513 if ((KnownZero2 & NewMask) == NewMask)
514 return TLO.CombineTo(Op, Op.getOperand(1));
515 // If the operation can be done in a smaller type, do so.
516 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
519 // If all of the unknown bits are known to be zero on one side or the other
520 // (but not both) turn this into an *inclusive* or.
521 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
522 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
523 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
527 // Output known-0 bits are known if clear or set in both the LHS & RHS.
528 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
529 // Output known-1 are known to be set if set in only one of the LHS, RHS.
530 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
532 // If all of the demanded bits on one side are known, and all of the set
533 // bits on that side are also known to be set on the other side, turn this
534 // into an AND, as we know the bits will be cleared.
535 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
536 // NB: it is okay if more bits are known than are requested
537 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
538 if (KnownOne == KnownOne2) { // set bits are the same on both sides
539 EVT VT = Op.getValueType();
540 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
541 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
542 Op.getOperand(0), ANDC));
546 // If the RHS is a constant, see if we can simplify it.
547 // for XOR, we prefer to force bits to 1 if they will make a -1.
548 // if we can't force bits, try to shrink constant
549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
550 APInt Expanded = C->getAPIntValue() | (~NewMask);
551 // if we can expand it to have all bits set, do it
552 if (Expanded.isAllOnesValue()) {
553 if (Expanded != C->getAPIntValue()) {
554 EVT VT = Op.getValueType();
555 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
556 TLO.DAG.getConstant(Expanded, dl, VT));
557 return TLO.CombineTo(Op, New);
559 // if it already has all the bits set, nothing to change
560 // but don't shrink either!
561 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
566 KnownZero = KnownZeroOut;
567 KnownOne = KnownOneOut;
570 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
571 KnownOne, TLO, Depth+1))
573 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
574 KnownOne2, TLO, Depth+1))
576 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
577 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
579 // If the operands are constants, see if we can simplify them.
580 if (TLO.ShrinkDemandedConstant(Op, NewMask))
583 // Only known if known in both the LHS and RHS.
584 KnownOne &= KnownOne2;
585 KnownZero &= KnownZero2;
588 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
589 KnownOne, TLO, Depth+1))
591 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
592 KnownOne2, TLO, Depth+1))
594 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
595 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
597 // If the operands are constants, see if we can simplify them.
598 if (TLO.ShrinkDemandedConstant(Op, NewMask))
601 // Only known if known in both the LHS and RHS.
602 KnownOne &= KnownOne2;
603 KnownZero &= KnownZero2;
606 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
607 unsigned ShAmt = SA->getZExtValue();
608 SDValue InOp = Op.getOperand(0);
610 // If the shift count is an invalid immediate, don't do anything.
611 if (ShAmt >= BitWidth)
614 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
615 // single shift. We can do this if the bottom bits (which are shifted
616 // out) are never demanded.
617 if (InOp.getOpcode() == ISD::SRL &&
618 isa<ConstantSDNode>(InOp.getOperand(1))) {
619 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
620 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
621 unsigned Opc = ISD::SHL;
629 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
630 EVT VT = Op.getValueType();
631 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
632 InOp.getOperand(0), NewSA));
636 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
637 KnownZero, KnownOne, TLO, Depth+1))
640 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
641 // are not demanded. This will likely allow the anyext to be folded away.
642 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
643 SDValue InnerOp = InOp.getNode()->getOperand(0);
644 EVT InnerVT = InnerOp.getValueType();
645 unsigned InnerBits = InnerVT.getSizeInBits();
646 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
647 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
648 EVT ShTy = getShiftAmountTy(InnerVT);
649 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
652 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
653 TLO.DAG.getConstant(ShAmt, dl, ShTy));
656 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
659 // Repeat the SHL optimization above in cases where an extension
660 // intervenes: (shl (anyext (shr x, c1)), c2) to
661 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
662 // aren't demanded (as above) and that the shifted upper c1 bits of
663 // x aren't demanded.
664 if (InOp.hasOneUse() &&
665 InnerOp.getOpcode() == ISD::SRL &&
666 InnerOp.hasOneUse() &&
667 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
668 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
670 if (InnerShAmt < ShAmt &&
671 InnerShAmt < InnerBits &&
672 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
673 NewMask.trunc(ShAmt) == 0) {
675 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
676 Op.getOperand(1).getValueType());
677 EVT VT = Op.getValueType();
678 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
679 InnerOp.getOperand(0));
680 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
686 KnownZero <<= SA->getZExtValue();
687 KnownOne <<= SA->getZExtValue();
688 // low bits known zero.
689 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
693 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
694 EVT VT = Op.getValueType();
695 unsigned ShAmt = SA->getZExtValue();
696 unsigned VTSize = VT.getSizeInBits();
697 SDValue InOp = Op.getOperand(0);
699 // If the shift count is an invalid immediate, don't do anything.
700 if (ShAmt >= BitWidth)
703 APInt InDemandedMask = (NewMask << ShAmt);
705 // If the shift is exact, then it does demand the low bits (and knows that
707 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
708 InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
710 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
711 // single shift. We can do this if the top bits (which are shifted out)
712 // are never demanded.
713 if (InOp.getOpcode() == ISD::SHL &&
714 isa<ConstantSDNode>(InOp.getOperand(1))) {
715 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
716 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
717 unsigned Opc = ISD::SRL;
725 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
726 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
727 InOp.getOperand(0), NewSA));
731 // Compute the new bits that are at the top now.
732 if (SimplifyDemandedBits(InOp, InDemandedMask,
733 KnownZero, KnownOne, TLO, Depth+1))
735 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
736 KnownZero = KnownZero.lshr(ShAmt);
737 KnownOne = KnownOne.lshr(ShAmt);
739 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
740 KnownZero |= HighBits; // High bits known zero.
744 // If this is an arithmetic shift right and only the low-bit is set, we can
745 // always convert this into a logical shr, even if the shift amount is
746 // variable. The low bit of the shift cannot be an input sign bit unless
747 // the shift amount is >= the size of the datatype, which is undefined.
749 return TLO.CombineTo(Op,
750 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
751 Op.getOperand(0), Op.getOperand(1)));
753 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
754 EVT VT = Op.getValueType();
755 unsigned ShAmt = SA->getZExtValue();
757 // If the shift count is an invalid immediate, don't do anything.
758 if (ShAmt >= BitWidth)
761 APInt InDemandedMask = (NewMask << ShAmt);
763 // If the shift is exact, then it does demand the low bits (and knows that
765 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
766 InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
768 // If any of the demanded bits are produced by the sign extension, we also
769 // demand the input sign bit.
770 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
771 if (HighBits.intersects(NewMask))
772 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
774 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
775 KnownZero, KnownOne, TLO, Depth+1))
777 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
778 KnownZero = KnownZero.lshr(ShAmt);
779 KnownOne = KnownOne.lshr(ShAmt);
781 // Handle the sign bit, adjusted to where it is now in the mask.
782 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
784 // If the input sign bit is known to be zero, or if none of the top bits
785 // are demanded, turn this into an unsigned shift right.
786 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
788 Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
789 return TLO.CombineTo(Op,
790 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
791 Op.getOperand(1), &Flags));
794 int Log2 = NewMask.exactLogBase2();
796 // The bit must come from the sign.
798 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
799 Op.getOperand(1).getValueType());
800 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
801 Op.getOperand(0), NewSA));
804 if (KnownOne.intersects(SignBit))
805 // New bits are known one.
806 KnownOne |= HighBits;
809 case ISD::SIGN_EXTEND_INREG: {
810 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
812 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
813 // If we only care about the highest bit, don't bother shifting right.
814 if (MsbMask == NewMask) {
815 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
816 SDValue InOp = Op.getOperand(0);
817 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
818 bool AlreadySignExtended =
819 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
820 // However if the input is already sign extended we expect the sign
821 // extension to be dropped altogether later and do not simplify.
822 if (!AlreadySignExtended) {
823 // Compute the correct shift amount type, which must be getShiftAmountTy
824 // for scalar types after legalization.
825 EVT ShiftAmtTy = Op.getValueType();
826 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
827 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
829 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
831 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
832 Op.getValueType(), InOp,
837 // Sign extension. Compute the demanded bits in the result that are not
838 // present in the input.
840 APInt::getHighBitsSet(BitWidth,
841 BitWidth - ExVT.getScalarType().getSizeInBits());
843 // If none of the extended bits are demanded, eliminate the sextinreg.
844 if ((NewBits & NewMask) == 0)
845 return TLO.CombineTo(Op, Op.getOperand(0));
848 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
849 APInt InputDemandedBits =
850 APInt::getLowBitsSet(BitWidth,
851 ExVT.getScalarType().getSizeInBits()) &
854 // Since the sign extended bits are demanded, we know that the sign
856 InputDemandedBits |= InSignBit;
858 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
859 KnownZero, KnownOne, TLO, Depth+1))
861 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
863 // If the sign bit of the input is known set or clear, then we know the
864 // top bits of the result.
866 // If the input sign bit is known zero, convert this into a zero extension.
867 if (KnownZero.intersects(InSignBit))
868 return TLO.CombineTo(Op,
869 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
871 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
873 KnownZero &= ~NewBits;
874 } else { // Input sign bit unknown
875 KnownZero &= ~NewBits;
876 KnownOne &= ~NewBits;
880 case ISD::BUILD_PAIR: {
881 EVT HalfVT = Op.getOperand(0).getValueType();
882 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
884 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
885 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
887 APInt KnownZeroLo, KnownOneLo;
888 APInt KnownZeroHi, KnownOneHi;
890 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
891 KnownOneLo, TLO, Depth + 1))
894 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
895 KnownOneHi, TLO, Depth + 1))
898 KnownZero = KnownZeroLo.zext(BitWidth) |
899 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
901 KnownOne = KnownOneLo.zext(BitWidth) |
902 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
905 case ISD::ZERO_EXTEND: {
906 unsigned OperandBitWidth =
907 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
908 APInt InMask = NewMask.trunc(OperandBitWidth);
910 // If none of the top bits are demanded, convert this into an any_extend.
912 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
913 if (!NewBits.intersects(NewMask))
914 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
918 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
919 KnownZero, KnownOne, TLO, Depth+1))
921 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
922 KnownZero = KnownZero.zext(BitWidth);
923 KnownOne = KnownOne.zext(BitWidth);
924 KnownZero |= NewBits;
927 case ISD::SIGN_EXTEND: {
928 EVT InVT = Op.getOperand(0).getValueType();
929 unsigned InBits = InVT.getScalarType().getSizeInBits();
930 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
931 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
932 APInt NewBits = ~InMask & NewMask;
934 // If none of the top bits are demanded, convert this into an any_extend.
936 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
940 // Since some of the sign extended bits are demanded, we know that the sign
942 APInt InDemandedBits = InMask & NewMask;
943 InDemandedBits |= InSignBit;
944 InDemandedBits = InDemandedBits.trunc(InBits);
946 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
947 KnownOne, TLO, Depth+1))
949 KnownZero = KnownZero.zext(BitWidth);
950 KnownOne = KnownOne.zext(BitWidth);
952 // If the sign bit is known zero, convert this to a zero extend.
953 if (KnownZero.intersects(InSignBit))
954 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
958 // If the sign bit is known one, the top bits match.
959 if (KnownOne.intersects(InSignBit)) {
961 assert((KnownZero & NewBits) == 0);
962 } else { // Otherwise, top bits aren't known.
963 assert((KnownOne & NewBits) == 0);
964 assert((KnownZero & NewBits) == 0);
968 case ISD::ANY_EXTEND: {
969 unsigned OperandBitWidth =
970 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
971 APInt InMask = NewMask.trunc(OperandBitWidth);
972 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
973 KnownZero, KnownOne, TLO, Depth+1))
975 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
976 KnownZero = KnownZero.zext(BitWidth);
977 KnownOne = KnownOne.zext(BitWidth);
980 case ISD::TRUNCATE: {
981 // Simplify the input, using demanded bit information, and compute the known
982 // zero/one bits live out.
983 unsigned OperandBitWidth =
984 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
985 APInt TruncMask = NewMask.zext(OperandBitWidth);
986 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
987 KnownZero, KnownOne, TLO, Depth+1))
989 KnownZero = KnownZero.trunc(BitWidth);
990 KnownOne = KnownOne.trunc(BitWidth);
992 // If the input is only used by this truncate, see if we can shrink it based
993 // on the known demanded bits.
994 if (Op.getOperand(0).getNode()->hasOneUse()) {
995 SDValue In = Op.getOperand(0);
996 switch (In.getOpcode()) {
999 // Shrink SRL by a constant if none of the high bits shifted in are
1001 if (TLO.LegalTypes() &&
1002 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1003 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1006 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1009 SDValue Shift = In.getOperand(1);
1010 if (TLO.LegalTypes()) {
1011 uint64_t ShVal = ShAmt->getZExtValue();
1013 TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(Op.getValueType()));
1016 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1017 OperandBitWidth - BitWidth);
1018 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1020 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1021 // None of the shifted in bits are needed. Add a truncate of the
1022 // shift input, then shift it.
1023 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1026 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1035 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1038 case ISD::AssertZext: {
1039 // AssertZext demands all of the high bits, plus any of the low bits
1040 // demanded by its users.
1041 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1042 APInt InMask = APInt::getLowBitsSet(BitWidth,
1043 VT.getSizeInBits());
1044 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1045 KnownZero, KnownOne, TLO, Depth+1))
1047 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1049 KnownZero |= ~InMask & NewMask;
1053 // If this is an FP->Int bitcast and if the sign bit is the only
1054 // thing demanded, turn this into a FGETSIGN.
1055 if (!TLO.LegalOperations() &&
1056 !Op.getValueType().isVector() &&
1057 !Op.getOperand(0).getValueType().isVector() &&
1058 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1059 Op.getOperand(0).getValueType().isFloatingPoint()) {
1060 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1061 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1062 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1063 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1064 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1065 // place. We expect the SHL to be eliminated by other optimizations.
1066 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1067 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1068 if (!OpVTLegal && OpVTSizeInBits > 32)
1069 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1070 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1071 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType());
1072 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1081 // Add, Sub, and Mul don't demand any bits in positions beyond that
1082 // of the highest bit demanded of them.
1083 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1084 BitWidth - NewMask.countLeadingZeros());
1085 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1086 KnownOne2, TLO, Depth+1))
1088 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1089 KnownOne2, TLO, Depth+1))
1091 // See if the operation should be performed at a smaller bit width.
1092 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1097 // Just use computeKnownBits to compute output bits.
1098 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1102 // If we know the value of all of the demanded bits, return this as a
1104 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1105 // Avoid folding to a constant if any OpaqueConstant is involved.
1106 const SDNode *N = Op.getNode();
1107 for (SDNodeIterator I = SDNodeIterator::begin(N),
1108 E = SDNodeIterator::end(N); I != E; ++I) {
1110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1114 return TLO.CombineTo(Op,
1115 TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1121 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1122 /// in Mask are known to be either zero or one and return them in the
1123 /// KnownZero/KnownOne bitsets.
1124 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1127 const SelectionDAG &DAG,
1128 unsigned Depth) const {
1129 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1130 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1131 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1132 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1133 "Should use MaskedValueIsZero if you don't know whether Op"
1134 " is a target node!");
1135 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1138 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1139 /// targets that want to expose additional information about sign bits to the
1141 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1142 const SelectionDAG &,
1143 unsigned Depth) const {
1144 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1145 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1146 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1147 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1148 "Should use ComputeNumSignBits if you don't know whether Op"
1149 " is a target node!");
1153 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1154 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1155 /// determine which bit is set.
1157 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1158 // A left-shift of a constant one will have exactly one bit set, because
1159 // shifting the bit off the end is undefined.
1160 if (Val.getOpcode() == ISD::SHL)
1161 if (ConstantSDNode *C =
1162 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1163 if (C->getAPIntValue() == 1)
1166 // Similarly, a right-shift of a constant sign-bit will have exactly
1168 if (Val.getOpcode() == ISD::SRL)
1169 if (ConstantSDNode *C =
1170 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1171 if (C->getAPIntValue().isSignBit())
1174 // More could be done here, though the above checks are enough
1175 // to handle some common cases.
1177 // Fall back to computeKnownBits to catch other known cases.
1178 EVT OpVT = Val.getValueType();
1179 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1180 APInt KnownZero, KnownOne;
1181 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1182 return (KnownZero.countPopulation() == BitWidth - 1) &&
1183 (KnownOne.countPopulation() == 1);
1186 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1190 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1192 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1196 BitVector UndefElements;
1197 CN = BV->getConstantSplatNode(&UndefElements);
1198 // Only interested in constant splats, and we don't try to handle undef
1199 // elements in identifying boolean constants.
1200 if (!CN || UndefElements.none())
1204 switch (getBooleanContents(N->getValueType(0))) {
1205 case UndefinedBooleanContent:
1206 return CN->getAPIntValue()[0];
1207 case ZeroOrOneBooleanContent:
1209 case ZeroOrNegativeOneBooleanContent:
1210 return CN->isAllOnesValue();
1213 llvm_unreachable("Invalid boolean contents");
1216 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1220 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1222 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1226 BitVector UndefElements;
1227 CN = BV->getConstantSplatNode(&UndefElements);
1228 // Only interested in constant splats, and we don't try to handle undef
1229 // elements in identifying boolean constants.
1230 if (!CN || UndefElements.none())
1234 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1235 return !CN->getAPIntValue()[0];
1237 return CN->isNullValue();
1240 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1241 /// and cc. If it is unable to simplify it, return a null SDValue.
1243 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1244 ISD::CondCode Cond, bool foldBooleans,
1245 DAGCombinerInfo &DCI, SDLoc dl) const {
1246 SelectionDAG &DAG = DCI.DAG;
1248 // These setcc operations always fold.
1252 case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT);
1254 case ISD::SETTRUE2: {
1255 TargetLowering::BooleanContent Cnt =
1256 getBooleanContents(N0->getValueType(0));
1257 return DAG.getConstant(
1258 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl,
1263 // Ensure that the constant occurs on the RHS, and fold constant
1265 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1266 if (isa<ConstantSDNode>(N0.getNode()) &&
1267 (DCI.isBeforeLegalizeOps() ||
1268 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1269 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1271 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1272 const APInt &C1 = N1C->getAPIntValue();
1274 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1275 // equality comparison, then we're just comparing whether X itself is
1277 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1278 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1279 N0.getOperand(1).getOpcode() == ISD::Constant) {
1281 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1282 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1283 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1284 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1285 // (srl (ctlz x), 5) == 0 -> X != 0
1286 // (srl (ctlz x), 5) != 1 -> X != 0
1289 // (srl (ctlz x), 5) != 0 -> X == 0
1290 // (srl (ctlz x), 5) == 1 -> X == 0
1293 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1294 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1300 // Look through truncs that don't change the value of a ctpop.
1301 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1302 CTPOP = N0.getOperand(0);
1304 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1305 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1306 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1307 EVT CTVT = CTPOP.getValueType();
1308 SDValue CTOp = CTPOP.getOperand(0);
1310 // (ctpop x) u< 2 -> (x & x-1) == 0
1311 // (ctpop x) u> 1 -> (x & x-1) != 0
1312 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1313 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1314 DAG.getConstant(1, dl, CTVT));
1315 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1316 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1317 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1320 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1323 // (zext x) == C --> x == (trunc C)
1324 // (sext x) == C --> x == (trunc C)
1325 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1326 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1327 unsigned MinBits = N0.getValueSizeInBits();
1329 bool Signed = false;
1330 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1332 MinBits = N0->getOperand(0).getValueSizeInBits();
1333 PreExt = N0->getOperand(0);
1334 } else if (N0->getOpcode() == ISD::AND) {
1335 // DAGCombine turns costly ZExts into ANDs
1336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1337 if ((C->getAPIntValue()+1).isPowerOf2()) {
1338 MinBits = C->getAPIntValue().countTrailingOnes();
1339 PreExt = N0->getOperand(0);
1341 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1343 MinBits = N0->getOperand(0).getValueSizeInBits();
1344 PreExt = N0->getOperand(0);
1346 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1347 // ZEXTLOAD / SEXTLOAD
1348 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1349 MinBits = LN0->getMemoryVT().getSizeInBits();
1351 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1353 MinBits = LN0->getMemoryVT().getSizeInBits();
1358 // Figure out how many bits we need to preserve this constant.
1359 unsigned ReqdBits = Signed ?
1360 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1363 // Make sure we're not losing bits from the constant.
1365 MinBits < C1.getBitWidth() &&
1366 MinBits >= ReqdBits) {
1367 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1368 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1369 // Will get folded away.
1370 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1371 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1372 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1377 // If the LHS is '(and load, const)', the RHS is 0,
1378 // the test is for equality or unsigned, and all 1 bits of the const are
1379 // in the same partial word, see if we can shorten the load.
1380 if (DCI.isBeforeLegalize() &&
1381 !ISD::isSignedIntSetCC(Cond) &&
1382 N0.getOpcode() == ISD::AND && C1 == 0 &&
1383 N0.getNode()->hasOneUse() &&
1384 isa<LoadSDNode>(N0.getOperand(0)) &&
1385 N0.getOperand(0).getNode()->hasOneUse() &&
1386 isa<ConstantSDNode>(N0.getOperand(1))) {
1387 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1389 unsigned bestWidth = 0, bestOffset = 0;
1390 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1391 unsigned origWidth = N0.getValueType().getSizeInBits();
1392 unsigned maskWidth = origWidth;
1393 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1394 // 8 bits, but have to be careful...
1395 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1396 origWidth = Lod->getMemoryVT().getSizeInBits();
1398 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1399 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1400 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1401 for (unsigned offset=0; offset<origWidth/width; offset++) {
1402 if ((newMask & Mask) == Mask) {
1403 if (!getDataLayout()->isLittleEndian())
1404 bestOffset = (origWidth/width - offset - 1) * (width/8);
1406 bestOffset = (uint64_t)offset * (width/8);
1407 bestMask = Mask.lshr(offset * (width/8) * 8);
1411 newMask = newMask << width;
1416 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1417 if (newVT.isRound()) {
1418 EVT PtrType = Lod->getOperand(1).getValueType();
1419 SDValue Ptr = Lod->getBasePtr();
1420 if (bestOffset != 0)
1421 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1422 DAG.getConstant(bestOffset, dl, PtrType));
1423 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1424 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1425 Lod->getPointerInfo().getWithOffset(bestOffset),
1426 false, false, false, NewAlign);
1427 return DAG.getSetCC(dl, VT,
1428 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1429 DAG.getConstant(bestMask.trunc(bestWidth),
1431 DAG.getConstant(0LL, dl, newVT), Cond);
1436 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1437 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1438 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1440 // If the comparison constant has bits in the upper part, the
1441 // zero-extended value could never match.
1442 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1443 C1.getBitWidth() - InSize))) {
1447 case ISD::SETEQ: return DAG.getConstant(0, dl, VT);
1450 case ISD::SETNE: return DAG.getConstant(1, dl, VT);
1453 // True if the sign bit of C1 is set.
1454 return DAG.getConstant(C1.isNegative(), dl, VT);
1457 // True if the sign bit of C1 isn't set.
1458 return DAG.getConstant(C1.isNonNegative(), dl, VT);
1464 // Otherwise, we can perform the comparison with the low bits.
1472 EVT newVT = N0.getOperand(0).getValueType();
1473 if (DCI.isBeforeLegalizeOps() ||
1474 (isOperationLegal(ISD::SETCC, newVT) &&
1475 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1476 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1477 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1479 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1481 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1486 break; // todo, be more careful with signed comparisons
1488 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1489 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1490 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1491 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1492 EVT ExtDstTy = N0.getValueType();
1493 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1495 // If the constant doesn't fit into the number of bits for the source of
1496 // the sign extension, it is impossible for both sides to be equal.
1497 if (C1.getMinSignedBits() > ExtSrcTyBits)
1498 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
1501 EVT Op0Ty = N0.getOperand(0).getValueType();
1502 if (Op0Ty == ExtSrcTy) {
1503 ZextOp = N0.getOperand(0);
1505 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1506 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1507 DAG.getConstant(Imm, dl, Op0Ty));
1509 if (!DCI.isCalledByLegalizer())
1510 DCI.AddToWorklist(ZextOp.getNode());
1511 // Otherwise, make this a use of a zext.
1512 return DAG.getSetCC(dl, VT, ZextOp,
1513 DAG.getConstant(C1 & APInt::getLowBitsSet(
1518 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1519 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1520 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1521 if (N0.getOpcode() == ISD::SETCC &&
1522 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1523 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1525 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1526 // Invert the condition.
1527 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1528 CC = ISD::getSetCCInverse(CC,
1529 N0.getOperand(0).getValueType().isInteger());
1530 if (DCI.isBeforeLegalizeOps() ||
1531 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1532 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1535 if ((N0.getOpcode() == ISD::XOR ||
1536 (N0.getOpcode() == ISD::AND &&
1537 N0.getOperand(0).getOpcode() == ISD::XOR &&
1538 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1539 isa<ConstantSDNode>(N0.getOperand(1)) &&
1540 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1541 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1542 // can only do this if the top bits are known zero.
1543 unsigned BitWidth = N0.getValueSizeInBits();
1544 if (DAG.MaskedValueIsZero(N0,
1545 APInt::getHighBitsSet(BitWidth,
1547 // Okay, get the un-inverted input value.
1549 if (N0.getOpcode() == ISD::XOR)
1550 Val = N0.getOperand(0);
1552 assert(N0.getOpcode() == ISD::AND &&
1553 N0.getOperand(0).getOpcode() == ISD::XOR);
1554 // ((X^1)&1)^1 -> X & 1
1555 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1556 N0.getOperand(0).getOperand(0),
1560 return DAG.getSetCC(dl, VT, Val, N1,
1561 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1563 } else if (N1C->getAPIntValue() == 1 &&
1565 getBooleanContents(N0->getValueType(0)) ==
1566 ZeroOrOneBooleanContent)) {
1568 if (Op0.getOpcode() == ISD::TRUNCATE)
1569 Op0 = Op0.getOperand(0);
1571 if ((Op0.getOpcode() == ISD::XOR) &&
1572 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1573 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1574 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1575 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1576 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1579 if (Op0.getOpcode() == ISD::AND &&
1580 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1581 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1582 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1583 if (Op0.getValueType().bitsGT(VT))
1584 Op0 = DAG.getNode(ISD::AND, dl, VT,
1585 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1586 DAG.getConstant(1, dl, VT));
1587 else if (Op0.getValueType().bitsLT(VT))
1588 Op0 = DAG.getNode(ISD::AND, dl, VT,
1589 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1590 DAG.getConstant(1, dl, VT));
1592 return DAG.getSetCC(dl, VT, Op0,
1593 DAG.getConstant(0, dl, Op0.getValueType()),
1594 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1596 if (Op0.getOpcode() == ISD::AssertZext &&
1597 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1598 return DAG.getSetCC(dl, VT, Op0,
1599 DAG.getConstant(0, dl, Op0.getValueType()),
1600 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1604 APInt MinVal, MaxVal;
1605 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1606 if (ISD::isSignedIntSetCC(Cond)) {
1607 MinVal = APInt::getSignedMinValue(OperandBitSize);
1608 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1610 MinVal = APInt::getMinValue(OperandBitSize);
1611 MaxVal = APInt::getMaxValue(OperandBitSize);
1614 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1615 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1616 if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1617 // X >= C0 --> X > (C0 - 1)
1619 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1620 if ((DCI.isBeforeLegalizeOps() ||
1621 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1622 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1623 isLegalICmpImmediate(C.getSExtValue())))) {
1624 return DAG.getSetCC(dl, VT, N0,
1625 DAG.getConstant(C, dl, N1.getValueType()),
1630 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1631 if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1632 // X <= C0 --> X < (C0 + 1)
1634 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1635 if ((DCI.isBeforeLegalizeOps() ||
1636 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1637 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1638 isLegalICmpImmediate(C.getSExtValue())))) {
1639 return DAG.getSetCC(dl, VT, N0,
1640 DAG.getConstant(C, dl, N1.getValueType()),
1645 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1646 return DAG.getConstant(0, dl, VT); // X < MIN --> false
1647 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1648 return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1649 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1650 return DAG.getConstant(0, dl, VT); // X > MAX --> false
1651 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1652 return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1654 // Canonicalize setgt X, Min --> setne X, Min
1655 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1656 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1657 // Canonicalize setlt X, Max --> setne X, Max
1658 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1659 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1661 // If we have setult X, 1, turn it into seteq X, 0
1662 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1663 return DAG.getSetCC(dl, VT, N0,
1664 DAG.getConstant(MinVal, dl, N0.getValueType()),
1666 // If we have setugt X, Max-1, turn it into seteq X, Max
1667 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1668 return DAG.getSetCC(dl, VT, N0,
1669 DAG.getConstant(MaxVal, dl, N0.getValueType()),
1672 // If we have "setcc X, C0", check to see if we can shrink the immediate
1675 // SETUGT X, SINTMAX -> SETLT X, 0
1676 if (Cond == ISD::SETUGT &&
1677 C1 == APInt::getSignedMaxValue(OperandBitSize))
1678 return DAG.getSetCC(dl, VT, N0,
1679 DAG.getConstant(0, dl, N1.getValueType()),
1682 // SETULT X, SINTMIN -> SETGT X, -1
1683 if (Cond == ISD::SETULT &&
1684 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1685 SDValue ConstMinusOne =
1686 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
1688 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1691 // Fold bit comparisons when we can.
1692 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1693 (VT == N0.getValueType() ||
1694 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1695 N0.getOpcode() == ISD::AND)
1696 if (ConstantSDNode *AndRHS =
1697 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1698 EVT ShiftTy = DCI.isBeforeLegalize() ?
1699 getPointerTy() : getShiftAmountTy(N0.getValueType());
1700 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1701 // Perform the xform if the AND RHS is a single bit.
1702 if (AndRHS->getAPIntValue().isPowerOf2()) {
1703 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1704 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1705 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1708 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1709 // (X & 8) == 8 --> (X & 8) >> 3
1710 // Perform the xform if C1 is a single bit.
1711 if (C1.isPowerOf2()) {
1712 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1713 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1714 DAG.getConstant(C1.logBase2(), dl,
1720 if (C1.getMinSignedBits() <= 64 &&
1721 !isLegalICmpImmediate(C1.getSExtValue())) {
1722 // (X & -256) == 256 -> (X >> 8) == 1
1723 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1724 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1725 if (ConstantSDNode *AndRHS =
1726 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1727 const APInt &AndRHSC = AndRHS->getAPIntValue();
1728 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1729 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1730 EVT ShiftTy = DCI.isBeforeLegalize() ?
1731 getPointerTy() : getShiftAmountTy(N0.getValueType());
1732 EVT CmpTy = N0.getValueType();
1733 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1734 DAG.getConstant(ShiftBits, dl,
1736 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
1737 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1740 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1741 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1742 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1743 // X < 0x100000000 -> (X >> 32) < 1
1744 // X >= 0x100000000 -> (X >> 32) >= 1
1745 // X <= 0x0ffffffff -> (X >> 32) < 1
1746 // X > 0x0ffffffff -> (X >> 32) >= 1
1749 ISD::CondCode NewCond = Cond;
1751 ShiftBits = C1.countTrailingOnes();
1753 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1755 ShiftBits = C1.countTrailingZeros();
1757 NewC = NewC.lshr(ShiftBits);
1758 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
1759 isLegalICmpImmediate(NewC.getSExtValue())) {
1760 EVT ShiftTy = DCI.isBeforeLegalize() ?
1761 getPointerTy() : getShiftAmountTy(N0.getValueType());
1762 EVT CmpTy = N0.getValueType();
1763 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1764 DAG.getConstant(ShiftBits, dl, ShiftTy));
1765 SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
1766 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1772 if (isa<ConstantFPSDNode>(N0.getNode())) {
1773 // Constant fold or commute setcc.
1774 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1775 if (O.getNode()) return O;
1776 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1777 // If the RHS of an FP comparison is a constant, simplify it away in
1779 if (CFP->getValueAPF().isNaN()) {
1780 // If an operand is known to be a nan, we can fold it.
1781 switch (ISD::getUnorderedFlavor(Cond)) {
1782 default: llvm_unreachable("Unknown flavor!");
1783 case 0: // Known false.
1784 return DAG.getConstant(0, dl, VT);
1785 case 1: // Known true.
1786 return DAG.getConstant(1, dl, VT);
1787 case 2: // Undefined.
1788 return DAG.getUNDEF(VT);
1792 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1793 // constant if knowing that the operand is non-nan is enough. We prefer to
1794 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1796 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1797 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1799 // If the condition is not legal, see if we can find an equivalent one
1801 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1802 // If the comparison was an awkward floating-point == or != and one of
1803 // the comparison operands is infinity or negative infinity, convert the
1804 // condition to a less-awkward <= or >=.
1805 if (CFP->getValueAPF().isInfinity()) {
1806 if (CFP->getValueAPF().isNegative()) {
1807 if (Cond == ISD::SETOEQ &&
1808 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1809 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1810 if (Cond == ISD::SETUEQ &&
1811 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1812 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1813 if (Cond == ISD::SETUNE &&
1814 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1815 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1816 if (Cond == ISD::SETONE &&
1817 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1818 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1820 if (Cond == ISD::SETOEQ &&
1821 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1822 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1823 if (Cond == ISD::SETUEQ &&
1824 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1825 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1826 if (Cond == ISD::SETUNE &&
1827 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1828 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1829 if (Cond == ISD::SETONE &&
1830 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1831 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1838 // The sext(setcc()) => setcc() optimization relies on the appropriate
1839 // constant being emitted.
1841 switch (getBooleanContents(N0.getValueType())) {
1842 case UndefinedBooleanContent:
1843 case ZeroOrOneBooleanContent:
1844 EqVal = ISD::isTrueWhenEqual(Cond);
1846 case ZeroOrNegativeOneBooleanContent:
1847 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1851 // We can always fold X == X for integer setcc's.
1852 if (N0.getValueType().isInteger()) {
1853 return DAG.getConstant(EqVal, dl, VT);
1855 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1856 if (UOF == 2) // FP operators that are undefined on NaNs.
1857 return DAG.getConstant(EqVal, dl, VT);
1858 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1859 return DAG.getConstant(EqVal, dl, VT);
1860 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1861 // if it is not already.
1862 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1863 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1864 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1865 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1868 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1869 N0.getValueType().isInteger()) {
1870 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1871 N0.getOpcode() == ISD::XOR) {
1872 // Simplify (X+Y) == (X+Z) --> Y == Z
1873 if (N0.getOpcode() == N1.getOpcode()) {
1874 if (N0.getOperand(0) == N1.getOperand(0))
1875 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1876 if (N0.getOperand(1) == N1.getOperand(1))
1877 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1878 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1879 // If X op Y == Y op X, try other combinations.
1880 if (N0.getOperand(0) == N1.getOperand(1))
1881 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1883 if (N0.getOperand(1) == N1.getOperand(0))
1884 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1889 // If RHS is a legal immediate value for a compare instruction, we need
1890 // to be careful about increasing register pressure needlessly.
1891 bool LegalRHSImm = false;
1893 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1894 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1895 // Turn (X+C1) == C2 --> X == C2-C1
1896 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1897 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1898 DAG.getConstant(RHSC->getAPIntValue()-
1899 LHSR->getAPIntValue(),
1900 dl, N0.getValueType()), Cond);
1903 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1904 if (N0.getOpcode() == ISD::XOR)
1905 // If we know that all of the inverted bits are zero, don't bother
1906 // performing the inversion.
1907 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1909 DAG.getSetCC(dl, VT, N0.getOperand(0),
1910 DAG.getConstant(LHSR->getAPIntValue() ^
1911 RHSC->getAPIntValue(),
1912 dl, N0.getValueType()),
1916 // Turn (C1-X) == C2 --> X == C1-C2
1917 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1918 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1920 DAG.getSetCC(dl, VT, N0.getOperand(1),
1921 DAG.getConstant(SUBC->getAPIntValue() -
1922 RHSC->getAPIntValue(),
1923 dl, N0.getValueType()),
1928 // Could RHSC fold directly into a compare?
1929 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1930 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1933 // Simplify (X+Z) == X --> Z == 0
1934 // Don't do this if X is an immediate that can fold into a cmp
1935 // instruction and X+Z has other uses. It could be an induction variable
1936 // chain, and the transform would increase register pressure.
1937 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1938 if (N0.getOperand(0) == N1)
1939 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1940 DAG.getConstant(0, dl, N0.getValueType()), Cond);
1941 if (N0.getOperand(1) == N1) {
1942 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1943 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1944 DAG.getConstant(0, dl, N0.getValueType()),
1946 if (N0.getNode()->hasOneUse()) {
1947 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1948 // (Z-X) == X --> Z == X<<1
1949 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1950 DAG.getConstant(1, dl,
1951 getShiftAmountTy(N1.getValueType())));
1952 if (!DCI.isCalledByLegalizer())
1953 DCI.AddToWorklist(SH.getNode());
1954 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1960 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1961 N1.getOpcode() == ISD::XOR) {
1962 // Simplify X == (X+Z) --> Z == 0
1963 if (N1.getOperand(0) == N0)
1964 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1965 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1966 if (N1.getOperand(1) == N0) {
1967 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1968 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1969 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1970 if (N1.getNode()->hasOneUse()) {
1971 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1972 // X == (Z-X) --> X<<1 == Z
1973 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1974 DAG.getConstant(1, dl,
1975 getShiftAmountTy(N0.getValueType())));
1976 if (!DCI.isCalledByLegalizer())
1977 DCI.AddToWorklist(SH.getNode());
1978 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1983 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1984 // Note that where y is variable and is known to have at most
1985 // one bit set (for example, if it is z&1) we cannot do this;
1986 // the expressions are not equivalent when y==0.
1987 if (N0.getOpcode() == ISD::AND)
1988 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1989 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1990 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1991 if (DCI.isBeforeLegalizeOps() ||
1992 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1993 SDValue Zero = DAG.getConstant(0, dl, N1.getValueType());
1994 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1998 if (N1.getOpcode() == ISD::AND)
1999 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2000 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2001 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2002 if (DCI.isBeforeLegalizeOps() ||
2003 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
2004 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2005 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2011 // Fold away ALL boolean setcc's.
2013 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2015 default: llvm_unreachable("Unknown integer setcc!");
2016 case ISD::SETEQ: // X == Y -> ~(X^Y)
2017 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2018 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2019 if (!DCI.isCalledByLegalizer())
2020 DCI.AddToWorklist(Temp.getNode());
2022 case ISD::SETNE: // X != Y --> (X^Y)
2023 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2025 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2026 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2027 Temp = DAG.getNOT(dl, N0, MVT::i1);
2028 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2029 if (!DCI.isCalledByLegalizer())
2030 DCI.AddToWorklist(Temp.getNode());
2032 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2033 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2034 Temp = DAG.getNOT(dl, N1, MVT::i1);
2035 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2036 if (!DCI.isCalledByLegalizer())
2037 DCI.AddToWorklist(Temp.getNode());
2039 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2040 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2041 Temp = DAG.getNOT(dl, N0, MVT::i1);
2042 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2043 if (!DCI.isCalledByLegalizer())
2044 DCI.AddToWorklist(Temp.getNode());
2046 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2047 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2048 Temp = DAG.getNOT(dl, N1, MVT::i1);
2049 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2052 if (VT != MVT::i1) {
2053 if (!DCI.isCalledByLegalizer())
2054 DCI.AddToWorklist(N0.getNode());
2055 // FIXME: If running after legalize, we probably can't do this.
2056 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2061 // Could not fold it.
2065 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2066 /// node is a GlobalAddress + offset.
2067 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2068 int64_t &Offset) const {
2069 if (isa<GlobalAddressSDNode>(N)) {
2070 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2071 GA = GASD->getGlobal();
2072 Offset += GASD->getOffset();
2076 if (N->getOpcode() == ISD::ADD) {
2077 SDValue N1 = N->getOperand(0);
2078 SDValue N2 = N->getOperand(1);
2079 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2080 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2082 Offset += V->getSExtValue();
2085 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2086 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2088 Offset += V->getSExtValue();
2098 SDValue TargetLowering::
2099 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2100 // Default implementation: no optimization.
2104 //===----------------------------------------------------------------------===//
2105 // Inline Assembler Implementation Methods
2106 //===----------------------------------------------------------------------===//
2109 TargetLowering::ConstraintType
2110 TargetLowering::getConstraintType(const std::string &Constraint) const {
2111 unsigned S = Constraint.size();
2114 switch (Constraint[0]) {
2116 case 'r': return C_RegisterClass;
2118 case 'o': // offsetable
2119 case 'V': // not offsetable
2121 case 'i': // Simple Integer or Relocatable Constant
2122 case 'n': // Simple Integer
2123 case 'E': // Floating Point Constant
2124 case 'F': // Floating Point Constant
2125 case 's': // Relocatable Constant
2126 case 'p': // Address.
2127 case 'X': // Allow ANY value.
2128 case 'I': // Target registers.
2142 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2143 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
2150 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2151 /// with another that has more specific requirements based on the type of the
2152 /// corresponding operand.
2153 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2154 if (ConstraintVT.isInteger())
2156 if (ConstraintVT.isFloatingPoint())
2157 return "f"; // works for many targets
2161 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2162 /// vector. If it is invalid, don't add anything to Ops.
2163 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2164 std::string &Constraint,
2165 std::vector<SDValue> &Ops,
2166 SelectionDAG &DAG) const {
2168 if (Constraint.length() > 1) return;
2170 char ConstraintLetter = Constraint[0];
2171 switch (ConstraintLetter) {
2173 case 'X': // Allows any operand; labels (basic block) use this.
2174 if (Op.getOpcode() == ISD::BasicBlock) {
2179 case 'i': // Simple Integer or Relocatable Constant
2180 case 'n': // Simple Integer
2181 case 's': { // Relocatable Constant
2182 // These operands are interested in values of the form (GV+C), where C may
2183 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2184 // is possible and fine if either GV or C are missing.
2185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2186 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2188 // If we have "(add GV, C)", pull out GV/C
2189 if (Op.getOpcode() == ISD::ADD) {
2190 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2191 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2193 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2194 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2197 C = nullptr, GA = nullptr;
2200 // If we find a valid operand, map to the TargetXXX version so that the
2201 // value itself doesn't get selected.
2202 if (GA) { // Either &GV or &GV+C
2203 if (ConstraintLetter != 'n') {
2204 int64_t Offs = GA->getOffset();
2205 if (C) Offs += C->getZExtValue();
2206 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2207 C ? SDLoc(C) : SDLoc(),
2208 Op.getValueType(), Offs));
2212 if (C) { // just C, no GV.
2213 // Simple constants are not allowed for 's'.
2214 if (ConstraintLetter != 's') {
2215 // gcc prints these as sign extended. Sign extend value to 64 bits
2216 // now; without this it would get ZExt'd later in
2217 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2218 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2219 SDLoc(C), MVT::i64));
2228 std::pair<unsigned, const TargetRegisterClass *>
2229 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
2230 const std::string &Constraint,
2232 if (Constraint.empty() || Constraint[0] != '{')
2233 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2234 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2236 // Remove the braces from around the name.
2237 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2239 std::pair<unsigned, const TargetRegisterClass*> R =
2240 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2242 // Figure out which register class contains this reg.
2243 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2244 E = RI->regclass_end(); RCI != E; ++RCI) {
2245 const TargetRegisterClass *RC = *RCI;
2247 // If none of the value types for this register class are valid, we
2248 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2252 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2254 if (RegName.equals_lower(RI->getName(*I))) {
2255 std::pair<unsigned, const TargetRegisterClass*> S =
2256 std::make_pair(*I, RC);
2258 // If this register class has the requested value type, return it,
2259 // otherwise keep searching and return the first class found
2260 // if no other is found which explicitly has the requested type.
2261 if (RC->hasType(VT))
2272 //===----------------------------------------------------------------------===//
2273 // Constraint Selection.
2275 /// isMatchingInputConstraint - Return true of this is an input operand that is
2276 /// a matching constraint like "4".
2277 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2278 assert(!ConstraintCode.empty() && "No known constraint!");
2279 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2282 /// getMatchedOperand - If this is an input matching constraint, this method
2283 /// returns the output operand it matches.
2284 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2285 assert(!ConstraintCode.empty() && "No known constraint!");
2286 return atoi(ConstraintCode.c_str());
2290 /// ParseConstraints - Split up the constraint string from the inline
2291 /// assembly value into the specific constraints and their prefixes,
2292 /// and also tie in the associated operand values.
2293 /// If this returns an empty vector, and if the constraint string itself
2294 /// isn't empty, there was an error parsing.
2295 TargetLowering::AsmOperandInfoVector
2296 TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI,
2297 ImmutableCallSite CS) const {
2298 /// ConstraintOperands - Information about all of the constraints.
2299 AsmOperandInfoVector ConstraintOperands;
2300 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2301 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2303 // Do a prepass over the constraints, canonicalizing them, and building up the
2304 // ConstraintOperands list.
2305 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2306 unsigned ResNo = 0; // ResNo - The result number of the next output.
2308 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2309 ConstraintOperands.emplace_back(std::move(CI));
2310 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2312 // Update multiple alternative constraint count.
2313 if (OpInfo.multipleAlternatives.size() > maCount)
2314 maCount = OpInfo.multipleAlternatives.size();
2316 OpInfo.ConstraintVT = MVT::Other;
2318 // Compute the value type for each operand.
2319 switch (OpInfo.Type) {
2320 case InlineAsm::isOutput:
2321 // Indirect outputs just consume an argument.
2322 if (OpInfo.isIndirect) {
2323 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2327 // The return value of the call is this value. As such, there is no
2328 // corresponding argument.
2329 assert(!CS.getType()->isVoidTy() &&
2331 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2332 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2334 assert(ResNo == 0 && "Asm only has one result!");
2335 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2339 case InlineAsm::isInput:
2340 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2342 case InlineAsm::isClobber:
2347 if (OpInfo.CallOperandVal) {
2348 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2349 if (OpInfo.isIndirect) {
2350 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2352 report_fatal_error("Indirect operand for inline asm not a pointer!");
2353 OpTy = PtrTy->getElementType();
2356 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2357 if (StructType *STy = dyn_cast<StructType>(OpTy))
2358 if (STy->getNumElements() == 1)
2359 OpTy = STy->getElementType(0);
2361 // If OpTy is not a single value, it may be a struct/union that we
2362 // can tile with integers.
2363 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2364 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2373 OpInfo.ConstraintVT =
2374 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2377 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2379 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2380 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2382 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2387 // If we have multiple alternative constraints, select the best alternative.
2388 if (!ConstraintOperands.empty()) {
2390 unsigned bestMAIndex = 0;
2391 int bestWeight = -1;
2392 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2395 // Compute the sums of the weights for each alternative, keeping track
2396 // of the best (highest weight) one so far.
2397 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2399 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2400 cIndex != eIndex; ++cIndex) {
2401 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2402 if (OpInfo.Type == InlineAsm::isClobber)
2405 // If this is an output operand with a matching input operand,
2406 // look up the matching input. If their types mismatch, e.g. one
2407 // is an integer, the other is floating point, or their sizes are
2408 // different, flag it as an maCantMatch.
2409 if (OpInfo.hasMatchingInput()) {
2410 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2411 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2412 if ((OpInfo.ConstraintVT.isInteger() !=
2413 Input.ConstraintVT.isInteger()) ||
2414 (OpInfo.ConstraintVT.getSizeInBits() !=
2415 Input.ConstraintVT.getSizeInBits())) {
2416 weightSum = -1; // Can't match.
2421 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2426 weightSum += weight;
2429 if (weightSum > bestWeight) {
2430 bestWeight = weightSum;
2431 bestMAIndex = maIndex;
2435 // Now select chosen alternative in each constraint.
2436 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2437 cIndex != eIndex; ++cIndex) {
2438 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2439 if (cInfo.Type == InlineAsm::isClobber)
2441 cInfo.selectAlternative(bestMAIndex);
2446 // Check and hook up tied operands, choose constraint code to use.
2447 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2448 cIndex != eIndex; ++cIndex) {
2449 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2451 // If this is an output operand with a matching input operand, look up the
2452 // matching input. If their types mismatch, e.g. one is an integer, the
2453 // other is floating point, or their sizes are different, flag it as an
2455 if (OpInfo.hasMatchingInput()) {
2456 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2458 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2459 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2460 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
2461 OpInfo.ConstraintVT);
2462 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2463 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
2464 Input.ConstraintVT);
2465 if ((OpInfo.ConstraintVT.isInteger() !=
2466 Input.ConstraintVT.isInteger()) ||
2467 (MatchRC.second != InputRC.second)) {
2468 report_fatal_error("Unsupported asm: input constraint"
2469 " with a matching output constraint of"
2470 " incompatible type!");
2477 return ConstraintOperands;
2481 /// getConstraintGenerality - Return an integer indicating how general CT
2483 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2485 case TargetLowering::C_Other:
2486 case TargetLowering::C_Unknown:
2488 case TargetLowering::C_Register:
2490 case TargetLowering::C_RegisterClass:
2492 case TargetLowering::C_Memory:
2495 llvm_unreachable("Invalid constraint type");
2498 /// Examine constraint type and operand type and determine a weight value.
2499 /// This object must already have been set up with the operand type
2500 /// and the current alternative constraint selected.
2501 TargetLowering::ConstraintWeight
2502 TargetLowering::getMultipleConstraintMatchWeight(
2503 AsmOperandInfo &info, int maIndex) const {
2504 InlineAsm::ConstraintCodeVector *rCodes;
2505 if (maIndex >= (int)info.multipleAlternatives.size())
2506 rCodes = &info.Codes;
2508 rCodes = &info.multipleAlternatives[maIndex].Codes;
2509 ConstraintWeight BestWeight = CW_Invalid;
2511 // Loop over the options, keeping track of the most general one.
2512 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2513 ConstraintWeight weight =
2514 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2515 if (weight > BestWeight)
2516 BestWeight = weight;
2522 /// Examine constraint type and operand type and determine a weight value.
2523 /// This object must already have been set up with the operand type
2524 /// and the current alternative constraint selected.
2525 TargetLowering::ConstraintWeight
2526 TargetLowering::getSingleConstraintMatchWeight(
2527 AsmOperandInfo &info, const char *constraint) const {
2528 ConstraintWeight weight = CW_Invalid;
2529 Value *CallOperandVal = info.CallOperandVal;
2530 // If we don't have a value, we can't do a match,
2531 // but allow it at the lowest weight.
2532 if (!CallOperandVal)
2534 // Look at the constraint type.
2535 switch (*constraint) {
2536 case 'i': // immediate integer.
2537 case 'n': // immediate integer with a known value.
2538 if (isa<ConstantInt>(CallOperandVal))
2539 weight = CW_Constant;
2541 case 's': // non-explicit intregal immediate.
2542 if (isa<GlobalValue>(CallOperandVal))
2543 weight = CW_Constant;
2545 case 'E': // immediate float if host format.
2546 case 'F': // immediate float.
2547 if (isa<ConstantFP>(CallOperandVal))
2548 weight = CW_Constant;
2550 case '<': // memory operand with autodecrement.
2551 case '>': // memory operand with autoincrement.
2552 case 'm': // memory operand.
2553 case 'o': // offsettable memory operand
2554 case 'V': // non-offsettable memory operand
2557 case 'r': // general register.
2558 case 'g': // general register, memory operand or immediate integer.
2559 // note: Clang converts "g" to "imr".
2560 if (CallOperandVal->getType()->isIntegerTy())
2561 weight = CW_Register;
2563 case 'X': // any operand.
2565 weight = CW_Default;
2571 /// ChooseConstraint - If there are multiple different constraints that we
2572 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2573 /// This is somewhat tricky: constraints fall into four classes:
2574 /// Other -> immediates and magic values
2575 /// Register -> one specific register
2576 /// RegisterClass -> a group of regs
2577 /// Memory -> memory
2578 /// Ideally, we would pick the most specific constraint possible: if we have
2579 /// something that fits into a register, we would pick it. The problem here
2580 /// is that if we have something that could either be in a register or in
2581 /// memory that use of the register could cause selection of *other*
2582 /// operands to fail: they might only succeed if we pick memory. Because of
2583 /// this the heuristic we use is:
2585 /// 1) If there is an 'other' constraint, and if the operand is valid for
2586 /// that constraint, use it. This makes us take advantage of 'i'
2587 /// constraints when available.
2588 /// 2) Otherwise, pick the most general constraint present. This prefers
2589 /// 'm' over 'r', for example.
2591 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2592 const TargetLowering &TLI,
2593 SDValue Op, SelectionDAG *DAG) {
2594 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2595 unsigned BestIdx = 0;
2596 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2597 int BestGenerality = -1;
2599 // Loop over the options, keeping track of the most general one.
2600 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2601 TargetLowering::ConstraintType CType =
2602 TLI.getConstraintType(OpInfo.Codes[i]);
2604 // If this is an 'other' constraint, see if the operand is valid for it.
2605 // For example, on X86 we might have an 'rI' constraint. If the operand
2606 // is an integer in the range [0..31] we want to use I (saving a load
2607 // of a register), otherwise we must use 'r'.
2608 if (CType == TargetLowering::C_Other && Op.getNode()) {
2609 assert(OpInfo.Codes[i].size() == 1 &&
2610 "Unhandled multi-letter 'other' constraint");
2611 std::vector<SDValue> ResultOps;
2612 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2614 if (!ResultOps.empty()) {
2621 // Things with matching constraints can only be registers, per gcc
2622 // documentation. This mainly affects "g" constraints.
2623 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2626 // This constraint letter is more general than the previous one, use it.
2627 int Generality = getConstraintGenerality(CType);
2628 if (Generality > BestGenerality) {
2631 BestGenerality = Generality;
2635 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2636 OpInfo.ConstraintType = BestType;
2639 /// ComputeConstraintToUse - Determines the constraint code and constraint
2640 /// type to use for the specific AsmOperandInfo, setting
2641 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2642 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2644 SelectionDAG *DAG) const {
2645 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2647 // Single-letter constraints ('r') are very common.
2648 if (OpInfo.Codes.size() == 1) {
2649 OpInfo.ConstraintCode = OpInfo.Codes[0];
2650 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2652 ChooseConstraint(OpInfo, *this, Op, DAG);
2655 // 'X' matches anything.
2656 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2657 // Labels and constants are handled elsewhere ('X' is the only thing
2658 // that matches labels). For Functions, the type here is the type of
2659 // the result, which is not what we want to look at; leave them alone.
2660 Value *v = OpInfo.CallOperandVal;
2661 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2662 OpInfo.CallOperandVal = v;
2666 // Otherwise, try to resolve it to something we know about by looking at
2667 // the actual operand type.
2668 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2669 OpInfo.ConstraintCode = Repl;
2670 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2675 /// \brief Given an exact SDIV by a constant, create a multiplication
2676 /// with the multiplicative inverse of the constant.
2677 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2678 SelectionDAG &DAG) const {
2679 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2680 APInt d = C->getAPIntValue();
2681 assert(d != 0 && "Division by zero!");
2683 // Shift the value upfront if it is even, so the LSB is one.
2684 unsigned ShAmt = d.countTrailingZeros();
2686 // TODO: For UDIV use SRL instead of SRA.
2688 DAG.getConstant(ShAmt, dl, getShiftAmountTy(Op1.getValueType()));
2690 Flags.setExact(true);
2691 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
2695 // Calculate the multiplicative inverse, using Newton's method.
2697 while ((t = d*xn) != 1)
2698 xn *= APInt(d.getBitWidth(), 2) - t;
2700 Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
2701 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2704 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2705 /// return a DAG expression to select that will generate the same value by
2706 /// multiplying by a magic number.
2707 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2708 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2709 SelectionDAG &DAG, bool IsAfterLegalization,
2710 std::vector<SDNode *> *Created) const {
2711 assert(Created && "No vector to hold sdiv ops.");
2713 EVT VT = N->getValueType(0);
2716 // Check to see if we can do this.
2717 // FIXME: We should be more aggressive here.
2718 if (!isTypeLegal(VT))
2721 APInt::ms magics = Divisor.magic();
2723 // Multiply the numerator (operand 0) by the magic value
2724 // FIXME: We should support doing a MUL in a wider type
2726 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2727 isOperationLegalOrCustom(ISD::MULHS, VT))
2728 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2729 DAG.getConstant(magics.m, dl, VT));
2730 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2731 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2732 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2734 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2736 return SDValue(); // No mulhs or equvialent
2737 // If d > 0 and m < 0, add the numerator
2738 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2739 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2740 Created->push_back(Q.getNode());
2742 // If d < 0 and m > 0, subtract the numerator.
2743 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2744 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2745 Created->push_back(Q.getNode());
2747 // Shift right algebraic if shift value is nonzero
2749 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2750 DAG.getConstant(magics.s, dl,
2751 getShiftAmountTy(Q.getValueType())));
2752 Created->push_back(Q.getNode());
2754 // Extract the sign bit and add it to the quotient
2755 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2756 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
2757 getShiftAmountTy(Q.getValueType())));
2758 Created->push_back(T.getNode());
2759 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2762 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2763 /// return a DAG expression to select that will generate the same value by
2764 /// multiplying by a magic number.
2765 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2766 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2767 SelectionDAG &DAG, bool IsAfterLegalization,
2768 std::vector<SDNode *> *Created) const {
2769 assert(Created && "No vector to hold udiv ops.");
2771 EVT VT = N->getValueType(0);
2774 // Check to see if we can do this.
2775 // FIXME: We should be more aggressive here.
2776 if (!isTypeLegal(VT))
2779 // FIXME: We should use a narrower constant when the upper
2780 // bits are known to be zero.
2781 APInt::mu magics = Divisor.magicu();
2783 SDValue Q = N->getOperand(0);
2785 // If the divisor is even, we can avoid using the expensive fixup by shifting
2786 // the divided value upfront.
2787 if (magics.a != 0 && !Divisor[0]) {
2788 unsigned Shift = Divisor.countTrailingZeros();
2789 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2790 DAG.getConstant(Shift, dl,
2791 getShiftAmountTy(Q.getValueType())));
2792 Created->push_back(Q.getNode());
2794 // Get magic number for the shifted divisor.
2795 magics = Divisor.lshr(Shift).magicu(Shift);
2796 assert(magics.a == 0 && "Should use cheap fixup now");
2799 // Multiply the numerator (operand 0) by the magic value
2800 // FIXME: We should support doing a MUL in a wider type
2801 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2802 isOperationLegalOrCustom(ISD::MULHU, VT))
2803 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
2804 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2805 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2806 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2807 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2809 return SDValue(); // No mulhu or equvialent
2811 Created->push_back(Q.getNode());
2813 if (magics.a == 0) {
2814 assert(magics.s < Divisor.getBitWidth() &&
2815 "We shouldn't generate an undefined shift!");
2816 return DAG.getNode(ISD::SRL, dl, VT, Q,
2817 DAG.getConstant(magics.s, dl,
2818 getShiftAmountTy(Q.getValueType())));
2820 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2821 Created->push_back(NPQ.getNode());
2822 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2823 DAG.getConstant(1, dl,
2824 getShiftAmountTy(NPQ.getValueType())));
2825 Created->push_back(NPQ.getNode());
2826 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2827 Created->push_back(NPQ.getNode());
2828 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2829 DAG.getConstant(magics.s - 1, dl,
2830 getShiftAmountTy(NPQ.getValueType())));
2834 bool TargetLowering::
2835 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2836 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2837 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2838 "be a constant integer");
2845 //===----------------------------------------------------------------------===//
2846 // Legalization Utilities
2847 //===----------------------------------------------------------------------===//
2849 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2850 SelectionDAG &DAG, SDValue LL, SDValue LH,
2851 SDValue RL, SDValue RH) const {
2852 EVT VT = N->getValueType(0);
2855 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2856 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2857 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2858 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2859 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2860 unsigned OuterBitSize = VT.getSizeInBits();
2861 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2862 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2863 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2865 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2866 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2867 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2869 if (!LL.getNode() && !RL.getNode() &&
2870 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2871 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2872 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2878 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2879 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2880 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2881 // The inputs are both zero-extended.
2883 // We can emit a umul_lohi.
2884 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2886 Hi = SDValue(Lo.getNode(), 1);
2890 // We can emit a mulhu+mul.
2891 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2892 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2896 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2897 // The input values are both sign-extended.
2899 // We can emit a smul_lohi.
2900 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2902 Hi = SDValue(Lo.getNode(), 1);
2906 // We can emit a mulhs+mul.
2907 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2908 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2913 if (!LH.getNode() && !RH.getNode() &&
2914 isOperationLegalOrCustom(ISD::SRL, VT) &&
2915 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2916 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2917 SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT));
2918 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2919 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2920 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2921 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2928 // Lo,Hi = umul LHS, RHS.
2929 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2930 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2932 Hi = UMulLOHI.getValue(1);
2933 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2934 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2935 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2936 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2940 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2941 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2942 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2943 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2944 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2945 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2952 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2953 SelectionDAG &DAG) const {
2954 EVT VT = Node->getOperand(0).getValueType();
2955 EVT NVT = Node->getValueType(0);
2956 SDLoc dl(SDValue(Node, 0));
2958 // FIXME: Only f32 to i64 conversions are supported.
2959 if (VT != MVT::f32 || NVT != MVT::i64)
2962 // Expand f32 -> i64 conversion
2963 // This algorithm comes from compiler-rt's implementation of fixsfdi:
2964 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2965 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2966 VT.getSizeInBits());
2967 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
2968 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
2969 SDValue Bias = DAG.getConstant(127, dl, IntVT);
2970 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
2972 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
2973 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
2975 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2977 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2978 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2979 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2980 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2982 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2983 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2984 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2985 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2987 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2988 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2989 DAG.getConstant(0x00800000, dl, IntVT));
2991 R = DAG.getZExtOrTrunc(R, dl, NVT);
2994 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2995 DAG.getNode(ISD::SHL, dl, NVT, R,
2997 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2998 dl, getShiftAmountTy(IntVT))),
2999 DAG.getNode(ISD::SRL, dl, NVT, R,
3001 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3002 dl, getShiftAmountTy(IntVT))),
3005 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3006 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3009 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
3010 DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);