1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtarget.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
34 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
45 return TLSModel::GeneralDynamic;
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
50 return TLSModel::InitialExec;
55 /// InitLibcallNames - Set default libcall names.
57 static void InitLibcallNames(const char **Names) {
58 Names[RTLIB::SHL_I16] = "__ashlhi3";
59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
61 Names[RTLIB::SHL_I128] = "__ashlti3";
62 Names[RTLIB::SRL_I16] = "__lshrhi3";
63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
65 Names[RTLIB::SRL_I128] = "__lshrti3";
66 Names[RTLIB::SRA_I16] = "__ashrhi3";
67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
69 Names[RTLIB::SRA_I128] = "__ashrti3";
70 Names[RTLIB::MUL_I8] = "__mulqi3";
71 Names[RTLIB::MUL_I16] = "__mulhi3";
72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
74 Names[RTLIB::MUL_I128] = "__multi3";
75 Names[RTLIB::SDIV_I8] = "__divqi3";
76 Names[RTLIB::SDIV_I16] = "__divhi3";
77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
79 Names[RTLIB::SDIV_I128] = "__divti3";
80 Names[RTLIB::UDIV_I8] = "__udivqi3";
81 Names[RTLIB::UDIV_I16] = "__udivhi3";
82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
84 Names[RTLIB::UDIV_I128] = "__udivti3";
85 Names[RTLIB::SREM_I8] = "__modqi3";
86 Names[RTLIB::SREM_I16] = "__modhi3";
87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
89 Names[RTLIB::SREM_I128] = "__modti3";
90 Names[RTLIB::UREM_I8] = "__umodqi3";
91 Names[RTLIB::UREM_I16] = "__umodhi3";
92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
94 Names[RTLIB::UREM_I128] = "__umodti3";
95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
99 Names[RTLIB::ADD_F80] = "__addxf3";
100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
103 Names[RTLIB::SUB_F80] = "__subxf3";
104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
107 Names[RTLIB::MUL_F80] = "__mulxf3";
108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
111 Names[RTLIB::DIV_F80] = "__divxf3";
112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
115 Names[RTLIB::REM_F80] = "fmodl";
116 Names[RTLIB::REM_PPCF128] = "fmodl";
117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
177 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
178 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
179 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
180 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
181 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
182 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
183 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
184 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
185 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
186 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
187 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
188 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
189 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
190 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
191 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
192 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
193 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
194 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
195 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
196 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
197 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
198 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
199 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
200 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
201 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
202 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
203 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
204 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
205 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
206 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
207 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
208 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
209 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
210 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
211 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
212 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
213 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
214 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
215 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
216 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
217 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
218 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
219 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
220 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
221 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
222 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
223 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
224 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
225 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
226 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
227 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
228 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
229 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
230 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
231 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
232 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
233 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
234 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
235 Names[RTLIB::OEQ_F32] = "__eqsf2";
236 Names[RTLIB::OEQ_F64] = "__eqdf2";
237 Names[RTLIB::UNE_F32] = "__nesf2";
238 Names[RTLIB::UNE_F64] = "__nedf2";
239 Names[RTLIB::OGE_F32] = "__gesf2";
240 Names[RTLIB::OGE_F64] = "__gedf2";
241 Names[RTLIB::OLT_F32] = "__ltsf2";
242 Names[RTLIB::OLT_F64] = "__ltdf2";
243 Names[RTLIB::OLE_F32] = "__lesf2";
244 Names[RTLIB::OLE_F64] = "__ledf2";
245 Names[RTLIB::OGT_F32] = "__gtsf2";
246 Names[RTLIB::OGT_F64] = "__gtdf2";
247 Names[RTLIB::UO_F32] = "__unordsf2";
248 Names[RTLIB::UO_F64] = "__unorddf2";
249 Names[RTLIB::O_F32] = "__unordsf2";
250 Names[RTLIB::O_F64] = "__unorddf2";
251 Names[RTLIB::MEMCPY] = "memcpy";
252 Names[RTLIB::MEMMOVE] = "memmove";
253 Names[RTLIB::MEMSET] = "memset";
254 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
257 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
259 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
260 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
261 CCs[i] = CallingConv::C;
265 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
266 /// UNKNOWN_LIBCALL if there is none.
267 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
268 if (OpVT == MVT::f32) {
269 if (RetVT == MVT::f64)
270 return FPEXT_F32_F64;
272 return UNKNOWN_LIBCALL;
275 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
276 /// UNKNOWN_LIBCALL if there is none.
277 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
278 if (RetVT == MVT::f32) {
279 if (OpVT == MVT::f64)
280 return FPROUND_F64_F32;
281 if (OpVT == MVT::f80)
282 return FPROUND_F80_F32;
283 if (OpVT == MVT::ppcf128)
284 return FPROUND_PPCF128_F32;
285 } else if (RetVT == MVT::f64) {
286 if (OpVT == MVT::f80)
287 return FPROUND_F80_F64;
288 if (OpVT == MVT::ppcf128)
289 return FPROUND_PPCF128_F64;
291 return UNKNOWN_LIBCALL;
294 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
295 /// UNKNOWN_LIBCALL if there is none.
296 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
297 if (OpVT == MVT::f32) {
298 if (RetVT == MVT::i8)
299 return FPTOSINT_F32_I8;
300 if (RetVT == MVT::i16)
301 return FPTOSINT_F32_I16;
302 if (RetVT == MVT::i32)
303 return FPTOSINT_F32_I32;
304 if (RetVT == MVT::i64)
305 return FPTOSINT_F32_I64;
306 if (RetVT == MVT::i128)
307 return FPTOSINT_F32_I128;
308 } else if (OpVT == MVT::f64) {
309 if (RetVT == MVT::i32)
310 return FPTOSINT_F64_I32;
311 if (RetVT == MVT::i64)
312 return FPTOSINT_F64_I64;
313 if (RetVT == MVT::i128)
314 return FPTOSINT_F64_I128;
315 } else if (OpVT == MVT::f80) {
316 if (RetVT == MVT::i32)
317 return FPTOSINT_F80_I32;
318 if (RetVT == MVT::i64)
319 return FPTOSINT_F80_I64;
320 if (RetVT == MVT::i128)
321 return FPTOSINT_F80_I128;
322 } else if (OpVT == MVT::ppcf128) {
323 if (RetVT == MVT::i32)
324 return FPTOSINT_PPCF128_I32;
325 if (RetVT == MVT::i64)
326 return FPTOSINT_PPCF128_I64;
327 if (RetVT == MVT::i128)
328 return FPTOSINT_PPCF128_I128;
330 return UNKNOWN_LIBCALL;
333 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
334 /// UNKNOWN_LIBCALL if there is none.
335 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
336 if (OpVT == MVT::f32) {
337 if (RetVT == MVT::i8)
338 return FPTOUINT_F32_I8;
339 if (RetVT == MVT::i16)
340 return FPTOUINT_F32_I16;
341 if (RetVT == MVT::i32)
342 return FPTOUINT_F32_I32;
343 if (RetVT == MVT::i64)
344 return FPTOUINT_F32_I64;
345 if (RetVT == MVT::i128)
346 return FPTOUINT_F32_I128;
347 } else if (OpVT == MVT::f64) {
348 if (RetVT == MVT::i32)
349 return FPTOUINT_F64_I32;
350 if (RetVT == MVT::i64)
351 return FPTOUINT_F64_I64;
352 if (RetVT == MVT::i128)
353 return FPTOUINT_F64_I128;
354 } else if (OpVT == MVT::f80) {
355 if (RetVT == MVT::i32)
356 return FPTOUINT_F80_I32;
357 if (RetVT == MVT::i64)
358 return FPTOUINT_F80_I64;
359 if (RetVT == MVT::i128)
360 return FPTOUINT_F80_I128;
361 } else if (OpVT == MVT::ppcf128) {
362 if (RetVT == MVT::i32)
363 return FPTOUINT_PPCF128_I32;
364 if (RetVT == MVT::i64)
365 return FPTOUINT_PPCF128_I64;
366 if (RetVT == MVT::i128)
367 return FPTOUINT_PPCF128_I128;
369 return UNKNOWN_LIBCALL;
372 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
373 /// UNKNOWN_LIBCALL if there is none.
374 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
375 if (OpVT == MVT::i32) {
376 if (RetVT == MVT::f32)
377 return SINTTOFP_I32_F32;
378 else if (RetVT == MVT::f64)
379 return SINTTOFP_I32_F64;
380 else if (RetVT == MVT::f80)
381 return SINTTOFP_I32_F80;
382 else if (RetVT == MVT::ppcf128)
383 return SINTTOFP_I32_PPCF128;
384 } else if (OpVT == MVT::i64) {
385 if (RetVT == MVT::f32)
386 return SINTTOFP_I64_F32;
387 else if (RetVT == MVT::f64)
388 return SINTTOFP_I64_F64;
389 else if (RetVT == MVT::f80)
390 return SINTTOFP_I64_F80;
391 else if (RetVT == MVT::ppcf128)
392 return SINTTOFP_I64_PPCF128;
393 } else if (OpVT == MVT::i128) {
394 if (RetVT == MVT::f32)
395 return SINTTOFP_I128_F32;
396 else if (RetVT == MVT::f64)
397 return SINTTOFP_I128_F64;
398 else if (RetVT == MVT::f80)
399 return SINTTOFP_I128_F80;
400 else if (RetVT == MVT::ppcf128)
401 return SINTTOFP_I128_PPCF128;
403 return UNKNOWN_LIBCALL;
406 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
407 /// UNKNOWN_LIBCALL if there is none.
408 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
409 if (OpVT == MVT::i32) {
410 if (RetVT == MVT::f32)
411 return UINTTOFP_I32_F32;
412 else if (RetVT == MVT::f64)
413 return UINTTOFP_I32_F64;
414 else if (RetVT == MVT::f80)
415 return UINTTOFP_I32_F80;
416 else if (RetVT == MVT::ppcf128)
417 return UINTTOFP_I32_PPCF128;
418 } else if (OpVT == MVT::i64) {
419 if (RetVT == MVT::f32)
420 return UINTTOFP_I64_F32;
421 else if (RetVT == MVT::f64)
422 return UINTTOFP_I64_F64;
423 else if (RetVT == MVT::f80)
424 return UINTTOFP_I64_F80;
425 else if (RetVT == MVT::ppcf128)
426 return UINTTOFP_I64_PPCF128;
427 } else if (OpVT == MVT::i128) {
428 if (RetVT == MVT::f32)
429 return UINTTOFP_I128_F32;
430 else if (RetVT == MVT::f64)
431 return UINTTOFP_I128_F64;
432 else if (RetVT == MVT::f80)
433 return UINTTOFP_I128_F80;
434 else if (RetVT == MVT::ppcf128)
435 return UINTTOFP_I128_PPCF128;
437 return UNKNOWN_LIBCALL;
440 /// InitCmpLibcallCCs - Set default comparison libcall CC.
442 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
443 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
444 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
445 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
446 CCs[RTLIB::UNE_F32] = ISD::SETNE;
447 CCs[RTLIB::UNE_F64] = ISD::SETNE;
448 CCs[RTLIB::OGE_F32] = ISD::SETGE;
449 CCs[RTLIB::OGE_F64] = ISD::SETGE;
450 CCs[RTLIB::OLT_F32] = ISD::SETLT;
451 CCs[RTLIB::OLT_F64] = ISD::SETLT;
452 CCs[RTLIB::OLE_F32] = ISD::SETLE;
453 CCs[RTLIB::OLE_F64] = ISD::SETLE;
454 CCs[RTLIB::OGT_F32] = ISD::SETGT;
455 CCs[RTLIB::OGT_F64] = ISD::SETGT;
456 CCs[RTLIB::UO_F32] = ISD::SETNE;
457 CCs[RTLIB::UO_F64] = ISD::SETNE;
458 CCs[RTLIB::O_F32] = ISD::SETEQ;
459 CCs[RTLIB::O_F64] = ISD::SETEQ;
462 /// NOTE: The constructor takes ownership of TLOF.
463 TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
464 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
465 // All operations default to being supported.
466 memset(OpActions, 0, sizeof(OpActions));
467 memset(LoadExtActions, 0, sizeof(LoadExtActions));
468 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
469 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
470 memset(ConvertActions, 0, sizeof(ConvertActions));
471 memset(CondCodeActions, 0, sizeof(CondCodeActions));
473 // Set default actions for various operations.
474 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
475 // Default all indexed load / store to expand.
476 for (unsigned IM = (unsigned)ISD::PRE_INC;
477 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
478 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
479 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
482 // These operations default to expand.
483 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
484 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
487 // Most targets ignore the @llvm.prefetch intrinsic.
488 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
490 // ConstantFP nodes default to expand. Targets can either change this to
491 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
492 // to optimize expansions for certain constants.
493 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
494 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
495 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
497 // These library functions default to expand.
498 setOperationAction(ISD::FLOG , MVT::f64, Expand);
499 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
500 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
501 setOperationAction(ISD::FEXP , MVT::f64, Expand);
502 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
503 setOperationAction(ISD::FLOG , MVT::f32, Expand);
504 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
505 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
506 setOperationAction(ISD::FEXP , MVT::f32, Expand);
507 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
509 // Default ISD::TRAP to expand (which turns it into abort).
510 setOperationAction(ISD::TRAP, MVT::Other, Expand);
512 IsLittleEndian = TD->isLittleEndian();
513 UsesGlobalOffsetTable = false;
514 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
515 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
516 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
517 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
518 benefitFromCodePlacementOpt = false;
519 UseUnderscoreSetJmp = false;
520 UseUnderscoreLongJmp = false;
521 SelectIsExpensive = false;
522 IntDivIsCheap = false;
523 Pow2DivIsCheap = false;
524 StackPointerRegisterToSaveRestore = 0;
525 ExceptionPointerRegister = 0;
526 ExceptionSelectorRegister = 0;
527 BooleanContents = UndefinedBooleanContent;
528 SchedPreferenceInfo = SchedulingForLatency;
530 JumpBufAlignment = 0;
531 IfCvtBlockSizeLimit = 2;
532 IfCvtDupBlockSizeLimit = 0;
533 PrefLoopAlignment = 0;
535 InitLibcallNames(LibcallRoutineNames);
536 InitCmpLibcallCCs(CmpLibcallCCs);
537 InitLibcallCallingConvs(LibcallCallingConvs);
540 TargetLowering::~TargetLowering() {
544 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
545 unsigned &NumIntermediates,
547 TargetLowering* TLI) {
548 // Figure out the right, legal destination reg to copy into.
549 unsigned NumElts = VT.getVectorNumElements();
550 MVT EltTy = VT.getVectorElementType();
552 unsigned NumVectorRegs = 1;
554 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
555 // could break down into LHS/RHS like LegalizeDAG does.
556 if (!isPowerOf2_32(NumElts)) {
557 NumVectorRegs = NumElts;
561 // Divide the input until we get to a supported size. This will always
562 // end with a scalar if the target doesn't support vectors.
563 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
568 NumIntermediates = NumVectorRegs;
570 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
571 if (!TLI->isTypeLegal(NewVT))
573 IntermediateVT = NewVT;
575 EVT DestVT = TLI->getRegisterType(NewVT);
577 if (EVT(DestVT).bitsLT(NewVT)) {
578 // Value is expanded, e.g. i64 -> i16.
579 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
581 // Otherwise, promotion or legal types use the same number of registers as
582 // the vector decimated to the appropriate level.
583 return NumVectorRegs;
589 /// computeRegisterProperties - Once all of the register classes are added,
590 /// this allows us to compute derived properties we expose.
591 void TargetLowering::computeRegisterProperties() {
592 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
593 "Too many value types for ValueTypeActions to hold!");
595 // Everything defaults to needing one register.
596 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
597 NumRegistersForVT[i] = 1;
598 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
600 // ...except isVoid, which doesn't need any registers.
601 NumRegistersForVT[MVT::isVoid] = 0;
603 // Find the largest integer register class.
604 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
605 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
606 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
608 // Every integer value type larger than this largest register takes twice as
609 // many registers to represent as the previous ValueType.
610 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
611 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
612 if (!ExpandedVT.isInteger())
614 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
615 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
616 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
617 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
620 // Inspect all of the ValueType's smaller than the largest integer
621 // register to see which ones need promotion.
622 unsigned LegalIntReg = LargestIntReg;
623 for (unsigned IntReg = LargestIntReg - 1;
624 IntReg >= (unsigned)MVT::i1; --IntReg) {
625 EVT IVT = (MVT::SimpleValueType)IntReg;
626 if (isTypeLegal(IVT)) {
627 LegalIntReg = IntReg;
629 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
630 (MVT::SimpleValueType)LegalIntReg;
631 ValueTypeActions.setTypeAction(IVT, Promote);
635 // ppcf128 type is really two f64's.
636 if (!isTypeLegal(MVT::ppcf128)) {
637 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
638 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
639 TransformToType[MVT::ppcf128] = MVT::f64;
640 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
643 // Decide how to handle f64. If the target does not have native f64 support,
644 // expand it to i64 and we will be generating soft float library calls.
645 if (!isTypeLegal(MVT::f64)) {
646 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
647 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
648 TransformToType[MVT::f64] = MVT::i64;
649 ValueTypeActions.setTypeAction(MVT::f64, Expand);
652 // Decide how to handle f32. If the target does not have native support for
653 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
654 if (!isTypeLegal(MVT::f32)) {
655 if (isTypeLegal(MVT::f64)) {
656 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
657 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
658 TransformToType[MVT::f32] = MVT::f64;
659 ValueTypeActions.setTypeAction(MVT::f32, Promote);
661 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
662 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
663 TransformToType[MVT::f32] = MVT::i32;
664 ValueTypeActions.setTypeAction(MVT::f32, Expand);
668 // Loop over all of the vector value types to see which need transformations.
669 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
670 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
671 MVT VT = (MVT::SimpleValueType)i;
672 if (!isTypeLegal(VT)) {
675 unsigned NumIntermediates;
676 NumRegistersForVT[i] =
677 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
679 RegisterTypeForVT[i] = RegisterVT;
681 // Determine if there is a legal wider type.
682 bool IsLegalWiderType = false;
683 EVT EltVT = VT.getVectorElementType();
684 unsigned NElts = VT.getVectorNumElements();
685 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
686 EVT SVT = (MVT::SimpleValueType)nVT;
687 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
688 SVT.getVectorNumElements() > NElts && NElts != 1) {
689 TransformToType[i] = SVT;
690 ValueTypeActions.setTypeAction(VT, Promote);
691 IsLegalWiderType = true;
695 if (!IsLegalWiderType) {
696 EVT NVT = VT.getPow2VectorType();
698 // Type is already a power of 2. The default action is to split.
699 TransformToType[i] = MVT::Other;
700 ValueTypeActions.setTypeAction(VT, Expand);
702 TransformToType[i] = NVT;
703 ValueTypeActions.setTypeAction(VT, Promote);
710 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
715 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
716 return PointerTy.SimpleTy;
719 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
720 return MVT::i32; // return the default value
723 /// getVectorTypeBreakdown - Vector types are broken down into some number of
724 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
725 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
726 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
728 /// This method returns the number of registers needed, and the VT for each
729 /// register. It also returns the VT and quantity of the intermediate values
730 /// before they are promoted/expanded.
732 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
734 unsigned &NumIntermediates,
735 EVT &RegisterVT) const {
736 // Figure out the right, legal destination reg to copy into.
737 unsigned NumElts = VT.getVectorNumElements();
738 EVT EltTy = VT.getVectorElementType();
740 unsigned NumVectorRegs = 1;
742 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
743 // could break down into LHS/RHS like LegalizeDAG does.
744 if (!isPowerOf2_32(NumElts)) {
745 NumVectorRegs = NumElts;
749 // Divide the input until we get to a supported size. This will always
750 // end with a scalar if the target doesn't support vectors.
751 while (NumElts > 1 && !isTypeLegal(
752 EVT::getVectorVT(Context, EltTy, NumElts))) {
757 NumIntermediates = NumVectorRegs;
759 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
760 if (!isTypeLegal(NewVT))
762 IntermediateVT = NewVT;
764 EVT DestVT = getRegisterType(Context, NewVT);
766 if (DestVT.bitsLT(NewVT)) {
767 // Value is expanded, e.g. i64 -> i16.
768 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
770 // Otherwise, promotion or legal types use the same number of registers as
771 // the vector decimated to the appropriate level.
772 return NumVectorRegs;
778 /// getWidenVectorType: given a vector type, returns the type to widen to
779 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
780 /// If there is no vector type that we want to widen to, returns MVT::Other
781 /// When and where to widen is target dependent based on the cost of
782 /// scalarizing vs using the wider vector type.
783 EVT TargetLowering::getWidenVectorType(EVT VT) const {
784 assert(VT.isVector());
788 // Default is not to widen until moved to LegalizeTypes
792 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
793 /// function arguments in the caller parameter area. This is the actual
794 /// alignment, not its logarithm.
795 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
796 return TD->getCallFrameTypeAlignment(Ty);
799 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
800 /// current function. The returned value is a member of the
801 /// MachineJumpTableInfo::JTEntryKind enum.
802 unsigned TargetLowering::getJumpTableEncoding() const {
803 // In non-pic modes, just use the address of a block.
804 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
805 return MachineJumpTableInfo::EK_BlockAddress;
807 // In PIC mode, if the target supports a GPRel32 directive, use it.
808 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
809 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
811 // Otherwise, use a label difference.
812 return MachineJumpTableInfo::EK_LabelDifference32;
815 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
816 SelectionDAG &DAG) const {
817 // FIXME: Eliminate usesGlobalOffsetTable() in favor of JTEntryKind.
818 if (usesGlobalOffsetTable())
819 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
823 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
824 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
827 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
828 unsigned JTI,MCContext &Ctx) const{
829 // The normal PIC reloc base is the label at the start of the jump table.
830 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
834 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
835 // Assume that everything is safe in static mode.
836 if (getTargetMachine().getRelocationModel() == Reloc::Static)
839 // In dynamic-no-pic mode, assume that known defined values are safe.
840 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
842 !GA->getGlobal()->isDeclaration() &&
843 !GA->getGlobal()->isWeakForLinker())
846 // Otherwise assume nothing is safe.
850 //===----------------------------------------------------------------------===//
851 // Optimization Methods
852 //===----------------------------------------------------------------------===//
854 /// ShrinkDemandedConstant - Check to see if the specified operand of the
855 /// specified instruction is a constant integer. If so, check to see if there
856 /// are any bits set in the constant that are not demanded. If so, shrink the
857 /// constant and return true.
858 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
859 const APInt &Demanded) {
860 DebugLoc dl = Op.getDebugLoc();
862 // FIXME: ISD::SELECT, ISD::SELECT_CC
863 switch (Op.getOpcode()) {
868 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
869 if (!C) return false;
871 if (Op.getOpcode() == ISD::XOR &&
872 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
875 // if we can expand it to have all bits set, do it
876 if (C->getAPIntValue().intersects(~Demanded)) {
877 EVT VT = Op.getValueType();
878 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
879 DAG.getConstant(Demanded &
882 return CombineTo(Op, New);
892 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
893 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
894 /// cast, but it could be generalized for targets with other types of
895 /// implicit widening casts.
897 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
899 const APInt &Demanded,
901 assert(Op.getNumOperands() == 2 &&
902 "ShrinkDemandedOp only supports binary operators!");
903 assert(Op.getNode()->getNumValues() == 1 &&
904 "ShrinkDemandedOp only supports nodes with one result!");
906 // Don't do this if the node has another user, which may require the
908 if (!Op.getNode()->hasOneUse())
911 // Search for the smallest integer type with free casts to and from
912 // Op's type. For expedience, just check power-of-2 integer types.
913 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
914 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
915 if (!isPowerOf2_32(SmallVTBits))
916 SmallVTBits = NextPowerOf2(SmallVTBits);
917 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
918 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
919 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
920 TLI.isZExtFree(SmallVT, Op.getValueType())) {
921 // We found a type with free casts.
922 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
923 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
924 Op.getNode()->getOperand(0)),
925 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
926 Op.getNode()->getOperand(1)));
927 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
928 return CombineTo(Op, Z);
934 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
935 /// DemandedMask bits of the result of Op are ever used downstream. If we can
936 /// use this information to simplify Op, create a new simplified DAG node and
937 /// return true, returning the original and new nodes in Old and New. Otherwise,
938 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
939 /// the expression (used to simplify the caller). The KnownZero/One bits may
940 /// only be accurate for those bits in the DemandedMask.
941 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
942 const APInt &DemandedMask,
945 TargetLoweringOpt &TLO,
946 unsigned Depth) const {
947 unsigned BitWidth = DemandedMask.getBitWidth();
948 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
949 "Mask size mismatches value type size!");
950 APInt NewMask = DemandedMask;
951 DebugLoc dl = Op.getDebugLoc();
953 // Don't know anything.
954 KnownZero = KnownOne = APInt(BitWidth, 0);
956 // Other users may use these bits.
957 if (!Op.getNode()->hasOneUse()) {
959 // If not at the root, Just compute the KnownZero/KnownOne bits to
960 // simplify things downstream.
961 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
964 // If this is the root being simplified, allow it to have multiple uses,
965 // just set the NewMask to all bits.
966 NewMask = APInt::getAllOnesValue(BitWidth);
967 } else if (DemandedMask == 0) {
968 // Not demanding any bits from Op.
969 if (Op.getOpcode() != ISD::UNDEF)
970 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
972 } else if (Depth == 6) { // Limit search depth.
976 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
977 switch (Op.getOpcode()) {
979 // We know all of the bits for a constant!
980 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
981 KnownZero = ~KnownOne & NewMask;
982 return false; // Don't fall through, will infinitely loop.
984 // If the RHS is a constant, check to see if the LHS would be zero without
985 // using the bits from the RHS. Below, we use knowledge about the RHS to
986 // simplify the LHS, here we're using information from the LHS to simplify
988 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
989 APInt LHSZero, LHSOne;
990 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
991 LHSZero, LHSOne, Depth+1);
992 // If the LHS already has zeros where RHSC does, this and is dead.
993 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
994 return TLO.CombineTo(Op, Op.getOperand(0));
995 // If any of the set bits in the RHS are known zero on the LHS, shrink
997 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1001 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1002 KnownOne, TLO, Depth+1))
1004 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1005 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1006 KnownZero2, KnownOne2, TLO, Depth+1))
1008 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1010 // If all of the demanded bits are known one on one side, return the other.
1011 // These bits cannot contribute to the result of the 'and'.
1012 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1013 return TLO.CombineTo(Op, Op.getOperand(0));
1014 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1015 return TLO.CombineTo(Op, Op.getOperand(1));
1016 // If all of the demanded bits in the inputs are known zeros, return zero.
1017 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1018 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1019 // If the RHS is a constant, see if we can simplify it.
1020 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1022 // If the operation can be done in a smaller type, do so.
1023 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1026 // Output known-1 bits are only known if set in both the LHS & RHS.
1027 KnownOne &= KnownOne2;
1028 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1029 KnownZero |= KnownZero2;
1032 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1033 KnownOne, TLO, Depth+1))
1035 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1036 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1037 KnownZero2, KnownOne2, TLO, Depth+1))
1039 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1041 // If all of the demanded bits are known zero on one side, return the other.
1042 // These bits cannot contribute to the result of the 'or'.
1043 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1044 return TLO.CombineTo(Op, Op.getOperand(0));
1045 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1046 return TLO.CombineTo(Op, Op.getOperand(1));
1047 // If all of the potentially set bits on one side are known to be set on
1048 // the other side, just use the 'other' side.
1049 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1050 return TLO.CombineTo(Op, Op.getOperand(0));
1051 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1052 return TLO.CombineTo(Op, Op.getOperand(1));
1053 // If the RHS is a constant, see if we can simplify it.
1054 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1056 // If the operation can be done in a smaller type, do so.
1057 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1060 // Output known-0 bits are only known if clear in both the LHS & RHS.
1061 KnownZero &= KnownZero2;
1062 // Output known-1 are known to be set if set in either the LHS | RHS.
1063 KnownOne |= KnownOne2;
1066 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1067 KnownOne, TLO, Depth+1))
1069 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1070 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1071 KnownOne2, TLO, Depth+1))
1073 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1075 // If all of the demanded bits are known zero on one side, return the other.
1076 // These bits cannot contribute to the result of the 'xor'.
1077 if ((KnownZero & NewMask) == NewMask)
1078 return TLO.CombineTo(Op, Op.getOperand(0));
1079 if ((KnownZero2 & NewMask) == NewMask)
1080 return TLO.CombineTo(Op, Op.getOperand(1));
1081 // If the operation can be done in a smaller type, do so.
1082 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1085 // If all of the unknown bits are known to be zero on one side or the other
1086 // (but not both) turn this into an *inclusive* or.
1087 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1088 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1089 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1093 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1094 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1095 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1096 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1098 // If all of the demanded bits on one side are known, and all of the set
1099 // bits on that side are also known to be set on the other side, turn this
1100 // into an AND, as we know the bits will be cleared.
1101 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1102 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1103 if ((KnownOne & KnownOne2) == KnownOne) {
1104 EVT VT = Op.getValueType();
1105 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1106 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1107 Op.getOperand(0), ANDC));
1111 // If the RHS is a constant, see if we can simplify it.
1112 // for XOR, we prefer to force bits to 1 if they will make a -1.
1113 // if we can't force bits, try to shrink constant
1114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1115 APInt Expanded = C->getAPIntValue() | (~NewMask);
1116 // if we can expand it to have all bits set, do it
1117 if (Expanded.isAllOnesValue()) {
1118 if (Expanded != C->getAPIntValue()) {
1119 EVT VT = Op.getValueType();
1120 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1121 TLO.DAG.getConstant(Expanded, VT));
1122 return TLO.CombineTo(Op, New);
1124 // if it already has all the bits set, nothing to change
1125 // but don't shrink either!
1126 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1131 KnownZero = KnownZeroOut;
1132 KnownOne = KnownOneOut;
1135 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1136 KnownOne, TLO, Depth+1))
1138 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1139 KnownOne2, TLO, Depth+1))
1141 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1142 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1144 // If the operands are constants, see if we can simplify them.
1145 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1148 // Only known if known in both the LHS and RHS.
1149 KnownOne &= KnownOne2;
1150 KnownZero &= KnownZero2;
1152 case ISD::SELECT_CC:
1153 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1154 KnownOne, TLO, Depth+1))
1156 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1157 KnownOne2, TLO, Depth+1))
1159 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1160 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1162 // If the operands are constants, see if we can simplify them.
1163 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1166 // Only known if known in both the LHS and RHS.
1167 KnownOne &= KnownOne2;
1168 KnownZero &= KnownZero2;
1171 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1172 unsigned ShAmt = SA->getZExtValue();
1173 SDValue InOp = Op.getOperand(0);
1175 // If the shift count is an invalid immediate, don't do anything.
1176 if (ShAmt >= BitWidth)
1179 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1180 // single shift. We can do this if the bottom bits (which are shifted
1181 // out) are never demanded.
1182 if (InOp.getOpcode() == ISD::SRL &&
1183 isa<ConstantSDNode>(InOp.getOperand(1))) {
1184 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1185 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1186 unsigned Opc = ISD::SHL;
1187 int Diff = ShAmt-C1;
1194 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1195 EVT VT = Op.getValueType();
1196 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1197 InOp.getOperand(0), NewSA));
1201 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1202 KnownZero, KnownOne, TLO, Depth+1))
1204 KnownZero <<= SA->getZExtValue();
1205 KnownOne <<= SA->getZExtValue();
1206 // low bits known zero.
1207 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1211 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1212 EVT VT = Op.getValueType();
1213 unsigned ShAmt = SA->getZExtValue();
1214 unsigned VTSize = VT.getSizeInBits();
1215 SDValue InOp = Op.getOperand(0);
1217 // If the shift count is an invalid immediate, don't do anything.
1218 if (ShAmt >= BitWidth)
1221 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1222 // single shift. We can do this if the top bits (which are shifted out)
1223 // are never demanded.
1224 if (InOp.getOpcode() == ISD::SHL &&
1225 isa<ConstantSDNode>(InOp.getOperand(1))) {
1226 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1227 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1228 unsigned Opc = ISD::SRL;
1229 int Diff = ShAmt-C1;
1236 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1237 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1238 InOp.getOperand(0), NewSA));
1242 // Compute the new bits that are at the top now.
1243 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1244 KnownZero, KnownOne, TLO, Depth+1))
1246 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1247 KnownZero = KnownZero.lshr(ShAmt);
1248 KnownOne = KnownOne.lshr(ShAmt);
1250 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1251 KnownZero |= HighBits; // High bits known zero.
1255 // If this is an arithmetic shift right and only the low-bit is set, we can
1256 // always convert this into a logical shr, even if the shift amount is
1257 // variable. The low bit of the shift cannot be an input sign bit unless
1258 // the shift amount is >= the size of the datatype, which is undefined.
1259 if (DemandedMask == 1)
1260 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1261 Op.getOperand(0), Op.getOperand(1)));
1263 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1264 EVT VT = Op.getValueType();
1265 unsigned ShAmt = SA->getZExtValue();
1267 // If the shift count is an invalid immediate, don't do anything.
1268 if (ShAmt >= BitWidth)
1271 APInt InDemandedMask = (NewMask << ShAmt);
1273 // If any of the demanded bits are produced by the sign extension, we also
1274 // demand the input sign bit.
1275 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1276 if (HighBits.intersects(NewMask))
1277 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1279 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1280 KnownZero, KnownOne, TLO, Depth+1))
1282 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1283 KnownZero = KnownZero.lshr(ShAmt);
1284 KnownOne = KnownOne.lshr(ShAmt);
1286 // Handle the sign bit, adjusted to where it is now in the mask.
1287 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1289 // If the input sign bit is known to be zero, or if none of the top bits
1290 // are demanded, turn this into an unsigned shift right.
1291 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1292 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1295 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1296 KnownOne |= HighBits;
1300 case ISD::SIGN_EXTEND_INREG: {
1301 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1303 // Sign extension. Compute the demanded bits in the result that are not
1304 // present in the input.
1306 APInt::getHighBitsSet(BitWidth,
1307 BitWidth - EVT.getScalarType().getSizeInBits()) &
1310 // If none of the extended bits are demanded, eliminate the sextinreg.
1312 return TLO.CombineTo(Op, Op.getOperand(0));
1314 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
1315 InSignBit.zext(BitWidth);
1316 APInt InputDemandedBits =
1317 APInt::getLowBitsSet(BitWidth,
1318 EVT.getScalarType().getSizeInBits()) &
1321 // Since the sign extended bits are demanded, we know that the sign
1323 InputDemandedBits |= InSignBit;
1325 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1326 KnownZero, KnownOne, TLO, Depth+1))
1328 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1330 // If the sign bit of the input is known set or clear, then we know the
1331 // top bits of the result.
1333 // If the input sign bit is known zero, convert this into a zero extension.
1334 if (KnownZero.intersects(InSignBit))
1335 return TLO.CombineTo(Op,
1336 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1338 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1339 KnownOne |= NewBits;
1340 KnownZero &= ~NewBits;
1341 } else { // Input sign bit unknown
1342 KnownZero &= ~NewBits;
1343 KnownOne &= ~NewBits;
1347 case ISD::ZERO_EXTEND: {
1348 unsigned OperandBitWidth =
1349 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1350 APInt InMask = NewMask;
1351 InMask.trunc(OperandBitWidth);
1353 // If none of the top bits are demanded, convert this into an any_extend.
1355 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1356 if (!NewBits.intersects(NewMask))
1357 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1361 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1362 KnownZero, KnownOne, TLO, Depth+1))
1364 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1365 KnownZero.zext(BitWidth);
1366 KnownOne.zext(BitWidth);
1367 KnownZero |= NewBits;
1370 case ISD::SIGN_EXTEND: {
1371 EVT InVT = Op.getOperand(0).getValueType();
1372 unsigned InBits = InVT.getScalarType().getSizeInBits();
1373 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1374 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1375 APInt NewBits = ~InMask & NewMask;
1377 // If none of the top bits are demanded, convert this into an any_extend.
1379 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1383 // Since some of the sign extended bits are demanded, we know that the sign
1385 APInt InDemandedBits = InMask & NewMask;
1386 InDemandedBits |= InSignBit;
1387 InDemandedBits.trunc(InBits);
1389 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1390 KnownOne, TLO, Depth+1))
1392 KnownZero.zext(BitWidth);
1393 KnownOne.zext(BitWidth);
1395 // If the sign bit is known zero, convert this to a zero extend.
1396 if (KnownZero.intersects(InSignBit))
1397 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1401 // If the sign bit is known one, the top bits match.
1402 if (KnownOne.intersects(InSignBit)) {
1403 KnownOne |= NewBits;
1404 KnownZero &= ~NewBits;
1405 } else { // Otherwise, top bits aren't known.
1406 KnownOne &= ~NewBits;
1407 KnownZero &= ~NewBits;
1411 case ISD::ANY_EXTEND: {
1412 unsigned OperandBitWidth =
1413 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1414 APInt InMask = NewMask;
1415 InMask.trunc(OperandBitWidth);
1416 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1417 KnownZero, KnownOne, TLO, Depth+1))
1419 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1420 KnownZero.zext(BitWidth);
1421 KnownOne.zext(BitWidth);
1424 case ISD::TRUNCATE: {
1425 // Simplify the input, using demanded bit information, and compute the known
1426 // zero/one bits live out.
1427 APInt TruncMask = NewMask;
1428 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1429 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1430 KnownZero, KnownOne, TLO, Depth+1))
1432 KnownZero.trunc(BitWidth);
1433 KnownOne.trunc(BitWidth);
1435 // If the input is only used by this truncate, see if we can shrink it based
1436 // on the known demanded bits.
1437 if (Op.getOperand(0).getNode()->hasOneUse()) {
1438 SDValue In = Op.getOperand(0);
1439 unsigned InBitWidth = In.getValueSizeInBits();
1440 switch (In.getOpcode()) {
1443 // Shrink SRL by a constant if none of the high bits shifted in are
1445 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1446 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1447 InBitWidth - BitWidth);
1448 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1449 HighBits.trunc(BitWidth);
1451 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1452 // None of the shifted in bits are needed. Add a truncate of the
1453 // shift input, then shift it.
1454 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1457 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1467 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1470 case ISD::AssertZext: {
1471 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1472 APInt InMask = APInt::getLowBitsSet(BitWidth,
1473 VT.getSizeInBits());
1474 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1475 KnownZero, KnownOne, TLO, Depth+1))
1477 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1478 KnownZero |= ~InMask & NewMask;
1481 case ISD::BIT_CONVERT:
1483 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1484 // is demanded, turn this into a FGETSIGN.
1485 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1486 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1487 !MVT::isVector(Op.getOperand(0).getValueType())) {
1488 // Only do this xform if FGETSIGN is valid or if before legalize.
1489 if (!TLO.AfterLegalize ||
1490 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1491 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1492 // place. We expect the SHL to be eliminated by other optimizations.
1493 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1495 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1496 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1497 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1506 // Add, Sub, and Mul don't demand any bits in positions beyond that
1507 // of the highest bit demanded of them.
1508 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1509 BitWidth - NewMask.countLeadingZeros());
1510 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1511 KnownOne2, TLO, Depth+1))
1513 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1514 KnownOne2, TLO, Depth+1))
1516 // See if the operation should be performed at a smaller bit width.
1517 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1522 // Just use ComputeMaskedBits to compute output bits.
1523 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1527 // If we know the value of all of the demanded bits, return this as a
1529 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1530 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1535 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1536 /// in Mask are known to be either zero or one and return them in the
1537 /// KnownZero/KnownOne bitsets.
1538 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1542 const SelectionDAG &DAG,
1543 unsigned Depth) const {
1544 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1545 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1546 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1547 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1548 "Should use MaskedValueIsZero if you don't know whether Op"
1549 " is a target node!");
1550 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1553 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1554 /// targets that want to expose additional information about sign bits to the
1556 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1557 unsigned Depth) const {
1558 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1559 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1560 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1561 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1562 "Should use ComputeNumSignBits if you don't know whether Op"
1563 " is a target node!");
1567 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1568 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1569 /// determine which bit is set.
1571 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1572 // A left-shift of a constant one will have exactly one bit set, because
1573 // shifting the bit off the end is undefined.
1574 if (Val.getOpcode() == ISD::SHL)
1575 if (ConstantSDNode *C =
1576 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1577 if (C->getAPIntValue() == 1)
1580 // Similarly, a right-shift of a constant sign-bit will have exactly
1582 if (Val.getOpcode() == ISD::SRL)
1583 if (ConstantSDNode *C =
1584 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1585 if (C->getAPIntValue().isSignBit())
1588 // More could be done here, though the above checks are enough
1589 // to handle some common cases.
1591 // Fall back to ComputeMaskedBits to catch other known cases.
1592 EVT OpVT = Val.getValueType();
1593 unsigned BitWidth = OpVT.getSizeInBits();
1594 APInt Mask = APInt::getAllOnesValue(BitWidth);
1595 APInt KnownZero, KnownOne;
1596 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1597 return (KnownZero.countPopulation() == BitWidth - 1) &&
1598 (KnownOne.countPopulation() == 1);
1601 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1602 /// and cc. If it is unable to simplify it, return a null SDValue.
1604 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1605 ISD::CondCode Cond, bool foldBooleans,
1606 DAGCombinerInfo &DCI, DebugLoc dl) const {
1607 SelectionDAG &DAG = DCI.DAG;
1608 LLVMContext &Context = *DAG.getContext();
1610 // These setcc operations always fold.
1614 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1616 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1619 if (isa<ConstantSDNode>(N0.getNode())) {
1620 // Ensure that the constant occurs on the RHS, and fold constant
1622 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1625 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1626 const APInt &C1 = N1C->getAPIntValue();
1628 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1629 // equality comparison, then we're just comparing whether X itself is
1631 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1632 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1633 N0.getOperand(1).getOpcode() == ISD::Constant) {
1635 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1636 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1637 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1638 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1639 // (srl (ctlz x), 5) == 0 -> X != 0
1640 // (srl (ctlz x), 5) != 1 -> X != 0
1643 // (srl (ctlz x), 5) != 0 -> X == 0
1644 // (srl (ctlz x), 5) == 1 -> X == 0
1647 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1648 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1653 // If the LHS is '(and load, const)', the RHS is 0,
1654 // the test is for equality or unsigned, and all 1 bits of the const are
1655 // in the same partial word, see if we can shorten the load.
1656 if (DCI.isBeforeLegalize() &&
1657 N0.getOpcode() == ISD::AND && C1 == 0 &&
1658 N0.getNode()->hasOneUse() &&
1659 isa<LoadSDNode>(N0.getOperand(0)) &&
1660 N0.getOperand(0).getNode()->hasOneUse() &&
1661 isa<ConstantSDNode>(N0.getOperand(1))) {
1662 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1664 unsigned bestWidth = 0, bestOffset = 0;
1665 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1666 unsigned origWidth = N0.getValueType().getSizeInBits();
1667 unsigned maskWidth = origWidth;
1668 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1669 // 8 bits, but have to be careful...
1670 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1671 origWidth = Lod->getMemoryVT().getSizeInBits();
1673 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1674 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1675 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1676 for (unsigned offset=0; offset<origWidth/width; offset++) {
1677 if ((newMask & Mask) == Mask) {
1678 if (!TD->isLittleEndian())
1679 bestOffset = (origWidth/width - offset - 1) * (width/8);
1681 bestOffset = (uint64_t)offset * (width/8);
1682 bestMask = Mask.lshr(offset * (width/8) * 8);
1686 newMask = newMask << width;
1691 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1692 if (newVT.isRound()) {
1693 EVT PtrType = Lod->getOperand(1).getValueType();
1694 SDValue Ptr = Lod->getBasePtr();
1695 if (bestOffset != 0)
1696 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1697 DAG.getConstant(bestOffset, PtrType));
1698 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1699 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1701 Lod->getSrcValueOffset() + bestOffset,
1703 return DAG.getSetCC(dl, VT,
1704 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1705 DAG.getConstant(bestMask.trunc(bestWidth),
1707 DAG.getConstant(0LL, newVT), Cond);
1712 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1713 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1714 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1716 // If the comparison constant has bits in the upper part, the
1717 // zero-extended value could never match.
1718 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1719 C1.getBitWidth() - InSize))) {
1723 case ISD::SETEQ: return DAG.getConstant(0, VT);
1726 case ISD::SETNE: return DAG.getConstant(1, VT);
1729 // True if the sign bit of C1 is set.
1730 return DAG.getConstant(C1.isNegative(), VT);
1733 // True if the sign bit of C1 isn't set.
1734 return DAG.getConstant(C1.isNonNegative(), VT);
1740 // Otherwise, we can perform the comparison with the low bits.
1748 EVT newVT = N0.getOperand(0).getValueType();
1749 if (DCI.isBeforeLegalizeOps() ||
1750 (isOperationLegal(ISD::SETCC, newVT) &&
1751 getCondCodeAction(Cond, newVT)==Legal))
1752 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1753 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1758 break; // todo, be more careful with signed comparisons
1760 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1761 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1762 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1763 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1764 EVT ExtDstTy = N0.getValueType();
1765 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1767 // If the extended part has any inconsistent bits, it cannot ever
1768 // compare equal. In other words, they have to be all ones or all
1771 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1772 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1773 return DAG.getConstant(Cond == ISD::SETNE, VT);
1776 EVT Op0Ty = N0.getOperand(0).getValueType();
1777 if (Op0Ty == ExtSrcTy) {
1778 ZextOp = N0.getOperand(0);
1780 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1781 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1782 DAG.getConstant(Imm, Op0Ty));
1784 if (!DCI.isCalledByLegalizer())
1785 DCI.AddToWorklist(ZextOp.getNode());
1786 // Otherwise, make this a use of a zext.
1787 return DAG.getSetCC(dl, VT, ZextOp,
1788 DAG.getConstant(C1 & APInt::getLowBitsSet(
1793 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1794 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1796 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1797 if (N0.getOpcode() == ISD::SETCC) {
1798 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1802 // Invert the condition.
1803 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1804 CC = ISD::getSetCCInverse(CC,
1805 N0.getOperand(0).getValueType().isInteger());
1806 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1809 if ((N0.getOpcode() == ISD::XOR ||
1810 (N0.getOpcode() == ISD::AND &&
1811 N0.getOperand(0).getOpcode() == ISD::XOR &&
1812 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1813 isa<ConstantSDNode>(N0.getOperand(1)) &&
1814 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1815 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1816 // can only do this if the top bits are known zero.
1817 unsigned BitWidth = N0.getValueSizeInBits();
1818 if (DAG.MaskedValueIsZero(N0,
1819 APInt::getHighBitsSet(BitWidth,
1821 // Okay, get the un-inverted input value.
1823 if (N0.getOpcode() == ISD::XOR)
1824 Val = N0.getOperand(0);
1826 assert(N0.getOpcode() == ISD::AND &&
1827 N0.getOperand(0).getOpcode() == ISD::XOR);
1828 // ((X^1)&1)^1 -> X & 1
1829 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1830 N0.getOperand(0).getOperand(0),
1833 return DAG.getSetCC(dl, VT, Val, N1,
1834 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1839 APInt MinVal, MaxVal;
1840 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1841 if (ISD::isSignedIntSetCC(Cond)) {
1842 MinVal = APInt::getSignedMinValue(OperandBitSize);
1843 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1845 MinVal = APInt::getMinValue(OperandBitSize);
1846 MaxVal = APInt::getMaxValue(OperandBitSize);
1849 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1850 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1851 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1852 // X >= C0 --> X > (C0-1)
1853 return DAG.getSetCC(dl, VT, N0,
1854 DAG.getConstant(C1-1, N1.getValueType()),
1855 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1858 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1859 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1860 // X <= C0 --> X < (C0+1)
1861 return DAG.getSetCC(dl, VT, N0,
1862 DAG.getConstant(C1+1, N1.getValueType()),
1863 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1866 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1867 return DAG.getConstant(0, VT); // X < MIN --> false
1868 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1869 return DAG.getConstant(1, VT); // X >= MIN --> true
1870 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1871 return DAG.getConstant(0, VT); // X > MAX --> false
1872 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1873 return DAG.getConstant(1, VT); // X <= MAX --> true
1875 // Canonicalize setgt X, Min --> setne X, Min
1876 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1877 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1878 // Canonicalize setlt X, Max --> setne X, Max
1879 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1880 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1882 // If we have setult X, 1, turn it into seteq X, 0
1883 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1884 return DAG.getSetCC(dl, VT, N0,
1885 DAG.getConstant(MinVal, N0.getValueType()),
1887 // If we have setugt X, Max-1, turn it into seteq X, Max
1888 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1889 return DAG.getSetCC(dl, VT, N0,
1890 DAG.getConstant(MaxVal, N0.getValueType()),
1893 // If we have "setcc X, C0", check to see if we can shrink the immediate
1896 // SETUGT X, SINTMAX -> SETLT X, 0
1897 if (Cond == ISD::SETUGT &&
1898 C1 == APInt::getSignedMaxValue(OperandBitSize))
1899 return DAG.getSetCC(dl, VT, N0,
1900 DAG.getConstant(0, N1.getValueType()),
1903 // SETULT X, SINTMIN -> SETGT X, -1
1904 if (Cond == ISD::SETULT &&
1905 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1906 SDValue ConstMinusOne =
1907 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1909 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1912 // Fold bit comparisons when we can.
1913 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1914 (VT == N0.getValueType() ||
1915 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1916 N0.getOpcode() == ISD::AND)
1917 if (ConstantSDNode *AndRHS =
1918 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1919 EVT ShiftTy = DCI.isBeforeLegalize() ?
1920 getPointerTy() : getShiftAmountTy();
1921 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1922 // Perform the xform if the AND RHS is a single bit.
1923 if (AndRHS->getAPIntValue().isPowerOf2()) {
1924 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1925 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1926 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1928 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1929 // (X & 8) == 8 --> (X & 8) >> 3
1930 // Perform the xform if C1 is a single bit.
1931 if (C1.isPowerOf2()) {
1932 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1933 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1934 DAG.getConstant(C1.logBase2(), ShiftTy)));
1940 if (isa<ConstantFPSDNode>(N0.getNode())) {
1941 // Constant fold or commute setcc.
1942 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1943 if (O.getNode()) return O;
1944 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1945 // If the RHS of an FP comparison is a constant, simplify it away in
1947 if (CFP->getValueAPF().isNaN()) {
1948 // If an operand is known to be a nan, we can fold it.
1949 switch (ISD::getUnorderedFlavor(Cond)) {
1950 default: llvm_unreachable("Unknown flavor!");
1951 case 0: // Known false.
1952 return DAG.getConstant(0, VT);
1953 case 1: // Known true.
1954 return DAG.getConstant(1, VT);
1955 case 2: // Undefined.
1956 return DAG.getUNDEF(VT);
1960 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1961 // constant if knowing that the operand is non-nan is enough. We prefer to
1962 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1964 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1965 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1967 // If the condition is not legal, see if we can find an equivalent one
1969 if (!isCondCodeLegal(Cond, N0.getValueType())) {
1970 // If the comparison was an awkward floating-point == or != and one of
1971 // the comparison operands is infinity or negative infinity, convert the
1972 // condition to a less-awkward <= or >=.
1973 if (CFP->getValueAPF().isInfinity()) {
1974 if (CFP->getValueAPF().isNegative()) {
1975 if (Cond == ISD::SETOEQ &&
1976 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1977 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1978 if (Cond == ISD::SETUEQ &&
1979 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
1980 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1981 if (Cond == ISD::SETUNE &&
1982 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1983 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1984 if (Cond == ISD::SETONE &&
1985 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
1986 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1988 if (Cond == ISD::SETOEQ &&
1989 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1990 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1991 if (Cond == ISD::SETUEQ &&
1992 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
1993 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1994 if (Cond == ISD::SETUNE &&
1995 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1996 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1997 if (Cond == ISD::SETONE &&
1998 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
1999 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2006 // We can always fold X == X for integer setcc's.
2007 if (N0.getValueType().isInteger())
2008 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2009 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2010 if (UOF == 2) // FP operators that are undefined on NaNs.
2011 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2012 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2013 return DAG.getConstant(UOF, VT);
2014 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2015 // if it is not already.
2016 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2017 if (NewCond != Cond)
2018 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2021 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2022 N0.getValueType().isInteger()) {
2023 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2024 N0.getOpcode() == ISD::XOR) {
2025 // Simplify (X+Y) == (X+Z) --> Y == Z
2026 if (N0.getOpcode() == N1.getOpcode()) {
2027 if (N0.getOperand(0) == N1.getOperand(0))
2028 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2029 if (N0.getOperand(1) == N1.getOperand(1))
2030 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2031 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2032 // If X op Y == Y op X, try other combinations.
2033 if (N0.getOperand(0) == N1.getOperand(1))
2034 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2036 if (N0.getOperand(1) == N1.getOperand(0))
2037 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2042 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2043 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2044 // Turn (X+C1) == C2 --> X == C2-C1
2045 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2046 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2047 DAG.getConstant(RHSC->getAPIntValue()-
2048 LHSR->getAPIntValue(),
2049 N0.getValueType()), Cond);
2052 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2053 if (N0.getOpcode() == ISD::XOR)
2054 // If we know that all of the inverted bits are zero, don't bother
2055 // performing the inversion.
2056 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2058 DAG.getSetCC(dl, VT, N0.getOperand(0),
2059 DAG.getConstant(LHSR->getAPIntValue() ^
2060 RHSC->getAPIntValue(),
2065 // Turn (C1-X) == C2 --> X == C1-C2
2066 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2067 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2069 DAG.getSetCC(dl, VT, N0.getOperand(1),
2070 DAG.getConstant(SUBC->getAPIntValue() -
2071 RHSC->getAPIntValue(),
2078 // Simplify (X+Z) == X --> Z == 0
2079 if (N0.getOperand(0) == N1)
2080 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2081 DAG.getConstant(0, N0.getValueType()), Cond);
2082 if (N0.getOperand(1) == N1) {
2083 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2084 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2085 DAG.getConstant(0, N0.getValueType()), Cond);
2086 else if (N0.getNode()->hasOneUse()) {
2087 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2088 // (Z-X) == X --> Z == X<<1
2089 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2091 DAG.getConstant(1, getShiftAmountTy()));
2092 if (!DCI.isCalledByLegalizer())
2093 DCI.AddToWorklist(SH.getNode());
2094 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2099 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2100 N1.getOpcode() == ISD::XOR) {
2101 // Simplify X == (X+Z) --> Z == 0
2102 if (N1.getOperand(0) == N0) {
2103 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2104 DAG.getConstant(0, N1.getValueType()), Cond);
2105 } else if (N1.getOperand(1) == N0) {
2106 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2107 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2108 DAG.getConstant(0, N1.getValueType()), Cond);
2109 } else if (N1.getNode()->hasOneUse()) {
2110 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2111 // X == (Z-X) --> X<<1 == Z
2112 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2113 DAG.getConstant(1, getShiftAmountTy()));
2114 if (!DCI.isCalledByLegalizer())
2115 DCI.AddToWorklist(SH.getNode());
2116 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2121 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2122 // Note that where y is variable and is known to have at most
2123 // one bit set (for example, if it is z&1) we cannot do this;
2124 // the expressions are not equivalent when y==0.
2125 if (N0.getOpcode() == ISD::AND)
2126 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2127 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2128 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2129 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2130 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2133 if (N1.getOpcode() == ISD::AND)
2134 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2135 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2136 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2137 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2138 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2143 // Fold away ALL boolean setcc's.
2145 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2147 default: llvm_unreachable("Unknown integer setcc!");
2148 case ISD::SETEQ: // X == Y -> ~(X^Y)
2149 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2150 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2151 if (!DCI.isCalledByLegalizer())
2152 DCI.AddToWorklist(Temp.getNode());
2154 case ISD::SETNE: // X != Y --> (X^Y)
2155 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2157 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2158 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2159 Temp = DAG.getNOT(dl, N0, MVT::i1);
2160 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2161 if (!DCI.isCalledByLegalizer())
2162 DCI.AddToWorklist(Temp.getNode());
2164 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2165 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2166 Temp = DAG.getNOT(dl, N1, MVT::i1);
2167 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2168 if (!DCI.isCalledByLegalizer())
2169 DCI.AddToWorklist(Temp.getNode());
2171 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2172 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2173 Temp = DAG.getNOT(dl, N0, MVT::i1);
2174 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2175 if (!DCI.isCalledByLegalizer())
2176 DCI.AddToWorklist(Temp.getNode());
2178 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2179 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2180 Temp = DAG.getNOT(dl, N1, MVT::i1);
2181 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2184 if (VT != MVT::i1) {
2185 if (!DCI.isCalledByLegalizer())
2186 DCI.AddToWorklist(N0.getNode());
2187 // FIXME: If running after legalize, we probably can't do this.
2188 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2193 // Could not fold it.
2197 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2198 /// node is a GlobalAddress + offset.
2199 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2200 int64_t &Offset) const {
2201 if (isa<GlobalAddressSDNode>(N)) {
2202 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2203 GA = GASD->getGlobal();
2204 Offset += GASD->getOffset();
2208 if (N->getOpcode() == ISD::ADD) {
2209 SDValue N1 = N->getOperand(0);
2210 SDValue N2 = N->getOperand(1);
2211 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2212 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2214 Offset += V->getSExtValue();
2217 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2218 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2220 Offset += V->getSExtValue();
2229 SDValue TargetLowering::
2230 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2231 // Default implementation: no optimization.
2235 //===----------------------------------------------------------------------===//
2236 // Inline Assembler Implementation Methods
2237 //===----------------------------------------------------------------------===//
2240 TargetLowering::ConstraintType
2241 TargetLowering::getConstraintType(const std::string &Constraint) const {
2242 // FIXME: lots more standard ones to handle.
2243 if (Constraint.size() == 1) {
2244 switch (Constraint[0]) {
2246 case 'r': return C_RegisterClass;
2248 case 'o': // offsetable
2249 case 'V': // not offsetable
2251 case 'i': // Simple Integer or Relocatable Constant
2252 case 'n': // Simple Integer
2253 case 's': // Relocatable Constant
2254 case 'X': // Allow ANY value.
2255 case 'I': // Target registers.
2267 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2268 Constraint[Constraint.size()-1] == '}')
2273 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2274 /// with another that has more specific requirements based on the type of the
2275 /// corresponding operand.
2276 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2277 if (ConstraintVT.isInteger())
2279 if (ConstraintVT.isFloatingPoint())
2280 return "f"; // works for many targets
2284 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2285 /// vector. If it is invalid, don't add anything to Ops.
2286 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2287 char ConstraintLetter,
2289 std::vector<SDValue> &Ops,
2290 SelectionDAG &DAG) const {
2291 switch (ConstraintLetter) {
2293 case 'X': // Allows any operand; labels (basic block) use this.
2294 if (Op.getOpcode() == ISD::BasicBlock) {
2299 case 'i': // Simple Integer or Relocatable Constant
2300 case 'n': // Simple Integer
2301 case 's': { // Relocatable Constant
2302 // These operands are interested in values of the form (GV+C), where C may
2303 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2304 // is possible and fine if either GV or C are missing.
2305 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2306 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2308 // If we have "(add GV, C)", pull out GV/C
2309 if (Op.getOpcode() == ISD::ADD) {
2310 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2311 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2312 if (C == 0 || GA == 0) {
2313 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2314 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2316 if (C == 0 || GA == 0)
2320 // If we find a valid operand, map to the TargetXXX version so that the
2321 // value itself doesn't get selected.
2322 if (GA) { // Either &GV or &GV+C
2323 if (ConstraintLetter != 'n') {
2324 int64_t Offs = GA->getOffset();
2325 if (C) Offs += C->getZExtValue();
2326 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2327 Op.getValueType(), Offs));
2331 if (C) { // just C, no GV.
2332 // Simple constants are not allowed for 's'.
2333 if (ConstraintLetter != 's') {
2334 // gcc prints these as sign extended. Sign extend value to 64 bits
2335 // now; without this it would get ZExt'd later in
2336 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2337 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2347 std::vector<unsigned> TargetLowering::
2348 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2350 return std::vector<unsigned>();
2354 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2355 getRegForInlineAsmConstraint(const std::string &Constraint,
2357 if (Constraint[0] != '{')
2358 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2359 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2361 // Remove the braces from around the name.
2362 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2364 // Figure out which register class contains this reg.
2365 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2366 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2367 E = RI->regclass_end(); RCI != E; ++RCI) {
2368 const TargetRegisterClass *RC = *RCI;
2370 // If none of the the value types for this register class are valid, we
2371 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2372 bool isLegal = false;
2373 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2375 if (isTypeLegal(*I)) {
2381 if (!isLegal) continue;
2383 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2385 if (RegName.equals_lower(RI->getName(*I)))
2386 return std::make_pair(*I, RC);
2390 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2393 //===----------------------------------------------------------------------===//
2394 // Constraint Selection.
2396 /// isMatchingInputConstraint - Return true of this is an input operand that is
2397 /// a matching constraint like "4".
2398 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2399 assert(!ConstraintCode.empty() && "No known constraint!");
2400 return isdigit(ConstraintCode[0]);
2403 /// getMatchedOperand - If this is an input matching constraint, this method
2404 /// returns the output operand it matches.
2405 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2406 assert(!ConstraintCode.empty() && "No known constraint!");
2407 return atoi(ConstraintCode.c_str());
2411 /// getConstraintGenerality - Return an integer indicating how general CT
2413 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2415 default: llvm_unreachable("Unknown constraint type!");
2416 case TargetLowering::C_Other:
2417 case TargetLowering::C_Unknown:
2419 case TargetLowering::C_Register:
2421 case TargetLowering::C_RegisterClass:
2423 case TargetLowering::C_Memory:
2428 /// ChooseConstraint - If there are multiple different constraints that we
2429 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2430 /// This is somewhat tricky: constraints fall into four classes:
2431 /// Other -> immediates and magic values
2432 /// Register -> one specific register
2433 /// RegisterClass -> a group of regs
2434 /// Memory -> memory
2435 /// Ideally, we would pick the most specific constraint possible: if we have
2436 /// something that fits into a register, we would pick it. The problem here
2437 /// is that if we have something that could either be in a register or in
2438 /// memory that use of the register could cause selection of *other*
2439 /// operands to fail: they might only succeed if we pick memory. Because of
2440 /// this the heuristic we use is:
2442 /// 1) If there is an 'other' constraint, and if the operand is valid for
2443 /// that constraint, use it. This makes us take advantage of 'i'
2444 /// constraints when available.
2445 /// 2) Otherwise, pick the most general constraint present. This prefers
2446 /// 'm' over 'r', for example.
2448 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2449 bool hasMemory, const TargetLowering &TLI,
2450 SDValue Op, SelectionDAG *DAG) {
2451 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2452 unsigned BestIdx = 0;
2453 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2454 int BestGenerality = -1;
2456 // Loop over the options, keeping track of the most general one.
2457 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2458 TargetLowering::ConstraintType CType =
2459 TLI.getConstraintType(OpInfo.Codes[i]);
2461 // If this is an 'other' constraint, see if the operand is valid for it.
2462 // For example, on X86 we might have an 'rI' constraint. If the operand
2463 // is an integer in the range [0..31] we want to use I (saving a load
2464 // of a register), otherwise we must use 'r'.
2465 if (CType == TargetLowering::C_Other && Op.getNode()) {
2466 assert(OpInfo.Codes[i].size() == 1 &&
2467 "Unhandled multi-letter 'other' constraint");
2468 std::vector<SDValue> ResultOps;
2469 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2471 if (!ResultOps.empty()) {
2478 // This constraint letter is more general than the previous one, use it.
2479 int Generality = getConstraintGenerality(CType);
2480 if (Generality > BestGenerality) {
2483 BestGenerality = Generality;
2487 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2488 OpInfo.ConstraintType = BestType;
2491 /// ComputeConstraintToUse - Determines the constraint code and constraint
2492 /// type to use for the specific AsmOperandInfo, setting
2493 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2494 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2497 SelectionDAG *DAG) const {
2498 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2500 // Single-letter constraints ('r') are very common.
2501 if (OpInfo.Codes.size() == 1) {
2502 OpInfo.ConstraintCode = OpInfo.Codes[0];
2503 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2505 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2508 // 'X' matches anything.
2509 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2510 // Labels and constants are handled elsewhere ('X' is the only thing
2511 // that matches labels). For Functions, the type here is the type of
2512 // the result, which is not what we want to look at; leave them alone.
2513 Value *v = OpInfo.CallOperandVal;
2514 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2515 OpInfo.CallOperandVal = v;
2519 // Otherwise, try to resolve it to something we know about by looking at
2520 // the actual operand type.
2521 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2522 OpInfo.ConstraintCode = Repl;
2523 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2528 //===----------------------------------------------------------------------===//
2529 // Loop Strength Reduction hooks
2530 //===----------------------------------------------------------------------===//
2532 /// isLegalAddressingMode - Return true if the addressing mode represented
2533 /// by AM is legal for this target, for a load/store of the specified type.
2534 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2535 const Type *Ty) const {
2536 // The default implementation of this implements a conservative RISCy, r+r and
2539 // Allows a sign-extended 16-bit immediate field.
2540 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2543 // No global is ever allowed as a base.
2547 // Only support r+r,
2549 case 0: // "r+i" or just "i", depending on HasBaseReg.
2552 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2554 // Otherwise we have r+r or r+i.
2557 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2559 // Allow 2*r as r+r.
2566 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2567 /// return a DAG expression to select that will generate the same value by
2568 /// multiplying by a magic number. See:
2569 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2570 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2571 std::vector<SDNode*>* Created) const {
2572 EVT VT = N->getValueType(0);
2573 DebugLoc dl= N->getDebugLoc();
2575 // Check to see if we can do this.
2576 // FIXME: We should be more aggressive here.
2577 if (!isTypeLegal(VT))
2580 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2581 APInt::ms magics = d.magic();
2583 // Multiply the numerator (operand 0) by the magic value
2584 // FIXME: We should support doing a MUL in a wider type
2586 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2587 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2588 DAG.getConstant(magics.m, VT));
2589 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2590 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2592 DAG.getConstant(magics.m, VT)).getNode(), 1);
2594 return SDValue(); // No mulhs or equvialent
2595 // If d > 0 and m < 0, add the numerator
2596 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2597 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2599 Created->push_back(Q.getNode());
2601 // If d < 0 and m > 0, subtract the numerator.
2602 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2603 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2605 Created->push_back(Q.getNode());
2607 // Shift right algebraic if shift value is nonzero
2609 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2610 DAG.getConstant(magics.s, getShiftAmountTy()));
2612 Created->push_back(Q.getNode());
2614 // Extract the sign bit and add it to the quotient
2616 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2617 getShiftAmountTy()));
2619 Created->push_back(T.getNode());
2620 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2623 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2624 /// return a DAG expression to select that will generate the same value by
2625 /// multiplying by a magic number. See:
2626 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2627 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2628 std::vector<SDNode*>* Created) const {
2629 EVT VT = N->getValueType(0);
2630 DebugLoc dl = N->getDebugLoc();
2632 // Check to see if we can do this.
2633 // FIXME: We should be more aggressive here.
2634 if (!isTypeLegal(VT))
2637 // FIXME: We should use a narrower constant when the upper
2638 // bits are known to be zero.
2639 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2640 APInt::mu magics = N1C->getAPIntValue().magicu();
2642 // Multiply the numerator (operand 0) by the magic value
2643 // FIXME: We should support doing a MUL in a wider type
2645 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2646 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2647 DAG.getConstant(magics.m, VT));
2648 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2649 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2651 DAG.getConstant(magics.m, VT)).getNode(), 1);
2653 return SDValue(); // No mulhu or equvialent
2655 Created->push_back(Q.getNode());
2657 if (magics.a == 0) {
2658 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2659 "We shouldn't generate an undefined shift!");
2660 return DAG.getNode(ISD::SRL, dl, VT, Q,
2661 DAG.getConstant(magics.s, getShiftAmountTy()));
2663 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2665 Created->push_back(NPQ.getNode());
2666 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2667 DAG.getConstant(1, getShiftAmountTy()));
2669 Created->push_back(NPQ.getNode());
2670 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2672 Created->push_back(NPQ.getNode());
2673 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2674 DAG.getConstant(magics.s-1, getShiftAmountTy()));