1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/Support/MathExtras.h"
23 TargetLowering::TargetLowering(TargetMachine &tm)
24 : TM(tm), TD(TM.getTargetData()) {
25 assert(ISD::BUILTIN_OP_END <= 156 &&
26 "Fixed size array in TargetLowering is not large enough!");
27 // All operations default to being supported.
28 memset(OpActions, 0, sizeof(OpActions));
30 IsLittleEndian = TD->isLittleEndian();
31 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
32 ShiftAmtHandling = Undefined;
33 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
34 memset(TargetDAGCombineArray, 0,
35 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
36 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
37 allowUnalignedMemoryAccesses = false;
38 UseUnderscoreSetJmpLongJmp = false;
39 IntDivIsCheap = false;
40 Pow2DivIsCheap = false;
41 StackPointerRegisterToSaveRestore = 0;
42 SchedPreferenceInfo = SchedulingForLatency;
45 TargetLowering::~TargetLowering() {}
47 /// setValueTypeAction - Set the action for a particular value type. This
48 /// assumes an action has not already been set for this value type.
49 static void SetValueTypeAction(MVT::ValueType VT,
50 TargetLowering::LegalizeAction Action,
52 MVT::ValueType *TransformToType,
53 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
54 ValueTypeActions.setTypeAction(VT, Action);
55 if (Action == TargetLowering::Promote) {
56 MVT::ValueType PromoteTo;
60 unsigned LargerReg = VT+1;
61 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
63 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
64 "Nothing to promote to??");
66 PromoteTo = (MVT::ValueType)LargerReg;
69 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
70 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
71 "Can only promote from int->int or fp->fp!");
72 assert(VT < PromoteTo && "Must promote to a larger type!");
73 TransformToType[VT] = PromoteTo;
74 } else if (Action == TargetLowering::Expand) {
75 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
76 "Cannot expand this type: target must support SOME integer reg!");
77 // Expand to the next smaller integer type!
78 TransformToType[VT] = (MVT::ValueType)(VT-1);
83 /// computeRegisterProperties - Once all of the register classes are added,
84 /// this allows us to compute derived properties we expose.
85 void TargetLowering::computeRegisterProperties() {
86 assert(MVT::LAST_VALUETYPE <= 32 &&
87 "Too many value types for ValueTypeActions to hold!");
89 // Everything defaults to one.
90 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
91 NumElementsForVT[i] = 1;
93 // Find the largest integer register class.
94 unsigned LargestIntReg = MVT::i128;
95 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
96 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
98 // Every integer value type larger than this largest register takes twice as
99 // many registers to represent as the previous ValueType.
100 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
101 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
102 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
104 // Inspect all of the ValueType's possible, deciding how to process them.
105 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
106 // If we are expanding this type, expand it!
107 if (getNumElements((MVT::ValueType)IntReg) != 1)
108 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
110 else if (!isTypeLegal((MVT::ValueType)IntReg))
111 // Otherwise, if we don't have native support, we must promote to a
113 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
114 TransformToType, ValueTypeActions);
116 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
118 // If the target does not have native support for F32, promote it to F64.
119 if (!isTypeLegal(MVT::f32))
120 SetValueTypeAction(MVT::f32, Promote, *this,
121 TransformToType, ValueTypeActions);
123 TransformToType[MVT::f32] = MVT::f32;
125 // Set MVT::Vector to always be Expanded
126 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
129 // Loop over all of the legal vector value types, specifying an identity type
131 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
132 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
133 if (isTypeLegal((MVT::ValueType)i))
134 TransformToType[i] = (MVT::ValueType)i;
137 assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
138 TransformToType[MVT::f64] = MVT::f64;
141 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
145 /// getPackedTypeBreakdown - Packed types are broken down into some number of
146 /// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values
147 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
149 /// This method returns the number and type of the resultant breakdown.
151 unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
152 MVT::ValueType &PTyElementVT,
153 MVT::ValueType &PTyLegalElementVT) const {
154 // Figure out the right, legal destination reg to copy into.
155 unsigned NumElts = PTy->getNumElements();
156 MVT::ValueType EltTy = getValueType(PTy->getElementType());
158 unsigned NumVectorRegs = 1;
160 // Divide the input until we get to a supported size. This will always
161 // end with a scalar if the target doesn't support vectors.
162 while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) {
171 VT = getVectorType(EltTy, NumElts);
175 MVT::ValueType DestVT = getTypeToTransformTo(VT);
176 PTyLegalElementVT = DestVT;
178 // Value is expanded, e.g. i64 -> i16.
179 return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
181 // Otherwise, promotion or legal types use the same number of registers as
182 // the vector decimated to the appropriate level.
183 return NumVectorRegs;
189 //===----------------------------------------------------------------------===//
190 // Optimization Methods
191 //===----------------------------------------------------------------------===//
193 /// ShrinkDemandedConstant - Check to see if the specified operand of the
194 /// specified instruction is a constant integer. If so, check to see if there
195 /// are any bits set in the constant that are not demanded. If so, shrink the
196 /// constant and return true.
197 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
199 // FIXME: ISD::SELECT, ISD::SELECT_CC
200 switch(Op.getOpcode()) {
205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
206 if ((~Demanded & C->getValue()) != 0) {
207 MVT::ValueType VT = Op.getValueType();
208 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
209 DAG.getConstant(Demanded & C->getValue(),
211 return CombineTo(Op, New);
218 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
219 /// DemandedMask bits of the result of Op are ever used downstream. If we can
220 /// use this information to simplify Op, create a new simplified DAG node and
221 /// return true, returning the original and new nodes in Old and New. Otherwise,
222 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
223 /// the expression (used to simplify the caller). The KnownZero/One bits may
224 /// only be accurate for those bits in the DemandedMask.
225 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
228 TargetLoweringOpt &TLO,
229 unsigned Depth) const {
230 KnownZero = KnownOne = 0; // Don't know anything.
231 // Other users may use these bits.
232 if (!Op.Val->hasOneUse()) {
234 // If not at the root, Just compute the KnownZero/KnownOne bits to
235 // simplify things downstream.
236 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
239 // If this is the root being simplified, allow it to have multiple uses,
240 // just set the DemandedMask to all bits.
241 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
242 } else if (DemandedMask == 0) {
243 // Not demanding any bits from Op.
244 if (Op.getOpcode() != ISD::UNDEF)
245 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
247 } else if (Depth == 6) { // Limit search depth.
251 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
252 switch (Op.getOpcode()) {
254 // We know all of the bits for a constant!
255 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
256 KnownZero = ~KnownOne & DemandedMask;
257 return false; // Don't fall through, will infinitely loop.
259 // If the RHS is a constant, check to see if the LHS would be zero without
260 // using the bits from the RHS. Below, we use knowledge about the RHS to
261 // simplify the LHS, here we're using information from the LHS to simplify
263 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
264 uint64_t LHSZero, LHSOne;
265 ComputeMaskedBits(Op.getOperand(0), DemandedMask,
266 LHSZero, LHSOne, Depth+1);
267 // If the LHS already has zeros where RHSC does, this and is dead.
268 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
269 return TLO.CombineTo(Op, Op.getOperand(0));
270 // If any of the set bits in the RHS are known zero on the LHS, shrink
272 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
276 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
277 KnownOne, TLO, Depth+1))
279 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
280 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
281 KnownZero2, KnownOne2, TLO, Depth+1))
283 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
285 // If all of the demanded bits are known one on one side, return the other.
286 // These bits cannot contribute to the result of the 'and'.
287 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
288 return TLO.CombineTo(Op, Op.getOperand(0));
289 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
290 return TLO.CombineTo(Op, Op.getOperand(1));
291 // If all of the demanded bits in the inputs are known zeros, return zero.
292 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
293 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
294 // If the RHS is a constant, see if we can simplify it.
295 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
298 // Output known-1 bits are only known if set in both the LHS & RHS.
299 KnownOne &= KnownOne2;
300 // Output known-0 are known to be clear if zero in either the LHS | RHS.
301 KnownZero |= KnownZero2;
304 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
305 KnownOne, TLO, Depth+1))
307 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
308 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
309 KnownZero2, KnownOne2, TLO, Depth+1))
311 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
313 // If all of the demanded bits are known zero on one side, return the other.
314 // These bits cannot contribute to the result of the 'or'.
315 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
316 return TLO.CombineTo(Op, Op.getOperand(0));
317 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
318 return TLO.CombineTo(Op, Op.getOperand(1));
319 // If all of the potentially set bits on one side are known to be set on
320 // the other side, just use the 'other' side.
321 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
322 (DemandedMask & (~KnownZero)))
323 return TLO.CombineTo(Op, Op.getOperand(0));
324 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
325 (DemandedMask & (~KnownZero2)))
326 return TLO.CombineTo(Op, Op.getOperand(1));
327 // If the RHS is a constant, see if we can simplify it.
328 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
331 // Output known-0 bits are only known if clear in both the LHS & RHS.
332 KnownZero &= KnownZero2;
333 // Output known-1 are known to be set if set in either the LHS | RHS.
334 KnownOne |= KnownOne2;
337 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
338 KnownOne, TLO, Depth+1))
340 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
341 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
342 KnownOne2, TLO, Depth+1))
344 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
346 // If all of the demanded bits are known zero on one side, return the other.
347 // These bits cannot contribute to the result of the 'xor'.
348 if ((DemandedMask & KnownZero) == DemandedMask)
349 return TLO.CombineTo(Op, Op.getOperand(0));
350 if ((DemandedMask & KnownZero2) == DemandedMask)
351 return TLO.CombineTo(Op, Op.getOperand(1));
353 // Output known-0 bits are known if clear or set in both the LHS & RHS.
354 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
355 // Output known-1 are known to be set if set in only one of the LHS, RHS.
356 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
358 // If all of the unknown bits are known to be zero on one side or the other
359 // (but not both) turn this into an *inclusive* or.
360 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
361 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut))
362 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits)
363 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
366 // If all of the demanded bits on one side are known, and all of the set
367 // bits on that side are also known to be set on the other side, turn this
368 // into an AND, as we know the bits will be cleared.
369 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
370 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
371 if ((KnownOne & KnownOne2) == KnownOne) {
372 MVT::ValueType VT = Op.getValueType();
373 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
374 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
379 // If the RHS is a constant, see if we can simplify it.
380 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
381 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
384 KnownZero = KnownZeroOut;
385 KnownOne = KnownOneOut;
388 // If we know the result of a setcc has the top bits zero, use this info.
389 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
390 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
393 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
394 KnownOne, TLO, Depth+1))
396 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
397 KnownOne2, TLO, Depth+1))
399 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
400 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
402 // If the operands are constants, see if we can simplify them.
403 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
406 // Only known if known in both the LHS and RHS.
407 KnownOne &= KnownOne2;
408 KnownZero &= KnownZero2;
411 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
412 KnownOne, TLO, Depth+1))
414 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
415 KnownOne2, TLO, Depth+1))
417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
418 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
420 // If the operands are constants, see if we can simplify them.
421 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
424 // Only known if known in both the LHS and RHS.
425 KnownOne &= KnownOne2;
426 KnownZero &= KnownZero2;
429 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
430 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
431 KnownZero, KnownOne, TLO, Depth+1))
433 KnownZero <<= SA->getValue();
434 KnownOne <<= SA->getValue();
435 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
439 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
440 MVT::ValueType VT = Op.getValueType();
441 unsigned ShAmt = SA->getValue();
443 // Compute the new bits that are at the top now.
444 uint64_t HighBits = (1ULL << ShAmt)-1;
445 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
446 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
448 if (SimplifyDemandedBits(Op.getOperand(0),
449 (DemandedMask << ShAmt) & TypeMask,
450 KnownZero, KnownOne, TLO, Depth+1))
452 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
453 KnownZero &= TypeMask;
454 KnownOne &= TypeMask;
457 KnownZero |= HighBits; // high bits known zero.
461 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
462 MVT::ValueType VT = Op.getValueType();
463 unsigned ShAmt = SA->getValue();
465 // Compute the new bits that are at the top now.
466 uint64_t HighBits = (1ULL << ShAmt)-1;
467 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
468 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
470 if (SimplifyDemandedBits(Op.getOperand(0),
471 (DemandedMask << ShAmt) & TypeMask,
472 KnownZero, KnownOne, TLO, Depth+1))
474 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
475 KnownZero &= TypeMask;
476 KnownOne &= TypeMask;
477 KnownZero >>= SA->getValue();
478 KnownOne >>= SA->getValue();
480 // Handle the sign bits.
481 uint64_t SignBit = MVT::getIntVTSignBit(VT);
482 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
484 // If the input sign bit is known to be zero, or if none of the top bits
485 // are demanded, turn this into an unsigned shift right.
486 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
487 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
489 } else if (KnownOne & SignBit) { // New bits are known one.
490 KnownOne |= HighBits;
494 case ISD::SIGN_EXTEND_INREG: {
495 MVT::ValueType VT = Op.getValueType();
496 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
498 // Sign extension. Compute the demanded bits in the result that are not
499 // present in the input.
500 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
502 // If none of the extended bits are demanded, eliminate the sextinreg.
504 return TLO.CombineTo(Op, Op.getOperand(0));
506 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
507 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
509 // Since the sign extended bits are demanded, we know that the sign
511 InputDemandedBits |= InSignBit;
513 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
514 KnownZero, KnownOne, TLO, Depth+1))
516 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
518 // If the sign bit of the input is known set or clear, then we know the
519 // top bits of the result.
521 // If the input sign bit is known zero, convert this into a zero extension.
522 if (KnownZero & InSignBit)
523 return TLO.CombineTo(Op,
524 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
526 if (KnownOne & InSignBit) { // Input sign bit known set
528 KnownZero &= ~NewBits;
529 } else { // Input sign bit unknown
530 KnownZero &= ~NewBits;
531 KnownOne &= ~NewBits;
538 MVT::ValueType VT = Op.getValueType();
539 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
540 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
544 case ISD::ZEXTLOAD: {
545 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
546 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
549 case ISD::ZERO_EXTEND: {
550 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
552 // If none of the top bits are demanded, convert this into an any_extend.
553 uint64_t NewBits = (~InMask) & DemandedMask;
555 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
559 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
560 KnownZero, KnownOne, TLO, Depth+1))
562 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
563 KnownZero |= NewBits;
566 case ISD::SIGN_EXTEND: {
567 MVT::ValueType InVT = Op.getOperand(0).getValueType();
568 uint64_t InMask = MVT::getIntVTBitMask(InVT);
569 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
570 uint64_t NewBits = (~InMask) & DemandedMask;
572 // If none of the top bits are demanded, convert this into an any_extend.
574 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
577 // Since some of the sign extended bits are demanded, we know that the sign
579 uint64_t InDemandedBits = DemandedMask & InMask;
580 InDemandedBits |= InSignBit;
582 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
583 KnownOne, TLO, Depth+1))
586 // If the sign bit is known zero, convert this to a zero extend.
587 if (KnownZero & InSignBit)
588 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
592 // If the sign bit is known one, the top bits match.
593 if (KnownOne & InSignBit) {
595 KnownZero &= ~NewBits;
596 } else { // Otherwise, top bits aren't known.
597 KnownOne &= ~NewBits;
598 KnownZero &= ~NewBits;
602 case ISD::ANY_EXTEND: {
603 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
604 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
605 KnownZero, KnownOne, TLO, Depth+1))
607 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
610 case ISD::TRUNCATE: {
611 // Simplify the input, using demanded bit information, and compute the known
612 // zero/one bits live out.
613 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
614 KnownZero, KnownOne, TLO, Depth+1))
617 // If the input is only used by this truncate, see if we can shrink it based
618 // on the known demanded bits.
619 if (Op.getOperand(0).Val->hasOneUse()) {
620 SDOperand In = Op.getOperand(0);
621 switch (In.getOpcode()) {
624 // Shrink SRL by a constant if none of the high bits shifted in are
626 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
627 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
628 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
629 HighBits >>= ShAmt->getValue();
631 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
632 (DemandedMask & HighBits) == 0) {
633 // None of the shifted in bits are needed. Add a truncate of the
634 // shift input, then shift it.
635 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
638 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
639 NewTrunc, In.getOperand(1)));
646 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
647 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
648 KnownZero &= OutMask;
652 case ISD::AssertZext: {
653 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
654 uint64_t InMask = MVT::getIntVTBitMask(VT);
655 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
656 KnownZero, KnownOne, TLO, Depth+1))
658 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
659 KnownZero |= ~InMask & DemandedMask;
664 case ISD::INTRINSIC_WO_CHAIN:
665 case ISD::INTRINSIC_W_CHAIN:
666 case ISD::INTRINSIC_VOID:
667 // Just use ComputeMaskedBits to compute output bits.
668 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
672 // If we know the value of all of the demanded bits, return this as a
674 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
675 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
680 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
681 /// this predicate to simplify operations downstream. Mask is known to be zero
682 /// for bits that V cannot have.
683 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
684 unsigned Depth) const {
685 uint64_t KnownZero, KnownOne;
686 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
687 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
688 return (KnownZero & Mask) == Mask;
691 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
692 /// known to be either zero or one and return them in the KnownZero/KnownOne
693 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
695 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
696 uint64_t &KnownZero, uint64_t &KnownOne,
697 unsigned Depth) const {
698 KnownZero = KnownOne = 0; // Don't know anything.
699 if (Depth == 6 || Mask == 0)
700 return; // Limit search depth.
702 uint64_t KnownZero2, KnownOne2;
704 switch (Op.getOpcode()) {
706 // We know all of the bits for a constant!
707 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
708 KnownZero = ~KnownOne & Mask;
711 // If either the LHS or the RHS are Zero, the result is zero.
712 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
714 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
715 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
716 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
718 // Output known-1 bits are only known if set in both the LHS & RHS.
719 KnownOne &= KnownOne2;
720 // Output known-0 are known to be clear if zero in either the LHS | RHS.
721 KnownZero |= KnownZero2;
724 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
726 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
727 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
728 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
730 // Output known-0 bits are only known if clear in both the LHS & RHS.
731 KnownZero &= KnownZero2;
732 // Output known-1 are known to be set if set in either the LHS | RHS.
733 KnownOne |= KnownOne2;
736 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
737 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
738 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
739 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
741 // Output known-0 bits are known if clear or set in both the LHS & RHS.
742 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
743 // Output known-1 are known to be set if set in only one of the LHS, RHS.
744 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
745 KnownZero = KnownZeroOut;
749 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
750 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
751 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
752 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
754 // Only known if known in both the LHS and RHS.
755 KnownOne &= KnownOne2;
756 KnownZero &= KnownZero2;
759 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
760 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
761 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
762 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
764 // Only known if known in both the LHS and RHS.
765 KnownOne &= KnownOne2;
766 KnownZero &= KnownZero2;
769 // If we know the result of a setcc has the top bits zero, use this info.
770 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
771 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
774 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
775 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
776 Mask >>= SA->getValue();
777 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
778 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
779 KnownZero <<= SA->getValue();
780 KnownOne <<= SA->getValue();
781 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
785 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
786 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
787 uint64_t HighBits = (1ULL << SA->getValue())-1;
788 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
789 Mask <<= SA->getValue();
790 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
791 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
792 KnownZero >>= SA->getValue();
793 KnownOne >>= SA->getValue();
794 KnownZero |= HighBits; // high bits known zero.
798 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
799 uint64_t HighBits = (1ULL << SA->getValue())-1;
800 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
801 Mask <<= SA->getValue();
802 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
803 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
804 KnownZero >>= SA->getValue();
805 KnownOne >>= SA->getValue();
807 // Handle the sign bits.
808 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
809 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
811 if (KnownZero & SignBit) { // New bits are known zero.
812 KnownZero |= HighBits;
813 } else if (KnownOne & SignBit) { // New bits are known one.
814 KnownOne |= HighBits;
818 case ISD::SIGN_EXTEND_INREG: {
819 MVT::ValueType VT = Op.getValueType();
820 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
822 // Sign extension. Compute the demanded bits in the result that are not
823 // present in the input.
824 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask;
826 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
827 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT);
829 // If the sign extended bits are demanded, we know that the sign
832 InputDemandedBits |= InSignBit;
834 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
835 KnownZero, KnownOne, Depth+1);
836 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
838 // If the sign bit of the input is known set or clear, then we know the
839 // top bits of the result.
840 if (KnownZero & InSignBit) { // Input sign bit known clear
841 KnownZero |= NewBits;
842 KnownOne &= ~NewBits;
843 } else if (KnownOne & InSignBit) { // Input sign bit known set
845 KnownZero &= ~NewBits;
846 } else { // Input sign bit unknown
847 KnownZero &= ~NewBits;
848 KnownOne &= ~NewBits;
855 MVT::ValueType VT = Op.getValueType();
856 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
857 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
861 case ISD::ZEXTLOAD: {
862 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
863 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
866 case ISD::ZERO_EXTEND: {
867 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
868 uint64_t NewBits = (~InMask) & Mask;
869 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
871 KnownZero |= NewBits & Mask;
872 KnownOne &= ~NewBits;
875 case ISD::SIGN_EXTEND: {
876 MVT::ValueType InVT = Op.getOperand(0).getValueType();
877 unsigned InBits = MVT::getSizeInBits(InVT);
878 uint64_t InMask = MVT::getIntVTBitMask(InVT);
879 uint64_t InSignBit = 1ULL << (InBits-1);
880 uint64_t NewBits = (~InMask) & Mask;
881 uint64_t InDemandedBits = Mask & InMask;
883 // If any of the sign extended bits are demanded, we know that the sign
886 InDemandedBits |= InSignBit;
888 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero,
890 // If the sign bit is known zero or one, the top bits match.
891 if (KnownZero & InSignBit) {
892 KnownZero |= NewBits;
893 KnownOne &= ~NewBits;
894 } else if (KnownOne & InSignBit) {
896 KnownZero &= ~NewBits;
897 } else { // Otherwise, top bits aren't known.
898 KnownOne &= ~NewBits;
899 KnownZero &= ~NewBits;
903 case ISD::ANY_EXTEND: {
904 MVT::ValueType VT = Op.getOperand(0).getValueType();
905 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT),
906 KnownZero, KnownOne, Depth+1);
909 case ISD::TRUNCATE: {
910 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
911 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
912 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
913 KnownZero &= OutMask;
917 case ISD::AssertZext: {
918 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
919 uint64_t InMask = MVT::getIntVTBitMask(VT);
920 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
922 KnownZero |= (~InMask) & Mask;
926 // If either the LHS or the RHS are Zero, the result is zero.
927 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
928 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
929 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
930 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
932 // Output known-0 bits are known if clear or set in both the low clear bits
933 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
935 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
936 CountTrailingZeros_64(~KnownZero2));
938 KnownZero = (1ULL << KnownZeroOut) - 1;
943 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
946 // We know that the top bits of C-X are clear if X contains less bits
947 // than C (i.e. no wrap-around can happen). For example, 20-X is
948 // positive if we can prove that X is >= 0 and < 16.
949 MVT::ValueType VT = CLHS->getValueType(0);
950 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
951 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
952 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
953 MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
954 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
956 // If all of the MaskV bits are known to be zero, then we know the output
957 // top bits are zero, because we now know that the output is from [0-C].
958 if ((KnownZero & MaskV) == MaskV) {
959 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
960 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
961 KnownOne = 0; // No one bits known.
963 KnownOne = KnownOne = 0; // Otherwise, nothing known.
969 // Allow the target to implement this method for its nodes.
970 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
971 case ISD::INTRINSIC_WO_CHAIN:
972 case ISD::INTRINSIC_W_CHAIN:
973 case ISD::INTRINSIC_VOID:
974 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
980 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
981 /// in Mask are known to be either zero or one and return them in the
982 /// KnownZero/KnownOne bitsets.
983 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
987 unsigned Depth) const {
988 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
989 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
990 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
991 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
992 "Should use MaskedValueIsZero if you don't know whether Op"
993 " is a target node!");
998 /// ComputeNumSignBits - Return the number of times the sign bit of the
999 /// register is replicated into the other bits. We know that at least 1 bit
1000 /// is always equal to the sign bit (itself), but other cases can give us
1001 /// information. For example, immediately after an "SRA X, 2", we know that
1002 /// the top 3 bits are all equal to each other, so we return 3.
1003 unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
1004 MVT::ValueType VT = Op.getValueType();
1005 assert(MVT::isInteger(VT) && "Invalid VT!");
1006 unsigned VTBits = MVT::getSizeInBits(VT);
1010 return 1; // Limit search depth.
1012 switch (Op.getOpcode()) {
1014 // Allow the target to implement this method for its nodes.
1015 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) {
1016 case ISD::INTRINSIC_WO_CHAIN:
1017 case ISD::INTRINSIC_W_CHAIN:
1018 case ISD::INTRINSIC_VOID:
1019 unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth);
1020 if (NumBits > 1) return NumBits;
1023 // FIXME: Should use computemaskedbits to look at the top bits.
1026 case ISD::AssertSext:
1027 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1028 return VTBits-Tmp+1;
1029 case ISD::AssertZext:
1030 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1033 case ISD::SIGN_EXTEND_INREG:
1034 // Max of the input and what this extends.
1035 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
1038 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1039 return std::max(Tmp, Tmp2);
1042 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1043 // SRA X, C -> adds C sign bits.
1044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1045 Tmp += C->getValue();
1046 if (Tmp > VTBits) Tmp = VTBits;
1052 // Add and sub can have at most one carry bit. Thus we know that the output
1053 // is, at worst, one more bit than the inputs.
1054 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
1055 if (Tmp == 1) return 1;
1056 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
1057 if (Tmp2 == 1) return 1;
1058 return std::min(Tmp, Tmp2)-1;
1060 //case ISD::ZEXTLOAD: // 16 bits known
1061 //case ISD::SEXTLOAD: // 17 bits known
1062 //case ISD::Constant:
1063 //case ISD::SIGN_EXTEND:
1068 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1069 if (N0.getOpcode() == ISD::SETCC &&
1070 TLI.getSetCCResultContents() ==
1071 TargetLowering::ZeroOrNegativeOneSetCCResult)
1078 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1079 /// targets that want to expose additional information about sign bits to the
1081 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1082 unsigned Depth) const {
1083 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1084 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1085 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1086 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1087 "Should use ComputeNumSignBits if you don't know whether Op"
1088 " is a target node!");
1093 SDOperand TargetLowering::
1094 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1095 // Default implementation: no optimization.
1099 //===----------------------------------------------------------------------===//
1100 // Inline Assembler Implementation Methods
1101 //===----------------------------------------------------------------------===//
1103 TargetLowering::ConstraintType
1104 TargetLowering::getConstraintType(char ConstraintLetter) const {
1105 // FIXME: lots more standard ones to handle.
1106 switch (ConstraintLetter) {
1107 default: return C_Unknown;
1108 case 'r': return C_RegisterClass;
1110 case 'o': // offsetable
1111 case 'V': // not offsetable
1113 case 'i': // Simple Integer or Relocatable Constant
1114 case 'n': // Simple Integer
1115 case 's': // Relocatable Constant
1116 case 'I': // Target registers.
1128 bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
1129 char ConstraintLetter) {
1130 switch (ConstraintLetter) {
1131 default: return false;
1132 case 'i': // Simple Integer or Relocatable Constant
1133 case 'n': // Simple Integer
1134 case 's': // Relocatable Constant
1135 return true; // FIXME: not right.
1140 std::vector<unsigned> TargetLowering::
1141 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1142 MVT::ValueType VT) const {
1143 return std::vector<unsigned>();
1147 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1148 getRegForInlineAsmConstraint(const std::string &Constraint,
1149 MVT::ValueType VT) const {
1150 if (Constraint[0] != '{')
1151 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1152 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1154 // Remove the braces from around the name.
1155 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1157 // Figure out which register class contains this reg.
1158 const MRegisterInfo *RI = TM.getRegisterInfo();
1159 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1160 E = RI->regclass_end(); RCI != E; ++RCI) {
1161 const TargetRegisterClass *RC = *RCI;
1163 // If none of the the value types for this register class are valid, we
1164 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1165 bool isLegal = false;
1166 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1168 if (isTypeLegal(*I)) {
1174 if (!isLegal) continue;
1176 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1178 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1179 return std::make_pair(*I, RC);
1183 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1186 //===----------------------------------------------------------------------===//
1187 // Loop Strength Reduction hooks
1188 //===----------------------------------------------------------------------===//
1190 /// isLegalAddressImmediate - Return true if the integer value or
1191 /// GlobalValue can be used as the offset of the target addressing mode.
1192 bool TargetLowering::isLegalAddressImmediate(int64_t V) const {
1195 bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {