1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetAsmInfo.h"
15 #include "llvm/Target/TargetLowering.h"
16 #include "llvm/Target/TargetSubtarget.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/GlobalVariable.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/Support/MathExtras.h"
28 /// InitLibcallNames - Set default libcall names.
30 static void InitLibcallNames(const char **Names) {
31 Names[RTLIB::SHL_I32] = "__ashlsi3";
32 Names[RTLIB::SHL_I64] = "__ashldi3";
33 Names[RTLIB::SRL_I32] = "__lshrsi3";
34 Names[RTLIB::SRL_I64] = "__lshrdi3";
35 Names[RTLIB::SRA_I32] = "__ashrsi3";
36 Names[RTLIB::SRA_I64] = "__ashrdi3";
37 Names[RTLIB::MUL_I32] = "__mulsi3";
38 Names[RTLIB::MUL_I64] = "__muldi3";
39 Names[RTLIB::SDIV_I32] = "__divsi3";
40 Names[RTLIB::SDIV_I64] = "__divdi3";
41 Names[RTLIB::UDIV_I32] = "__udivsi3";
42 Names[RTLIB::UDIV_I64] = "__udivdi3";
43 Names[RTLIB::SREM_I32] = "__modsi3";
44 Names[RTLIB::SREM_I64] = "__moddi3";
45 Names[RTLIB::UREM_I32] = "__umodsi3";
46 Names[RTLIB::UREM_I64] = "__umoddi3";
47 Names[RTLIB::NEG_I32] = "__negsi2";
48 Names[RTLIB::NEG_I64] = "__negdi2";
49 Names[RTLIB::ADD_F32] = "__addsf3";
50 Names[RTLIB::ADD_F64] = "__adddf3";
51 Names[RTLIB::ADD_F80] = "__addxf3";
52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
53 Names[RTLIB::SUB_F32] = "__subsf3";
54 Names[RTLIB::SUB_F64] = "__subdf3";
55 Names[RTLIB::SUB_F80] = "__subxf3";
56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
57 Names[RTLIB::MUL_F32] = "__mulsf3";
58 Names[RTLIB::MUL_F64] = "__muldf3";
59 Names[RTLIB::MUL_F80] = "__mulxf3";
60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
61 Names[RTLIB::DIV_F32] = "__divsf3";
62 Names[RTLIB::DIV_F64] = "__divdf3";
63 Names[RTLIB::DIV_F80] = "__divxf3";
64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
65 Names[RTLIB::REM_F32] = "fmodf";
66 Names[RTLIB::REM_F64] = "fmod";
67 Names[RTLIB::REM_F80] = "fmodl";
68 Names[RTLIB::REM_PPCF128] = "fmodl";
69 Names[RTLIB::POWI_F32] = "__powisf2";
70 Names[RTLIB::POWI_F64] = "__powidf2";
71 Names[RTLIB::POWI_F80] = "__powixf2";
72 Names[RTLIB::POWI_PPCF128] = "__powitf2";
73 Names[RTLIB::SQRT_F32] = "sqrtf";
74 Names[RTLIB::SQRT_F64] = "sqrt";
75 Names[RTLIB::SQRT_F80] = "sqrtl";
76 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
77 Names[RTLIB::SIN_F32] = "sinf";
78 Names[RTLIB::SIN_F64] = "sin";
79 Names[RTLIB::SIN_F80] = "sinl";
80 Names[RTLIB::SIN_PPCF128] = "sinl";
81 Names[RTLIB::COS_F32] = "cosf";
82 Names[RTLIB::COS_F64] = "cos";
83 Names[RTLIB::COS_F80] = "cosl";
84 Names[RTLIB::COS_PPCF128] = "cosl";
85 Names[RTLIB::POW_F32] = "powf";
86 Names[RTLIB::POW_F64] = "pow";
87 Names[RTLIB::POW_F80] = "powl";
88 Names[RTLIB::POW_PPCF128] = "powl";
89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
93 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
94 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
95 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
96 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
97 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
98 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
99 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
100 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
101 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
102 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
103 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
104 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
105 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
106 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
107 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
108 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
109 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
110 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
111 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
112 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
113 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
114 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
115 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
116 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
117 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
118 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
119 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
120 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
121 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
122 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
123 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
124 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
125 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
126 Names[RTLIB::OEQ_F32] = "__eqsf2";
127 Names[RTLIB::OEQ_F64] = "__eqdf2";
128 Names[RTLIB::UNE_F32] = "__nesf2";
129 Names[RTLIB::UNE_F64] = "__nedf2";
130 Names[RTLIB::OGE_F32] = "__gesf2";
131 Names[RTLIB::OGE_F64] = "__gedf2";
132 Names[RTLIB::OLT_F32] = "__ltsf2";
133 Names[RTLIB::OLT_F64] = "__ltdf2";
134 Names[RTLIB::OLE_F32] = "__lesf2";
135 Names[RTLIB::OLE_F64] = "__ledf2";
136 Names[RTLIB::OGT_F32] = "__gtsf2";
137 Names[RTLIB::OGT_F64] = "__gtdf2";
138 Names[RTLIB::UO_F32] = "__unordsf2";
139 Names[RTLIB::UO_F64] = "__unorddf2";
140 Names[RTLIB::O_F32] = "__unordsf2";
141 Names[RTLIB::O_F64] = "__unorddf2";
144 /// InitCmpLibcallCCs - Set default comparison libcall CC.
146 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
147 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
148 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
149 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
150 CCs[RTLIB::UNE_F32] = ISD::SETNE;
151 CCs[RTLIB::UNE_F64] = ISD::SETNE;
152 CCs[RTLIB::OGE_F32] = ISD::SETGE;
153 CCs[RTLIB::OGE_F64] = ISD::SETGE;
154 CCs[RTLIB::OLT_F32] = ISD::SETLT;
155 CCs[RTLIB::OLT_F64] = ISD::SETLT;
156 CCs[RTLIB::OLE_F32] = ISD::SETLE;
157 CCs[RTLIB::OLE_F64] = ISD::SETLE;
158 CCs[RTLIB::OGT_F32] = ISD::SETGT;
159 CCs[RTLIB::OGT_F64] = ISD::SETGT;
160 CCs[RTLIB::UO_F32] = ISD::SETNE;
161 CCs[RTLIB::UO_F64] = ISD::SETNE;
162 CCs[RTLIB::O_F32] = ISD::SETEQ;
163 CCs[RTLIB::O_F64] = ISD::SETEQ;
166 TargetLowering::TargetLowering(TargetMachine &tm)
167 : TM(tm), TD(TM.getTargetData()) {
168 assert(ISD::BUILTIN_OP_END <= 156 &&
169 "Fixed size array in TargetLowering is not large enough!");
170 // All operations default to being supported.
171 memset(OpActions, 0, sizeof(OpActions));
172 memset(LoadXActions, 0, sizeof(LoadXActions));
173 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
174 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
175 memset(ConvertActions, 0, sizeof(ConvertActions));
177 // Set default actions for various operations.
178 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
179 // Default all indexed load / store to expand.
180 for (unsigned IM = (unsigned)ISD::PRE_INC;
181 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
182 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
183 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
186 // These operations default to expand.
187 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand);
190 // Most targets ignore the @llvm.prefetch intrinsic.
191 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
193 // ConstantFP nodes default to expand. Targets can either change this to
194 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
195 // to optimize expansions for certain constants.
196 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
197 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
198 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
200 // Default ISD::TRAP to expand (which turns it into abort).
201 setOperationAction(ISD::TRAP, MVT::Other, Expand);
203 IsLittleEndian = TD->isLittleEndian();
204 UsesGlobalOffsetTable = false;
205 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
206 ShiftAmtHandling = Undefined;
207 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
208 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
209 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
210 allowUnalignedMemoryAccesses = false;
211 UseUnderscoreSetJmp = false;
212 UseUnderscoreLongJmp = false;
213 SelectIsExpensive = false;
214 IntDivIsCheap = false;
215 Pow2DivIsCheap = false;
216 StackPointerRegisterToSaveRestore = 0;
217 ExceptionPointerRegister = 0;
218 ExceptionSelectorRegister = 0;
219 SetCCResultContents = UndefinedSetCCResult;
220 SchedPreferenceInfo = SchedulingForLatency;
222 JumpBufAlignment = 0;
223 IfCvtBlockSizeLimit = 2;
224 IfCvtDupBlockSizeLimit = 0;
225 PrefLoopAlignment = 0;
227 InitLibcallNames(LibcallRoutineNames);
228 InitCmpLibcallCCs(CmpLibcallCCs);
230 // Tell Legalize whether the assembler supports DEBUG_LOC.
231 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile())
232 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
235 TargetLowering::~TargetLowering() {}
237 /// computeRegisterProperties - Once all of the register classes are added,
238 /// this allows us to compute derived properties we expose.
239 void TargetLowering::computeRegisterProperties() {
240 assert(MVT::LAST_VALUETYPE <= 32 &&
241 "Too many value types for ValueTypeActions to hold!");
243 // Everything defaults to needing one register.
244 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
245 NumRegistersForVT[i] = 1;
246 RegisterTypeForVT[i] = TransformToType[i] = i;
248 // ...except isVoid, which doesn't need any registers.
249 NumRegistersForVT[MVT::isVoid] = 0;
251 // Find the largest integer register class.
252 unsigned LargestIntReg = MVT::i128;
253 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
254 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
256 // Every integer value type larger than this largest register takes twice as
257 // many registers to represent as the previous ValueType.
258 for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
259 MVT::isInteger(ExpandedReg); ++ExpandedReg) {
260 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
261 RegisterTypeForVT[ExpandedReg] = LargestIntReg;
262 TransformToType[ExpandedReg] = ExpandedReg - 1;
263 ValueTypeActions.setTypeAction(ExpandedReg, Expand);
266 // Inspect all of the ValueType's smaller than the largest integer
267 // register to see which ones need promotion.
268 MVT::ValueType LegalIntReg = LargestIntReg;
269 for (MVT::ValueType IntReg = LargestIntReg - 1;
270 IntReg >= MVT::i1; --IntReg) {
271 if (isTypeLegal(IntReg)) {
272 LegalIntReg = IntReg;
274 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
275 ValueTypeActions.setTypeAction(IntReg, Promote);
279 // ppcf128 type is really two f64's.
280 if (!isTypeLegal(MVT::ppcf128)) {
281 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
282 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
283 TransformToType[MVT::ppcf128] = MVT::f64;
284 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
287 // Decide how to handle f64. If the target does not have native f64 support,
288 // expand it to i64 and we will be generating soft float library calls.
289 if (!isTypeLegal(MVT::f64)) {
290 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
291 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
292 TransformToType[MVT::f64] = MVT::i64;
293 ValueTypeActions.setTypeAction(MVT::f64, Expand);
296 // Decide how to handle f32. If the target does not have native support for
297 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
298 if (!isTypeLegal(MVT::f32)) {
299 if (isTypeLegal(MVT::f64)) {
300 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
301 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
302 TransformToType[MVT::f32] = MVT::f64;
303 ValueTypeActions.setTypeAction(MVT::f32, Promote);
305 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
306 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
307 TransformToType[MVT::f32] = MVT::i32;
308 ValueTypeActions.setTypeAction(MVT::f32, Expand);
312 // Loop over all of the vector value types to see which need transformations.
313 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
315 if (!isTypeLegal(i)) {
316 MVT::ValueType IntermediateVT, RegisterVT;
317 unsigned NumIntermediates;
318 NumRegistersForVT[i] =
319 getVectorTypeBreakdown(i,
320 IntermediateVT, NumIntermediates,
322 RegisterTypeForVT[i] = RegisterVT;
323 TransformToType[i] = MVT::Other; // this isn't actually used
324 ValueTypeActions.setTypeAction(i, Expand);
329 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
335 TargetLowering::getSetCCResultType(const SDOperand &) const {
336 return getValueType(TD->getIntPtrType());
340 /// getVectorTypeBreakdown - Vector types are broken down into some number of
341 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
342 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
343 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
345 /// This method returns the number of registers needed, and the VT for each
346 /// register. It also returns the VT and quantity of the intermediate values
347 /// before they are promoted/expanded.
349 unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
350 MVT::ValueType &IntermediateVT,
351 unsigned &NumIntermediates,
352 MVT::ValueType &RegisterVT) const {
353 // Figure out the right, legal destination reg to copy into.
354 unsigned NumElts = MVT::getVectorNumElements(VT);
355 MVT::ValueType EltTy = MVT::getVectorElementType(VT);
357 unsigned NumVectorRegs = 1;
359 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
360 // could break down into LHS/RHS like LegalizeDAG does.
361 if (!isPowerOf2_32(NumElts)) {
362 NumVectorRegs = NumElts;
366 // Divide the input until we get to a supported size. This will always
367 // end with a scalar if the target doesn't support vectors.
368 while (NumElts > 1 &&
369 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
374 NumIntermediates = NumVectorRegs;
376 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
377 if (!isTypeLegal(NewVT))
379 IntermediateVT = NewVT;
381 MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
383 if (DestVT < NewVT) {
384 // Value is expanded, e.g. i64 -> i16.
385 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
387 // Otherwise, promotion or legal types use the same number of registers as
388 // the vector decimated to the appropriate level.
389 return NumVectorRegs;
395 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
396 /// function arguments in the caller parameter area. This is the actual
397 /// alignment, not its logarithm.
398 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
399 return TD->getCallFrameTypeAlignment(Ty);
402 SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
403 SelectionDAG &DAG) const {
404 if (usesGlobalOffsetTable())
405 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
409 //===----------------------------------------------------------------------===//
410 // Optimization Methods
411 //===----------------------------------------------------------------------===//
413 /// ShrinkDemandedConstant - Check to see if the specified operand of the
414 /// specified instruction is a constant integer. If so, check to see if there
415 /// are any bits set in the constant that are not demanded. If so, shrink the
416 /// constant and return true.
417 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
418 const APInt &Demanded) {
419 // FIXME: ISD::SELECT, ISD::SELECT_CC
420 switch(Op.getOpcode()) {
425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
426 if (C->getAPIntValue().intersects(~Demanded)) {
427 MVT::ValueType VT = Op.getValueType();
428 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
429 DAG.getConstant(Demanded &
432 return CombineTo(Op, New);
439 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
440 /// DemandedMask bits of the result of Op are ever used downstream. If we can
441 /// use this information to simplify Op, create a new simplified DAG node and
442 /// return true, returning the original and new nodes in Old and New. Otherwise,
443 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
444 /// the expression (used to simplify the caller). The KnownZero/One bits may
445 /// only be accurate for those bits in the DemandedMask.
446 bool TargetLowering::SimplifyDemandedBits(SDOperand Op,
447 const APInt &DemandedMask,
450 TargetLoweringOpt &TLO,
451 unsigned Depth) const {
452 unsigned BitWidth = DemandedMask.getBitWidth();
453 assert(Op.getValueSizeInBits() == BitWidth &&
454 "Mask size mismatches value type size!");
455 APInt NewMask = DemandedMask;
457 // Don't know anything.
458 KnownZero = KnownOne = APInt(BitWidth, 0);
460 // Other users may use these bits.
461 if (!Op.Val->hasOneUse()) {
463 // If not at the root, Just compute the KnownZero/KnownOne bits to
464 // simplify things downstream.
465 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
468 // If this is the root being simplified, allow it to have multiple uses,
469 // just set the NewMask to all bits.
470 NewMask = APInt::getAllOnesValue(BitWidth);
471 } else if (DemandedMask == 0) {
472 // Not demanding any bits from Op.
473 if (Op.getOpcode() != ISD::UNDEF)
474 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
476 } else if (Depth == 6) { // Limit search depth.
480 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
481 switch (Op.getOpcode()) {
483 // We know all of the bits for a constant!
484 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
485 KnownZero = ~KnownOne & NewMask;
486 return false; // Don't fall through, will infinitely loop.
488 // If the RHS is a constant, check to see if the LHS would be zero without
489 // using the bits from the RHS. Below, we use knowledge about the RHS to
490 // simplify the LHS, here we're using information from the LHS to simplify
492 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
493 APInt LHSZero, LHSOne;
494 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
495 LHSZero, LHSOne, Depth+1);
496 // If the LHS already has zeros where RHSC does, this and is dead.
497 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
498 return TLO.CombineTo(Op, Op.getOperand(0));
499 // If any of the set bits in the RHS are known zero on the LHS, shrink
501 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
505 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
506 KnownOne, TLO, Depth+1))
508 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
509 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
510 KnownZero2, KnownOne2, TLO, Depth+1))
512 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
514 // If all of the demanded bits are known one on one side, return the other.
515 // These bits cannot contribute to the result of the 'and'.
516 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
517 return TLO.CombineTo(Op, Op.getOperand(0));
518 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
519 return TLO.CombineTo(Op, Op.getOperand(1));
520 // If all of the demanded bits in the inputs are known zeros, return zero.
521 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
522 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
523 // If the RHS is a constant, see if we can simplify it.
524 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
527 // Output known-1 bits are only known if set in both the LHS & RHS.
528 KnownOne &= KnownOne2;
529 // Output known-0 are known to be clear if zero in either the LHS | RHS.
530 KnownZero |= KnownZero2;
533 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
534 KnownOne, TLO, Depth+1))
536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
537 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
538 KnownZero2, KnownOne2, TLO, Depth+1))
540 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
542 // If all of the demanded bits are known zero on one side, return the other.
543 // These bits cannot contribute to the result of the 'or'.
544 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
545 return TLO.CombineTo(Op, Op.getOperand(0));
546 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
547 return TLO.CombineTo(Op, Op.getOperand(1));
548 // If all of the potentially set bits on one side are known to be set on
549 // the other side, just use the 'other' side.
550 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
551 return TLO.CombineTo(Op, Op.getOperand(0));
552 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
553 return TLO.CombineTo(Op, Op.getOperand(1));
554 // If the RHS is a constant, see if we can simplify it.
555 if (TLO.ShrinkDemandedConstant(Op, NewMask))
558 // Output known-0 bits are only known if clear in both the LHS & RHS.
559 KnownZero &= KnownZero2;
560 // Output known-1 are known to be set if set in either the LHS | RHS.
561 KnownOne |= KnownOne2;
564 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
565 KnownOne, TLO, Depth+1))
567 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
568 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
569 KnownOne2, TLO, Depth+1))
571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
573 // If all of the demanded bits are known zero on one side, return the other.
574 // These bits cannot contribute to the result of the 'xor'.
575 if ((KnownZero & NewMask) == NewMask)
576 return TLO.CombineTo(Op, Op.getOperand(0));
577 if ((KnownZero2 & NewMask) == NewMask)
578 return TLO.CombineTo(Op, Op.getOperand(1));
580 // If all of the unknown bits are known to be zero on one side or the other
581 // (but not both) turn this into an *inclusive* or.
582 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
583 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
588 // Output known-0 bits are known if clear or set in both the LHS & RHS.
589 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
590 // Output known-1 are known to be set if set in only one of the LHS, RHS.
591 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
593 // If all of the demanded bits on one side are known, and all of the set
594 // bits on that side are also known to be set on the other side, turn this
595 // into an AND, as we know the bits will be cleared.
596 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
597 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
598 if ((KnownOne & KnownOne2) == KnownOne) {
599 MVT::ValueType VT = Op.getValueType();
600 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
601 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
606 // If the RHS is a constant, see if we can simplify it.
607 // for XOR, we prefer to force bits to 1 if they will make a -1.
608 // if we can't force bits, try to shrink constant
609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
610 APInt Expanded = C->getAPIntValue() | (~NewMask);
611 // if we can expand it to have all bits set, do it
612 if (Expanded.isAllOnesValue()) {
613 if (Expanded != C->getAPIntValue()) {
614 MVT::ValueType VT = Op.getValueType();
615 SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
616 TLO.DAG.getConstant(Expanded, VT));
617 return TLO.CombineTo(Op, New);
619 // if it already has all the bits set, nothing to change
620 // but don't shrink either!
621 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
626 KnownZero = KnownZeroOut;
627 KnownOne = KnownOneOut;
630 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
631 KnownOne, TLO, Depth+1))
633 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
634 KnownOne2, TLO, Depth+1))
636 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
637 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
639 // If the operands are constants, see if we can simplify them.
640 if (TLO.ShrinkDemandedConstant(Op, NewMask))
643 // Only known if known in both the LHS and RHS.
644 KnownOne &= KnownOne2;
645 KnownZero &= KnownZero2;
648 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
649 KnownOne, TLO, Depth+1))
651 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
652 KnownOne2, TLO, Depth+1))
654 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
655 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
657 // If the operands are constants, see if we can simplify them.
658 if (TLO.ShrinkDemandedConstant(Op, NewMask))
661 // Only known if known in both the LHS and RHS.
662 KnownOne &= KnownOne2;
663 KnownZero &= KnownZero2;
666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
667 unsigned ShAmt = SA->getValue();
668 SDOperand InOp = Op.getOperand(0);
670 // If the shift count is an invalid immediate, don't do anything.
671 if (ShAmt >= BitWidth)
674 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
675 // single shift. We can do this if the bottom bits (which are shifted
676 // out) are never demanded.
677 if (InOp.getOpcode() == ISD::SRL &&
678 isa<ConstantSDNode>(InOp.getOperand(1))) {
679 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
680 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
681 unsigned Opc = ISD::SHL;
689 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
690 MVT::ValueType VT = Op.getValueType();
691 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
692 InOp.getOperand(0), NewSA));
696 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
697 KnownZero, KnownOne, TLO, Depth+1))
699 KnownZero <<= SA->getValue();
700 KnownOne <<= SA->getValue();
701 // low bits known zero.
702 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue());
706 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
707 MVT::ValueType VT = Op.getValueType();
708 unsigned ShAmt = SA->getValue();
709 unsigned VTSize = MVT::getSizeInBits(VT);
710 SDOperand InOp = Op.getOperand(0);
712 // If the shift count is an invalid immediate, don't do anything.
713 if (ShAmt >= BitWidth)
716 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
717 // single shift. We can do this if the top bits (which are shifted out)
718 // are never demanded.
719 if (InOp.getOpcode() == ISD::SHL &&
720 isa<ConstantSDNode>(InOp.getOperand(1))) {
721 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
722 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
723 unsigned Opc = ISD::SRL;
731 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
732 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
733 InOp.getOperand(0), NewSA));
737 // Compute the new bits that are at the top now.
738 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
739 KnownZero, KnownOne, TLO, Depth+1))
741 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
742 KnownZero = KnownZero.lshr(ShAmt);
743 KnownOne = KnownOne.lshr(ShAmt);
745 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
746 KnownZero |= HighBits; // High bits known zero.
750 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
751 MVT::ValueType VT = Op.getValueType();
752 unsigned ShAmt = SA->getValue();
754 // If the shift count is an invalid immediate, don't do anything.
755 if (ShAmt >= BitWidth)
758 APInt InDemandedMask = (NewMask << ShAmt);
760 // If any of the demanded bits are produced by the sign extension, we also
761 // demand the input sign bit.
762 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
763 if (HighBits.intersects(NewMask))
764 InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT));
766 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
767 KnownZero, KnownOne, TLO, Depth+1))
769 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
770 KnownZero = KnownZero.lshr(ShAmt);
771 KnownOne = KnownOne.lshr(ShAmt);
773 // Handle the sign bit, adjusted to where it is now in the mask.
774 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
776 // If the input sign bit is known to be zero, or if none of the top bits
777 // are demanded, turn this into an unsigned shift right.
778 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
779 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
781 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
782 KnownOne |= HighBits;
786 case ISD::SIGN_EXTEND_INREG: {
787 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
789 // Sign extension. Compute the demanded bits in the result that are not
790 // present in the input.
791 APInt NewBits = APInt::getHighBitsSet(BitWidth,
792 BitWidth - MVT::getSizeInBits(EVT)) &
795 // If none of the extended bits are demanded, eliminate the sextinreg.
797 return TLO.CombineTo(Op, Op.getOperand(0));
799 APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT));
800 InSignBit.zext(BitWidth);
801 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
802 MVT::getSizeInBits(EVT)) &
805 // Since the sign extended bits are demanded, we know that the sign
807 InputDemandedBits |= InSignBit;
809 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
810 KnownZero, KnownOne, TLO, Depth+1))
812 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
814 // If the sign bit of the input is known set or clear, then we know the
815 // top bits of the result.
817 // If the input sign bit is known zero, convert this into a zero extension.
818 if (KnownZero.intersects(InSignBit))
819 return TLO.CombineTo(Op,
820 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
822 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
824 KnownZero &= ~NewBits;
825 } else { // Input sign bit unknown
826 KnownZero &= ~NewBits;
827 KnownOne &= ~NewBits;
831 case ISD::ZERO_EXTEND: {
832 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
833 APInt InMask = NewMask;
834 InMask.trunc(OperandBitWidth);
836 // If none of the top bits are demanded, convert this into an any_extend.
838 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
839 if (!NewBits.intersects(NewMask))
840 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
844 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
845 KnownZero, KnownOne, TLO, Depth+1))
847 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
848 KnownZero.zext(BitWidth);
849 KnownOne.zext(BitWidth);
850 KnownZero |= NewBits;
853 case ISD::SIGN_EXTEND: {
854 MVT::ValueType InVT = Op.getOperand(0).getValueType();
855 unsigned InBits = MVT::getSizeInBits(InVT);
856 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
857 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
858 APInt NewBits = ~InMask & NewMask;
860 // If none of the top bits are demanded, convert this into an any_extend.
862 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
865 // Since some of the sign extended bits are demanded, we know that the sign
867 APInt InDemandedBits = InMask & NewMask;
868 InDemandedBits |= InSignBit;
869 InDemandedBits.trunc(InBits);
871 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
872 KnownOne, TLO, Depth+1))
874 KnownZero.zext(BitWidth);
875 KnownOne.zext(BitWidth);
877 // If the sign bit is known zero, convert this to a zero extend.
878 if (KnownZero.intersects(InSignBit))
879 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
883 // If the sign bit is known one, the top bits match.
884 if (KnownOne.intersects(InSignBit)) {
886 KnownZero &= ~NewBits;
887 } else { // Otherwise, top bits aren't known.
888 KnownOne &= ~NewBits;
889 KnownZero &= ~NewBits;
893 case ISD::ANY_EXTEND: {
894 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
895 APInt InMask = NewMask;
896 InMask.trunc(OperandBitWidth);
897 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
898 KnownZero, KnownOne, TLO, Depth+1))
900 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
901 KnownZero.zext(BitWidth);
902 KnownOne.zext(BitWidth);
905 case ISD::TRUNCATE: {
906 // Simplify the input, using demanded bit information, and compute the known
907 // zero/one bits live out.
908 APInt TruncMask = NewMask;
909 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
910 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
911 KnownZero, KnownOne, TLO, Depth+1))
913 KnownZero.trunc(BitWidth);
914 KnownOne.trunc(BitWidth);
916 // If the input is only used by this truncate, see if we can shrink it based
917 // on the known demanded bits.
918 if (Op.getOperand(0).Val->hasOneUse()) {
919 SDOperand In = Op.getOperand(0);
920 unsigned InBitWidth = In.getValueSizeInBits();
921 switch (In.getOpcode()) {
924 // Shrink SRL by a constant if none of the high bits shifted in are
926 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
927 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
928 InBitWidth - BitWidth);
929 HighBits = HighBits.lshr(ShAmt->getValue());
930 HighBits.trunc(BitWidth);
932 if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) {
933 // None of the shifted in bits are needed. Add a truncate of the
934 // shift input, then shift it.
935 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
938 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
939 NewTrunc, In.getOperand(1)));
946 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
949 case ISD::AssertZext: {
950 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
951 APInt InMask = APInt::getLowBitsSet(BitWidth,
952 MVT::getSizeInBits(VT));
953 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
954 KnownZero, KnownOne, TLO, Depth+1))
956 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
957 KnownZero |= ~InMask & NewMask;
960 case ISD::BIT_CONVERT:
962 // If this is an FP->Int bitcast and if the sign bit is the only thing that
963 // is demanded, turn this into a FGETSIGN.
964 if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) &&
965 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
966 !MVT::isVector(Op.getOperand(0).getValueType())) {
967 // Only do this xform if FGETSIGN is valid or if before legalize.
968 if (!TLO.AfterLegalize ||
969 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
970 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
971 // place. We expect the SHL to be eliminated by other optimizations.
972 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
974 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1;
975 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
976 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
984 case ISD::INTRINSIC_WO_CHAIN:
985 case ISD::INTRINSIC_W_CHAIN:
986 case ISD::INTRINSIC_VOID:
993 // Just use ComputeMaskedBits to compute output bits.
994 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
998 // If we know the value of all of the demanded bits, return this as a
1000 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1001 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1006 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1007 /// in Mask are known to be either zero or one and return them in the
1008 /// KnownZero/KnownOne bitsets.
1009 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1013 const SelectionDAG &DAG,
1014 unsigned Depth) const {
1015 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1016 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1017 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1018 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1019 "Should use MaskedValueIsZero if you don't know whether Op"
1020 " is a target node!");
1021 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1024 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1025 /// targets that want to expose additional information about sign bits to the
1027 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1028 unsigned Depth) const {
1029 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1030 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1031 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1032 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1033 "Should use ComputeNumSignBits if you don't know whether Op"
1034 " is a target node!");
1039 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1040 /// and cc. If it is unable to simplify it, return a null SDOperand.
1042 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
1043 ISD::CondCode Cond, bool foldBooleans,
1044 DAGCombinerInfo &DCI) const {
1045 SelectionDAG &DAG = DCI.DAG;
1047 // These setcc operations always fold.
1051 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1053 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1056 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1057 const APInt &C1 = N1C->getAPIntValue();
1058 if (isa<ConstantSDNode>(N0.Val)) {
1059 return DAG.FoldSetCC(VT, N0, N1, Cond);
1061 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1062 // equality comparison, then we're just comparing whether X itself is
1064 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1065 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1066 N0.getOperand(1).getOpcode() == ISD::Constant) {
1067 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1068 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1069 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
1070 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1071 // (srl (ctlz x), 5) == 0 -> X != 0
1072 // (srl (ctlz x), 5) != 1 -> X != 0
1075 // (srl (ctlz x), 5) != 0 -> X == 0
1076 // (srl (ctlz x), 5) == 1 -> X == 0
1079 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
1080 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
1085 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1086 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1087 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1089 // If the comparison constant has bits in the upper part, the
1090 // zero-extended value could never match.
1091 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1092 C1.getBitWidth() - InSize))) {
1096 case ISD::SETEQ: return DAG.getConstant(0, VT);
1099 case ISD::SETNE: return DAG.getConstant(1, VT);
1102 // True if the sign bit of C1 is set.
1103 return DAG.getConstant(C1.isNegative(), VT);
1106 // True if the sign bit of C1 isn't set.
1107 return DAG.getConstant(C1.isNonNegative(), VT);
1113 // Otherwise, we can perform the comparison with the low bits.
1121 return DAG.getSetCC(VT, N0.getOperand(0),
1122 DAG.getConstant(APInt(C1).trunc(InSize),
1123 N0.getOperand(0).getValueType()),
1126 break; // todo, be more careful with signed comparisons
1128 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1129 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1130 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1131 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1132 MVT::ValueType ExtDstTy = N0.getValueType();
1133 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1135 // If the extended part has any inconsistent bits, it cannot ever
1136 // compare equal. In other words, they have to be all ones or all
1139 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1140 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1141 return DAG.getConstant(Cond == ISD::SETNE, VT);
1144 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1145 if (Op0Ty == ExtSrcTy) {
1146 ZextOp = N0.getOperand(0);
1148 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1149 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1150 DAG.getConstant(Imm, Op0Ty));
1152 if (!DCI.isCalledByLegalizer())
1153 DCI.AddToWorklist(ZextOp.Val);
1154 // Otherwise, make this a use of a zext.
1155 return DAG.getSetCC(VT, ZextOp,
1156 DAG.getConstant(C1 & APInt::getLowBitsSet(
1161 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1162 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1164 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1165 if (N0.getOpcode() == ISD::SETCC) {
1166 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1170 // Invert the condition.
1171 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1172 CC = ISD::getSetCCInverse(CC,
1173 MVT::isInteger(N0.getOperand(0).getValueType()));
1174 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1177 if ((N0.getOpcode() == ISD::XOR ||
1178 (N0.getOpcode() == ISD::AND &&
1179 N0.getOperand(0).getOpcode() == ISD::XOR &&
1180 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1181 isa<ConstantSDNode>(N0.getOperand(1)) &&
1182 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1183 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1184 // can only do this if the top bits are known zero.
1185 unsigned BitWidth = N0.getValueSizeInBits();
1186 if (DAG.MaskedValueIsZero(N0,
1187 APInt::getHighBitsSet(BitWidth,
1189 // Okay, get the un-inverted input value.
1191 if (N0.getOpcode() == ISD::XOR)
1192 Val = N0.getOperand(0);
1194 assert(N0.getOpcode() == ISD::AND &&
1195 N0.getOperand(0).getOpcode() == ISD::XOR);
1196 // ((X^1)&1)^1 -> X & 1
1197 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1198 N0.getOperand(0).getOperand(0),
1201 return DAG.getSetCC(VT, Val, N1,
1202 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1207 APInt MinVal, MaxVal;
1208 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1209 if (ISD::isSignedIntSetCC(Cond)) {
1210 MinVal = APInt::getSignedMinValue(OperandBitSize);
1211 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1213 MinVal = APInt::getMinValue(OperandBitSize);
1214 MaxVal = APInt::getMaxValue(OperandBitSize);
1217 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1218 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1219 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1220 // X >= C0 --> X > (C0-1)
1221 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()),
1222 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1225 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1226 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1227 // X <= C0 --> X < (C0+1)
1228 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()),
1229 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1232 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1233 return DAG.getConstant(0, VT); // X < MIN --> false
1234 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1235 return DAG.getConstant(1, VT); // X >= MIN --> true
1236 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1237 return DAG.getConstant(0, VT); // X > MAX --> false
1238 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1239 return DAG.getConstant(1, VT); // X <= MAX --> true
1241 // Canonicalize setgt X, Min --> setne X, Min
1242 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1243 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1244 // Canonicalize setlt X, Max --> setne X, Max
1245 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1246 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1248 // If we have setult X, 1, turn it into seteq X, 0
1249 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1250 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1252 // If we have setugt X, Max-1, turn it into seteq X, Max
1253 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1254 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1257 // If we have "setcc X, C0", check to see if we can shrink the immediate
1260 // SETUGT X, SINTMAX -> SETLT X, 0
1261 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1262 C1 == (~0ULL >> (65-OperandBitSize)))
1263 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1266 // FIXME: Implement the rest of these.
1268 // Fold bit comparisons when we can.
1269 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1270 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1271 if (ConstantSDNode *AndRHS =
1272 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1273 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1274 // Perform the xform if the AND RHS is a single bit.
1275 if (isPowerOf2_64(AndRHS->getValue())) {
1276 return DAG.getNode(ISD::SRL, VT, N0,
1277 DAG.getConstant(Log2_64(AndRHS->getValue()),
1278 getShiftAmountTy()));
1280 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1281 // (X & 8) == 8 --> (X & 8) >> 3
1282 // Perform the xform if C1 is a single bit.
1283 if (C1.isPowerOf2()) {
1284 return DAG.getNode(ISD::SRL, VT, N0,
1285 DAG.getConstant(C1.logBase2(), getShiftAmountTy()));
1290 } else if (isa<ConstantSDNode>(N0.Val)) {
1291 // Ensure that the constant occurs on the RHS.
1292 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1295 if (isa<ConstantFPSDNode>(N0.Val)) {
1296 // Constant fold or commute setcc.
1297 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1298 if (O.Val) return O;
1299 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) {
1300 // If the RHS of an FP comparison is a constant, simplify it away in
1302 if (CFP->getValueAPF().isNaN()) {
1303 // If an operand is known to be a nan, we can fold it.
1304 switch (ISD::getUnorderedFlavor(Cond)) {
1305 default: assert(0 && "Unknown flavor!");
1306 case 0: // Known false.
1307 return DAG.getConstant(0, VT);
1308 case 1: // Known true.
1309 return DAG.getConstant(1, VT);
1310 case 2: // Undefined.
1311 return DAG.getNode(ISD::UNDEF, VT);
1315 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1316 // constant if knowing that the operand is non-nan is enough. We prefer to
1317 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1319 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1320 return DAG.getSetCC(VT, N0, N0, Cond);
1324 // We can always fold X == X for integer setcc's.
1325 if (MVT::isInteger(N0.getValueType()))
1326 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1327 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1328 if (UOF == 2) // FP operators that are undefined on NaNs.
1329 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1330 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1331 return DAG.getConstant(UOF, VT);
1332 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1333 // if it is not already.
1334 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1335 if (NewCond != Cond)
1336 return DAG.getSetCC(VT, N0, N1, NewCond);
1339 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1340 MVT::isInteger(N0.getValueType())) {
1341 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1342 N0.getOpcode() == ISD::XOR) {
1343 // Simplify (X+Y) == (X+Z) --> Y == Z
1344 if (N0.getOpcode() == N1.getOpcode()) {
1345 if (N0.getOperand(0) == N1.getOperand(0))
1346 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1347 if (N0.getOperand(1) == N1.getOperand(1))
1348 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1349 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1350 // If X op Y == Y op X, try other combinations.
1351 if (N0.getOperand(0) == N1.getOperand(1))
1352 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1353 if (N0.getOperand(1) == N1.getOperand(0))
1354 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1358 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1359 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1360 // Turn (X+C1) == C2 --> X == C2-C1
1361 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1362 return DAG.getSetCC(VT, N0.getOperand(0),
1363 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1364 N0.getValueType()), Cond);
1367 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1368 if (N0.getOpcode() == ISD::XOR)
1369 // If we know that all of the inverted bits are zero, don't bother
1370 // performing the inversion.
1371 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1373 DAG.getSetCC(VT, N0.getOperand(0),
1374 DAG.getConstant(LHSR->getAPIntValue() ^
1375 RHSC->getAPIntValue(),
1380 // Turn (C1-X) == C2 --> X == C1-C2
1381 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1382 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1384 DAG.getSetCC(VT, N0.getOperand(1),
1385 DAG.getConstant(SUBC->getAPIntValue() -
1386 RHSC->getAPIntValue(),
1393 // Simplify (X+Z) == X --> Z == 0
1394 if (N0.getOperand(0) == N1)
1395 return DAG.getSetCC(VT, N0.getOperand(1),
1396 DAG.getConstant(0, N0.getValueType()), Cond);
1397 if (N0.getOperand(1) == N1) {
1398 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1399 return DAG.getSetCC(VT, N0.getOperand(0),
1400 DAG.getConstant(0, N0.getValueType()), Cond);
1401 else if (N0.Val->hasOneUse()) {
1402 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1403 // (Z-X) == X --> Z == X<<1
1404 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1406 DAG.getConstant(1, getShiftAmountTy()));
1407 if (!DCI.isCalledByLegalizer())
1408 DCI.AddToWorklist(SH.Val);
1409 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1414 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1415 N1.getOpcode() == ISD::XOR) {
1416 // Simplify X == (X+Z) --> Z == 0
1417 if (N1.getOperand(0) == N0) {
1418 return DAG.getSetCC(VT, N1.getOperand(1),
1419 DAG.getConstant(0, N1.getValueType()), Cond);
1420 } else if (N1.getOperand(1) == N0) {
1421 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1422 return DAG.getSetCC(VT, N1.getOperand(0),
1423 DAG.getConstant(0, N1.getValueType()), Cond);
1424 } else if (N1.Val->hasOneUse()) {
1425 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1426 // X == (Z-X) --> X<<1 == Z
1427 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1428 DAG.getConstant(1, getShiftAmountTy()));
1429 if (!DCI.isCalledByLegalizer())
1430 DCI.AddToWorklist(SH.Val);
1431 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1437 // Fold away ALL boolean setcc's.
1439 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1441 default: assert(0 && "Unknown integer setcc!");
1442 case ISD::SETEQ: // X == Y -> (X^Y)^1
1443 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1444 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1445 if (!DCI.isCalledByLegalizer())
1446 DCI.AddToWorklist(Temp.Val);
1448 case ISD::SETNE: // X != Y --> (X^Y)
1449 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1451 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1452 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1453 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1454 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1455 if (!DCI.isCalledByLegalizer())
1456 DCI.AddToWorklist(Temp.Val);
1458 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1459 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1460 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1461 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1462 if (!DCI.isCalledByLegalizer())
1463 DCI.AddToWorklist(Temp.Val);
1465 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1466 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1467 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1468 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1469 if (!DCI.isCalledByLegalizer())
1470 DCI.AddToWorklist(Temp.Val);
1472 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1473 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1474 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1475 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1478 if (VT != MVT::i1) {
1479 if (!DCI.isCalledByLegalizer())
1480 DCI.AddToWorklist(N0.Val);
1481 // FIXME: If running after legalize, we probably can't do this.
1482 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1487 // Could not fold it.
1491 SDOperand TargetLowering::
1492 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1493 // Default implementation: no optimization.
1497 //===----------------------------------------------------------------------===//
1498 // Inline Assembler Implementation Methods
1499 //===----------------------------------------------------------------------===//
1501 TargetLowering::ConstraintType
1502 TargetLowering::getConstraintType(const std::string &Constraint) const {
1503 // FIXME: lots more standard ones to handle.
1504 if (Constraint.size() == 1) {
1505 switch (Constraint[0]) {
1507 case 'r': return C_RegisterClass;
1509 case 'o': // offsetable
1510 case 'V': // not offsetable
1512 case 'i': // Simple Integer or Relocatable Constant
1513 case 'n': // Simple Integer
1514 case 's': // Relocatable Constant
1515 case 'X': // Allow ANY value.
1516 case 'I': // Target registers.
1528 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1529 Constraint[Constraint.size()-1] == '}')
1534 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1535 /// with another that has more specific requirements based on the type of the
1536 /// corresponding operand.
1537 void TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
1538 std::string& s) const {
1539 if (MVT::isInteger(ConstraintVT))
1541 else if (MVT::isFloatingPoint(ConstraintVT))
1542 s = "f"; // works for many targets
1547 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1548 /// vector. If it is invalid, don't add anything to Ops.
1549 void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
1550 char ConstraintLetter,
1551 std::vector<SDOperand> &Ops,
1552 SelectionDAG &DAG) {
1553 switch (ConstraintLetter) {
1555 case 'X': // Allows any operand; labels (basic block) use this.
1556 if (Op.getOpcode() == ISD::BasicBlock) {
1561 case 'i': // Simple Integer or Relocatable Constant
1562 case 'n': // Simple Integer
1563 case 's': { // Relocatable Constant
1564 // These operands are interested in values of the form (GV+C), where C may
1565 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1566 // is possible and fine if either GV or C are missing.
1567 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1568 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1570 // If we have "(add GV, C)", pull out GV/C
1571 if (Op.getOpcode() == ISD::ADD) {
1572 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1573 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1574 if (C == 0 || GA == 0) {
1575 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1576 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1578 if (C == 0 || GA == 0)
1582 // If we find a valid operand, map to the TargetXXX version so that the
1583 // value itself doesn't get selected.
1584 if (GA) { // Either &GV or &GV+C
1585 if (ConstraintLetter != 'n') {
1586 int64_t Offs = GA->getOffset();
1587 if (C) Offs += C->getValue();
1588 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1589 Op.getValueType(), Offs));
1593 if (C) { // just C, no GV.
1594 // Simple constants are not allowed for 's'.
1595 if (ConstraintLetter != 's') {
1596 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
1605 std::vector<unsigned> TargetLowering::
1606 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1607 MVT::ValueType VT) const {
1608 return std::vector<unsigned>();
1612 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1613 getRegForInlineAsmConstraint(const std::string &Constraint,
1614 MVT::ValueType VT) const {
1615 if (Constraint[0] != '{')
1616 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1617 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1619 // Remove the braces from around the name.
1620 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1622 // Figure out which register class contains this reg.
1623 const TargetRegisterInfo *RI = TM.getRegisterInfo();
1624 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1625 E = RI->regclass_end(); RCI != E; ++RCI) {
1626 const TargetRegisterClass *RC = *RCI;
1628 // If none of the the value types for this register class are valid, we
1629 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1630 bool isLegal = false;
1631 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1633 if (isTypeLegal(*I)) {
1639 if (!isLegal) continue;
1641 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1643 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
1644 return std::make_pair(*I, RC);
1648 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1651 //===----------------------------------------------------------------------===//
1652 // Loop Strength Reduction hooks
1653 //===----------------------------------------------------------------------===//
1655 /// isLegalAddressingMode - Return true if the addressing mode represented
1656 /// by AM is legal for this target, for a load/store of the specified type.
1657 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1658 const Type *Ty) const {
1659 // The default implementation of this implements a conservative RISCy, r+r and
1662 // Allows a sign-extended 16-bit immediate field.
1663 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1666 // No global is ever allowed as a base.
1670 // Only support r+r,
1672 case 0: // "r+i" or just "i", depending on HasBaseReg.
1675 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1677 // Otherwise we have r+r or r+i.
1680 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1682 // Allow 2*r as r+r.
1689 // Magic for divide replacement
1692 int64_t m; // magic number
1693 int64_t s; // shift amount
1697 uint64_t m; // magic number
1698 int64_t a; // add indicator
1699 int64_t s; // shift amount
1702 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1703 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1705 static ms magic32(int32_t d) {
1707 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1708 const uint32_t two31 = 0x80000000U;
1712 t = two31 + ((uint32_t)d >> 31);
1713 anc = t - 1 - t%ad; // absolute value of nc
1714 p = 31; // initialize p
1715 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1716 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1717 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1718 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1721 q1 = 2*q1; // update q1 = 2p/abs(nc)
1722 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1723 if (r1 >= anc) { // must be unsigned comparison
1727 q2 = 2*q2; // update q2 = 2p/abs(d)
1728 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1729 if (r2 >= ad) { // must be unsigned comparison
1734 } while (q1 < delta || (q1 == delta && r1 == 0));
1736 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1737 if (d < 0) mag.m = -mag.m; // resulting magic number
1738 mag.s = p - 32; // resulting shift
1742 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1743 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1744 static mu magicu32(uint32_t d) {
1746 uint32_t nc, delta, q1, r1, q2, r2;
1748 magu.a = 0; // initialize "add" indicator
1750 p = 31; // initialize p
1751 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1752 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1753 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1754 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1757 if (r1 >= nc - r1 ) {
1758 q1 = 2*q1 + 1; // update q1
1759 r1 = 2*r1 - nc; // update r1
1762 q1 = 2*q1; // update q1
1763 r1 = 2*r1; // update r1
1765 if (r2 + 1 >= d - r2) {
1766 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1767 q2 = 2*q2 + 1; // update q2
1768 r2 = 2*r2 + 1 - d; // update r2
1771 if (q2 >= 0x80000000) magu.a = 1;
1772 q2 = 2*q2; // update q2
1773 r2 = 2*r2 + 1; // update r2
1776 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1777 magu.m = q2 + 1; // resulting magic number
1778 magu.s = p - 32; // resulting shift
1782 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1783 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1785 static ms magic64(int64_t d) {
1787 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1788 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1791 ad = d >= 0 ? d : -d;
1792 t = two63 + ((uint64_t)d >> 63);
1793 anc = t - 1 - t%ad; // absolute value of nc
1794 p = 63; // initialize p
1795 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1796 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1797 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1798 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1801 q1 = 2*q1; // update q1 = 2p/abs(nc)
1802 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1803 if (r1 >= anc) { // must be unsigned comparison
1807 q2 = 2*q2; // update q2 = 2p/abs(d)
1808 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1809 if (r2 >= ad) { // must be unsigned comparison
1814 } while (q1 < delta || (q1 == delta && r1 == 0));
1817 if (d < 0) mag.m = -mag.m; // resulting magic number
1818 mag.s = p - 64; // resulting shift
1822 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1823 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1824 static mu magicu64(uint64_t d)
1827 uint64_t nc, delta, q1, r1, q2, r2;
1829 magu.a = 0; // initialize "add" indicator
1831 p = 63; // initialize p
1832 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1833 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1834 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1835 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1838 if (r1 >= nc - r1 ) {
1839 q1 = 2*q1 + 1; // update q1
1840 r1 = 2*r1 - nc; // update r1
1843 q1 = 2*q1; // update q1
1844 r1 = 2*r1; // update r1
1846 if (r2 + 1 >= d - r2) {
1847 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1848 q2 = 2*q2 + 1; // update q2
1849 r2 = 2*r2 + 1 - d; // update r2
1852 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1853 q2 = 2*q2; // update q2
1854 r2 = 2*r2 + 1; // update r2
1857 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1858 magu.m = q2 + 1; // resulting magic number
1859 magu.s = p - 64; // resulting shift
1863 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1864 /// return a DAG expression to select that will generate the same value by
1865 /// multiplying by a magic number. See:
1866 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1867 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1868 std::vector<SDNode*>* Created) const {
1869 MVT::ValueType VT = N->getValueType(0);
1871 // Check to see if we can do this.
1872 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1873 return SDOperand(); // BuildSDIV only operates on i32 or i64
1875 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1876 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1878 // Multiply the numerator (operand 0) by the magic value
1880 if (isOperationLegal(ISD::MULHS, VT))
1881 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1882 DAG.getConstant(magics.m, VT));
1883 else if (isOperationLegal(ISD::SMUL_LOHI, VT))
1884 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
1886 DAG.getConstant(magics.m, VT)).Val, 1);
1888 return SDOperand(); // No mulhs or equvialent
1889 // If d > 0 and m < 0, add the numerator
1890 if (d > 0 && magics.m < 0) {
1891 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1893 Created->push_back(Q.Val);
1895 // If d < 0 and m > 0, subtract the numerator.
1896 if (d < 0 && magics.m > 0) {
1897 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1899 Created->push_back(Q.Val);
1901 // Shift right algebraic if shift value is nonzero
1903 Q = DAG.getNode(ISD::SRA, VT, Q,
1904 DAG.getConstant(magics.s, getShiftAmountTy()));
1906 Created->push_back(Q.Val);
1908 // Extract the sign bit and add it to the quotient
1910 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1911 getShiftAmountTy()));
1913 Created->push_back(T.Val);
1914 return DAG.getNode(ISD::ADD, VT, Q, T);
1917 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1918 /// return a DAG expression to select that will generate the same value by
1919 /// multiplying by a magic number. See:
1920 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1921 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1922 std::vector<SDNode*>* Created) const {
1923 MVT::ValueType VT = N->getValueType(0);
1925 // Check to see if we can do this.
1926 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1927 return SDOperand(); // BuildUDIV only operates on i32 or i64
1929 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1930 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1932 // Multiply the numerator (operand 0) by the magic value
1934 if (isOperationLegal(ISD::MULHU, VT))
1935 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1936 DAG.getConstant(magics.m, VT));
1937 else if (isOperationLegal(ISD::UMUL_LOHI, VT))
1938 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
1940 DAG.getConstant(magics.m, VT)).Val, 1);
1942 return SDOperand(); // No mulhu or equvialent
1944 Created->push_back(Q.Val);
1946 if (magics.a == 0) {
1947 return DAG.getNode(ISD::SRL, VT, Q,
1948 DAG.getConstant(magics.s, getShiftAmountTy()));
1950 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1952 Created->push_back(NPQ.Val);
1953 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1954 DAG.getConstant(1, getShiftAmountTy()));
1956 Created->push_back(NPQ.Val);
1957 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1959 Created->push_back(NPQ.Val);
1960 return DAG.getNode(ISD::SRL, VT, NPQ,
1961 DAG.getConstant(magics.s-1, getShiftAmountTy()));