1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetSubtarget.h"
16 #include "llvm/Target/TargetData.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/CallingConv.h"
28 /// InitLibcallNames - Set default libcall names.
30 static void InitLibcallNames(const char **Names) {
31 Names[RTLIB::SHL_I32] = "__ashlsi3";
32 Names[RTLIB::SHL_I64] = "__ashldi3";
33 Names[RTLIB::SRL_I32] = "__lshrsi3";
34 Names[RTLIB::SRL_I64] = "__lshrdi3";
35 Names[RTLIB::SRA_I32] = "__ashrsi3";
36 Names[RTLIB::SRA_I64] = "__ashrdi3";
37 Names[RTLIB::MUL_I32] = "__mulsi3";
38 Names[RTLIB::MUL_I64] = "__muldi3";
39 Names[RTLIB::SDIV_I32] = "__divsi3";
40 Names[RTLIB::SDIV_I64] = "__divdi3";
41 Names[RTLIB::UDIV_I32] = "__udivsi3";
42 Names[RTLIB::UDIV_I64] = "__udivdi3";
43 Names[RTLIB::SREM_I32] = "__modsi3";
44 Names[RTLIB::SREM_I64] = "__moddi3";
45 Names[RTLIB::UREM_I32] = "__umodsi3";
46 Names[RTLIB::UREM_I64] = "__umoddi3";
47 Names[RTLIB::NEG_I32] = "__negsi2";
48 Names[RTLIB::NEG_I64] = "__negdi2";
49 Names[RTLIB::ADD_F32] = "__addsf3";
50 Names[RTLIB::ADD_F64] = "__adddf3";
51 Names[RTLIB::ADD_F80] = "__addxf3";
52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
53 Names[RTLIB::SUB_F32] = "__subsf3";
54 Names[RTLIB::SUB_F64] = "__subdf3";
55 Names[RTLIB::SUB_F80] = "__subxf3";
56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
57 Names[RTLIB::MUL_F32] = "__mulsf3";
58 Names[RTLIB::MUL_F64] = "__muldf3";
59 Names[RTLIB::MUL_F80] = "__mulxf3";
60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
61 Names[RTLIB::DIV_F32] = "__divsf3";
62 Names[RTLIB::DIV_F64] = "__divdf3";
63 Names[RTLIB::DIV_F80] = "__divxf3";
64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
65 Names[RTLIB::REM_F32] = "fmodf";
66 Names[RTLIB::REM_F64] = "fmod";
67 Names[RTLIB::REM_F80] = "fmodl";
68 Names[RTLIB::REM_PPCF128] = "fmodl";
69 Names[RTLIB::POWI_F32] = "__powisf2";
70 Names[RTLIB::POWI_F64] = "__powidf2";
71 Names[RTLIB::POWI_F80] = "__powixf2";
72 Names[RTLIB::POWI_PPCF128] = "__powitf2";
73 Names[RTLIB::SQRT_F32] = "sqrtf";
74 Names[RTLIB::SQRT_F64] = "sqrt";
75 Names[RTLIB::SQRT_F80] = "sqrtl";
76 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
77 Names[RTLIB::SIN_F32] = "sinf";
78 Names[RTLIB::SIN_F64] = "sin";
79 Names[RTLIB::SIN_F80] = "sinl";
80 Names[RTLIB::SIN_PPCF128] = "sinl";
81 Names[RTLIB::COS_F32] = "cosf";
82 Names[RTLIB::COS_F64] = "cos";
83 Names[RTLIB::COS_F80] = "cosl";
84 Names[RTLIB::COS_PPCF128] = "cosl";
85 Names[RTLIB::POW_F32] = "powf";
86 Names[RTLIB::POW_F64] = "pow";
87 Names[RTLIB::POW_F80] = "powl";
88 Names[RTLIB::POW_PPCF128] = "powl";
89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
93 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
94 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
95 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
96 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
97 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
98 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
99 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
100 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
101 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
102 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
103 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
104 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
105 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
106 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
107 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
108 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
109 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
110 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
111 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
112 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
113 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
114 Names[RTLIB::OEQ_F32] = "__eqsf2";
115 Names[RTLIB::OEQ_F64] = "__eqdf2";
116 Names[RTLIB::UNE_F32] = "__nesf2";
117 Names[RTLIB::UNE_F64] = "__nedf2";
118 Names[RTLIB::OGE_F32] = "__gesf2";
119 Names[RTLIB::OGE_F64] = "__gedf2";
120 Names[RTLIB::OLT_F32] = "__ltsf2";
121 Names[RTLIB::OLT_F64] = "__ltdf2";
122 Names[RTLIB::OLE_F32] = "__lesf2";
123 Names[RTLIB::OLE_F64] = "__ledf2";
124 Names[RTLIB::OGT_F32] = "__gtsf2";
125 Names[RTLIB::OGT_F64] = "__gtdf2";
126 Names[RTLIB::UO_F32] = "__unordsf2";
127 Names[RTLIB::UO_F64] = "__unorddf2";
128 Names[RTLIB::O_F32] = "__unordsf2";
129 Names[RTLIB::O_F64] = "__unorddf2";
132 /// InitCmpLibcallCCs - Set default comparison libcall CC.
134 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
135 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
136 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
137 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
138 CCs[RTLIB::UNE_F32] = ISD::SETNE;
139 CCs[RTLIB::UNE_F64] = ISD::SETNE;
140 CCs[RTLIB::OGE_F32] = ISD::SETGE;
141 CCs[RTLIB::OGE_F64] = ISD::SETGE;
142 CCs[RTLIB::OLT_F32] = ISD::SETLT;
143 CCs[RTLIB::OLT_F64] = ISD::SETLT;
144 CCs[RTLIB::OLE_F32] = ISD::SETLE;
145 CCs[RTLIB::OLE_F64] = ISD::SETLE;
146 CCs[RTLIB::OGT_F32] = ISD::SETGT;
147 CCs[RTLIB::OGT_F64] = ISD::SETGT;
148 CCs[RTLIB::UO_F32] = ISD::SETNE;
149 CCs[RTLIB::UO_F64] = ISD::SETNE;
150 CCs[RTLIB::O_F32] = ISD::SETEQ;
151 CCs[RTLIB::O_F64] = ISD::SETEQ;
154 TargetLowering::TargetLowering(TargetMachine &tm)
155 : TM(tm), TD(TM.getTargetData()) {
156 assert(ISD::BUILTIN_OP_END <= 156 &&
157 "Fixed size array in TargetLowering is not large enough!");
158 // All operations default to being supported.
159 memset(OpActions, 0, sizeof(OpActions));
160 memset(LoadXActions, 0, sizeof(LoadXActions));
161 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
162 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
163 memset(ConvertActions, 0, sizeof(ConvertActions));
165 // Set default actions for various operations.
166 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
167 // Default all indexed load / store to expand.
168 for (unsigned IM = (unsigned)ISD::PRE_INC;
169 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
170 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
171 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
174 // These operations default to expand.
175 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand);
178 // Default ISD::TRAP to expand (which turns it into abort).
179 setOperationAction(ISD::TRAP, MVT::Other, Expand);
181 IsLittleEndian = TD->isLittleEndian();
182 UsesGlobalOffsetTable = false;
183 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
184 ShiftAmtHandling = Undefined;
185 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
186 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
187 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
188 allowUnalignedMemoryAccesses = false;
189 UseUnderscoreSetJmp = false;
190 UseUnderscoreLongJmp = false;
191 SelectIsExpensive = false;
192 IntDivIsCheap = false;
193 Pow2DivIsCheap = false;
194 StackPointerRegisterToSaveRestore = 0;
195 ExceptionPointerRegister = 0;
196 ExceptionSelectorRegister = 0;
197 SetCCResultContents = UndefinedSetCCResult;
198 SchedPreferenceInfo = SchedulingForLatency;
200 JumpBufAlignment = 0;
201 IfCvtBlockSizeLimit = 2;
203 InitLibcallNames(LibcallRoutineNames);
204 InitCmpLibcallCCs(CmpLibcallCCs);
206 // Tell Legalize whether the assembler supports DEBUG_LOC.
207 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile())
208 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
211 TargetLowering::~TargetLowering() {}
214 SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
215 assert(getSubtarget() && "Subtarget not defined");
216 SDOperand ChainOp = Op.getOperand(0);
217 SDOperand DestOp = Op.getOperand(1);
218 SDOperand SourceOp = Op.getOperand(2);
219 SDOperand CountOp = Op.getOperand(3);
220 SDOperand AlignOp = Op.getOperand(4);
221 SDOperand AlwaysInlineOp = Op.getOperand(5);
223 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue();
224 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue();
225 if (Align == 0) Align = 1;
227 // If size is unknown, call memcpy.
228 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp);
230 assert(!AlwaysInline && "Cannot inline copy of unknown size");
231 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG);
234 // If not DWORD aligned or if size is more than threshold, then call memcpy.
235 // The libc version is likely to be faster for the following cases. It can
236 // use the address value and run time information about the CPU.
237 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster
238 unsigned Size = I->getValue();
240 (Size <= getSubtarget()->getMaxInlineSizeThreshold() &&
242 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG);
243 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG);
247 SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain,
252 MVT::ValueType IntPtr = getPointerTy();
253 TargetLowering::ArgListTy Args;
254 TargetLowering::ArgListEntry Entry;
255 Entry.Ty = getTargetData()->getIntPtrType();
256 Entry.Node = Dest; Args.push_back(Entry);
257 Entry.Node = Source; Args.push_back(Entry);
258 Entry.Node = Count; Args.push_back(Entry);
259 std::pair<SDOperand,SDOperand> CallResult =
260 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
261 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
262 return CallResult.second;
266 /// computeRegisterProperties - Once all of the register classes are added,
267 /// this allows us to compute derived properties we expose.
268 void TargetLowering::computeRegisterProperties() {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
272 // Everything defaults to needing one register.
273 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
274 NumRegistersForVT[i] = 1;
275 RegisterTypeForVT[i] = TransformToType[i] = i;
277 // ...except isVoid, which doesn't need any registers.
278 NumRegistersForVT[MVT::isVoid] = 0;
280 // Find the largest integer register class.
281 unsigned LargestIntReg = MVT::i128;
282 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
283 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
285 // Every integer value type larger than this largest register takes twice as
286 // many registers to represent as the previous ValueType.
287 for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
288 MVT::isInteger(ExpandedReg); ++ExpandedReg) {
289 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
290 RegisterTypeForVT[ExpandedReg] = LargestIntReg;
291 TransformToType[ExpandedReg] = ExpandedReg - 1;
292 ValueTypeActions.setTypeAction(ExpandedReg, Expand);
295 // Inspect all of the ValueType's smaller than the largest integer
296 // register to see which ones need promotion.
297 MVT::ValueType LegalIntReg = LargestIntReg;
298 for (MVT::ValueType IntReg = LargestIntReg - 1;
299 IntReg >= MVT::i1; --IntReg) {
300 if (isTypeLegal(IntReg)) {
301 LegalIntReg = IntReg;
303 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
304 ValueTypeActions.setTypeAction(IntReg, Promote);
308 // ppcf128 type is really two f64's.
309 if (!isTypeLegal(MVT::ppcf128)) {
310 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
311 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
312 TransformToType[MVT::ppcf128] = MVT::f64;
313 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
316 // Decide how to handle f64. If the target does not have native f64 support,
317 // expand it to i64 and we will be generating soft float library calls.
318 if (!isTypeLegal(MVT::f64)) {
319 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
320 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
321 TransformToType[MVT::f64] = MVT::i64;
322 ValueTypeActions.setTypeAction(MVT::f64, Expand);
325 // Decide how to handle f32. If the target does not have native support for
326 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
327 if (!isTypeLegal(MVT::f32)) {
328 if (isTypeLegal(MVT::f64)) {
329 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
330 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
331 TransformToType[MVT::f32] = MVT::f64;
332 ValueTypeActions.setTypeAction(MVT::f32, Promote);
334 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
335 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
336 TransformToType[MVT::f32] = MVT::i32;
337 ValueTypeActions.setTypeAction(MVT::f32, Expand);
341 // Loop over all of the vector value types to see which need transformations.
342 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
343 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
344 if (!isTypeLegal(i)) {
345 MVT::ValueType IntermediateVT, RegisterVT;
346 unsigned NumIntermediates;
347 NumRegistersForVT[i] =
348 getVectorTypeBreakdown(i,
349 IntermediateVT, NumIntermediates,
351 RegisterTypeForVT[i] = RegisterVT;
352 TransformToType[i] = MVT::Other; // this isn't actually used
353 ValueTypeActions.setTypeAction(i, Expand);
358 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
362 /// getVectorTypeBreakdown - Vector types are broken down into some number of
363 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
364 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
365 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
367 /// This method returns the number of registers needed, and the VT for each
368 /// register. It also returns the VT and quantity of the intermediate values
369 /// before they are promoted/expanded.
371 unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
372 MVT::ValueType &IntermediateVT,
373 unsigned &NumIntermediates,
374 MVT::ValueType &RegisterVT) const {
375 // Figure out the right, legal destination reg to copy into.
376 unsigned NumElts = MVT::getVectorNumElements(VT);
377 MVT::ValueType EltTy = MVT::getVectorElementType(VT);
379 unsigned NumVectorRegs = 1;
381 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
382 // could break down into LHS/RHS like LegalizeDAG does.
383 if (!isPowerOf2_32(NumElts)) {
384 NumVectorRegs = NumElts;
388 // Divide the input until we get to a supported size. This will always
389 // end with a scalar if the target doesn't support vectors.
390 while (NumElts > 1 &&
391 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
396 NumIntermediates = NumVectorRegs;
398 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
399 if (!isTypeLegal(NewVT))
401 IntermediateVT = NewVT;
403 MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
405 if (DestVT < NewVT) {
406 // Value is expanded, e.g. i64 -> i16.
407 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
409 // Otherwise, promotion or legal types use the same number of registers as
410 // the vector decimated to the appropriate level.
411 return NumVectorRegs;
417 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
418 /// function arguments in the caller parameter area.
419 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
420 return Log2_32(TD->getCallFrameTypeAlignment(Ty));
423 SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
424 SelectionDAG &DAG) const {
425 if (usesGlobalOffsetTable())
426 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
430 //===----------------------------------------------------------------------===//
431 // Optimization Methods
432 //===----------------------------------------------------------------------===//
434 /// ShrinkDemandedConstant - Check to see if the specified operand of the
435 /// specified instruction is a constant integer. If so, check to see if there
436 /// are any bits set in the constant that are not demanded. If so, shrink the
437 /// constant and return true.
438 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
440 // FIXME: ISD::SELECT, ISD::SELECT_CC
441 switch(Op.getOpcode()) {
446 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
447 if ((~Demanded & C->getValue()) != 0) {
448 MVT::ValueType VT = Op.getValueType();
449 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
450 DAG.getConstant(Demanded & C->getValue(),
452 return CombineTo(Op, New);
459 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
460 /// DemandedMask bits of the result of Op are ever used downstream. If we can
461 /// use this information to simplify Op, create a new simplified DAG node and
462 /// return true, returning the original and new nodes in Old and New. Otherwise,
463 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
464 /// the expression (used to simplify the caller). The KnownZero/One bits may
465 /// only be accurate for those bits in the DemandedMask.
466 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
469 TargetLoweringOpt &TLO,
470 unsigned Depth) const {
471 KnownZero = KnownOne = 0; // Don't know anything.
473 // The masks are not wide enough to represent this type! Should use APInt.
474 if (Op.getValueType() == MVT::i128)
477 // Other users may use these bits.
478 if (!Op.Val->hasOneUse()) {
480 // If not at the root, Just compute the KnownZero/KnownOne bits to
481 // simplify things downstream.
482 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
485 // If this is the root being simplified, allow it to have multiple uses,
486 // just set the DemandedMask to all bits.
487 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
488 } else if (DemandedMask == 0) {
489 // Not demanding any bits from Op.
490 if (Op.getOpcode() != ISD::UNDEF)
491 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
493 } else if (Depth == 6) { // Limit search depth.
497 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
498 switch (Op.getOpcode()) {
500 // We know all of the bits for a constant!
501 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
502 KnownZero = ~KnownOne & DemandedMask;
503 return false; // Don't fall through, will infinitely loop.
505 // If the RHS is a constant, check to see if the LHS would be zero without
506 // using the bits from the RHS. Below, we use knowledge about the RHS to
507 // simplify the LHS, here we're using information from the LHS to simplify
509 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
510 uint64_t LHSZero, LHSOne;
511 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask,
512 LHSZero, LHSOne, Depth+1);
513 // If the LHS already has zeros where RHSC does, this and is dead.
514 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
515 return TLO.CombineTo(Op, Op.getOperand(0));
516 // If any of the set bits in the RHS are known zero on the LHS, shrink
518 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
522 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
523 KnownOne, TLO, Depth+1))
525 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
526 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
527 KnownZero2, KnownOne2, TLO, Depth+1))
529 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
531 // If all of the demanded bits are known one on one side, return the other.
532 // These bits cannot contribute to the result of the 'and'.
533 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
534 return TLO.CombineTo(Op, Op.getOperand(0));
535 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
536 return TLO.CombineTo(Op, Op.getOperand(1));
537 // If all of the demanded bits in the inputs are known zeros, return zero.
538 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
539 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
540 // If the RHS is a constant, see if we can simplify it.
541 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
544 // Output known-1 bits are only known if set in both the LHS & RHS.
545 KnownOne &= KnownOne2;
546 // Output known-0 are known to be clear if zero in either the LHS | RHS.
547 KnownZero |= KnownZero2;
550 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
551 KnownOne, TLO, Depth+1))
553 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
554 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
555 KnownZero2, KnownOne2, TLO, Depth+1))
557 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
559 // If all of the demanded bits are known zero on one side, return the other.
560 // These bits cannot contribute to the result of the 'or'.
561 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
562 return TLO.CombineTo(Op, Op.getOperand(0));
563 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
564 return TLO.CombineTo(Op, Op.getOperand(1));
565 // If all of the potentially set bits on one side are known to be set on
566 // the other side, just use the 'other' side.
567 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
568 (DemandedMask & (~KnownZero)))
569 return TLO.CombineTo(Op, Op.getOperand(0));
570 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
571 (DemandedMask & (~KnownZero2)))
572 return TLO.CombineTo(Op, Op.getOperand(1));
573 // If the RHS is a constant, see if we can simplify it.
574 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
577 // Output known-0 bits are only known if clear in both the LHS & RHS.
578 KnownZero &= KnownZero2;
579 // Output known-1 are known to be set if set in either the LHS | RHS.
580 KnownOne |= KnownOne2;
583 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
584 KnownOne, TLO, Depth+1))
586 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
587 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
588 KnownOne2, TLO, Depth+1))
590 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
592 // If all of the demanded bits are known zero on one side, return the other.
593 // These bits cannot contribute to the result of the 'xor'.
594 if ((DemandedMask & KnownZero) == DemandedMask)
595 return TLO.CombineTo(Op, Op.getOperand(0));
596 if ((DemandedMask & KnownZero2) == DemandedMask)
597 return TLO.CombineTo(Op, Op.getOperand(1));
599 // If all of the unknown bits are known to be zero on one side or the other
600 // (but not both) turn this into an *inclusive* or.
601 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
602 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
603 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
607 // Output known-0 bits are known if clear or set in both the LHS & RHS.
608 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
609 // Output known-1 are known to be set if set in only one of the LHS, RHS.
610 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
612 // If all of the demanded bits on one side are known, and all of the set
613 // bits on that side are also known to be set on the other side, turn this
614 // into an AND, as we know the bits will be cleared.
615 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
616 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
617 if ((KnownOne & KnownOne2) == KnownOne) {
618 MVT::ValueType VT = Op.getValueType();
619 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
620 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
625 // If the RHS is a constant, see if we can simplify it.
626 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
627 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
630 KnownZero = KnownZeroOut;
631 KnownOne = KnownOneOut;
634 // If we know the result of a setcc has the top bits zero, use this info.
635 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
636 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
639 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
640 KnownOne, TLO, Depth+1))
642 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
643 KnownOne2, TLO, Depth+1))
645 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
646 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
648 // If the operands are constants, see if we can simplify them.
649 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
652 // Only known if known in both the LHS and RHS.
653 KnownOne &= KnownOne2;
654 KnownZero &= KnownZero2;
657 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
658 KnownOne, TLO, Depth+1))
660 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
661 KnownOne2, TLO, Depth+1))
663 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
664 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
666 // If the operands are constants, see if we can simplify them.
667 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
670 // Only known if known in both the LHS and RHS.
671 KnownOne &= KnownOne2;
672 KnownZero &= KnownZero2;
675 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
676 unsigned ShAmt = SA->getValue();
677 SDOperand InOp = Op.getOperand(0);
679 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
680 // single shift. We can do this if the bottom bits (which are shifted
681 // out) are never demanded.
682 if (InOp.getOpcode() == ISD::SRL &&
683 isa<ConstantSDNode>(InOp.getOperand(1))) {
684 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
685 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
686 unsigned Opc = ISD::SHL;
694 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
695 MVT::ValueType VT = Op.getValueType();
696 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
697 InOp.getOperand(0), NewSA));
701 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
702 KnownZero, KnownOne, TLO, Depth+1))
704 KnownZero <<= SA->getValue();
705 KnownOne <<= SA->getValue();
706 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
710 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
711 MVT::ValueType VT = Op.getValueType();
712 unsigned ShAmt = SA->getValue();
713 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
714 unsigned VTSize = MVT::getSizeInBits(VT);
715 SDOperand InOp = Op.getOperand(0);
717 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
718 // single shift. We can do this if the top bits (which are shifted out)
719 // are never demanded.
720 if (InOp.getOpcode() == ISD::SHL &&
721 isa<ConstantSDNode>(InOp.getOperand(1))) {
722 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
723 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
724 unsigned Opc = ISD::SRL;
732 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
733 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
734 InOp.getOperand(0), NewSA));
738 // Compute the new bits that are at the top now.
739 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
740 KnownZero, KnownOne, TLO, Depth+1))
742 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
743 KnownZero &= TypeMask;
744 KnownOne &= TypeMask;
748 uint64_t HighBits = (1ULL << ShAmt)-1;
749 HighBits <<= VTSize - ShAmt;
750 KnownZero |= HighBits; // High bits known zero.
754 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
755 MVT::ValueType VT = Op.getValueType();
756 unsigned ShAmt = SA->getValue();
758 // Compute the new bits that are at the top now.
759 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
761 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
763 // If any of the demanded bits are produced by the sign extension, we also
764 // demand the input sign bit.
765 uint64_t HighBits = (1ULL << ShAmt)-1;
766 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
767 if (HighBits & DemandedMask)
768 InDemandedMask |= MVT::getIntVTSignBit(VT);
770 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
771 KnownZero, KnownOne, TLO, Depth+1))
773 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
774 KnownZero &= TypeMask;
775 KnownOne &= TypeMask;
779 // Handle the sign bits.
780 uint64_t SignBit = MVT::getIntVTSignBit(VT);
781 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
783 // If the input sign bit is known to be zero, or if none of the top bits
784 // are demanded, turn this into an unsigned shift right.
785 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
786 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
788 } else if (KnownOne & SignBit) { // New bits are known one.
789 KnownOne |= HighBits;
793 case ISD::SIGN_EXTEND_INREG: {
794 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
796 // Sign extension. Compute the demanded bits in the result that are not
797 // present in the input.
798 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
800 // If none of the extended bits are demanded, eliminate the sextinreg.
802 return TLO.CombineTo(Op, Op.getOperand(0));
804 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
805 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
807 // Since the sign extended bits are demanded, we know that the sign
809 InputDemandedBits |= InSignBit;
811 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
812 KnownZero, KnownOne, TLO, Depth+1))
814 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
816 // If the sign bit of the input is known set or clear, then we know the
817 // top bits of the result.
819 // If the input sign bit is known zero, convert this into a zero extension.
820 if (KnownZero & InSignBit)
821 return TLO.CombineTo(Op,
822 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
824 if (KnownOne & InSignBit) { // Input sign bit known set
826 KnownZero &= ~NewBits;
827 } else { // Input sign bit unknown
828 KnownZero &= ~NewBits;
829 KnownOne &= ~NewBits;
836 MVT::ValueType VT = Op.getValueType();
837 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
838 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
843 if (ISD::isZEXTLoad(Op.Val)) {
844 LoadSDNode *LD = cast<LoadSDNode>(Op);
845 MVT::ValueType VT = LD->getMemoryVT();
846 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
850 case ISD::ZERO_EXTEND: {
851 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
853 // If none of the top bits are demanded, convert this into an any_extend.
854 uint64_t NewBits = (~InMask) & DemandedMask;
856 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
860 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
861 KnownZero, KnownOne, TLO, Depth+1))
863 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
864 KnownZero |= NewBits;
867 case ISD::SIGN_EXTEND: {
868 MVT::ValueType InVT = Op.getOperand(0).getValueType();
869 uint64_t InMask = MVT::getIntVTBitMask(InVT);
870 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
871 uint64_t NewBits = (~InMask) & DemandedMask;
873 // If none of the top bits are demanded, convert this into an any_extend.
875 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
878 // Since some of the sign extended bits are demanded, we know that the sign
880 uint64_t InDemandedBits = DemandedMask & InMask;
881 InDemandedBits |= InSignBit;
883 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
884 KnownOne, TLO, Depth+1))
887 // If the sign bit is known zero, convert this to a zero extend.
888 if (KnownZero & InSignBit)
889 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
893 // If the sign bit is known one, the top bits match.
894 if (KnownOne & InSignBit) {
896 KnownZero &= ~NewBits;
897 } else { // Otherwise, top bits aren't known.
898 KnownOne &= ~NewBits;
899 KnownZero &= ~NewBits;
903 case ISD::ANY_EXTEND: {
904 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
905 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
906 KnownZero, KnownOne, TLO, Depth+1))
908 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
911 case ISD::TRUNCATE: {
912 // Simplify the input, using demanded bit information, and compute the known
913 // zero/one bits live out.
914 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
915 KnownZero, KnownOne, TLO, Depth+1))
918 // If the input is only used by this truncate, see if we can shrink it based
919 // on the known demanded bits.
920 if (Op.getOperand(0).Val->hasOneUse()) {
921 SDOperand In = Op.getOperand(0);
922 switch (In.getOpcode()) {
925 // Shrink SRL by a constant if none of the high bits shifted in are
927 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
928 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
929 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
930 HighBits >>= ShAmt->getValue();
932 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
933 (DemandedMask & HighBits) == 0) {
934 // None of the shifted in bits are needed. Add a truncate of the
935 // shift input, then shift it.
936 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
939 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
940 NewTrunc, In.getOperand(1)));
947 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
948 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
949 KnownZero &= OutMask;
953 case ISD::AssertZext: {
954 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
955 uint64_t InMask = MVT::getIntVTBitMask(VT);
956 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
957 KnownZero, KnownOne, TLO, Depth+1))
959 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
960 KnownZero |= ~InMask & DemandedMask;
964 // All bits are zero except the low bit.
965 KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1;
967 case ISD::BIT_CONVERT:
969 // If this is an FP->Int bitcast and if the sign bit is the only thing that
970 // is demanded, turn this into a FGETSIGN.
971 if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) &&
972 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
973 !MVT::isVector(Op.getOperand(0).getValueType())) {
974 // Only do this xform if FGETSIGN is valid or if before legalize.
975 if (!TLO.AfterLegalize ||
976 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
977 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
978 // place. We expect the SHL to be eliminated by other optimizations.
979 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
981 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1;
982 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
983 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
991 case ISD::INTRINSIC_WO_CHAIN:
992 case ISD::INTRINSIC_W_CHAIN:
993 case ISD::INTRINSIC_VOID:
994 // Just use ComputeMaskedBits to compute output bits.
995 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
999 // If we know the value of all of the demanded bits, return this as a
1001 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
1002 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1007 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1008 /// in Mask are known to be either zero or one and return them in the
1009 /// KnownZero/KnownOne bitsets.
1010 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1014 const SelectionDAG &DAG,
1015 unsigned Depth) const {
1016 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1017 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1018 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1019 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1020 "Should use MaskedValueIsZero if you don't know whether Op"
1021 " is a target node!");
1022 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1025 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1026 /// targets that want to expose additional information about sign bits to the
1028 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
1029 unsigned Depth) const {
1030 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1031 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1032 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1033 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1034 "Should use ComputeNumSignBits if you don't know whether Op"
1035 " is a target node!");
1040 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1041 /// and cc. If it is unable to simplify it, return a null SDOperand.
1043 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
1044 ISD::CondCode Cond, bool foldBooleans,
1045 DAGCombinerInfo &DCI) const {
1046 SelectionDAG &DAG = DCI.DAG;
1048 // These setcc operations always fold.
1052 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1054 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1057 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1058 uint64_t C1 = N1C->getValue();
1059 if (isa<ConstantSDNode>(N0.Val)) {
1060 return DAG.FoldSetCC(VT, N0, N1, Cond);
1062 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1063 // equality comparison, then we're just comparing whether X itself is
1065 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1066 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1067 N0.getOperand(1).getOpcode() == ISD::Constant) {
1068 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1069 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1070 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
1071 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1072 // (srl (ctlz x), 5) == 0 -> X != 0
1073 // (srl (ctlz x), 5) != 1 -> X != 0
1076 // (srl (ctlz x), 5) != 0 -> X == 0
1077 // (srl (ctlz x), 5) == 1 -> X == 0
1080 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
1081 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
1086 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1087 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1088 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1090 // If the comparison constant has bits in the upper part, the
1091 // zero-extended value could never match.
1092 if (C1 & (~0ULL << InSize)) {
1093 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1097 case ISD::SETEQ: return DAG.getConstant(0, VT);
1100 case ISD::SETNE: return DAG.getConstant(1, VT);
1103 // True if the sign bit of C1 is set.
1104 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
1107 // True if the sign bit of C1 isn't set.
1108 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
1114 // Otherwise, we can perform the comparison with the low bits.
1122 return DAG.getSetCC(VT, N0.getOperand(0),
1123 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1126 break; // todo, be more careful with signed comparisons
1128 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1129 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1130 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1131 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1132 MVT::ValueType ExtDstTy = N0.getValueType();
1133 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1135 // If the extended part has any inconsistent bits, it cannot ever
1136 // compare equal. In other words, they have to be all ones or all
1139 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1140 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1141 return DAG.getConstant(Cond == ISD::SETNE, VT);
1144 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1145 if (Op0Ty == ExtSrcTy) {
1146 ZextOp = N0.getOperand(0);
1148 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1149 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1150 DAG.getConstant(Imm, Op0Ty));
1152 if (!DCI.isCalledByLegalizer())
1153 DCI.AddToWorklist(ZextOp.Val);
1154 // Otherwise, make this a use of a zext.
1155 return DAG.getSetCC(VT, ZextOp,
1156 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1159 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1160 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1162 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1163 if (N0.getOpcode() == ISD::SETCC) {
1164 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1168 // Invert the condition.
1169 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1170 CC = ISD::getSetCCInverse(CC,
1171 MVT::isInteger(N0.getOperand(0).getValueType()));
1172 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1175 if ((N0.getOpcode() == ISD::XOR ||
1176 (N0.getOpcode() == ISD::AND &&
1177 N0.getOperand(0).getOpcode() == ISD::XOR &&
1178 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1179 isa<ConstantSDNode>(N0.getOperand(1)) &&
1180 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1181 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1182 // can only do this if the top bits are known zero.
1183 if (DAG.MaskedValueIsZero(N0,
1184 MVT::getIntVTBitMask(N0.getValueType())-1)){
1185 // Okay, get the un-inverted input value.
1187 if (N0.getOpcode() == ISD::XOR)
1188 Val = N0.getOperand(0);
1190 assert(N0.getOpcode() == ISD::AND &&
1191 N0.getOperand(0).getOpcode() == ISD::XOR);
1192 // ((X^1)&1)^1 -> X & 1
1193 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1194 N0.getOperand(0).getOperand(0),
1197 return DAG.getSetCC(VT, Val, N1,
1198 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1203 uint64_t MinVal, MaxVal;
1204 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1205 if (ISD::isSignedIntSetCC(Cond)) {
1206 MinVal = 1ULL << (OperandBitSize-1);
1207 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1208 MaxVal = ~0ULL >> (65-OperandBitSize);
1213 MaxVal = ~0ULL >> (64-OperandBitSize);
1216 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1217 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1218 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1219 --C1; // X >= C0 --> X > (C0-1)
1220 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1221 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1224 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1225 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1226 ++C1; // X <= C0 --> X < (C0+1)
1227 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1228 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1231 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1232 return DAG.getConstant(0, VT); // X < MIN --> false
1233 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1234 return DAG.getConstant(1, VT); // X >= MIN --> true
1235 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1236 return DAG.getConstant(0, VT); // X > MAX --> false
1237 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1238 return DAG.getConstant(1, VT); // X <= MAX --> true
1240 // Canonicalize setgt X, Min --> setne X, Min
1241 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1242 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1243 // Canonicalize setlt X, Max --> setne X, Max
1244 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1245 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1247 // If we have setult X, 1, turn it into seteq X, 0
1248 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1249 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1251 // If we have setugt X, Max-1, turn it into seteq X, Max
1252 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1253 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1256 // If we have "setcc X, C0", check to see if we can shrink the immediate
1259 // SETUGT X, SINTMAX -> SETLT X, 0
1260 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1261 C1 == (~0ULL >> (65-OperandBitSize)))
1262 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1265 // FIXME: Implement the rest of these.
1267 // Fold bit comparisons when we can.
1268 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1269 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1270 if (ConstantSDNode *AndRHS =
1271 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1272 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1273 // Perform the xform if the AND RHS is a single bit.
1274 if (isPowerOf2_64(AndRHS->getValue())) {
1275 return DAG.getNode(ISD::SRL, VT, N0,
1276 DAG.getConstant(Log2_64(AndRHS->getValue()),
1277 getShiftAmountTy()));
1279 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1280 // (X & 8) == 8 --> (X & 8) >> 3
1281 // Perform the xform if C1 is a single bit.
1282 if (isPowerOf2_64(C1)) {
1283 return DAG.getNode(ISD::SRL, VT, N0,
1284 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1289 } else if (isa<ConstantSDNode>(N0.Val)) {
1290 // Ensure that the constant occurs on the RHS.
1291 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1294 if (isa<ConstantFPSDNode>(N0.Val)) {
1295 // Constant fold or commute setcc.
1296 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1297 if (O.Val) return O;
1298 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) {
1299 // If the RHS of an FP comparison is a constant, simplify it away in
1301 if (CFP->getValueAPF().isNaN()) {
1302 // If an operand is known to be a nan, we can fold it.
1303 switch (ISD::getUnorderedFlavor(Cond)) {
1304 default: assert(0 && "Unknown flavor!");
1305 case 0: // Known false.
1306 return DAG.getConstant(0, VT);
1307 case 1: // Known true.
1308 return DAG.getConstant(1, VT);
1309 case 2: // Undefined.
1310 return DAG.getNode(ISD::UNDEF, VT);
1314 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1315 // constant if knowing that the operand is non-nan is enough. We prefer to
1316 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1318 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1319 return DAG.getSetCC(VT, N0, N0, Cond);
1323 // We can always fold X == X for integer setcc's.
1324 if (MVT::isInteger(N0.getValueType()))
1325 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1326 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1327 if (UOF == 2) // FP operators that are undefined on NaNs.
1328 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1329 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1330 return DAG.getConstant(UOF, VT);
1331 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1332 // if it is not already.
1333 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1334 if (NewCond != Cond)
1335 return DAG.getSetCC(VT, N0, N1, NewCond);
1338 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1339 MVT::isInteger(N0.getValueType())) {
1340 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1341 N0.getOpcode() == ISD::XOR) {
1342 // Simplify (X+Y) == (X+Z) --> Y == Z
1343 if (N0.getOpcode() == N1.getOpcode()) {
1344 if (N0.getOperand(0) == N1.getOperand(0))
1345 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1346 if (N0.getOperand(1) == N1.getOperand(1))
1347 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1348 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1349 // If X op Y == Y op X, try other combinations.
1350 if (N0.getOperand(0) == N1.getOperand(1))
1351 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1352 if (N0.getOperand(1) == N1.getOperand(0))
1353 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1357 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1358 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1359 // Turn (X+C1) == C2 --> X == C2-C1
1360 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1361 return DAG.getSetCC(VT, N0.getOperand(0),
1362 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1363 N0.getValueType()), Cond);
1366 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1367 if (N0.getOpcode() == ISD::XOR)
1368 // If we know that all of the inverted bits are zero, don't bother
1369 // performing the inversion.
1370 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1371 return DAG.getSetCC(VT, N0.getOperand(0),
1372 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1373 N0.getValueType()), Cond);
1376 // Turn (C1-X) == C2 --> X == C1-C2
1377 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1378 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1379 return DAG.getSetCC(VT, N0.getOperand(1),
1380 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1381 N0.getValueType()), Cond);
1386 // Simplify (X+Z) == X --> Z == 0
1387 if (N0.getOperand(0) == N1)
1388 return DAG.getSetCC(VT, N0.getOperand(1),
1389 DAG.getConstant(0, N0.getValueType()), Cond);
1390 if (N0.getOperand(1) == N1) {
1391 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1392 return DAG.getSetCC(VT, N0.getOperand(0),
1393 DAG.getConstant(0, N0.getValueType()), Cond);
1394 else if (N0.Val->hasOneUse()) {
1395 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1396 // (Z-X) == X --> Z == X<<1
1397 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1399 DAG.getConstant(1, getShiftAmountTy()));
1400 if (!DCI.isCalledByLegalizer())
1401 DCI.AddToWorklist(SH.Val);
1402 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1407 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1408 N1.getOpcode() == ISD::XOR) {
1409 // Simplify X == (X+Z) --> Z == 0
1410 if (N1.getOperand(0) == N0) {
1411 return DAG.getSetCC(VT, N1.getOperand(1),
1412 DAG.getConstant(0, N1.getValueType()), Cond);
1413 } else if (N1.getOperand(1) == N0) {
1414 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1415 return DAG.getSetCC(VT, N1.getOperand(0),
1416 DAG.getConstant(0, N1.getValueType()), Cond);
1417 } else if (N1.Val->hasOneUse()) {
1418 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1419 // X == (Z-X) --> X<<1 == Z
1420 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1421 DAG.getConstant(1, getShiftAmountTy()));
1422 if (!DCI.isCalledByLegalizer())
1423 DCI.AddToWorklist(SH.Val);
1424 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1430 // Fold away ALL boolean setcc's.
1432 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1434 default: assert(0 && "Unknown integer setcc!");
1435 case ISD::SETEQ: // X == Y -> (X^Y)^1
1436 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1437 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1438 if (!DCI.isCalledByLegalizer())
1439 DCI.AddToWorklist(Temp.Val);
1441 case ISD::SETNE: // X != Y --> (X^Y)
1442 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1444 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1445 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1446 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1447 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1448 if (!DCI.isCalledByLegalizer())
1449 DCI.AddToWorklist(Temp.Val);
1451 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1452 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1453 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1454 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1455 if (!DCI.isCalledByLegalizer())
1456 DCI.AddToWorklist(Temp.Val);
1458 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1459 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1460 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1461 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1462 if (!DCI.isCalledByLegalizer())
1463 DCI.AddToWorklist(Temp.Val);
1465 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1466 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1467 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1468 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1471 if (VT != MVT::i1) {
1472 if (!DCI.isCalledByLegalizer())
1473 DCI.AddToWorklist(N0.Val);
1474 // FIXME: If running after legalize, we probably can't do this.
1475 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1480 // Could not fold it.
1484 SDOperand TargetLowering::
1485 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1486 // Default implementation: no optimization.
1490 //===----------------------------------------------------------------------===//
1491 // Inline Assembler Implementation Methods
1492 //===----------------------------------------------------------------------===//
1494 TargetLowering::ConstraintType
1495 TargetLowering::getConstraintType(const std::string &Constraint) const {
1496 // FIXME: lots more standard ones to handle.
1497 if (Constraint.size() == 1) {
1498 switch (Constraint[0]) {
1500 case 'r': return C_RegisterClass;
1502 case 'o': // offsetable
1503 case 'V': // not offsetable
1505 case 'i': // Simple Integer or Relocatable Constant
1506 case 'n': // Simple Integer
1507 case 's': // Relocatable Constant
1508 case 'X': // Allow ANY value.
1509 case 'I': // Target registers.
1521 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1522 Constraint[Constraint.size()-1] == '}')
1527 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1528 /// with another that has more specific requirements based on the type of the
1529 /// corresponding operand.
1530 void TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
1531 std::string& s) const {
1532 if (MVT::isInteger(ConstraintVT))
1534 else if (MVT::isFloatingPoint(ConstraintVT))
1535 s = "f"; // works for many targets
1540 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1541 /// vector. If it is invalid, don't add anything to Ops.
1542 void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
1543 char ConstraintLetter,
1544 std::vector<SDOperand> &Ops,
1545 SelectionDAG &DAG) {
1546 switch (ConstraintLetter) {
1548 case 'X': // Allows any operand; labels (basic block) use this.
1549 if (Op.getOpcode() == ISD::BasicBlock) {
1554 case 'i': // Simple Integer or Relocatable Constant
1555 case 'n': // Simple Integer
1556 case 's': { // Relocatable Constant
1557 // These operands are interested in values of the form (GV+C), where C may
1558 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1559 // is possible and fine if either GV or C are missing.
1560 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1561 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1563 // If we have "(add GV, C)", pull out GV/C
1564 if (Op.getOpcode() == ISD::ADD) {
1565 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1566 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1567 if (C == 0 || GA == 0) {
1568 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1569 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1571 if (C == 0 || GA == 0)
1575 // If we find a valid operand, map to the TargetXXX version so that the
1576 // value itself doesn't get selected.
1577 if (GA) { // Either &GV or &GV+C
1578 if (ConstraintLetter != 'n') {
1579 int64_t Offs = GA->getOffset();
1580 if (C) Offs += C->getValue();
1581 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1582 Op.getValueType(), Offs));
1586 if (C) { // just C, no GV.
1587 // Simple constants are not allowed for 's'.
1588 if (ConstraintLetter != 's') {
1589 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
1598 std::vector<unsigned> TargetLowering::
1599 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1600 MVT::ValueType VT) const {
1601 return std::vector<unsigned>();
1605 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1606 getRegForInlineAsmConstraint(const std::string &Constraint,
1607 MVT::ValueType VT) const {
1608 if (Constraint[0] != '{')
1609 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1610 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1612 // Remove the braces from around the name.
1613 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1615 // Figure out which register class contains this reg.
1616 const TargetRegisterInfo *RI = TM.getRegisterInfo();
1617 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1618 E = RI->regclass_end(); RCI != E; ++RCI) {
1619 const TargetRegisterClass *RC = *RCI;
1621 // If none of the the value types for this register class are valid, we
1622 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1623 bool isLegal = false;
1624 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1626 if (isTypeLegal(*I)) {
1632 if (!isLegal) continue;
1634 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1636 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1637 return std::make_pair(*I, RC);
1641 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1644 //===----------------------------------------------------------------------===//
1645 // Loop Strength Reduction hooks
1646 //===----------------------------------------------------------------------===//
1648 /// isLegalAddressingMode - Return true if the addressing mode represented
1649 /// by AM is legal for this target, for a load/store of the specified type.
1650 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1651 const Type *Ty) const {
1652 // The default implementation of this implements a conservative RISCy, r+r and
1655 // Allows a sign-extended 16-bit immediate field.
1656 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1659 // No global is ever allowed as a base.
1663 // Only support r+r,
1665 case 0: // "r+i" or just "i", depending on HasBaseReg.
1668 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1670 // Otherwise we have r+r or r+i.
1673 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1675 // Allow 2*r as r+r.
1682 // Magic for divide replacement
1685 int64_t m; // magic number
1686 int64_t s; // shift amount
1690 uint64_t m; // magic number
1691 int64_t a; // add indicator
1692 int64_t s; // shift amount
1695 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1696 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1698 static ms magic32(int32_t d) {
1700 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1701 const uint32_t two31 = 0x80000000U;
1705 t = two31 + ((uint32_t)d >> 31);
1706 anc = t - 1 - t%ad; // absolute value of nc
1707 p = 31; // initialize p
1708 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1709 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1710 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1711 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1714 q1 = 2*q1; // update q1 = 2p/abs(nc)
1715 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1716 if (r1 >= anc) { // must be unsigned comparison
1720 q2 = 2*q2; // update q2 = 2p/abs(d)
1721 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1722 if (r2 >= ad) { // must be unsigned comparison
1727 } while (q1 < delta || (q1 == delta && r1 == 0));
1729 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1730 if (d < 0) mag.m = -mag.m; // resulting magic number
1731 mag.s = p - 32; // resulting shift
1735 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1736 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1737 static mu magicu32(uint32_t d) {
1739 uint32_t nc, delta, q1, r1, q2, r2;
1741 magu.a = 0; // initialize "add" indicator
1743 p = 31; // initialize p
1744 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1745 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1746 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1747 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1750 if (r1 >= nc - r1 ) {
1751 q1 = 2*q1 + 1; // update q1
1752 r1 = 2*r1 - nc; // update r1
1755 q1 = 2*q1; // update q1
1756 r1 = 2*r1; // update r1
1758 if (r2 + 1 >= d - r2) {
1759 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1760 q2 = 2*q2 + 1; // update q2
1761 r2 = 2*r2 + 1 - d; // update r2
1764 if (q2 >= 0x80000000) magu.a = 1;
1765 q2 = 2*q2; // update q2
1766 r2 = 2*r2 + 1; // update r2
1769 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1770 magu.m = q2 + 1; // resulting magic number
1771 magu.s = p - 32; // resulting shift
1775 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1776 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1778 static ms magic64(int64_t d) {
1780 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1781 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1784 ad = d >= 0 ? d : -d;
1785 t = two63 + ((uint64_t)d >> 63);
1786 anc = t - 1 - t%ad; // absolute value of nc
1787 p = 63; // initialize p
1788 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1789 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1790 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1791 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1794 q1 = 2*q1; // update q1 = 2p/abs(nc)
1795 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1796 if (r1 >= anc) { // must be unsigned comparison
1800 q2 = 2*q2; // update q2 = 2p/abs(d)
1801 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1802 if (r2 >= ad) { // must be unsigned comparison
1807 } while (q1 < delta || (q1 == delta && r1 == 0));
1810 if (d < 0) mag.m = -mag.m; // resulting magic number
1811 mag.s = p - 64; // resulting shift
1815 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1816 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1817 static mu magicu64(uint64_t d)
1820 uint64_t nc, delta, q1, r1, q2, r2;
1822 magu.a = 0; // initialize "add" indicator
1824 p = 63; // initialize p
1825 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1826 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1827 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1828 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1831 if (r1 >= nc - r1 ) {
1832 q1 = 2*q1 + 1; // update q1
1833 r1 = 2*r1 - nc; // update r1
1836 q1 = 2*q1; // update q1
1837 r1 = 2*r1; // update r1
1839 if (r2 + 1 >= d - r2) {
1840 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1841 q2 = 2*q2 + 1; // update q2
1842 r2 = 2*r2 + 1 - d; // update r2
1845 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1846 q2 = 2*q2; // update q2
1847 r2 = 2*r2 + 1; // update r2
1850 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1851 magu.m = q2 + 1; // resulting magic number
1852 magu.s = p - 64; // resulting shift
1856 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1857 /// return a DAG expression to select that will generate the same value by
1858 /// multiplying by a magic number. See:
1859 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1860 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1861 std::vector<SDNode*>* Created) const {
1862 MVT::ValueType VT = N->getValueType(0);
1864 // Check to see if we can do this.
1865 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1866 return SDOperand(); // BuildSDIV only operates on i32 or i64
1868 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1869 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1871 // Multiply the numerator (operand 0) by the magic value
1873 if (isOperationLegal(ISD::MULHS, VT))
1874 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1875 DAG.getConstant(magics.m, VT));
1876 else if (isOperationLegal(ISD::SMUL_LOHI, VT))
1877 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
1879 DAG.getConstant(magics.m, VT)).Val, 1);
1881 return SDOperand(); // No mulhs or equvialent
1882 // If d > 0 and m < 0, add the numerator
1883 if (d > 0 && magics.m < 0) {
1884 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1886 Created->push_back(Q.Val);
1888 // If d < 0 and m > 0, subtract the numerator.
1889 if (d < 0 && magics.m > 0) {
1890 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1892 Created->push_back(Q.Val);
1894 // Shift right algebraic if shift value is nonzero
1896 Q = DAG.getNode(ISD::SRA, VT, Q,
1897 DAG.getConstant(magics.s, getShiftAmountTy()));
1899 Created->push_back(Q.Val);
1901 // Extract the sign bit and add it to the quotient
1903 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1904 getShiftAmountTy()));
1906 Created->push_back(T.Val);
1907 return DAG.getNode(ISD::ADD, VT, Q, T);
1910 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1911 /// return a DAG expression to select that will generate the same value by
1912 /// multiplying by a magic number. See:
1913 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1914 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1915 std::vector<SDNode*>* Created) const {
1916 MVT::ValueType VT = N->getValueType(0);
1918 // Check to see if we can do this.
1919 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1920 return SDOperand(); // BuildUDIV only operates on i32 or i64
1922 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1923 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1925 // Multiply the numerator (operand 0) by the magic value
1927 if (isOperationLegal(ISD::MULHU, VT))
1928 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1929 DAG.getConstant(magics.m, VT));
1930 else if (isOperationLegal(ISD::UMUL_LOHI, VT))
1931 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
1933 DAG.getConstant(magics.m, VT)).Val, 1);
1935 return SDOperand(); // No mulhu or equvialent
1937 Created->push_back(Q.Val);
1939 if (magics.a == 0) {
1940 return DAG.getNode(ISD::SRL, VT, Q,
1941 DAG.getConstant(magics.s, getShiftAmountTy()));
1943 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1945 Created->push_back(NPQ.Val);
1946 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1947 DAG.getConstant(1, getShiftAmountTy()));
1949 Created->push_back(NPQ.Val);
1950 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1952 Created->push_back(NPQ.Val);
1953 return DAG.getNode(ISD::SRL, VT, NPQ,
1954 DAG.getConstant(magics.s-1, getShiftAmountTy()));