1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/CodeGen/SelectionDAG.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/MathExtras.h"
22 TargetLowering::TargetLowering(TargetMachine &tm)
23 : TM(tm), TD(TM.getTargetData()) {
24 assert(ISD::BUILTIN_OP_END <= 128 &&
25 "Fixed size array in TargetLowering is not large enough!");
26 // All operations default to being supported.
27 memset(OpActions, 0, sizeof(OpActions));
29 IsLittleEndian = TD.isLittleEndian();
30 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
31 ShiftAmtHandling = Undefined;
32 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
33 maxStoresPerMemSet = maxStoresPerMemCpy = maxStoresPerMemMove = 8;
34 allowUnalignedMemoryAccesses = false;
35 UseUnderscoreSetJmpLongJmp = false;
36 IntDivIsCheap = false;
37 Pow2DivIsCheap = false;
38 StackPointerRegisterToSaveRestore = 0;
39 SchedPreferenceInfo = SchedulingForLatency;
42 TargetLowering::~TargetLowering() {}
44 /// setValueTypeAction - Set the action for a particular value type. This
45 /// assumes an action has not already been set for this value type.
46 static void SetValueTypeAction(MVT::ValueType VT,
47 TargetLowering::LegalizeAction Action,
49 MVT::ValueType *TransformToType,
50 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
51 ValueTypeActions.setTypeAction(VT, Action);
52 if (Action == TargetLowering::Promote) {
53 MVT::ValueType PromoteTo;
57 unsigned LargerReg = VT+1;
58 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
60 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
61 "Nothing to promote to??");
63 PromoteTo = (MVT::ValueType)LargerReg;
66 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
67 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
68 "Can only promote from int->int or fp->fp!");
69 assert(VT < PromoteTo && "Must promote to a larger type!");
70 TransformToType[VT] = PromoteTo;
71 } else if (Action == TargetLowering::Expand) {
72 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
73 "Cannot expand this type: target must support SOME integer reg!");
74 // Expand to the next smaller integer type!
75 TransformToType[VT] = (MVT::ValueType)(VT-1);
80 /// computeRegisterProperties - Once all of the register classes are added,
81 /// this allows us to compute derived properties we expose.
82 void TargetLowering::computeRegisterProperties() {
83 assert(MVT::LAST_VALUETYPE <= 32 &&
84 "Too many value types for ValueTypeActions to hold!");
86 // Everything defaults to one.
87 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
88 NumElementsForVT[i] = 1;
90 // Find the largest integer register class.
91 unsigned LargestIntReg = MVT::i128;
92 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
93 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
95 // Every integer value type larger than this largest register takes twice as
96 // many registers to represent as the previous ValueType.
97 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
98 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
99 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
101 // Inspect all of the ValueType's possible, deciding how to process them.
102 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
103 // If we are expanding this type, expand it!
104 if (getNumElements((MVT::ValueType)IntReg) != 1)
105 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
107 else if (!isTypeLegal((MVT::ValueType)IntReg))
108 // Otherwise, if we don't have native support, we must promote to a
110 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
111 TransformToType, ValueTypeActions);
113 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
115 // If the target does not have native support for F32, promote it to F64.
116 if (!isTypeLegal(MVT::f32))
117 SetValueTypeAction(MVT::f32, Promote, *this,
118 TransformToType, ValueTypeActions);
120 TransformToType[MVT::f32] = MVT::f32;
122 // Set MVT::Vector to always be Expanded
123 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
126 assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
127 TransformToType[MVT::f64] = MVT::f64;
130 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
136 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
137 /// this predicate to simplify operations downstream. Op and Mask are known to
138 /// be the same type.
139 bool TargetLowering::MaskedValueIsZero(const SDOperand &Op,
140 uint64_t Mask) const {
142 if (Mask == 0) return true;
144 // If we know the result of a setcc has the top bits zero, use this info.
145 switch (Op.getOpcode()) {
147 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
149 return ((Mask & 1) == 0) &&
150 getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
152 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
153 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
154 case ISD::ZERO_EXTEND:
155 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
156 return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)));
157 case ISD::ANY_EXTEND:
158 // If the mask only includes bits in the low part, recurse.
159 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
160 if (Mask >> SrcBits) return false; // Use of unknown top bits.
161 return MaskedValueIsZero(Op.getOperand(0), Mask);
162 case ISD::AssertZext:
163 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
164 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
166 // If either of the operands has zero bits, the result will too.
167 if (MaskedValueIsZero(Op.getOperand(1), Mask) ||
168 MaskedValueIsZero(Op.getOperand(0), Mask))
170 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
171 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
172 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask);
176 return MaskedValueIsZero(Op.getOperand(0), Mask) &&
177 MaskedValueIsZero(Op.getOperand(1), Mask);
179 return MaskedValueIsZero(Op.getOperand(1), Mask) &&
180 MaskedValueIsZero(Op.getOperand(2), Mask);
182 return MaskedValueIsZero(Op.getOperand(2), Mask) &&
183 MaskedValueIsZero(Op.getOperand(3), Mask);
185 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
186 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
187 uint64_t NewVal = Mask << ShAmt->getValue();
188 SrcBits = MVT::getSizeInBits(Op.getValueType());
189 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
190 return MaskedValueIsZero(Op.getOperand(0), NewVal);
194 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
195 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
196 uint64_t NewVal = Mask >> ShAmt->getValue();
197 return MaskedValueIsZero(Op.getOperand(0), NewVal);
201 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
202 if ((Mask&(Mask+1)) == 0) { // All low bits
203 if (MaskedValueIsZero(Op.getOperand(0), Mask) &&
204 MaskedValueIsZero(Op.getOperand(1), Mask))
209 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
210 // We know that the top bits of C-X are clear if X contains less bits
211 // than C (i.e. no wrap-around can happen). For example, 20-X is
212 // positive if we can prove that X is >= 0 and < 16.
213 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
214 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
215 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
216 uint64_t MaskV = (1ULL << (63-NLZ))-1;
217 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV)) {
218 // High bits are clear this value is known to be >= C.
219 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
220 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
229 // Bit counting instructions can not set the high bits of the result
230 // register. The max number of bits sets depends on the input.
231 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
233 // Allow the target to implement this method for its nodes.
234 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
235 return isMaskedValueZeroForTargetNode(Op, Mask);
241 bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
242 uint64_t Mask) const {
243 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
244 "Should use MaskedValueIsZero if you don't know whether Op"
245 " is a target node!");
249 std::vector<unsigned> TargetLowering::
250 getRegForInlineAsmConstraint(const std::string &Constraint) const {
251 // Not a physreg, must not be a register reference or something.
252 if (Constraint[0] != '{') return std::vector<unsigned>();
253 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
255 // Remove the braces from around the name.
256 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
258 // Scan to see if this constraint is a register name.
259 const MRegisterInfo *RI = TM.getRegisterInfo();
260 for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
261 if (const char *Name = RI->get(i).Name)
262 if (StringsEqualNoCase(RegName, Name))
263 return std::vector<unsigned>(1, i);
267 return std::vector<unsigned>();