1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
36 /// InitLibcallNames - Set default libcall names.
38 static void InitLibcallNames(const char **Names) {
39 Names[RTLIB::SHL_I16] = "__ashlhi3";
40 Names[RTLIB::SHL_I32] = "__ashlsi3";
41 Names[RTLIB::SHL_I64] = "__ashldi3";
42 Names[RTLIB::SHL_I128] = "__ashlti3";
43 Names[RTLIB::SRL_I16] = "__lshrhi3";
44 Names[RTLIB::SRL_I32] = "__lshrsi3";
45 Names[RTLIB::SRL_I64] = "__lshrdi3";
46 Names[RTLIB::SRL_I128] = "__lshrti3";
47 Names[RTLIB::SRA_I16] = "__ashrhi3";
48 Names[RTLIB::SRA_I32] = "__ashrsi3";
49 Names[RTLIB::SRA_I64] = "__ashrdi3";
50 Names[RTLIB::SRA_I128] = "__ashrti3";
51 Names[RTLIB::MUL_I8] = "__mulqi3";
52 Names[RTLIB::MUL_I16] = "__mulhi3";
53 Names[RTLIB::MUL_I32] = "__mulsi3";
54 Names[RTLIB::MUL_I64] = "__muldi3";
55 Names[RTLIB::MUL_I128] = "__multi3";
56 Names[RTLIB::MULO_I32] = "__mulosi4";
57 Names[RTLIB::MULO_I64] = "__mulodi4";
58 Names[RTLIB::MULO_I128] = "__muloti4";
59 Names[RTLIB::SDIV_I8] = "__divqi3";
60 Names[RTLIB::SDIV_I16] = "__divhi3";
61 Names[RTLIB::SDIV_I32] = "__divsi3";
62 Names[RTLIB::SDIV_I64] = "__divdi3";
63 Names[RTLIB::SDIV_I128] = "__divti3";
64 Names[RTLIB::UDIV_I8] = "__udivqi3";
65 Names[RTLIB::UDIV_I16] = "__udivhi3";
66 Names[RTLIB::UDIV_I32] = "__udivsi3";
67 Names[RTLIB::UDIV_I64] = "__udivdi3";
68 Names[RTLIB::UDIV_I128] = "__udivti3";
69 Names[RTLIB::SREM_I8] = "__modqi3";
70 Names[RTLIB::SREM_I16] = "__modhi3";
71 Names[RTLIB::SREM_I32] = "__modsi3";
72 Names[RTLIB::SREM_I64] = "__moddi3";
73 Names[RTLIB::SREM_I128] = "__modti3";
74 Names[RTLIB::UREM_I8] = "__umodqi3";
75 Names[RTLIB::UREM_I16] = "__umodhi3";
76 Names[RTLIB::UREM_I32] = "__umodsi3";
77 Names[RTLIB::UREM_I64] = "__umoddi3";
78 Names[RTLIB::UREM_I128] = "__umodti3";
80 // These are generally not available.
81 Names[RTLIB::SDIVREM_I8] = 0;
82 Names[RTLIB::SDIVREM_I16] = 0;
83 Names[RTLIB::SDIVREM_I32] = 0;
84 Names[RTLIB::SDIVREM_I64] = 0;
85 Names[RTLIB::SDIVREM_I128] = 0;
86 Names[RTLIB::UDIVREM_I8] = 0;
87 Names[RTLIB::UDIVREM_I16] = 0;
88 Names[RTLIB::UDIVREM_I32] = 0;
89 Names[RTLIB::UDIVREM_I64] = 0;
90 Names[RTLIB::UDIVREM_I128] = 0;
92 Names[RTLIB::NEG_I32] = "__negsi2";
93 Names[RTLIB::NEG_I64] = "__negdi2";
94 Names[RTLIB::ADD_F32] = "__addsf3";
95 Names[RTLIB::ADD_F64] = "__adddf3";
96 Names[RTLIB::ADD_F80] = "__addxf3";
97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98 Names[RTLIB::SUB_F32] = "__subsf3";
99 Names[RTLIB::SUB_F64] = "__subdf3";
100 Names[RTLIB::SUB_F80] = "__subxf3";
101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102 Names[RTLIB::MUL_F32] = "__mulsf3";
103 Names[RTLIB::MUL_F64] = "__muldf3";
104 Names[RTLIB::MUL_F80] = "__mulxf3";
105 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
106 Names[RTLIB::DIV_F32] = "__divsf3";
107 Names[RTLIB::DIV_F64] = "__divdf3";
108 Names[RTLIB::DIV_F80] = "__divxf3";
109 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
110 Names[RTLIB::REM_F32] = "fmodf";
111 Names[RTLIB::REM_F64] = "fmod";
112 Names[RTLIB::REM_F80] = "fmodl";
113 Names[RTLIB::REM_PPCF128] = "fmodl";
114 Names[RTLIB::FMA_F32] = "fmaf";
115 Names[RTLIB::FMA_F64] = "fma";
116 Names[RTLIB::FMA_F80] = "fmal";
117 Names[RTLIB::FMA_PPCF128] = "fmal";
118 Names[RTLIB::POWI_F32] = "__powisf2";
119 Names[RTLIB::POWI_F64] = "__powidf2";
120 Names[RTLIB::POWI_F80] = "__powixf2";
121 Names[RTLIB::POWI_PPCF128] = "__powitf2";
122 Names[RTLIB::SQRT_F32] = "sqrtf";
123 Names[RTLIB::SQRT_F64] = "sqrt";
124 Names[RTLIB::SQRT_F80] = "sqrtl";
125 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
126 Names[RTLIB::LOG_F32] = "logf";
127 Names[RTLIB::LOG_F64] = "log";
128 Names[RTLIB::LOG_F80] = "logl";
129 Names[RTLIB::LOG_PPCF128] = "logl";
130 Names[RTLIB::LOG2_F32] = "log2f";
131 Names[RTLIB::LOG2_F64] = "log2";
132 Names[RTLIB::LOG2_F80] = "log2l";
133 Names[RTLIB::LOG2_PPCF128] = "log2l";
134 Names[RTLIB::LOG10_F32] = "log10f";
135 Names[RTLIB::LOG10_F64] = "log10";
136 Names[RTLIB::LOG10_F80] = "log10l";
137 Names[RTLIB::LOG10_PPCF128] = "log10l";
138 Names[RTLIB::EXP_F32] = "expf";
139 Names[RTLIB::EXP_F64] = "exp";
140 Names[RTLIB::EXP_F80] = "expl";
141 Names[RTLIB::EXP_PPCF128] = "expl";
142 Names[RTLIB::EXP2_F32] = "exp2f";
143 Names[RTLIB::EXP2_F64] = "exp2";
144 Names[RTLIB::EXP2_F80] = "exp2l";
145 Names[RTLIB::EXP2_PPCF128] = "exp2l";
146 Names[RTLIB::SIN_F32] = "sinf";
147 Names[RTLIB::SIN_F64] = "sin";
148 Names[RTLIB::SIN_F80] = "sinl";
149 Names[RTLIB::SIN_PPCF128] = "sinl";
150 Names[RTLIB::COS_F32] = "cosf";
151 Names[RTLIB::COS_F64] = "cos";
152 Names[RTLIB::COS_F80] = "cosl";
153 Names[RTLIB::COS_PPCF128] = "cosl";
154 Names[RTLIB::POW_F32] = "powf";
155 Names[RTLIB::POW_F64] = "pow";
156 Names[RTLIB::POW_F80] = "powl";
157 Names[RTLIB::POW_PPCF128] = "powl";
158 Names[RTLIB::CEIL_F32] = "ceilf";
159 Names[RTLIB::CEIL_F64] = "ceil";
160 Names[RTLIB::CEIL_F80] = "ceill";
161 Names[RTLIB::CEIL_PPCF128] = "ceill";
162 Names[RTLIB::TRUNC_F32] = "truncf";
163 Names[RTLIB::TRUNC_F64] = "trunc";
164 Names[RTLIB::TRUNC_F80] = "truncl";
165 Names[RTLIB::TRUNC_PPCF128] = "truncl";
166 Names[RTLIB::RINT_F32] = "rintf";
167 Names[RTLIB::RINT_F64] = "rint";
168 Names[RTLIB::RINT_F80] = "rintl";
169 Names[RTLIB::RINT_PPCF128] = "rintl";
170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174 Names[RTLIB::FLOOR_F32] = "floorf";
175 Names[RTLIB::FLOOR_F64] = "floor";
176 Names[RTLIB::FLOOR_F80] = "floorl";
177 Names[RTLIB::FLOOR_PPCF128] = "floorl";
178 Names[RTLIB::COPYSIGN_F32] = "copysignf";
179 Names[RTLIB::COPYSIGN_F64] = "copysign";
180 Names[RTLIB::COPYSIGN_F80] = "copysignl";
181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
246 Names[RTLIB::OEQ_F32] = "__eqsf2";
247 Names[RTLIB::OEQ_F64] = "__eqdf2";
248 Names[RTLIB::UNE_F32] = "__nesf2";
249 Names[RTLIB::UNE_F64] = "__nedf2";
250 Names[RTLIB::OGE_F32] = "__gesf2";
251 Names[RTLIB::OGE_F64] = "__gedf2";
252 Names[RTLIB::OLT_F32] = "__ltsf2";
253 Names[RTLIB::OLT_F64] = "__ltdf2";
254 Names[RTLIB::OLE_F32] = "__lesf2";
255 Names[RTLIB::OLE_F64] = "__ledf2";
256 Names[RTLIB::OGT_F32] = "__gtsf2";
257 Names[RTLIB::OGT_F64] = "__gtdf2";
258 Names[RTLIB::UO_F32] = "__unordsf2";
259 Names[RTLIB::UO_F64] = "__unorddf2";
260 Names[RTLIB::O_F32] = "__unordsf2";
261 Names[RTLIB::O_F64] = "__unorddf2";
262 Names[RTLIB::MEMCPY] = "memcpy";
263 Names[RTLIB::MEMMOVE] = "memmove";
264 Names[RTLIB::MEMSET] = "memset";
265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
300 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
302 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304 CCs[i] = CallingConv::C;
308 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
309 /// UNKNOWN_LIBCALL if there is none.
310 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
311 if (OpVT == MVT::f32) {
312 if (RetVT == MVT::f64)
313 return FPEXT_F32_F64;
316 return UNKNOWN_LIBCALL;
319 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
320 /// UNKNOWN_LIBCALL if there is none.
321 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
322 if (RetVT == MVT::f32) {
323 if (OpVT == MVT::f64)
324 return FPROUND_F64_F32;
325 if (OpVT == MVT::f80)
326 return FPROUND_F80_F32;
327 if (OpVT == MVT::ppcf128)
328 return FPROUND_PPCF128_F32;
329 } else if (RetVT == MVT::f64) {
330 if (OpVT == MVT::f80)
331 return FPROUND_F80_F64;
332 if (OpVT == MVT::ppcf128)
333 return FPROUND_PPCF128_F64;
336 return UNKNOWN_LIBCALL;
339 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340 /// UNKNOWN_LIBCALL if there is none.
341 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
342 if (OpVT == MVT::f32) {
343 if (RetVT == MVT::i8)
344 return FPTOSINT_F32_I8;
345 if (RetVT == MVT::i16)
346 return FPTOSINT_F32_I16;
347 if (RetVT == MVT::i32)
348 return FPTOSINT_F32_I32;
349 if (RetVT == MVT::i64)
350 return FPTOSINT_F32_I64;
351 if (RetVT == MVT::i128)
352 return FPTOSINT_F32_I128;
353 } else if (OpVT == MVT::f64) {
354 if (RetVT == MVT::i8)
355 return FPTOSINT_F64_I8;
356 if (RetVT == MVT::i16)
357 return FPTOSINT_F64_I16;
358 if (RetVT == MVT::i32)
359 return FPTOSINT_F64_I32;
360 if (RetVT == MVT::i64)
361 return FPTOSINT_F64_I64;
362 if (RetVT == MVT::i128)
363 return FPTOSINT_F64_I128;
364 } else if (OpVT == MVT::f80) {
365 if (RetVT == MVT::i32)
366 return FPTOSINT_F80_I32;
367 if (RetVT == MVT::i64)
368 return FPTOSINT_F80_I64;
369 if (RetVT == MVT::i128)
370 return FPTOSINT_F80_I128;
371 } else if (OpVT == MVT::ppcf128) {
372 if (RetVT == MVT::i32)
373 return FPTOSINT_PPCF128_I32;
374 if (RetVT == MVT::i64)
375 return FPTOSINT_PPCF128_I64;
376 if (RetVT == MVT::i128)
377 return FPTOSINT_PPCF128_I128;
379 return UNKNOWN_LIBCALL;
382 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383 /// UNKNOWN_LIBCALL if there is none.
384 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
385 if (OpVT == MVT::f32) {
386 if (RetVT == MVT::i8)
387 return FPTOUINT_F32_I8;
388 if (RetVT == MVT::i16)
389 return FPTOUINT_F32_I16;
390 if (RetVT == MVT::i32)
391 return FPTOUINT_F32_I32;
392 if (RetVT == MVT::i64)
393 return FPTOUINT_F32_I64;
394 if (RetVT == MVT::i128)
395 return FPTOUINT_F32_I128;
396 } else if (OpVT == MVT::f64) {
397 if (RetVT == MVT::i8)
398 return FPTOUINT_F64_I8;
399 if (RetVT == MVT::i16)
400 return FPTOUINT_F64_I16;
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F64_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F64_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F64_I128;
407 } else if (OpVT == MVT::f80) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F80_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F80_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F80_I128;
414 } else if (OpVT == MVT::ppcf128) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_PPCF128_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_PPCF128_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_PPCF128_I128;
422 return UNKNOWN_LIBCALL;
425 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426 /// UNKNOWN_LIBCALL if there is none.
427 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
428 if (OpVT == MVT::i32) {
429 if (RetVT == MVT::f32)
430 return SINTTOFP_I32_F32;
431 else if (RetVT == MVT::f64)
432 return SINTTOFP_I32_F64;
433 else if (RetVT == MVT::f80)
434 return SINTTOFP_I32_F80;
435 else if (RetVT == MVT::ppcf128)
436 return SINTTOFP_I32_PPCF128;
437 } else if (OpVT == MVT::i64) {
438 if (RetVT == MVT::f32)
439 return SINTTOFP_I64_F32;
440 else if (RetVT == MVT::f64)
441 return SINTTOFP_I64_F64;
442 else if (RetVT == MVT::f80)
443 return SINTTOFP_I64_F80;
444 else if (RetVT == MVT::ppcf128)
445 return SINTTOFP_I64_PPCF128;
446 } else if (OpVT == MVT::i128) {
447 if (RetVT == MVT::f32)
448 return SINTTOFP_I128_F32;
449 else if (RetVT == MVT::f64)
450 return SINTTOFP_I128_F64;
451 else if (RetVT == MVT::f80)
452 return SINTTOFP_I128_F80;
453 else if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I128_PPCF128;
456 return UNKNOWN_LIBCALL;
459 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460 /// UNKNOWN_LIBCALL if there is none.
461 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
462 if (OpVT == MVT::i32) {
463 if (RetVT == MVT::f32)
464 return UINTTOFP_I32_F32;
465 else if (RetVT == MVT::f64)
466 return UINTTOFP_I32_F64;
467 else if (RetVT == MVT::f80)
468 return UINTTOFP_I32_F80;
469 else if (RetVT == MVT::ppcf128)
470 return UINTTOFP_I32_PPCF128;
471 } else if (OpVT == MVT::i64) {
472 if (RetVT == MVT::f32)
473 return UINTTOFP_I64_F32;
474 else if (RetVT == MVT::f64)
475 return UINTTOFP_I64_F64;
476 else if (RetVT == MVT::f80)
477 return UINTTOFP_I64_F80;
478 else if (RetVT == MVT::ppcf128)
479 return UINTTOFP_I64_PPCF128;
480 } else if (OpVT == MVT::i128) {
481 if (RetVT == MVT::f32)
482 return UINTTOFP_I128_F32;
483 else if (RetVT == MVT::f64)
484 return UINTTOFP_I128_F64;
485 else if (RetVT == MVT::f80)
486 return UINTTOFP_I128_F80;
487 else if (RetVT == MVT::ppcf128)
488 return UINTTOFP_I128_PPCF128;
490 return UNKNOWN_LIBCALL;
493 /// InitCmpLibcallCCs - Set default comparison libcall CC.
495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499 CCs[RTLIB::UNE_F32] = ISD::SETNE;
500 CCs[RTLIB::UNE_F64] = ISD::SETNE;
501 CCs[RTLIB::OGE_F32] = ISD::SETGE;
502 CCs[RTLIB::OGE_F64] = ISD::SETGE;
503 CCs[RTLIB::OLT_F32] = ISD::SETLT;
504 CCs[RTLIB::OLT_F64] = ISD::SETLT;
505 CCs[RTLIB::OLE_F32] = ISD::SETLE;
506 CCs[RTLIB::OLE_F64] = ISD::SETLE;
507 CCs[RTLIB::OGT_F32] = ISD::SETGT;
508 CCs[RTLIB::OGT_F64] = ISD::SETGT;
509 CCs[RTLIB::UO_F32] = ISD::SETNE;
510 CCs[RTLIB::UO_F64] = ISD::SETNE;
511 CCs[RTLIB::O_F32] = ISD::SETEQ;
512 CCs[RTLIB::O_F64] = ISD::SETEQ;
515 /// NOTE: The constructor takes ownership of TLOF.
516 TargetLowering::TargetLowering(const TargetMachine &tm,
517 const TargetLoweringObjectFile *tlof)
518 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
519 // All operations default to being supported.
520 memset(OpActions, 0, sizeof(OpActions));
521 memset(LoadExtActions, 0, sizeof(LoadExtActions));
522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
524 memset(CondCodeActions, 0, sizeof(CondCodeActions));
526 // Set default actions for various operations.
527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
528 // Default all indexed load / store to expand.
529 for (unsigned IM = (unsigned)ISD::PRE_INC;
530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
535 // These operations default to expand.
536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
540 // Most targets ignore the @llvm.prefetch intrinsic.
541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
543 // ConstantFP nodes default to expand. Targets can either change this to
544 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
545 // to optimize expansions for certain constants.
546 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
547 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
548 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
549 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
551 // These library functions default to expand.
552 setOperationAction(ISD::FLOG , MVT::f16, Expand);
553 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
554 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
555 setOperationAction(ISD::FEXP , MVT::f16, Expand);
556 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
557 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
558 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
559 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
560 setOperationAction(ISD::FRINT, MVT::f16, Expand);
561 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
562 setOperationAction(ISD::FLOG , MVT::f32, Expand);
563 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
564 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
565 setOperationAction(ISD::FEXP , MVT::f32, Expand);
566 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
567 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
568 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
569 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
570 setOperationAction(ISD::FRINT, MVT::f32, Expand);
571 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
572 setOperationAction(ISD::FLOG , MVT::f64, Expand);
573 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
574 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
575 setOperationAction(ISD::FEXP , MVT::f64, Expand);
576 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
577 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
578 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
579 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
580 setOperationAction(ISD::FRINT, MVT::f64, Expand);
581 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
583 // Default ISD::TRAP to expand (which turns it into abort).
584 setOperationAction(ISD::TRAP, MVT::Other, Expand);
586 IsLittleEndian = TD->isLittleEndian();
587 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
588 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
589 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
590 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
591 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
592 = maxStoresPerMemmoveOptSize = 4;
593 benefitFromCodePlacementOpt = false;
594 UseUnderscoreSetJmp = false;
595 UseUnderscoreLongJmp = false;
596 SelectIsExpensive = false;
597 IntDivIsCheap = false;
598 Pow2DivIsCheap = false;
599 JumpIsExpensive = false;
600 predictableSelectIsExpensive = false;
601 StackPointerRegisterToSaveRestore = 0;
602 ExceptionPointerRegister = 0;
603 ExceptionSelectorRegister = 0;
604 BooleanContents = UndefinedBooleanContent;
605 BooleanVectorContents = UndefinedBooleanContent;
606 SchedPreferenceInfo = Sched::ILP;
608 JumpBufAlignment = 0;
609 MinFunctionAlignment = 0;
610 PrefFunctionAlignment = 0;
611 PrefLoopAlignment = 0;
612 MinStackArgumentAlignment = 1;
613 ShouldFoldAtomicFences = false;
614 InsertFencesForAtomic = false;
615 SupportJumpTables = true;
617 InitLibcallNames(LibcallRoutineNames);
618 InitCmpLibcallCCs(CmpLibcallCCs);
619 InitLibcallCallingConvs(LibcallCallingConvs);
622 TargetLowering::~TargetLowering() {
626 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
627 return MVT::getIntegerVT(8*TD->getPointerSize());
630 /// canOpTrap - Returns true if the operation can trap for the value type.
631 /// VT must be a legal type.
632 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
633 assert(isTypeLegal(VT));
648 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
649 unsigned &NumIntermediates,
651 TargetLowering *TLI) {
652 // Figure out the right, legal destination reg to copy into.
653 unsigned NumElts = VT.getVectorNumElements();
654 MVT EltTy = VT.getVectorElementType();
656 unsigned NumVectorRegs = 1;
658 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
659 // could break down into LHS/RHS like LegalizeDAG does.
660 if (!isPowerOf2_32(NumElts)) {
661 NumVectorRegs = NumElts;
665 // Divide the input until we get to a supported size. This will always
666 // end with a scalar if the target doesn't support vectors.
667 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
672 NumIntermediates = NumVectorRegs;
674 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
675 if (!TLI->isTypeLegal(NewVT))
677 IntermediateVT = NewVT;
679 unsigned NewVTSize = NewVT.getSizeInBits();
681 // Convert sizes such as i33 to i64.
682 if (!isPowerOf2_32(NewVTSize))
683 NewVTSize = NextPowerOf2(NewVTSize);
685 EVT DestVT = TLI->getRegisterType(NewVT);
687 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
688 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
690 // Otherwise, promotion or legal types use the same number of registers as
691 // the vector decimated to the appropriate level.
692 return NumVectorRegs;
695 /// isLegalRC - Return true if the value types that can be represented by the
696 /// specified register class are all legal.
697 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
698 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
706 /// findRepresentativeClass - Return the largest legal super-reg register class
707 /// of the register class for the specified type and its associated "cost".
708 std::pair<const TargetRegisterClass*, uint8_t>
709 TargetLowering::findRepresentativeClass(EVT VT) const {
710 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
711 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
713 return std::make_pair(RC, 0);
715 // Compute the set of all super-register classes.
716 BitVector SuperRegRC(TRI->getNumRegClasses());
717 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
718 SuperRegRC.setBitsInMask(RCI.getMask());
720 // Find the first legal register class with the largest spill size.
721 const TargetRegisterClass *BestRC = RC;
722 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
723 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
724 // We want the largest possible spill size.
725 if (SuperRC->getSize() <= BestRC->getSize())
727 if (!isLegalRC(SuperRC))
731 return std::make_pair(BestRC, 1);
734 /// computeRegisterProperties - Once all of the register classes are added,
735 /// this allows us to compute derived properties we expose.
736 void TargetLowering::computeRegisterProperties() {
737 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
738 "Too many value types for ValueTypeActions to hold!");
740 // Everything defaults to needing one register.
741 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
742 NumRegistersForVT[i] = 1;
743 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
745 // ...except isVoid, which doesn't need any registers.
746 NumRegistersForVT[MVT::isVoid] = 0;
748 // Find the largest integer register class.
749 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
750 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
751 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
753 // Every integer value type larger than this largest register takes twice as
754 // many registers to represent as the previous ValueType.
755 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
756 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
757 if (!ExpandedVT.isInteger())
759 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
760 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
761 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
762 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
765 // Inspect all of the ValueType's smaller than the largest integer
766 // register to see which ones need promotion.
767 unsigned LegalIntReg = LargestIntReg;
768 for (unsigned IntReg = LargestIntReg - 1;
769 IntReg >= (unsigned)MVT::i1; --IntReg) {
770 EVT IVT = (MVT::SimpleValueType)IntReg;
771 if (isTypeLegal(IVT)) {
772 LegalIntReg = IntReg;
774 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
775 (MVT::SimpleValueType)LegalIntReg;
776 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
780 // ppcf128 type is really two f64's.
781 if (!isTypeLegal(MVT::ppcf128)) {
782 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
783 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
784 TransformToType[MVT::ppcf128] = MVT::f64;
785 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
788 // Decide how to handle f64. If the target does not have native f64 support,
789 // expand it to i64 and we will be generating soft float library calls.
790 if (!isTypeLegal(MVT::f64)) {
791 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
792 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
793 TransformToType[MVT::f64] = MVT::i64;
794 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
797 // Decide how to handle f32. If the target does not have native support for
798 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
799 if (!isTypeLegal(MVT::f32)) {
800 if (isTypeLegal(MVT::f64)) {
801 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
802 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
803 TransformToType[MVT::f32] = MVT::f64;
804 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
806 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
807 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
808 TransformToType[MVT::f32] = MVT::i32;
809 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
813 // Loop over all of the vector value types to see which need transformations.
814 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
815 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
816 MVT VT = (MVT::SimpleValueType)i;
817 if (isTypeLegal(VT)) continue;
819 // Determine if there is a legal wider type. If so, we should promote to
820 // that wider vector type.
821 EVT EltVT = VT.getVectorElementType();
822 unsigned NElts = VT.getVectorNumElements();
824 bool IsLegalWiderType = false;
825 // First try to promote the elements of integer vectors. If no legal
826 // promotion was found, fallback to the widen-vector method.
827 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
828 EVT SVT = (MVT::SimpleValueType)nVT;
829 // Promote vectors of integers to vectors with the same number
830 // of elements, with a wider element type.
831 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
832 && SVT.getVectorNumElements() == NElts &&
833 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
834 TransformToType[i] = SVT;
835 RegisterTypeForVT[i] = SVT;
836 NumRegistersForVT[i] = 1;
837 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
838 IsLegalWiderType = true;
843 if (IsLegalWiderType) continue;
845 // Try to widen the vector.
846 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
847 EVT SVT = (MVT::SimpleValueType)nVT;
848 if (SVT.getVectorElementType() == EltVT &&
849 SVT.getVectorNumElements() > NElts &&
851 TransformToType[i] = SVT;
852 RegisterTypeForVT[i] = SVT;
853 NumRegistersForVT[i] = 1;
854 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
855 IsLegalWiderType = true;
859 if (IsLegalWiderType) continue;
864 unsigned NumIntermediates;
865 NumRegistersForVT[i] =
866 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
868 RegisterTypeForVT[i] = RegisterVT;
870 EVT NVT = VT.getPow2VectorType();
872 // Type is already a power of 2. The default action is to split.
873 TransformToType[i] = MVT::Other;
874 unsigned NumElts = VT.getVectorNumElements();
875 ValueTypeActions.setTypeAction(VT,
876 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
878 TransformToType[i] = NVT;
879 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
883 // Determine the 'representative' register class for each value type.
884 // An representative register class is the largest (meaning one which is
885 // not a sub-register class / subreg register class) legal register class for
886 // a group of value types. For example, on i386, i8, i16, and i32
887 // representative would be GR32; while on x86_64 it's GR64.
888 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
889 const TargetRegisterClass* RRC;
891 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
892 RepRegClassForVT[i] = RRC;
893 RepRegClassCostForVT[i] = Cost;
897 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
902 EVT TargetLowering::getSetCCResultType(EVT VT) const {
903 assert(!VT.isVector() && "No default SetCC type for vectors!");
904 return PointerTy.SimpleTy;
907 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
908 return MVT::i32; // return the default value
911 /// getVectorTypeBreakdown - Vector types are broken down into some number of
912 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
913 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
914 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
916 /// This method returns the number of registers needed, and the VT for each
917 /// register. It also returns the VT and quantity of the intermediate values
918 /// before they are promoted/expanded.
920 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
922 unsigned &NumIntermediates,
923 EVT &RegisterVT) const {
924 unsigned NumElts = VT.getVectorNumElements();
926 // If there is a wider vector type with the same element type as this one,
927 // or a promoted vector type that has the same number of elements which
928 // are wider, then we should convert to that legal vector type.
929 // This handles things like <2 x float> -> <4 x float> and
930 // <4 x i1> -> <4 x i32>.
931 LegalizeTypeAction TA = getTypeAction(Context, VT);
932 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
933 RegisterVT = getTypeToTransformTo(Context, VT);
934 if (isTypeLegal(RegisterVT)) {
935 IntermediateVT = RegisterVT;
936 NumIntermediates = 1;
941 // Figure out the right, legal destination reg to copy into.
942 EVT EltTy = VT.getVectorElementType();
944 unsigned NumVectorRegs = 1;
946 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
947 // could break down into LHS/RHS like LegalizeDAG does.
948 if (!isPowerOf2_32(NumElts)) {
949 NumVectorRegs = NumElts;
953 // Divide the input until we get to a supported size. This will always
954 // end with a scalar if the target doesn't support vectors.
955 while (NumElts > 1 && !isTypeLegal(
956 EVT::getVectorVT(Context, EltTy, NumElts))) {
961 NumIntermediates = NumVectorRegs;
963 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
964 if (!isTypeLegal(NewVT))
966 IntermediateVT = NewVT;
968 EVT DestVT = getRegisterType(Context, NewVT);
970 unsigned NewVTSize = NewVT.getSizeInBits();
972 // Convert sizes such as i33 to i64.
973 if (!isPowerOf2_32(NewVTSize))
974 NewVTSize = NextPowerOf2(NewVTSize);
976 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
977 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
979 // Otherwise, promotion or legal types use the same number of registers as
980 // the vector decimated to the appropriate level.
981 return NumVectorRegs;
984 /// Get the EVTs and ArgFlags collections that represent the legalized return
985 /// type of the given function. This does not require a DAG or a return value,
986 /// and is suitable for use before any DAGs for the function are constructed.
987 /// TODO: Move this out of TargetLowering.cpp.
988 void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
989 SmallVectorImpl<ISD::OutputArg> &Outs,
990 const TargetLowering &TLI) {
991 SmallVector<EVT, 4> ValueVTs;
992 ComputeValueVTs(TLI, ReturnType, ValueVTs);
993 unsigned NumValues = ValueVTs.size();
994 if (NumValues == 0) return;
996 for (unsigned j = 0, f = NumValues; j != f; ++j) {
997 EVT VT = ValueVTs[j];
998 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1000 if (attr & Attribute::SExt)
1001 ExtendKind = ISD::SIGN_EXTEND;
1002 else if (attr & Attribute::ZExt)
1003 ExtendKind = ISD::ZERO_EXTEND;
1005 // FIXME: C calling convention requires the return type to be promoted to
1006 // at least 32-bit. But this is not necessary for non-C calling
1007 // conventions. The frontend should mark functions whose return values
1008 // require promoting with signext or zeroext attributes.
1009 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1010 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1011 if (VT.bitsLT(MinVT))
1015 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1016 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1018 // 'inreg' on function refers to return value
1019 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1020 if (attr & Attribute::InReg)
1023 // Propagate extension type if any
1024 if (attr & Attribute::SExt)
1026 else if (attr & Attribute::ZExt)
1029 for (unsigned i = 0; i < NumParts; ++i) {
1030 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1035 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1036 /// function arguments in the caller parameter area. This is the actual
1037 /// alignment, not its logarithm.
1038 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1039 return TD->getCallFrameTypeAlignment(Ty);
1042 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1043 /// current function. The returned value is a member of the
1044 /// MachineJumpTableInfo::JTEntryKind enum.
1045 unsigned TargetLowering::getJumpTableEncoding() const {
1046 // In non-pic modes, just use the address of a block.
1047 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1048 return MachineJumpTableInfo::EK_BlockAddress;
1050 // In PIC mode, if the target supports a GPRel32 directive, use it.
1051 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1052 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1054 // Otherwise, use a label difference.
1055 return MachineJumpTableInfo::EK_LabelDifference32;
1058 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1059 SelectionDAG &DAG) const {
1060 // If our PIC model is GP relative, use the global offset table as the base.
1061 unsigned JTEncoding = getJumpTableEncoding();
1063 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1064 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
1065 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1070 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1071 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1074 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1075 unsigned JTI,MCContext &Ctx) const{
1076 // The normal PIC reloc base is the label at the start of the jump table.
1077 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1081 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1082 // Assume that everything is safe in static mode.
1083 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1086 // In dynamic-no-pic mode, assume that known defined values are safe.
1087 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1089 !GA->getGlobal()->isDeclaration() &&
1090 !GA->getGlobal()->isWeakForLinker())
1093 // Otherwise assume nothing is safe.
1097 //===----------------------------------------------------------------------===//
1098 // Optimization Methods
1099 //===----------------------------------------------------------------------===//
1101 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1102 /// specified instruction is a constant integer. If so, check to see if there
1103 /// are any bits set in the constant that are not demanded. If so, shrink the
1104 /// constant and return true.
1105 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1106 const APInt &Demanded) {
1107 DebugLoc dl = Op.getDebugLoc();
1109 // FIXME: ISD::SELECT, ISD::SELECT_CC
1110 switch (Op.getOpcode()) {
1115 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1116 if (!C) return false;
1118 if (Op.getOpcode() == ISD::XOR &&
1119 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1122 // if we can expand it to have all bits set, do it
1123 if (C->getAPIntValue().intersects(~Demanded)) {
1124 EVT VT = Op.getValueType();
1125 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1126 DAG.getConstant(Demanded &
1129 return CombineTo(Op, New);
1139 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1140 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1141 /// cast, but it could be generalized for targets with other types of
1142 /// implicit widening casts.
1144 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1146 const APInt &Demanded,
1148 assert(Op.getNumOperands() == 2 &&
1149 "ShrinkDemandedOp only supports binary operators!");
1150 assert(Op.getNode()->getNumValues() == 1 &&
1151 "ShrinkDemandedOp only supports nodes with one result!");
1153 // Don't do this if the node has another user, which may require the
1155 if (!Op.getNode()->hasOneUse())
1158 // Search for the smallest integer type with free casts to and from
1159 // Op's type. For expedience, just check power-of-2 integer types.
1160 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1161 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1162 if (!isPowerOf2_32(SmallVTBits))
1163 SmallVTBits = NextPowerOf2(SmallVTBits);
1164 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1165 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1166 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1167 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1168 // We found a type with free casts.
1169 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1170 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1171 Op.getNode()->getOperand(0)),
1172 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1173 Op.getNode()->getOperand(1)));
1174 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1175 return CombineTo(Op, Z);
1181 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1182 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1183 /// use this information to simplify Op, create a new simplified DAG node and
1184 /// return true, returning the original and new nodes in Old and New. Otherwise,
1185 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1186 /// the expression (used to simplify the caller). The KnownZero/One bits may
1187 /// only be accurate for those bits in the DemandedMask.
1188 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1189 const APInt &DemandedMask,
1192 TargetLoweringOpt &TLO,
1193 unsigned Depth) const {
1194 unsigned BitWidth = DemandedMask.getBitWidth();
1195 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1196 "Mask size mismatches value type size!");
1197 APInt NewMask = DemandedMask;
1198 DebugLoc dl = Op.getDebugLoc();
1200 // Don't know anything.
1201 KnownZero = KnownOne = APInt(BitWidth, 0);
1203 // Other users may use these bits.
1204 if (!Op.getNode()->hasOneUse()) {
1206 // If not at the root, Just compute the KnownZero/KnownOne bits to
1207 // simplify things downstream.
1208 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1211 // If this is the root being simplified, allow it to have multiple uses,
1212 // just set the NewMask to all bits.
1213 NewMask = APInt::getAllOnesValue(BitWidth);
1214 } else if (DemandedMask == 0) {
1215 // Not demanding any bits from Op.
1216 if (Op.getOpcode() != ISD::UNDEF)
1217 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1219 } else if (Depth == 6) { // Limit search depth.
1223 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1224 switch (Op.getOpcode()) {
1226 // We know all of the bits for a constant!
1227 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1228 KnownZero = ~KnownOne;
1229 return false; // Don't fall through, will infinitely loop.
1231 // If the RHS is a constant, check to see if the LHS would be zero without
1232 // using the bits from the RHS. Below, we use knowledge about the RHS to
1233 // simplify the LHS, here we're using information from the LHS to simplify
1235 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1236 APInt LHSZero, LHSOne;
1237 // Do not increment Depth here; that can cause an infinite loop.
1238 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1239 // If the LHS already has zeros where RHSC does, this and is dead.
1240 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1241 return TLO.CombineTo(Op, Op.getOperand(0));
1242 // If any of the set bits in the RHS are known zero on the LHS, shrink
1244 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1248 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1249 KnownOne, TLO, Depth+1))
1251 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1252 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1253 KnownZero2, KnownOne2, TLO, Depth+1))
1255 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1257 // If all of the demanded bits are known one on one side, return the other.
1258 // These bits cannot contribute to the result of the 'and'.
1259 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1260 return TLO.CombineTo(Op, Op.getOperand(0));
1261 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1262 return TLO.CombineTo(Op, Op.getOperand(1));
1263 // If all of the demanded bits in the inputs are known zeros, return zero.
1264 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1265 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1266 // If the RHS is a constant, see if we can simplify it.
1267 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1269 // If the operation can be done in a smaller type, do so.
1270 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1273 // Output known-1 bits are only known if set in both the LHS & RHS.
1274 KnownOne &= KnownOne2;
1275 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1276 KnownZero |= KnownZero2;
1279 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1280 KnownOne, TLO, Depth+1))
1282 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1283 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1284 KnownZero2, KnownOne2, TLO, Depth+1))
1286 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1288 // If all of the demanded bits are known zero on one side, return the other.
1289 // These bits cannot contribute to the result of the 'or'.
1290 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1291 return TLO.CombineTo(Op, Op.getOperand(0));
1292 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1293 return TLO.CombineTo(Op, Op.getOperand(1));
1294 // If all of the potentially set bits on one side are known to be set on
1295 // the other side, just use the 'other' side.
1296 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1297 return TLO.CombineTo(Op, Op.getOperand(0));
1298 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1299 return TLO.CombineTo(Op, Op.getOperand(1));
1300 // If the RHS is a constant, see if we can simplify it.
1301 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1303 // If the operation can be done in a smaller type, do so.
1304 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1307 // Output known-0 bits are only known if clear in both the LHS & RHS.
1308 KnownZero &= KnownZero2;
1309 // Output known-1 are known to be set if set in either the LHS | RHS.
1310 KnownOne |= KnownOne2;
1313 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1314 KnownOne, TLO, Depth+1))
1316 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1317 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1318 KnownOne2, TLO, Depth+1))
1320 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1322 // If all of the demanded bits are known zero on one side, return the other.
1323 // These bits cannot contribute to the result of the 'xor'.
1324 if ((KnownZero & NewMask) == NewMask)
1325 return TLO.CombineTo(Op, Op.getOperand(0));
1326 if ((KnownZero2 & NewMask) == NewMask)
1327 return TLO.CombineTo(Op, Op.getOperand(1));
1328 // If the operation can be done in a smaller type, do so.
1329 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1332 // If all of the unknown bits are known to be zero on one side or the other
1333 // (but not both) turn this into an *inclusive* or.
1334 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1335 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1336 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1340 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1341 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1342 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1343 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1345 // If all of the demanded bits on one side are known, and all of the set
1346 // bits on that side are also known to be set on the other side, turn this
1347 // into an AND, as we know the bits will be cleared.
1348 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1349 // NB: it is okay if more bits are known than are requested
1350 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1351 if (KnownOne == KnownOne2) { // set bits are the same on both sides
1352 EVT VT = Op.getValueType();
1353 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1354 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1355 Op.getOperand(0), ANDC));
1359 // If the RHS is a constant, see if we can simplify it.
1360 // for XOR, we prefer to force bits to 1 if they will make a -1.
1361 // if we can't force bits, try to shrink constant
1362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1363 APInt Expanded = C->getAPIntValue() | (~NewMask);
1364 // if we can expand it to have all bits set, do it
1365 if (Expanded.isAllOnesValue()) {
1366 if (Expanded != C->getAPIntValue()) {
1367 EVT VT = Op.getValueType();
1368 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1369 TLO.DAG.getConstant(Expanded, VT));
1370 return TLO.CombineTo(Op, New);
1372 // if it already has all the bits set, nothing to change
1373 // but don't shrink either!
1374 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1379 KnownZero = KnownZeroOut;
1380 KnownOne = KnownOneOut;
1383 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1384 KnownOne, TLO, Depth+1))
1386 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1387 KnownOne2, TLO, Depth+1))
1389 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1390 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1392 // If the operands are constants, see if we can simplify them.
1393 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1396 // Only known if known in both the LHS and RHS.
1397 KnownOne &= KnownOne2;
1398 KnownZero &= KnownZero2;
1400 case ISD::SELECT_CC:
1401 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1402 KnownOne, TLO, Depth+1))
1404 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1405 KnownOne2, TLO, Depth+1))
1407 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1408 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1410 // If the operands are constants, see if we can simplify them.
1411 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1414 // Only known if known in both the LHS and RHS.
1415 KnownOne &= KnownOne2;
1416 KnownZero &= KnownZero2;
1419 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1420 unsigned ShAmt = SA->getZExtValue();
1421 SDValue InOp = Op.getOperand(0);
1423 // If the shift count is an invalid immediate, don't do anything.
1424 if (ShAmt >= BitWidth)
1427 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1428 // single shift. We can do this if the bottom bits (which are shifted
1429 // out) are never demanded.
1430 if (InOp.getOpcode() == ISD::SRL &&
1431 isa<ConstantSDNode>(InOp.getOperand(1))) {
1432 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1433 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1434 unsigned Opc = ISD::SHL;
1435 int Diff = ShAmt-C1;
1442 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1443 EVT VT = Op.getValueType();
1444 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1445 InOp.getOperand(0), NewSA));
1449 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1450 KnownZero, KnownOne, TLO, Depth+1))
1453 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1454 // are not demanded. This will likely allow the anyext to be folded away.
1455 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1456 SDValue InnerOp = InOp.getNode()->getOperand(0);
1457 EVT InnerVT = InnerOp.getValueType();
1458 unsigned InnerBits = InnerVT.getSizeInBits();
1459 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1460 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1461 EVT ShTy = getShiftAmountTy(InnerVT);
1462 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1465 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1466 TLO.DAG.getConstant(ShAmt, ShTy));
1469 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1474 KnownZero <<= SA->getZExtValue();
1475 KnownOne <<= SA->getZExtValue();
1476 // low bits known zero.
1477 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1481 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1482 EVT VT = Op.getValueType();
1483 unsigned ShAmt = SA->getZExtValue();
1484 unsigned VTSize = VT.getSizeInBits();
1485 SDValue InOp = Op.getOperand(0);
1487 // If the shift count is an invalid immediate, don't do anything.
1488 if (ShAmt >= BitWidth)
1491 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1492 // single shift. We can do this if the top bits (which are shifted out)
1493 // are never demanded.
1494 if (InOp.getOpcode() == ISD::SHL &&
1495 isa<ConstantSDNode>(InOp.getOperand(1))) {
1496 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1497 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1498 unsigned Opc = ISD::SRL;
1499 int Diff = ShAmt-C1;
1506 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1507 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1508 InOp.getOperand(0), NewSA));
1512 // Compute the new bits that are at the top now.
1513 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1514 KnownZero, KnownOne, TLO, Depth+1))
1516 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1517 KnownZero = KnownZero.lshr(ShAmt);
1518 KnownOne = KnownOne.lshr(ShAmt);
1520 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1521 KnownZero |= HighBits; // High bits known zero.
1525 // If this is an arithmetic shift right and only the low-bit is set, we can
1526 // always convert this into a logical shr, even if the shift amount is
1527 // variable. The low bit of the shift cannot be an input sign bit unless
1528 // the shift amount is >= the size of the datatype, which is undefined.
1530 return TLO.CombineTo(Op,
1531 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1532 Op.getOperand(0), Op.getOperand(1)));
1534 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1535 EVT VT = Op.getValueType();
1536 unsigned ShAmt = SA->getZExtValue();
1538 // If the shift count is an invalid immediate, don't do anything.
1539 if (ShAmt >= BitWidth)
1542 APInt InDemandedMask = (NewMask << ShAmt);
1544 // If any of the demanded bits are produced by the sign extension, we also
1545 // demand the input sign bit.
1546 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1547 if (HighBits.intersects(NewMask))
1548 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1550 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1551 KnownZero, KnownOne, TLO, Depth+1))
1553 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1554 KnownZero = KnownZero.lshr(ShAmt);
1555 KnownOne = KnownOne.lshr(ShAmt);
1557 // Handle the sign bit, adjusted to where it is now in the mask.
1558 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1560 // If the input sign bit is known to be zero, or if none of the top bits
1561 // are demanded, turn this into an unsigned shift right.
1562 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1563 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1566 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1567 KnownOne |= HighBits;
1571 case ISD::SIGN_EXTEND_INREG: {
1572 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1574 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1575 // If we only care about the highest bit, don't bother shifting right.
1576 if (MsbMask == DemandedMask) {
1577 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1578 SDValue InOp = Op.getOperand(0);
1580 // Compute the correct shift amount type, which must be getShiftAmountTy
1581 // for scalar types after legalization.
1582 EVT ShiftAmtTy = Op.getValueType();
1583 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1584 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1586 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1587 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1588 Op.getValueType(), InOp, ShiftAmt));
1591 // Sign extension. Compute the demanded bits in the result that are not
1592 // present in the input.
1594 APInt::getHighBitsSet(BitWidth,
1595 BitWidth - ExVT.getScalarType().getSizeInBits());
1597 // If none of the extended bits are demanded, eliminate the sextinreg.
1598 if ((NewBits & NewMask) == 0)
1599 return TLO.CombineTo(Op, Op.getOperand(0));
1602 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1603 APInt InputDemandedBits =
1604 APInt::getLowBitsSet(BitWidth,
1605 ExVT.getScalarType().getSizeInBits()) &
1608 // Since the sign extended bits are demanded, we know that the sign
1610 InputDemandedBits |= InSignBit;
1612 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1613 KnownZero, KnownOne, TLO, Depth+1))
1615 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1617 // If the sign bit of the input is known set or clear, then we know the
1618 // top bits of the result.
1620 // If the input sign bit is known zero, convert this into a zero extension.
1621 if (KnownZero.intersects(InSignBit))
1622 return TLO.CombineTo(Op,
1623 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1625 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1626 KnownOne |= NewBits;
1627 KnownZero &= ~NewBits;
1628 } else { // Input sign bit unknown
1629 KnownZero &= ~NewBits;
1630 KnownOne &= ~NewBits;
1634 case ISD::ZERO_EXTEND: {
1635 unsigned OperandBitWidth =
1636 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1637 APInt InMask = NewMask.trunc(OperandBitWidth);
1639 // If none of the top bits are demanded, convert this into an any_extend.
1641 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1642 if (!NewBits.intersects(NewMask))
1643 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1647 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1648 KnownZero, KnownOne, TLO, Depth+1))
1650 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1651 KnownZero = KnownZero.zext(BitWidth);
1652 KnownOne = KnownOne.zext(BitWidth);
1653 KnownZero |= NewBits;
1656 case ISD::SIGN_EXTEND: {
1657 EVT InVT = Op.getOperand(0).getValueType();
1658 unsigned InBits = InVT.getScalarType().getSizeInBits();
1659 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1660 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1661 APInt NewBits = ~InMask & NewMask;
1663 // If none of the top bits are demanded, convert this into an any_extend.
1665 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1669 // Since some of the sign extended bits are demanded, we know that the sign
1671 APInt InDemandedBits = InMask & NewMask;
1672 InDemandedBits |= InSignBit;
1673 InDemandedBits = InDemandedBits.trunc(InBits);
1675 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1676 KnownOne, TLO, Depth+1))
1678 KnownZero = KnownZero.zext(BitWidth);
1679 KnownOne = KnownOne.zext(BitWidth);
1681 // If the sign bit is known zero, convert this to a zero extend.
1682 if (KnownZero.intersects(InSignBit))
1683 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1687 // If the sign bit is known one, the top bits match.
1688 if (KnownOne.intersects(InSignBit)) {
1689 KnownOne |= NewBits;
1690 assert((KnownZero & NewBits) == 0);
1691 } else { // Otherwise, top bits aren't known.
1692 assert((KnownOne & NewBits) == 0);
1693 assert((KnownZero & NewBits) == 0);
1697 case ISD::ANY_EXTEND: {
1698 unsigned OperandBitWidth =
1699 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1700 APInt InMask = NewMask.trunc(OperandBitWidth);
1701 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1702 KnownZero, KnownOne, TLO, Depth+1))
1704 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1705 KnownZero = KnownZero.zext(BitWidth);
1706 KnownOne = KnownOne.zext(BitWidth);
1709 case ISD::TRUNCATE: {
1710 // Simplify the input, using demanded bit information, and compute the known
1711 // zero/one bits live out.
1712 unsigned OperandBitWidth =
1713 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1714 APInt TruncMask = NewMask.zext(OperandBitWidth);
1715 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1716 KnownZero, KnownOne, TLO, Depth+1))
1718 KnownZero = KnownZero.trunc(BitWidth);
1719 KnownOne = KnownOne.trunc(BitWidth);
1721 // If the input is only used by this truncate, see if we can shrink it based
1722 // on the known demanded bits.
1723 if (Op.getOperand(0).getNode()->hasOneUse()) {
1724 SDValue In = Op.getOperand(0);
1725 switch (In.getOpcode()) {
1728 // Shrink SRL by a constant if none of the high bits shifted in are
1730 if (TLO.LegalTypes() &&
1731 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1732 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1735 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1738 SDValue Shift = In.getOperand(1);
1739 if (TLO.LegalTypes()) {
1740 uint64_t ShVal = ShAmt->getZExtValue();
1742 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1745 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1746 OperandBitWidth - BitWidth);
1747 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1749 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1750 // None of the shifted in bits are needed. Add a truncate of the
1751 // shift input, then shift it.
1752 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1755 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1764 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1767 case ISD::AssertZext: {
1768 // AssertZext demands all of the high bits, plus any of the low bits
1769 // demanded by its users.
1770 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1771 APInt InMask = APInt::getLowBitsSet(BitWidth,
1772 VT.getSizeInBits());
1773 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1774 KnownZero, KnownOne, TLO, Depth+1))
1776 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1778 KnownZero |= ~InMask & NewMask;
1782 // If this is an FP->Int bitcast and if the sign bit is the only
1783 // thing demanded, turn this into a FGETSIGN.
1784 if (!TLO.LegalOperations() &&
1785 !Op.getValueType().isVector() &&
1786 !Op.getOperand(0).getValueType().isVector() &&
1787 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1788 Op.getOperand(0).getValueType().isFloatingPoint()) {
1789 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1790 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1791 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1792 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1793 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1794 // place. We expect the SHL to be eliminated by other optimizations.
1795 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1796 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1797 if (!OpVTLegal && OpVTSizeInBits > 32)
1798 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1799 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1800 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1801 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1810 // Add, Sub, and Mul don't demand any bits in positions beyond that
1811 // of the highest bit demanded of them.
1812 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1813 BitWidth - NewMask.countLeadingZeros());
1814 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1815 KnownOne2, TLO, Depth+1))
1817 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1818 KnownOne2, TLO, Depth+1))
1820 // See if the operation should be performed at a smaller bit width.
1821 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1826 // Just use ComputeMaskedBits to compute output bits.
1827 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1831 // If we know the value of all of the demanded bits, return this as a
1833 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1834 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1839 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1840 /// in Mask are known to be either zero or one and return them in the
1841 /// KnownZero/KnownOne bitsets.
1842 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1845 const SelectionDAG &DAG,
1846 unsigned Depth) const {
1847 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1848 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1849 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1850 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1851 "Should use MaskedValueIsZero if you don't know whether Op"
1852 " is a target node!");
1853 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1856 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1857 /// targets that want to expose additional information about sign bits to the
1859 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1860 unsigned Depth) const {
1861 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1862 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1863 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1864 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1865 "Should use ComputeNumSignBits if you don't know whether Op"
1866 " is a target node!");
1870 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1871 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1872 /// determine which bit is set.
1874 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1875 // A left-shift of a constant one will have exactly one bit set, because
1876 // shifting the bit off the end is undefined.
1877 if (Val.getOpcode() == ISD::SHL)
1878 if (ConstantSDNode *C =
1879 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1880 if (C->getAPIntValue() == 1)
1883 // Similarly, a right-shift of a constant sign-bit will have exactly
1885 if (Val.getOpcode() == ISD::SRL)
1886 if (ConstantSDNode *C =
1887 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1888 if (C->getAPIntValue().isSignBit())
1891 // More could be done here, though the above checks are enough
1892 // to handle some common cases.
1894 // Fall back to ComputeMaskedBits to catch other known cases.
1895 EVT OpVT = Val.getValueType();
1896 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1897 APInt KnownZero, KnownOne;
1898 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1899 return (KnownZero.countPopulation() == BitWidth - 1) &&
1900 (KnownOne.countPopulation() == 1);
1903 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1904 /// and cc. If it is unable to simplify it, return a null SDValue.
1906 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1907 ISD::CondCode Cond, bool foldBooleans,
1908 DAGCombinerInfo &DCI, DebugLoc dl) const {
1909 SelectionDAG &DAG = DCI.DAG;
1911 // These setcc operations always fold.
1915 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1917 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1920 // Ensure that the constant occurs on the RHS, and fold constant
1922 if (isa<ConstantSDNode>(N0.getNode()))
1923 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1925 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1926 const APInt &C1 = N1C->getAPIntValue();
1928 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1929 // equality comparison, then we're just comparing whether X itself is
1931 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1932 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1933 N0.getOperand(1).getOpcode() == ISD::Constant) {
1935 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1936 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1937 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1938 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1939 // (srl (ctlz x), 5) == 0 -> X != 0
1940 // (srl (ctlz x), 5) != 1 -> X != 0
1943 // (srl (ctlz x), 5) != 0 -> X == 0
1944 // (srl (ctlz x), 5) == 1 -> X == 0
1947 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1948 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1954 // Look through truncs that don't change the value of a ctpop.
1955 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1956 CTPOP = N0.getOperand(0);
1958 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1959 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1960 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1961 EVT CTVT = CTPOP.getValueType();
1962 SDValue CTOp = CTPOP.getOperand(0);
1964 // (ctpop x) u< 2 -> (x & x-1) == 0
1965 // (ctpop x) u> 1 -> (x & x-1) != 0
1966 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1967 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1968 DAG.getConstant(1, CTVT));
1969 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1970 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1971 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1974 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1977 // (zext x) == C --> x == (trunc C)
1978 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1979 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1980 unsigned MinBits = N0.getValueSizeInBits();
1982 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1984 MinBits = N0->getOperand(0).getValueSizeInBits();
1985 PreZExt = N0->getOperand(0);
1986 } else if (N0->getOpcode() == ISD::AND) {
1987 // DAGCombine turns costly ZExts into ANDs
1988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1989 if ((C->getAPIntValue()+1).isPowerOf2()) {
1990 MinBits = C->getAPIntValue().countTrailingOnes();
1991 PreZExt = N0->getOperand(0);
1993 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1995 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1996 MinBits = LN0->getMemoryVT().getSizeInBits();
2001 // Make sure we're not losing bits from the constant.
2002 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2003 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2004 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2005 // Will get folded away.
2006 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2007 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2008 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2013 // If the LHS is '(and load, const)', the RHS is 0,
2014 // the test is for equality or unsigned, and all 1 bits of the const are
2015 // in the same partial word, see if we can shorten the load.
2016 if (DCI.isBeforeLegalize() &&
2017 N0.getOpcode() == ISD::AND && C1 == 0 &&
2018 N0.getNode()->hasOneUse() &&
2019 isa<LoadSDNode>(N0.getOperand(0)) &&
2020 N0.getOperand(0).getNode()->hasOneUse() &&
2021 isa<ConstantSDNode>(N0.getOperand(1))) {
2022 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2024 unsigned bestWidth = 0, bestOffset = 0;
2025 if (!Lod->isVolatile() && Lod->isUnindexed()) {
2026 unsigned origWidth = N0.getValueType().getSizeInBits();
2027 unsigned maskWidth = origWidth;
2028 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2029 // 8 bits, but have to be careful...
2030 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2031 origWidth = Lod->getMemoryVT().getSizeInBits();
2033 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2034 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2035 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2036 for (unsigned offset=0; offset<origWidth/width; offset++) {
2037 if ((newMask & Mask) == Mask) {
2038 if (!TD->isLittleEndian())
2039 bestOffset = (origWidth/width - offset - 1) * (width/8);
2041 bestOffset = (uint64_t)offset * (width/8);
2042 bestMask = Mask.lshr(offset * (width/8) * 8);
2046 newMask = newMask << width;
2051 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2052 if (newVT.isRound()) {
2053 EVT PtrType = Lod->getOperand(1).getValueType();
2054 SDValue Ptr = Lod->getBasePtr();
2055 if (bestOffset != 0)
2056 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2057 DAG.getConstant(bestOffset, PtrType));
2058 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2059 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2060 Lod->getPointerInfo().getWithOffset(bestOffset),
2061 false, false, false, NewAlign);
2062 return DAG.getSetCC(dl, VT,
2063 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2064 DAG.getConstant(bestMask.trunc(bestWidth),
2066 DAG.getConstant(0LL, newVT), Cond);
2071 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2072 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2073 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2075 // If the comparison constant has bits in the upper part, the
2076 // zero-extended value could never match.
2077 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2078 C1.getBitWidth() - InSize))) {
2082 case ISD::SETEQ: return DAG.getConstant(0, VT);
2085 case ISD::SETNE: return DAG.getConstant(1, VT);
2088 // True if the sign bit of C1 is set.
2089 return DAG.getConstant(C1.isNegative(), VT);
2092 // True if the sign bit of C1 isn't set.
2093 return DAG.getConstant(C1.isNonNegative(), VT);
2099 // Otherwise, we can perform the comparison with the low bits.
2107 EVT newVT = N0.getOperand(0).getValueType();
2108 if (DCI.isBeforeLegalizeOps() ||
2109 (isOperationLegal(ISD::SETCC, newVT) &&
2110 getCondCodeAction(Cond, newVT)==Legal))
2111 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2112 DAG.getConstant(C1.trunc(InSize), newVT),
2117 break; // todo, be more careful with signed comparisons
2119 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2120 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2121 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2122 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2123 EVT ExtDstTy = N0.getValueType();
2124 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2126 // If the constant doesn't fit into the number of bits for the source of
2127 // the sign extension, it is impossible for both sides to be equal.
2128 if (C1.getMinSignedBits() > ExtSrcTyBits)
2129 return DAG.getConstant(Cond == ISD::SETNE, VT);
2132 EVT Op0Ty = N0.getOperand(0).getValueType();
2133 if (Op0Ty == ExtSrcTy) {
2134 ZextOp = N0.getOperand(0);
2136 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2137 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2138 DAG.getConstant(Imm, Op0Ty));
2140 if (!DCI.isCalledByLegalizer())
2141 DCI.AddToWorklist(ZextOp.getNode());
2142 // Otherwise, make this a use of a zext.
2143 return DAG.getSetCC(dl, VT, ZextOp,
2144 DAG.getConstant(C1 & APInt::getLowBitsSet(
2149 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2150 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2151 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2152 if (N0.getOpcode() == ISD::SETCC &&
2153 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2154 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2156 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2157 // Invert the condition.
2158 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2159 CC = ISD::getSetCCInverse(CC,
2160 N0.getOperand(0).getValueType().isInteger());
2161 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2164 if ((N0.getOpcode() == ISD::XOR ||
2165 (N0.getOpcode() == ISD::AND &&
2166 N0.getOperand(0).getOpcode() == ISD::XOR &&
2167 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2168 isa<ConstantSDNode>(N0.getOperand(1)) &&
2169 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2170 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2171 // can only do this if the top bits are known zero.
2172 unsigned BitWidth = N0.getValueSizeInBits();
2173 if (DAG.MaskedValueIsZero(N0,
2174 APInt::getHighBitsSet(BitWidth,
2176 // Okay, get the un-inverted input value.
2178 if (N0.getOpcode() == ISD::XOR)
2179 Val = N0.getOperand(0);
2181 assert(N0.getOpcode() == ISD::AND &&
2182 N0.getOperand(0).getOpcode() == ISD::XOR);
2183 // ((X^1)&1)^1 -> X & 1
2184 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2185 N0.getOperand(0).getOperand(0),
2189 return DAG.getSetCC(dl, VT, Val, N1,
2190 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2192 } else if (N1C->getAPIntValue() == 1 &&
2194 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2196 if (Op0.getOpcode() == ISD::TRUNCATE)
2197 Op0 = Op0.getOperand(0);
2199 if ((Op0.getOpcode() == ISD::XOR) &&
2200 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2201 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2202 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2203 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2204 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2206 } else if (Op0.getOpcode() == ISD::AND &&
2207 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2208 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2209 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2210 if (Op0.getValueType().bitsGT(VT))
2211 Op0 = DAG.getNode(ISD::AND, dl, VT,
2212 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2213 DAG.getConstant(1, VT));
2214 else if (Op0.getValueType().bitsLT(VT))
2215 Op0 = DAG.getNode(ISD::AND, dl, VT,
2216 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2217 DAG.getConstant(1, VT));
2219 return DAG.getSetCC(dl, VT, Op0,
2220 DAG.getConstant(0, Op0.getValueType()),
2221 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2226 APInt MinVal, MaxVal;
2227 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2228 if (ISD::isSignedIntSetCC(Cond)) {
2229 MinVal = APInt::getSignedMinValue(OperandBitSize);
2230 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2232 MinVal = APInt::getMinValue(OperandBitSize);
2233 MaxVal = APInt::getMaxValue(OperandBitSize);
2236 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2237 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2238 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2239 // X >= C0 --> X > (C0-1)
2240 return DAG.getSetCC(dl, VT, N0,
2241 DAG.getConstant(C1-1, N1.getValueType()),
2242 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2245 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2246 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2247 // X <= C0 --> X < (C0+1)
2248 return DAG.getSetCC(dl, VT, N0,
2249 DAG.getConstant(C1+1, N1.getValueType()),
2250 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2253 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2254 return DAG.getConstant(0, VT); // X < MIN --> false
2255 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2256 return DAG.getConstant(1, VT); // X >= MIN --> true
2257 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2258 return DAG.getConstant(0, VT); // X > MAX --> false
2259 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2260 return DAG.getConstant(1, VT); // X <= MAX --> true
2262 // Canonicalize setgt X, Min --> setne X, Min
2263 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2264 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2265 // Canonicalize setlt X, Max --> setne X, Max
2266 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2267 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2269 // If we have setult X, 1, turn it into seteq X, 0
2270 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2271 return DAG.getSetCC(dl, VT, N0,
2272 DAG.getConstant(MinVal, N0.getValueType()),
2274 // If we have setugt X, Max-1, turn it into seteq X, Max
2275 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2276 return DAG.getSetCC(dl, VT, N0,
2277 DAG.getConstant(MaxVal, N0.getValueType()),
2280 // If we have "setcc X, C0", check to see if we can shrink the immediate
2283 // SETUGT X, SINTMAX -> SETLT X, 0
2284 if (Cond == ISD::SETUGT &&
2285 C1 == APInt::getSignedMaxValue(OperandBitSize))
2286 return DAG.getSetCC(dl, VT, N0,
2287 DAG.getConstant(0, N1.getValueType()),
2290 // SETULT X, SINTMIN -> SETGT X, -1
2291 if (Cond == ISD::SETULT &&
2292 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2293 SDValue ConstMinusOne =
2294 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2296 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2299 // Fold bit comparisons when we can.
2300 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2301 (VT == N0.getValueType() ||
2302 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2303 N0.getOpcode() == ISD::AND)
2304 if (ConstantSDNode *AndRHS =
2305 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2306 EVT ShiftTy = DCI.isBeforeLegalize() ?
2307 getPointerTy() : getShiftAmountTy(N0.getValueType());
2308 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2309 // Perform the xform if the AND RHS is a single bit.
2310 if (AndRHS->getAPIntValue().isPowerOf2()) {
2311 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2312 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2313 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2315 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2316 // (X & 8) == 8 --> (X & 8) >> 3
2317 // Perform the xform if C1 is a single bit.
2318 if (C1.isPowerOf2()) {
2319 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2320 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2321 DAG.getConstant(C1.logBase2(), ShiftTy)));
2326 if (C1.getMinSignedBits() <= 64 &&
2327 !isLegalICmpImmediate(C1.getSExtValue())) {
2328 // (X & -256) == 256 -> (X >> 8) == 1
2329 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2330 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2331 if (ConstantSDNode *AndRHS =
2332 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2333 const APInt &AndRHSC = AndRHS->getAPIntValue();
2334 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2335 unsigned ShiftBits = AndRHSC.countTrailingZeros();
2336 EVT ShiftTy = DCI.isBeforeLegalize() ?
2337 getPointerTy() : getShiftAmountTy(N0.getValueType());
2338 EVT CmpTy = N0.getValueType();
2339 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2340 DAG.getConstant(ShiftBits, ShiftTy));
2341 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2342 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2349 if (isa<ConstantFPSDNode>(N0.getNode())) {
2350 // Constant fold or commute setcc.
2351 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2352 if (O.getNode()) return O;
2353 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2354 // If the RHS of an FP comparison is a constant, simplify it away in
2356 if (CFP->getValueAPF().isNaN()) {
2357 // If an operand is known to be a nan, we can fold it.
2358 switch (ISD::getUnorderedFlavor(Cond)) {
2359 default: llvm_unreachable("Unknown flavor!");
2360 case 0: // Known false.
2361 return DAG.getConstant(0, VT);
2362 case 1: // Known true.
2363 return DAG.getConstant(1, VT);
2364 case 2: // Undefined.
2365 return DAG.getUNDEF(VT);
2369 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2370 // constant if knowing that the operand is non-nan is enough. We prefer to
2371 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2373 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2374 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2376 // If the condition is not legal, see if we can find an equivalent one
2378 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2379 // If the comparison was an awkward floating-point == or != and one of
2380 // the comparison operands is infinity or negative infinity, convert the
2381 // condition to a less-awkward <= or >=.
2382 if (CFP->getValueAPF().isInfinity()) {
2383 if (CFP->getValueAPF().isNegative()) {
2384 if (Cond == ISD::SETOEQ &&
2385 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2386 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2387 if (Cond == ISD::SETUEQ &&
2388 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2389 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2390 if (Cond == ISD::SETUNE &&
2391 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2392 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2393 if (Cond == ISD::SETONE &&
2394 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2395 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2397 if (Cond == ISD::SETOEQ &&
2398 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2399 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2400 if (Cond == ISD::SETUEQ &&
2401 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2402 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2403 if (Cond == ISD::SETUNE &&
2404 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2405 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2406 if (Cond == ISD::SETONE &&
2407 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2408 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2415 // The sext(setcc()) => setcc() optimization relies on the appropriate
2416 // constant being emitted.
2418 switch (getBooleanContents(N0.getValueType().isVector())) {
2419 case UndefinedBooleanContent:
2420 case ZeroOrOneBooleanContent:
2421 EqVal = ISD::isTrueWhenEqual(Cond);
2423 case ZeroOrNegativeOneBooleanContent:
2424 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2428 // We can always fold X == X for integer setcc's.
2429 if (N0.getValueType().isInteger()) {
2430 return DAG.getConstant(EqVal, VT);
2432 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2433 if (UOF == 2) // FP operators that are undefined on NaNs.
2434 return DAG.getConstant(EqVal, VT);
2435 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2436 return DAG.getConstant(EqVal, VT);
2437 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2438 // if it is not already.
2439 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2440 if (NewCond != Cond)
2441 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2444 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2445 N0.getValueType().isInteger()) {
2446 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2447 N0.getOpcode() == ISD::XOR) {
2448 // Simplify (X+Y) == (X+Z) --> Y == Z
2449 if (N0.getOpcode() == N1.getOpcode()) {
2450 if (N0.getOperand(0) == N1.getOperand(0))
2451 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2452 if (N0.getOperand(1) == N1.getOperand(1))
2453 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2454 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2455 // If X op Y == Y op X, try other combinations.
2456 if (N0.getOperand(0) == N1.getOperand(1))
2457 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2459 if (N0.getOperand(1) == N1.getOperand(0))
2460 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2465 // If RHS is a legal immediate value for a compare instruction, we need
2466 // to be careful about increasing register pressure needlessly.
2467 bool LegalRHSImm = false;
2469 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2470 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2471 // Turn (X+C1) == C2 --> X == C2-C1
2472 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2473 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2474 DAG.getConstant(RHSC->getAPIntValue()-
2475 LHSR->getAPIntValue(),
2476 N0.getValueType()), Cond);
2479 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2480 if (N0.getOpcode() == ISD::XOR)
2481 // If we know that all of the inverted bits are zero, don't bother
2482 // performing the inversion.
2483 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2485 DAG.getSetCC(dl, VT, N0.getOperand(0),
2486 DAG.getConstant(LHSR->getAPIntValue() ^
2487 RHSC->getAPIntValue(),
2492 // Turn (C1-X) == C2 --> X == C1-C2
2493 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2494 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2496 DAG.getSetCC(dl, VT, N0.getOperand(1),
2497 DAG.getConstant(SUBC->getAPIntValue() -
2498 RHSC->getAPIntValue(),
2504 // Could RHSC fold directly into a compare?
2505 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2506 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2509 // Simplify (X+Z) == X --> Z == 0
2510 // Don't do this if X is an immediate that can fold into a cmp
2511 // instruction and X+Z has other uses. It could be an induction variable
2512 // chain, and the transform would increase register pressure.
2513 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2514 if (N0.getOperand(0) == N1)
2515 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2516 DAG.getConstant(0, N0.getValueType()), Cond);
2517 if (N0.getOperand(1) == N1) {
2518 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2519 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2520 DAG.getConstant(0, N0.getValueType()), Cond);
2521 else if (N0.getNode()->hasOneUse()) {
2522 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2523 // (Z-X) == X --> Z == X<<1
2524 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2525 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2526 if (!DCI.isCalledByLegalizer())
2527 DCI.AddToWorklist(SH.getNode());
2528 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2534 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2535 N1.getOpcode() == ISD::XOR) {
2536 // Simplify X == (X+Z) --> Z == 0
2537 if (N1.getOperand(0) == N0) {
2538 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2539 DAG.getConstant(0, N1.getValueType()), Cond);
2540 } else if (N1.getOperand(1) == N0) {
2541 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2542 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2543 DAG.getConstant(0, N1.getValueType()), Cond);
2544 } else if (N1.getNode()->hasOneUse()) {
2545 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2546 // X == (Z-X) --> X<<1 == Z
2547 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2548 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2549 if (!DCI.isCalledByLegalizer())
2550 DCI.AddToWorklist(SH.getNode());
2551 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2556 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2557 // Note that where y is variable and is known to have at most
2558 // one bit set (for example, if it is z&1) we cannot do this;
2559 // the expressions are not equivalent when y==0.
2560 if (N0.getOpcode() == ISD::AND)
2561 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2562 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2563 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2564 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2565 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2568 if (N1.getOpcode() == ISD::AND)
2569 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2570 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2571 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2572 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2573 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2578 // Fold away ALL boolean setcc's.
2580 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2582 default: llvm_unreachable("Unknown integer setcc!");
2583 case ISD::SETEQ: // X == Y -> ~(X^Y)
2584 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2585 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2586 if (!DCI.isCalledByLegalizer())
2587 DCI.AddToWorklist(Temp.getNode());
2589 case ISD::SETNE: // X != Y --> (X^Y)
2590 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2592 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2593 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2594 Temp = DAG.getNOT(dl, N0, MVT::i1);
2595 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2596 if (!DCI.isCalledByLegalizer())
2597 DCI.AddToWorklist(Temp.getNode());
2599 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2600 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2601 Temp = DAG.getNOT(dl, N1, MVT::i1);
2602 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2603 if (!DCI.isCalledByLegalizer())
2604 DCI.AddToWorklist(Temp.getNode());
2606 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2607 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2608 Temp = DAG.getNOT(dl, N0, MVT::i1);
2609 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2610 if (!DCI.isCalledByLegalizer())
2611 DCI.AddToWorklist(Temp.getNode());
2613 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2614 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2615 Temp = DAG.getNOT(dl, N1, MVT::i1);
2616 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2619 if (VT != MVT::i1) {
2620 if (!DCI.isCalledByLegalizer())
2621 DCI.AddToWorklist(N0.getNode());
2622 // FIXME: If running after legalize, we probably can't do this.
2623 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2628 // Could not fold it.
2632 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2633 /// node is a GlobalAddress + offset.
2634 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2635 int64_t &Offset) const {
2636 if (isa<GlobalAddressSDNode>(N)) {
2637 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2638 GA = GASD->getGlobal();
2639 Offset += GASD->getOffset();
2643 if (N->getOpcode() == ISD::ADD) {
2644 SDValue N1 = N->getOperand(0);
2645 SDValue N2 = N->getOperand(1);
2646 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2647 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2649 Offset += V->getSExtValue();
2652 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2653 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2655 Offset += V->getSExtValue();
2665 SDValue TargetLowering::
2666 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2667 // Default implementation: no optimization.
2671 //===----------------------------------------------------------------------===//
2672 // Inline Assembler Implementation Methods
2673 //===----------------------------------------------------------------------===//
2676 TargetLowering::ConstraintType
2677 TargetLowering::getConstraintType(const std::string &Constraint) const {
2678 if (Constraint.size() == 1) {
2679 switch (Constraint[0]) {
2681 case 'r': return C_RegisterClass;
2683 case 'o': // offsetable
2684 case 'V': // not offsetable
2686 case 'i': // Simple Integer or Relocatable Constant
2687 case 'n': // Simple Integer
2688 case 'E': // Floating Point Constant
2689 case 'F': // Floating Point Constant
2690 case 's': // Relocatable Constant
2691 case 'p': // Address.
2692 case 'X': // Allow ANY value.
2693 case 'I': // Target registers.
2707 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2708 Constraint[Constraint.size()-1] == '}')
2713 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2714 /// with another that has more specific requirements based on the type of the
2715 /// corresponding operand.
2716 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2717 if (ConstraintVT.isInteger())
2719 if (ConstraintVT.isFloatingPoint())
2720 return "f"; // works for many targets
2724 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2725 /// vector. If it is invalid, don't add anything to Ops.
2726 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2727 std::string &Constraint,
2728 std::vector<SDValue> &Ops,
2729 SelectionDAG &DAG) const {
2731 if (Constraint.length() > 1) return;
2733 char ConstraintLetter = Constraint[0];
2734 switch (ConstraintLetter) {
2736 case 'X': // Allows any operand; labels (basic block) use this.
2737 if (Op.getOpcode() == ISD::BasicBlock) {
2742 case 'i': // Simple Integer or Relocatable Constant
2743 case 'n': // Simple Integer
2744 case 's': { // Relocatable Constant
2745 // These operands are interested in values of the form (GV+C), where C may
2746 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2747 // is possible and fine if either GV or C are missing.
2748 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2749 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2751 // If we have "(add GV, C)", pull out GV/C
2752 if (Op.getOpcode() == ISD::ADD) {
2753 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2754 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2755 if (C == 0 || GA == 0) {
2756 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2757 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2759 if (C == 0 || GA == 0)
2763 // If we find a valid operand, map to the TargetXXX version so that the
2764 // value itself doesn't get selected.
2765 if (GA) { // Either &GV or &GV+C
2766 if (ConstraintLetter != 'n') {
2767 int64_t Offs = GA->getOffset();
2768 if (C) Offs += C->getZExtValue();
2769 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2770 C ? C->getDebugLoc() : DebugLoc(),
2771 Op.getValueType(), Offs));
2775 if (C) { // just C, no GV.
2776 // Simple constants are not allowed for 's'.
2777 if (ConstraintLetter != 's') {
2778 // gcc prints these as sign extended. Sign extend value to 64 bits
2779 // now; without this it would get ZExt'd later in
2780 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2781 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2791 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2792 getRegForInlineAsmConstraint(const std::string &Constraint,
2794 if (Constraint[0] != '{')
2795 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2796 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2798 // Remove the braces from around the name.
2799 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2801 // Figure out which register class contains this reg.
2802 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2803 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2804 E = RI->regclass_end(); RCI != E; ++RCI) {
2805 const TargetRegisterClass *RC = *RCI;
2807 // If none of the value types for this register class are valid, we
2808 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2812 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2814 if (RegName.equals_lower(RI->getName(*I)))
2815 return std::make_pair(*I, RC);
2819 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2822 //===----------------------------------------------------------------------===//
2823 // Constraint Selection.
2825 /// isMatchingInputConstraint - Return true of this is an input operand that is
2826 /// a matching constraint like "4".
2827 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2828 assert(!ConstraintCode.empty() && "No known constraint!");
2829 return isdigit(ConstraintCode[0]);
2832 /// getMatchedOperand - If this is an input matching constraint, this method
2833 /// returns the output operand it matches.
2834 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2835 assert(!ConstraintCode.empty() && "No known constraint!");
2836 return atoi(ConstraintCode.c_str());
2840 /// ParseConstraints - Split up the constraint string from the inline
2841 /// assembly value into the specific constraints and their prefixes,
2842 /// and also tie in the associated operand values.
2843 /// If this returns an empty vector, and if the constraint string itself
2844 /// isn't empty, there was an error parsing.
2845 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2846 ImmutableCallSite CS) const {
2847 /// ConstraintOperands - Information about all of the constraints.
2848 AsmOperandInfoVector ConstraintOperands;
2849 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2850 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2852 // Do a prepass over the constraints, canonicalizing them, and building up the
2853 // ConstraintOperands list.
2854 InlineAsm::ConstraintInfoVector
2855 ConstraintInfos = IA->ParseConstraints();
2857 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2858 unsigned ResNo = 0; // ResNo - The result number of the next output.
2860 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2861 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2862 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2864 // Update multiple alternative constraint count.
2865 if (OpInfo.multipleAlternatives.size() > maCount)
2866 maCount = OpInfo.multipleAlternatives.size();
2868 OpInfo.ConstraintVT = MVT::Other;
2870 // Compute the value type for each operand.
2871 switch (OpInfo.Type) {
2872 case InlineAsm::isOutput:
2873 // Indirect outputs just consume an argument.
2874 if (OpInfo.isIndirect) {
2875 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2879 // The return value of the call is this value. As such, there is no
2880 // corresponding argument.
2881 assert(!CS.getType()->isVoidTy() &&
2883 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2884 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2886 assert(ResNo == 0 && "Asm only has one result!");
2887 OpInfo.ConstraintVT = getValueType(CS.getType());
2891 case InlineAsm::isInput:
2892 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2894 case InlineAsm::isClobber:
2899 if (OpInfo.CallOperandVal) {
2900 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2901 if (OpInfo.isIndirect) {
2902 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2904 report_fatal_error("Indirect operand for inline asm not a pointer!");
2905 OpTy = PtrTy->getElementType();
2908 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2909 if (StructType *STy = dyn_cast<StructType>(OpTy))
2910 if (STy->getNumElements() == 1)
2911 OpTy = STy->getElementType(0);
2913 // If OpTy is not a single value, it may be a struct/union that we
2914 // can tile with integers.
2915 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2916 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2925 OpInfo.ConstraintVT =
2926 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2929 } else if (dyn_cast<PointerType>(OpTy)) {
2930 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2932 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2937 // If we have multiple alternative constraints, select the best alternative.
2938 if (ConstraintInfos.size()) {
2940 unsigned bestMAIndex = 0;
2941 int bestWeight = -1;
2942 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2945 // Compute the sums of the weights for each alternative, keeping track
2946 // of the best (highest weight) one so far.
2947 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2949 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2950 cIndex != eIndex; ++cIndex) {
2951 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2952 if (OpInfo.Type == InlineAsm::isClobber)
2955 // If this is an output operand with a matching input operand,
2956 // look up the matching input. If their types mismatch, e.g. one
2957 // is an integer, the other is floating point, or their sizes are
2958 // different, flag it as an maCantMatch.
2959 if (OpInfo.hasMatchingInput()) {
2960 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2961 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2962 if ((OpInfo.ConstraintVT.isInteger() !=
2963 Input.ConstraintVT.isInteger()) ||
2964 (OpInfo.ConstraintVT.getSizeInBits() !=
2965 Input.ConstraintVT.getSizeInBits())) {
2966 weightSum = -1; // Can't match.
2971 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2976 weightSum += weight;
2979 if (weightSum > bestWeight) {
2980 bestWeight = weightSum;
2981 bestMAIndex = maIndex;
2985 // Now select chosen alternative in each constraint.
2986 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2987 cIndex != eIndex; ++cIndex) {
2988 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2989 if (cInfo.Type == InlineAsm::isClobber)
2991 cInfo.selectAlternative(bestMAIndex);
2996 // Check and hook up tied operands, choose constraint code to use.
2997 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2998 cIndex != eIndex; ++cIndex) {
2999 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3001 // If this is an output operand with a matching input operand, look up the
3002 // matching input. If their types mismatch, e.g. one is an integer, the
3003 // other is floating point, or their sizes are different, flag it as an
3005 if (OpInfo.hasMatchingInput()) {
3006 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3008 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3009 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3010 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
3011 std::pair<unsigned, const TargetRegisterClass*> InputRC =
3012 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
3013 if ((OpInfo.ConstraintVT.isInteger() !=
3014 Input.ConstraintVT.isInteger()) ||
3015 (MatchRC.second != InputRC.second)) {
3016 report_fatal_error("Unsupported asm: input constraint"
3017 " with a matching output constraint of"
3018 " incompatible type!");
3025 return ConstraintOperands;
3029 /// getConstraintGenerality - Return an integer indicating how general CT
3031 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3033 case TargetLowering::C_Other:
3034 case TargetLowering::C_Unknown:
3036 case TargetLowering::C_Register:
3038 case TargetLowering::C_RegisterClass:
3040 case TargetLowering::C_Memory:
3043 llvm_unreachable("Invalid constraint type");
3046 /// Examine constraint type and operand type and determine a weight value.
3047 /// This object must already have been set up with the operand type
3048 /// and the current alternative constraint selected.
3049 TargetLowering::ConstraintWeight
3050 TargetLowering::getMultipleConstraintMatchWeight(
3051 AsmOperandInfo &info, int maIndex) const {
3052 InlineAsm::ConstraintCodeVector *rCodes;
3053 if (maIndex >= (int)info.multipleAlternatives.size())
3054 rCodes = &info.Codes;
3056 rCodes = &info.multipleAlternatives[maIndex].Codes;
3057 ConstraintWeight BestWeight = CW_Invalid;
3059 // Loop over the options, keeping track of the most general one.
3060 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3061 ConstraintWeight weight =
3062 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3063 if (weight > BestWeight)
3064 BestWeight = weight;
3070 /// Examine constraint type and operand type and determine a weight value.
3071 /// This object must already have been set up with the operand type
3072 /// and the current alternative constraint selected.
3073 TargetLowering::ConstraintWeight
3074 TargetLowering::getSingleConstraintMatchWeight(
3075 AsmOperandInfo &info, const char *constraint) const {
3076 ConstraintWeight weight = CW_Invalid;
3077 Value *CallOperandVal = info.CallOperandVal;
3078 // If we don't have a value, we can't do a match,
3079 // but allow it at the lowest weight.
3080 if (CallOperandVal == NULL)
3082 // Look at the constraint type.
3083 switch (*constraint) {
3084 case 'i': // immediate integer.
3085 case 'n': // immediate integer with a known value.
3086 if (isa<ConstantInt>(CallOperandVal))
3087 weight = CW_Constant;
3089 case 's': // non-explicit intregal immediate.
3090 if (isa<GlobalValue>(CallOperandVal))
3091 weight = CW_Constant;
3093 case 'E': // immediate float if host format.
3094 case 'F': // immediate float.
3095 if (isa<ConstantFP>(CallOperandVal))
3096 weight = CW_Constant;
3098 case '<': // memory operand with autodecrement.
3099 case '>': // memory operand with autoincrement.
3100 case 'm': // memory operand.
3101 case 'o': // offsettable memory operand
3102 case 'V': // non-offsettable memory operand
3105 case 'r': // general register.
3106 case 'g': // general register, memory operand or immediate integer.
3107 // note: Clang converts "g" to "imr".
3108 if (CallOperandVal->getType()->isIntegerTy())
3109 weight = CW_Register;
3111 case 'X': // any operand.
3113 weight = CW_Default;
3119 /// ChooseConstraint - If there are multiple different constraints that we
3120 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3121 /// This is somewhat tricky: constraints fall into four classes:
3122 /// Other -> immediates and magic values
3123 /// Register -> one specific register
3124 /// RegisterClass -> a group of regs
3125 /// Memory -> memory
3126 /// Ideally, we would pick the most specific constraint possible: if we have
3127 /// something that fits into a register, we would pick it. The problem here
3128 /// is that if we have something that could either be in a register or in
3129 /// memory that use of the register could cause selection of *other*
3130 /// operands to fail: they might only succeed if we pick memory. Because of
3131 /// this the heuristic we use is:
3133 /// 1) If there is an 'other' constraint, and if the operand is valid for
3134 /// that constraint, use it. This makes us take advantage of 'i'
3135 /// constraints when available.
3136 /// 2) Otherwise, pick the most general constraint present. This prefers
3137 /// 'm' over 'r', for example.
3139 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3140 const TargetLowering &TLI,
3141 SDValue Op, SelectionDAG *DAG) {
3142 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3143 unsigned BestIdx = 0;
3144 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3145 int BestGenerality = -1;
3147 // Loop over the options, keeping track of the most general one.
3148 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3149 TargetLowering::ConstraintType CType =
3150 TLI.getConstraintType(OpInfo.Codes[i]);
3152 // If this is an 'other' constraint, see if the operand is valid for it.
3153 // For example, on X86 we might have an 'rI' constraint. If the operand
3154 // is an integer in the range [0..31] we want to use I (saving a load
3155 // of a register), otherwise we must use 'r'.
3156 if (CType == TargetLowering::C_Other && Op.getNode()) {
3157 assert(OpInfo.Codes[i].size() == 1 &&
3158 "Unhandled multi-letter 'other' constraint");
3159 std::vector<SDValue> ResultOps;
3160 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3162 if (!ResultOps.empty()) {
3169 // Things with matching constraints can only be registers, per gcc
3170 // documentation. This mainly affects "g" constraints.
3171 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3174 // This constraint letter is more general than the previous one, use it.
3175 int Generality = getConstraintGenerality(CType);
3176 if (Generality > BestGenerality) {
3179 BestGenerality = Generality;
3183 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3184 OpInfo.ConstraintType = BestType;
3187 /// ComputeConstraintToUse - Determines the constraint code and constraint
3188 /// type to use for the specific AsmOperandInfo, setting
3189 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3190 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3192 SelectionDAG *DAG) const {
3193 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3195 // Single-letter constraints ('r') are very common.
3196 if (OpInfo.Codes.size() == 1) {
3197 OpInfo.ConstraintCode = OpInfo.Codes[0];
3198 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3200 ChooseConstraint(OpInfo, *this, Op, DAG);
3203 // 'X' matches anything.
3204 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3205 // Labels and constants are handled elsewhere ('X' is the only thing
3206 // that matches labels). For Functions, the type here is the type of
3207 // the result, which is not what we want to look at; leave them alone.
3208 Value *v = OpInfo.CallOperandVal;
3209 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3210 OpInfo.CallOperandVal = v;
3214 // Otherwise, try to resolve it to something we know about by looking at
3215 // the actual operand type.
3216 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3217 OpInfo.ConstraintCode = Repl;
3218 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3223 //===----------------------------------------------------------------------===//
3224 // Loop Strength Reduction hooks
3225 //===----------------------------------------------------------------------===//
3227 /// isLegalAddressingMode - Return true if the addressing mode represented
3228 /// by AM is legal for this target, for a load/store of the specified type.
3229 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3231 // The default implementation of this implements a conservative RISCy, r+r and
3234 // Allows a sign-extended 16-bit immediate field.
3235 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3238 // No global is ever allowed as a base.
3242 // Only support r+r,
3244 case 0: // "r+i" or just "i", depending on HasBaseReg.
3247 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3249 // Otherwise we have r+r or r+i.
3252 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3254 // Allow 2*r as r+r.
3261 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3262 /// with the multiplicative inverse of the constant.
3263 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3264 SelectionDAG &DAG) const {
3265 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3266 APInt d = C->getAPIntValue();
3267 assert(d != 0 && "Division by zero!");
3269 // Shift the value upfront if it is even, so the LSB is one.
3270 unsigned ShAmt = d.countTrailingZeros();
3272 // TODO: For UDIV use SRL instead of SRA.
3273 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3274 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3278 // Calculate the multiplicative inverse, using Newton's method.
3280 while ((t = d*xn) != 1)
3281 xn *= APInt(d.getBitWidth(), 2) - t;
3283 Op2 = DAG.getConstant(xn, Op1.getValueType());
3284 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3287 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3288 /// return a DAG expression to select that will generate the same value by
3289 /// multiplying by a magic number. See:
3290 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3291 SDValue TargetLowering::
3292 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3293 std::vector<SDNode*>* Created) const {
3294 EVT VT = N->getValueType(0);
3295 DebugLoc dl= N->getDebugLoc();
3297 // Check to see if we can do this.
3298 // FIXME: We should be more aggressive here.
3299 if (!isTypeLegal(VT))
3302 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3303 APInt::ms magics = d.magic();
3305 // Multiply the numerator (operand 0) by the magic value
3306 // FIXME: We should support doing a MUL in a wider type
3308 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3309 isOperationLegalOrCustom(ISD::MULHS, VT))
3310 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3311 DAG.getConstant(magics.m, VT));
3312 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3313 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3314 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3316 DAG.getConstant(magics.m, VT)).getNode(), 1);
3318 return SDValue(); // No mulhs or equvialent
3319 // If d > 0 and m < 0, add the numerator
3320 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3321 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3323 Created->push_back(Q.getNode());
3325 // If d < 0 and m > 0, subtract the numerator.
3326 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3327 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3329 Created->push_back(Q.getNode());
3331 // Shift right algebraic if shift value is nonzero
3333 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3334 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3336 Created->push_back(Q.getNode());
3338 // Extract the sign bit and add it to the quotient
3340 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3341 getShiftAmountTy(Q.getValueType())));
3343 Created->push_back(T.getNode());
3344 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3347 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3348 /// return a DAG expression to select that will generate the same value by
3349 /// multiplying by a magic number. See:
3350 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3351 SDValue TargetLowering::
3352 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3353 std::vector<SDNode*>* Created) const {
3354 EVT VT = N->getValueType(0);
3355 DebugLoc dl = N->getDebugLoc();
3357 // Check to see if we can do this.
3358 // FIXME: We should be more aggressive here.
3359 if (!isTypeLegal(VT))
3362 // FIXME: We should use a narrower constant when the upper
3363 // bits are known to be zero.
3364 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3365 APInt::mu magics = N1C.magicu();
3367 SDValue Q = N->getOperand(0);
3369 // If the divisor is even, we can avoid using the expensive fixup by shifting
3370 // the divided value upfront.
3371 if (magics.a != 0 && !N1C[0]) {
3372 unsigned Shift = N1C.countTrailingZeros();
3373 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3374 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3376 Created->push_back(Q.getNode());
3378 // Get magic number for the shifted divisor.
3379 magics = N1C.lshr(Shift).magicu(Shift);
3380 assert(magics.a == 0 && "Should use cheap fixup now");
3383 // Multiply the numerator (operand 0) by the magic value
3384 // FIXME: We should support doing a MUL in a wider type
3385 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3386 isOperationLegalOrCustom(ISD::MULHU, VT))
3387 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3388 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3389 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3390 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3391 DAG.getConstant(magics.m, VT)).getNode(), 1);
3393 return SDValue(); // No mulhu or equvialent
3395 Created->push_back(Q.getNode());
3397 if (magics.a == 0) {
3398 assert(magics.s < N1C.getBitWidth() &&
3399 "We shouldn't generate an undefined shift!");
3400 return DAG.getNode(ISD::SRL, dl, VT, Q,
3401 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3403 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3405 Created->push_back(NPQ.getNode());
3406 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3407 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3409 Created->push_back(NPQ.getNode());
3410 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3412 Created->push_back(NPQ.getNode());
3413 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3414 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));