1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/CodeGen/SelectionDAG.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/MathExtras.h"
22 TargetLowering::TargetLowering(TargetMachine &tm)
23 : TM(tm), TD(TM.getTargetData()) {
24 assert(ISD::BUILTIN_OP_END <= 156 &&
25 "Fixed size array in TargetLowering is not large enough!");
26 // All operations default to being supported.
27 memset(OpActions, 0, sizeof(OpActions));
29 IsLittleEndian = TD.isLittleEndian();
30 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
31 ShiftAmtHandling = Undefined;
32 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
33 memset(TargetDAGCombineArray, 0,
34 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0]));
35 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
36 allowUnalignedMemoryAccesses = false;
37 UseUnderscoreSetJmpLongJmp = false;
38 IntDivIsCheap = false;
39 Pow2DivIsCheap = false;
40 StackPointerRegisterToSaveRestore = 0;
41 SchedPreferenceInfo = SchedulingForLatency;
44 TargetLowering::~TargetLowering() {}
46 /// setValueTypeAction - Set the action for a particular value type. This
47 /// assumes an action has not already been set for this value type.
48 static void SetValueTypeAction(MVT::ValueType VT,
49 TargetLowering::LegalizeAction Action,
51 MVT::ValueType *TransformToType,
52 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
53 ValueTypeActions.setTypeAction(VT, Action);
54 if (Action == TargetLowering::Promote) {
55 MVT::ValueType PromoteTo;
59 unsigned LargerReg = VT+1;
60 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
62 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
63 "Nothing to promote to??");
65 PromoteTo = (MVT::ValueType)LargerReg;
68 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
69 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
70 "Can only promote from int->int or fp->fp!");
71 assert(VT < PromoteTo && "Must promote to a larger type!");
72 TransformToType[VT] = PromoteTo;
73 } else if (Action == TargetLowering::Expand) {
74 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
75 "Cannot expand this type: target must support SOME integer reg!");
76 // Expand to the next smaller integer type!
77 TransformToType[VT] = (MVT::ValueType)(VT-1);
82 /// computeRegisterProperties - Once all of the register classes are added,
83 /// this allows us to compute derived properties we expose.
84 void TargetLowering::computeRegisterProperties() {
85 assert(MVT::LAST_VALUETYPE <= 32 &&
86 "Too many value types for ValueTypeActions to hold!");
88 // Everything defaults to one.
89 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
90 NumElementsForVT[i] = 1;
92 // Find the largest integer register class.
93 unsigned LargestIntReg = MVT::i128;
94 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
95 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
97 // Every integer value type larger than this largest register takes twice as
98 // many registers to represent as the previous ValueType.
99 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
100 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
101 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
103 // Inspect all of the ValueType's possible, deciding how to process them.
104 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
105 // If we are expanding this type, expand it!
106 if (getNumElements((MVT::ValueType)IntReg) != 1)
107 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
109 else if (!isTypeLegal((MVT::ValueType)IntReg))
110 // Otherwise, if we don't have native support, we must promote to a
112 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
113 TransformToType, ValueTypeActions);
115 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
117 // If the target does not have native support for F32, promote it to F64.
118 if (!isTypeLegal(MVT::f32))
119 SetValueTypeAction(MVT::f32, Promote, *this,
120 TransformToType, ValueTypeActions);
122 TransformToType[MVT::f32] = MVT::f32;
124 // Set MVT::Vector to always be Expanded
125 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
128 assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
129 TransformToType[MVT::f64] = MVT::f64;
132 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
136 //===----------------------------------------------------------------------===//
137 // Optimization Methods
138 //===----------------------------------------------------------------------===//
140 /// ShrinkDemandedConstant - Check to see if the specified operand of the
141 /// specified instruction is a constant integer. If so, check to see if there
142 /// are any bits set in the constant that are not demanded. If so, shrink the
143 /// constant and return true.
144 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
146 // FIXME: ISD::SELECT, ISD::SELECT_CC
147 switch(Op.getOpcode()) {
152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
153 if ((~Demanded & C->getValue()) != 0) {
154 MVT::ValueType VT = Op.getValueType();
155 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
156 DAG.getConstant(Demanded & C->getValue(),
158 return CombineTo(Op, New);
165 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
166 /// DemandedMask bits of the result of Op are ever used downstream. If we can
167 /// use this information to simplify Op, create a new simplified DAG node and
168 /// return true, returning the original and new nodes in Old and New. Otherwise,
169 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
170 /// the expression (used to simplify the caller). The KnownZero/One bits may
171 /// only be accurate for those bits in the DemandedMask.
172 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
175 TargetLoweringOpt &TLO,
176 unsigned Depth) const {
177 KnownZero = KnownOne = 0; // Don't know anything.
178 // Other users may use these bits.
179 if (!Op.Val->hasOneUse()) {
181 // If not at the root, Just compute the KnownZero/KnownOne bits to
182 // simplify things downstream.
183 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
186 // If this is the root being simplified, allow it to have multiple uses,
187 // just set the DemandedMask to all bits.
188 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
189 } else if (DemandedMask == 0) {
190 // Not demanding any bits from Op.
191 if (Op.getOpcode() != ISD::UNDEF)
192 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
194 } else if (Depth == 6) { // Limit search depth.
198 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
199 switch (Op.getOpcode()) {
201 // We know all of the bits for a constant!
202 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
203 KnownZero = ~KnownOne & DemandedMask;
204 return false; // Don't fall through, will infinitely loop.
206 // If the RHS is a constant, check to see if the LHS would be zero without
207 // using the bits from the RHS. Below, we use knowledge about the RHS to
208 // simplify the LHS, here we're using information from the LHS to simplify
210 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
211 uint64_t LHSZero, LHSOne;
212 ComputeMaskedBits(Op.getOperand(0), DemandedMask,
213 LHSZero, LHSOne, Depth+1);
214 // If the LHS already has zeros where RHSC does, this and is dead.
215 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
216 return TLO.CombineTo(Op, Op.getOperand(0));
217 // If any of the set bits in the RHS are known zero on the LHS, shrink
219 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
223 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
224 KnownOne, TLO, Depth+1))
226 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
227 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
228 KnownZero2, KnownOne2, TLO, Depth+1))
230 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
232 // If all of the demanded bits are known one on one side, return the other.
233 // These bits cannot contribute to the result of the 'and'.
234 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
235 return TLO.CombineTo(Op, Op.getOperand(0));
236 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
237 return TLO.CombineTo(Op, Op.getOperand(1));
238 // If all of the demanded bits in the inputs are known zeros, return zero.
239 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
240 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
241 // If the RHS is a constant, see if we can simplify it.
242 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
245 // Output known-1 bits are only known if set in both the LHS & RHS.
246 KnownOne &= KnownOne2;
247 // Output known-0 are known to be clear if zero in either the LHS | RHS.
248 KnownZero |= KnownZero2;
251 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
252 KnownOne, TLO, Depth+1))
254 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
255 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
256 KnownZero2, KnownOne2, TLO, Depth+1))
258 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
260 // If all of the demanded bits are known zero on one side, return the other.
261 // These bits cannot contribute to the result of the 'or'.
262 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
263 return TLO.CombineTo(Op, Op.getOperand(0));
264 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
265 return TLO.CombineTo(Op, Op.getOperand(1));
266 // If all of the potentially set bits on one side are known to be set on
267 // the other side, just use the 'other' side.
268 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
269 (DemandedMask & (~KnownZero)))
270 return TLO.CombineTo(Op, Op.getOperand(0));
271 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
272 (DemandedMask & (~KnownZero2)))
273 return TLO.CombineTo(Op, Op.getOperand(1));
274 // If the RHS is a constant, see if we can simplify it.
275 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
278 // Output known-0 bits are only known if clear in both the LHS & RHS.
279 KnownZero &= KnownZero2;
280 // Output known-1 are known to be set if set in either the LHS | RHS.
281 KnownOne |= KnownOne2;
284 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
285 KnownOne, TLO, Depth+1))
287 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
288 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
289 KnownOne2, TLO, Depth+1))
291 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
293 // If all of the demanded bits are known zero on one side, return the other.
294 // These bits cannot contribute to the result of the 'xor'.
295 if ((DemandedMask & KnownZero) == DemandedMask)
296 return TLO.CombineTo(Op, Op.getOperand(0));
297 if ((DemandedMask & KnownZero2) == DemandedMask)
298 return TLO.CombineTo(Op, Op.getOperand(1));
300 // Output known-0 bits are known if clear or set in both the LHS & RHS.
301 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
302 // Output known-1 are known to be set if set in only one of the LHS, RHS.
303 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
305 // If all of the unknown bits are known to be zero on one side or the other
306 // (but not both) turn this into an *inclusive* or.
307 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
308 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut))
309 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits)
310 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
313 // If all of the demanded bits on one side are known, and all of the set
314 // bits on that side are also known to be set on the other side, turn this
315 // into an AND, as we know the bits will be cleared.
316 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
317 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
318 if ((KnownOne & KnownOne2) == KnownOne) {
319 MVT::ValueType VT = Op.getValueType();
320 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
321 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
326 // If the RHS is a constant, see if we can simplify it.
327 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
328 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
331 KnownZero = KnownZeroOut;
332 KnownOne = KnownOneOut;
335 // If we know the result of a setcc has the top bits zero, use this info.
336 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
337 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
340 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
341 KnownOne, TLO, Depth+1))
343 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
344 KnownOne2, TLO, Depth+1))
346 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
347 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
349 // If the operands are constants, see if we can simplify them.
350 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
353 // Only known if known in both the LHS and RHS.
354 KnownOne &= KnownOne2;
355 KnownZero &= KnownZero2;
358 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
359 KnownOne, TLO, Depth+1))
361 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
362 KnownOne2, TLO, Depth+1))
364 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
365 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
367 // If the operands are constants, see if we can simplify them.
368 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
371 // Only known if known in both the LHS and RHS.
372 KnownOne &= KnownOne2;
373 KnownZero &= KnownZero2;
376 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
377 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
378 KnownZero, KnownOne, TLO, Depth+1))
380 KnownZero <<= SA->getValue();
381 KnownOne <<= SA->getValue();
382 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
386 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
387 MVT::ValueType VT = Op.getValueType();
388 unsigned ShAmt = SA->getValue();
390 // Compute the new bits that are at the top now.
391 uint64_t HighBits = (1ULL << ShAmt)-1;
392 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
393 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
395 if (SimplifyDemandedBits(Op.getOperand(0),
396 (DemandedMask << ShAmt) & TypeMask,
397 KnownZero, KnownOne, TLO, Depth+1))
399 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
400 KnownZero &= TypeMask;
401 KnownOne &= TypeMask;
404 KnownZero |= HighBits; // high bits known zero.
408 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
409 MVT::ValueType VT = Op.getValueType();
410 unsigned ShAmt = SA->getValue();
412 // Compute the new bits that are at the top now.
413 uint64_t HighBits = (1ULL << ShAmt)-1;
414 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
415 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
417 if (SimplifyDemandedBits(Op.getOperand(0),
418 (DemandedMask << ShAmt) & TypeMask,
419 KnownZero, KnownOne, TLO, Depth+1))
421 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
422 KnownZero &= TypeMask;
423 KnownOne &= TypeMask;
424 KnownZero >>= SA->getValue();
425 KnownOne >>= SA->getValue();
427 // Handle the sign bits.
428 uint64_t SignBit = MVT::getIntVTSignBit(VT);
429 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
431 // If the input sign bit is known to be zero, or if none of the top bits
432 // are demanded, turn this into an unsigned shift right.
433 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
434 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
436 } else if (KnownOne & SignBit) { // New bits are known one.
437 KnownOne |= HighBits;
441 case ISD::SIGN_EXTEND_INREG: {
442 MVT::ValueType VT = Op.getValueType();
443 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
445 // Sign extension. Compute the demanded bits in the result that are not
446 // present in the input.
447 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
449 // If none of the extended bits are demanded, eliminate the sextinreg.
451 return TLO.CombineTo(Op, Op.getOperand(0));
453 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
454 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
456 // Since the sign extended bits are demanded, we know that the sign
458 InputDemandedBits |= InSignBit;
460 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
461 KnownZero, KnownOne, TLO, Depth+1))
463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
465 // If the sign bit of the input is known set or clear, then we know the
466 // top bits of the result.
468 // If the input sign bit is known zero, convert this into a zero extension.
469 if (KnownZero & InSignBit)
470 return TLO.CombineTo(Op,
471 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
473 if (KnownOne & InSignBit) { // Input sign bit known set
475 KnownZero &= ~NewBits;
476 } else { // Input sign bit unknown
477 KnownZero &= ~NewBits;
478 KnownOne &= ~NewBits;
485 MVT::ValueType VT = Op.getValueType();
486 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
487 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
491 case ISD::ZEXTLOAD: {
492 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
493 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
496 case ISD::ZERO_EXTEND: {
497 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
499 // If none of the top bits are demanded, convert this into an any_extend.
500 uint64_t NewBits = (~InMask) & DemandedMask;
502 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
506 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
507 KnownZero, KnownOne, TLO, Depth+1))
509 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
510 KnownZero |= NewBits;
513 case ISD::SIGN_EXTEND: {
514 MVT::ValueType InVT = Op.getOperand(0).getValueType();
515 uint64_t InMask = MVT::getIntVTBitMask(InVT);
516 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
517 uint64_t NewBits = (~InMask) & DemandedMask;
519 // If none of the top bits are demanded, convert this into an any_extend.
521 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
524 // Since some of the sign extended bits are demanded, we know that the sign
526 uint64_t InDemandedBits = DemandedMask & InMask;
527 InDemandedBits |= InSignBit;
529 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
530 KnownOne, TLO, Depth+1))
533 // If the sign bit is known zero, convert this to a zero extend.
534 if (KnownZero & InSignBit)
535 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
539 // If the sign bit is known one, the top bits match.
540 if (KnownOne & InSignBit) {
542 KnownZero &= ~NewBits;
543 } else { // Otherwise, top bits aren't known.
544 KnownOne &= ~NewBits;
545 KnownZero &= ~NewBits;
549 case ISD::ANY_EXTEND: {
550 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
551 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
552 KnownZero, KnownOne, TLO, Depth+1))
554 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
557 case ISD::AssertZext: {
558 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
559 uint64_t InMask = MVT::getIntVTBitMask(VT);
560 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
561 KnownZero, KnownOne, TLO, Depth+1))
563 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
564 KnownZero |= ~InMask & DemandedMask;
568 if (ConstantSDNode *AA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
569 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero,
570 KnownOne, TLO, Depth+1))
572 // Compute the KnownOne/KnownZero masks for the constant, so we can set
573 // KnownZero appropriately if we're adding a constant that has all low
575 ComputeMaskedBits(Op.getOperand(1),
576 MVT::getIntVTBitMask(Op.getValueType()),
577 KnownZero2, KnownOne2, Depth+1);
579 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
580 CountTrailingZeros_64(~KnownZero2));
581 KnownZero = (1ULL << KnownZeroOut) - 1;
586 // Just use ComputeMaskedBits to compute output bits, there are no
587 // simplifications that can be done here, and sub always demands all input
589 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
593 // If we know the value of all of the demanded bits, return this as a
595 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
596 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
601 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
602 /// this predicate to simplify operations downstream. Mask is known to be zero
603 /// for bits that V cannot have.
604 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
605 unsigned Depth) const {
606 uint64_t KnownZero, KnownOne;
607 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
608 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
609 return (KnownZero & Mask) == Mask;
612 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
613 /// known to be either zero or one and return them in the KnownZero/KnownOne
614 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
616 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
617 uint64_t &KnownZero, uint64_t &KnownOne,
618 unsigned Depth) const {
619 KnownZero = KnownOne = 0; // Don't know anything.
620 if (Depth == 6 || Mask == 0)
621 return; // Limit search depth.
623 uint64_t KnownZero2, KnownOne2;
625 switch (Op.getOpcode()) {
627 // We know all of the bits for a constant!
628 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
629 KnownZero = ~KnownOne & Mask;
632 // If either the LHS or the RHS are Zero, the result is zero.
633 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
635 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
636 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
637 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
639 // Output known-1 bits are only known if set in both the LHS & RHS.
640 KnownOne &= KnownOne2;
641 // Output known-0 are known to be clear if zero in either the LHS | RHS.
642 KnownZero |= KnownZero2;
645 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
647 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
648 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
649 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
651 // Output known-0 bits are only known if clear in both the LHS & RHS.
652 KnownZero &= KnownZero2;
653 // Output known-1 are known to be set if set in either the LHS | RHS.
654 KnownOne |= KnownOne2;
657 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
658 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
659 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
660 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
662 // Output known-0 bits are known if clear or set in both the LHS & RHS.
663 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
664 // Output known-1 are known to be set if set in only one of the LHS, RHS.
665 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
666 KnownZero = KnownZeroOut;
670 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
671 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
672 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
673 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
675 // Only known if known in both the LHS and RHS.
676 KnownOne &= KnownOne2;
677 KnownZero &= KnownZero2;
680 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
681 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
683 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
685 // Only known if known in both the LHS and RHS.
686 KnownOne &= KnownOne2;
687 KnownZero &= KnownZero2;
690 // If we know the result of a setcc has the top bits zero, use this info.
691 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
692 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
695 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
696 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
697 Mask >>= SA->getValue();
698 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
699 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
700 KnownZero <<= SA->getValue();
701 KnownOne <<= SA->getValue();
702 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
706 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
707 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
708 uint64_t HighBits = (1ULL << SA->getValue())-1;
709 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
710 Mask <<= SA->getValue();
711 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
712 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
713 KnownZero >>= SA->getValue();
714 KnownOne >>= SA->getValue();
715 KnownZero |= HighBits; // high bits known zero.
719 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
720 uint64_t HighBits = (1ULL << SA->getValue())-1;
721 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
722 Mask <<= SA->getValue();
723 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
724 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
725 KnownZero >>= SA->getValue();
726 KnownOne >>= SA->getValue();
728 // Handle the sign bits.
729 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
730 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
732 if (KnownZero & SignBit) { // New bits are known zero.
733 KnownZero |= HighBits;
734 } else if (KnownOne & SignBit) { // New bits are known one.
735 KnownOne |= HighBits;
739 case ISD::SIGN_EXTEND_INREG: {
740 MVT::ValueType VT = Op.getValueType();
741 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
743 // Sign extension. Compute the demanded bits in the result that are not
744 // present in the input.
745 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask;
747 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
748 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT);
750 // If the sign extended bits are demanded, we know that the sign
753 InputDemandedBits |= InSignBit;
755 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits,
756 KnownZero, KnownOne, Depth+1);
757 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
759 // If the sign bit of the input is known set or clear, then we know the
760 // top bits of the result.
761 if (KnownZero & InSignBit) { // Input sign bit known clear
762 KnownZero |= NewBits;
763 KnownOne &= ~NewBits;
764 } else if (KnownOne & InSignBit) { // Input sign bit known set
766 KnownZero &= ~NewBits;
767 } else { // Input sign bit unknown
768 KnownZero &= ~NewBits;
769 KnownOne &= ~NewBits;
776 MVT::ValueType VT = Op.getValueType();
777 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
778 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
782 case ISD::ZEXTLOAD: {
783 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
784 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
787 case ISD::ZERO_EXTEND: {
788 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
789 uint64_t NewBits = (~InMask) & Mask;
790 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
792 KnownZero |= NewBits & Mask;
793 KnownOne &= ~NewBits;
796 case ISD::SIGN_EXTEND: {
797 MVT::ValueType InVT = Op.getOperand(0).getValueType();
798 unsigned InBits = MVT::getSizeInBits(InVT);
799 uint64_t InMask = MVT::getIntVTBitMask(InVT);
800 uint64_t InSignBit = 1ULL << (InBits-1);
801 uint64_t NewBits = (~InMask) & Mask;
802 uint64_t InDemandedBits = Mask & InMask;
804 // If any of the sign extended bits are demanded, we know that the sign
807 InDemandedBits |= InSignBit;
809 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero,
811 // If the sign bit is known zero or one, the top bits match.
812 if (KnownZero & InSignBit) {
813 KnownZero |= NewBits;
814 KnownOne &= ~NewBits;
815 } else if (KnownOne & InSignBit) {
817 KnownZero &= ~NewBits;
818 } else { // Otherwise, top bits aren't known.
819 KnownOne &= ~NewBits;
820 KnownZero &= ~NewBits;
824 case ISD::ANY_EXTEND: {
825 MVT::ValueType VT = Op.getOperand(0).getValueType();
826 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT),
827 KnownZero, KnownOne, Depth+1);
830 case ISD::AssertZext: {
831 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
832 uint64_t InMask = MVT::getIntVTBitMask(VT);
833 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
835 KnownZero |= (~InMask) & Mask;
839 // If either the LHS or the RHS are Zero, the result is zero.
840 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
841 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
842 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
843 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
845 // Output known-0 bits are known if clear or set in both the low clear bits
846 // common to both LHS & RHS;
847 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
848 CountTrailingZeros_64(~KnownZero2));
850 KnownZero = (1ULL << KnownZeroOut) - 1;
855 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
858 // We know that the top bits of C-X are clear if X contains less bits
859 // than C (i.e. no wrap-around can happen). For example, 20-X is
860 // positive if we can prove that X is >= 0 and < 16.
861 MVT::ValueType VT = CLHS->getValueType(0);
862 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
863 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
864 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
865 MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
866 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
868 // If all of the MaskV bits are known to be zero, then we know the output
869 // top bits are zero, because we now know that the output is from [0-C].
870 if ((KnownZero & MaskV) == MaskV) {
871 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
872 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
873 KnownOne = 0; // No one bits known.
875 KnownOne = KnownOne = 0; // Otherwise, nothing known.
881 // Allow the target to implement this method for its nodes.
882 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
883 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
888 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
889 /// in Mask are known to be either zero or one and return them in the
890 /// KnownZero/KnownOne bitsets.
891 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
895 unsigned Depth) const {
896 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
897 "Should use MaskedValueIsZero if you don't know whether Op"
898 " is a target node!");
903 SDOperand TargetLowering::
904 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
905 // Default implementation: no optimization.
909 //===----------------------------------------------------------------------===//
910 // Inline Assembler Implementation Methods
911 //===----------------------------------------------------------------------===//
913 TargetLowering::ConstraintType
914 TargetLowering::getConstraintType(char ConstraintLetter) const {
915 // FIXME: lots more standard ones to handle.
916 switch (ConstraintLetter) {
917 default: return C_Unknown;
918 case 'r': return C_RegisterClass;
920 case 'o': // offsetable
921 case 'V': // not offsetable
923 case 'i': // Simple Integer or Relocatable Constant
924 case 'n': // Simple Integer
925 case 's': // Relocatable Constant
926 case 'I': // Target registers.
938 bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
939 char ConstraintLetter) {
940 switch (ConstraintLetter) {
941 default: return false;
942 case 'i': // Simple Integer or Relocatable Constant
943 case 'n': // Simple Integer
944 case 's': // Relocatable Constant
945 return true; // FIXME: not right.
950 std::vector<unsigned> TargetLowering::
951 getRegClassForInlineAsmConstraint(const std::string &Constraint,
952 MVT::ValueType VT) const {
953 return std::vector<unsigned>();
957 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
958 getRegForInlineAsmConstraint(const std::string &Constraint,
959 MVT::ValueType VT) const {
960 if (Constraint[0] != '{')
961 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
962 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
964 // Remove the braces from around the name.
965 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
967 // Figure out which register class contains this reg.
968 const MRegisterInfo *RI = TM.getRegisterInfo();
969 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
970 E = RI->regclass_end(); RCI != E; ++RCI) {
971 const TargetRegisterClass *RC = *RCI;
973 // If none of the the value types for this register class are valid, we
974 // can't use it. For example, 64-bit reg classes on 32-bit targets.
975 bool isLegal = false;
976 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
978 if (isTypeLegal(*I)) {
984 if (!isLegal) continue;
986 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
988 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
989 return std::make_pair(*I, RC);
993 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);