1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numCommutes , "Number of instruction commuting performed");
40 STATISTIC(numExtends , "Number of copies extended");
41 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
42 STATISTIC(numAborts , "Number of times interval joining aborted");
44 char SimpleRegisterCoalescing::ID = 0;
47 EnableJoining("join-liveintervals",
48 cl::desc("Coalesce copies (default=true)"),
52 NewHeuristic("new-coalescer-heuristic",
53 cl::desc("Use new coalescer heuristic"),
57 CommuteDef("coalescer-commute-instrs",
58 cl::init(false), cl::Hidden);
60 RegisterPass<SimpleRegisterCoalescing>
61 X("simple-register-coalescing", "Simple Register Coalescing");
63 // Declare that we implement the RegisterCoalescer interface
64 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
67 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
69 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addPreserved<LiveIntervals>();
71 AU.addPreserved<MachineLoopInfo>();
72 AU.addPreservedID(MachineDominatorsID);
73 AU.addPreservedID(PHIEliminationID);
74 AU.addPreservedID(TwoAddressInstructionPassID);
75 AU.addRequired<LiveVariables>();
76 AU.addRequired<LiveIntervals>();
77 AU.addRequired<MachineLoopInfo>();
78 MachineFunctionPass::getAnalysisUsage(AU);
81 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
82 /// being the source and IntB being the dest, thus this defines a value number
83 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
84 /// see if we can merge these two pieces of B into a single value number,
85 /// eliminating a copy. For example:
89 /// B1 = A3 <- this copy
91 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
92 /// value number to be replaced with B0 (which simplifies the B liveinterval).
94 /// This returns true if an interval was modified.
96 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
98 MachineInstr *CopyMI) {
99 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
101 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
102 // the example above.
103 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
104 VNInfo *BValNo = BLR->valno;
106 // Get the location that B is defined at. Two options: either this value has
107 // an unknown definition point or it is defined at CopyIdx. If unknown, we
109 if (!BValNo->copy) return false;
110 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
112 // AValNo is the value number in A that defines the copy, A3 in the example.
113 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
114 VNInfo *AValNo = ALR->valno;
116 // If AValNo is defined as a copy from IntB, we can potentially process this.
117 // Get the instruction that defines this value number.
118 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
119 if (!SrcReg) return false; // Not defined by a copy.
121 // If the value number is not defined by a copy instruction, ignore it.
123 // If the source register comes from an interval other than IntB, we can't
125 if (SrcReg != IntB.reg) return false;
127 // Get the LiveRange in IntB that this value number starts with.
128 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
130 // Make sure that the end of the live range is inside the same block as
132 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
134 ValLREndInst->getParent() != CopyMI->getParent()) return false;
136 // Okay, we now know that ValLR ends in the same block that the CopyMI
137 // live-range starts. If there are no intervening live ranges between them in
138 // IntB, we can merge them.
139 if (ValLR+1 != BLR) return false;
141 // If a live interval is a physical register, conservatively check if any
142 // of its sub-registers is overlapping the live interval of the virtual
143 // register. If so, do not coalesce.
144 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
145 *tri_->getSubRegisters(IntB.reg)) {
146 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
147 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
148 DOUT << "Interfere with sub-register ";
149 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
154 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
156 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
157 // We are about to delete CopyMI, so need to remove it as the 'instruction
158 // that defines this value #'. Update the the valnum with the new defining
160 BValNo->def = FillerStart;
163 // Okay, we can merge them. We need to insert a new liverange:
164 // [ValLR.end, BLR.begin) of either value number, then we merge the
165 // two value numbers.
166 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
168 // If the IntB live range is assigned to a physical register, and if that
169 // physreg has aliases,
170 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
171 // Update the liveintervals of sub-registers.
172 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
173 LiveInterval &AliasLI = li_->getInterval(*AS);
174 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
175 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
179 // Okay, merge "B1" into the same value number as "B0".
180 if (BValNo != ValLR->valno)
181 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
182 DOUT << " result = "; IntB.print(DOUT, tri_);
185 // If the source instruction was killing the source register before the
186 // merge, unset the isKill marker given the live range has been extended.
187 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
189 ValLREndInst->getOperand(UIdx).setIsKill(false);
195 /// HasOtherReachingDefs - Return true if there are definitions of IntB
196 /// other than BValNo val# that can reach uses of AValno val# of IntA.
197 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
201 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
203 if (AI->valno != AValNo) continue;
204 LiveInterval::Ranges::iterator BI =
205 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
206 if (BI != IntB.ranges.begin())
208 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
209 if (BI->valno == BValNo)
211 if (BI->start <= AI->start && BI->end > AI->start)
213 if (BI->start > AI->start && BI->start < AI->end)
220 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
221 /// being the source and IntB being the dest, thus this defines a value number
222 /// in IntB. If the source value number (in IntA) is defined by a commutable
223 /// instruction and its other operand is coalesced to the copy dest register,
224 /// see if we can transform the copy into a noop by commuting the definition. For
227 /// A3 = op A2 B0<kill>
229 /// B1 = A3 <- this copy
231 /// = op A3 <- more uses
235 /// B2 = op B0 A2<kill>
237 /// B1 = B2 <- now an identify copy
239 /// = op B2 <- more uses
241 /// This returns true if an interval was modified.
243 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
245 MachineInstr *CopyMI) {
246 if (!CommuteDef) return false;
248 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
250 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
251 // the example above.
252 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
253 VNInfo *BValNo = BLR->valno;
255 // Get the location that B is defined at. Two options: either this value has
256 // an unknown definition point or it is defined at CopyIdx. If unknown, we
258 if (!BValNo->copy) return false;
259 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
261 // AValNo is the value number in A that defines the copy, A3 in the example.
262 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
263 VNInfo *AValNo = ALR->valno;
264 // If other defs can reach uses of this def, then it's not safe to perform
266 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
268 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
269 const TargetInstrDesc &TID = DefMI->getDesc();
271 if (!TID.isCommutable() ||
272 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
275 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
276 unsigned NewReg = NewDstMO.getReg();
277 if (NewReg != IntB.reg || !NewDstMO.isKill())
280 // Make sure there are no other definitions of IntB that would reach the
281 // uses which the new definition can reach.
282 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
285 // At this point we have decided that it is legal to do this
286 // transformation. Start by commuting the instruction.
287 MachineBasicBlock *MBB = DefMI->getParent();
288 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
291 if (NewMI != DefMI) {
292 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
293 MBB->insert(DefMI, NewMI);
296 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg);
297 NewMI->getOperand(OpIdx).setIsKill();
299 // Update uses of IntA of the specific Val# with IntB.
300 bool BHasPHIKill = BValNo->hasPHIKill;
301 SmallVector<VNInfo*, 4> BDeadValNos;
302 SmallVector<unsigned, 4> BKills;
303 std::map<unsigned, unsigned> BExtend;
304 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
305 UE = mri_->use_end(); UI != UE;) {
306 MachineOperand &UseMO = UI.getOperand();
307 MachineInstr *UseMI = &*UI;
309 if (JoinedCopies.count(UseMI))
311 unsigned UseIdx = li_->getInstructionIndex(UseMI);
312 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
313 if (ULR->valno != AValNo)
315 UseMO.setReg(NewReg);
319 BKills.push_back(li_->getUseIndex(UseIdx)+1);
320 unsigned SrcReg, DstReg;
321 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
323 if (DstReg == IntB.reg) {
324 // This copy will become a noop. If it's defining a new val#,
325 // remove that val# as well. However this live range is being
326 // extended to the end of the existing live range defined by the copy.
327 unsigned DefIdx = li_->getDefIndex(UseIdx);
328 LiveInterval::iterator DLR = IntB.FindLiveRangeContaining(DefIdx);
329 BHasPHIKill |= DLR->valno->hasPHIKill;
330 assert(DLR->valno->def == DefIdx);
331 BDeadValNos.push_back(DLR->valno);
332 BExtend[DLR->start] = DLR->end;
333 JoinedCopies.insert(UseMI);
334 // If this is a kill but it's going to be removed, the last use
335 // of the same val# is the new kill.
336 if (UseMO.isKill()) {
342 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
343 // simply extend BLR if CopyMI doesn't end the range.
344 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
346 IntB.removeValNo(BValNo);
347 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
348 IntB.removeValNo(BDeadValNos[i]);
349 VNInfo *ValNo = IntB.getNextValue(ALR->start, 0, li_->getVNInfoAllocator());
350 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
352 if (AI->valno != AValNo) continue;
353 unsigned End = AI->end;
354 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
355 if (EI != BExtend.end())
357 IntB.addRange(LiveRange(AI->start, End, ValNo));
359 IntB.addKills(ValNo, BKills);
360 ValNo->hasPHIKill = BHasPHIKill;
362 DOUT << " result = "; IntB.print(DOUT, tri_);
365 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
366 IntA.removeValNo(AValNo);
367 DOUT << " result = "; IntA.print(DOUT, tri_);
374 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
375 /// due to live range lengthening as the result of coalescing.
376 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
378 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
379 UE = mri_->use_end(); UI != UE; ++UI) {
380 MachineOperand &UseMO = UI.getOperand();
381 if (UseMO.isKill()) {
382 MachineInstr *UseMI = UseMO.getParent();
383 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
384 if (JoinedCopies.count(UseMI))
386 LiveInterval::const_iterator UI = LI.FindLiveRangeContaining(UseIdx);
387 assert(UI != LI.end());
388 if (!LI.isKill(UI->valno, UseIdx+1))
389 UseMO.setIsKill(false);
394 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
396 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
398 MachineBasicBlock *MBB = CopyMI->getParent();
399 const MachineLoop *L = loopInfo->getLoopFor(MBB);
402 if (MBB != L->getLoopLatch())
405 LiveInterval &LI = li_->getInterval(DstReg);
406 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
407 LiveInterval::const_iterator DstLR =
408 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
409 if (DstLR == LI.end())
411 unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM;
412 if (DstLR->valno->kills.size() == 1 &&
413 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
418 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
419 /// update the subregister number if it is not zero. If DstReg is a
420 /// physical register and the existing subregister number of the def / use
421 /// being updated is not zero, make sure to set it to the correct physical
424 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
426 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
427 if (DstIsPhys && SubIdx) {
428 // Figure out the real physical register we are updating with.
429 DstReg = tri_->getSubReg(DstReg, SubIdx);
433 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
434 E = mri_->reg_end(); I != E; ) {
435 MachineOperand &O = I.getOperand();
438 unsigned UseSubIdx = O.getSubReg();
439 unsigned UseDstReg = DstReg;
441 UseDstReg = tri_->getSubReg(DstReg, UseSubIdx);
445 unsigned OldSubIdx = O.getSubReg();
446 assert((!SubIdx || !OldSubIdx) && "Conflicting sub-register index!");
454 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
455 /// which are the src/dst of the copy instruction CopyMI. This returns true
456 /// if the copy was successfully coalesced away. If it is not currently
457 /// possible to coalesce this interval, but it may be possible if other
458 /// things get coalesced, then it returns true by reference in 'Again'.
459 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
460 MachineInstr *CopyMI = TheCopy.MI;
463 if (JoinedCopies.count(CopyMI))
464 return false; // Already done.
466 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
470 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
473 DstReg = CopyMI->getOperand(0).getReg();
474 SrcReg = CopyMI->getOperand(1).getReg();
475 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
476 assert(0 && "Unrecognized copy instruction!");
480 // If they are already joined we continue.
481 if (SrcReg == DstReg) {
482 DOUT << "\tCopy already coalesced.\n";
483 return false; // Not coalescable.
486 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
487 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
489 // If they are both physical registers, we cannot join them.
490 if (SrcIsPhys && DstIsPhys) {
491 DOUT << "\tCan not coalesce physregs.\n";
492 return false; // Not coalescable.
495 // We only join virtual registers with allocatable physical registers.
496 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
497 DOUT << "\tSrc reg is unallocatable physreg.\n";
498 return false; // Not coalescable.
500 if (DstIsPhys && !allocatableRegs_[DstReg]) {
501 DOUT << "\tDst reg is unallocatable physreg.\n";
502 return false; // Not coalescable.
505 unsigned RealDstReg = 0;
507 SubIdx = CopyMI->getOperand(2).getImm();
509 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
510 // coalesced with AX.
511 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
513 } else if (DstIsPhys) {
514 // If this is a extract_subreg where dst is a physical register, e.g.
515 // cl = EXTRACT_SUBREG reg1024, 1
516 // then create and update the actual physical register allocated to RHS.
517 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
518 for (const unsigned *SRs = tri_->getSuperRegisters(DstReg);
519 unsigned SR = *SRs; ++SRs) {
520 if (DstReg == tri_->getSubReg(SR, SubIdx) &&
526 assert(RealDstReg && "Invalid extra_subreg instruction!");
528 // For this type of EXTRACT_SUBREG, conservatively
529 // check if the live interval of the source register interfere with the
530 // actual super physical register we are trying to coalesce with.
531 LiveInterval &RHS = li_->getInterval(SrcReg);
532 if (li_->hasInterval(RealDstReg) &&
533 RHS.overlaps(li_->getInterval(RealDstReg))) {
534 DOUT << "Interfere with register ";
535 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
536 return false; // Not coalescable
538 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
539 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
540 DOUT << "Interfere with sub-register ";
541 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
542 return false; // Not coalescable
546 unsigned SrcSize= li_->getInterval(SrcReg).getSize() / InstrSlots::NUM;
547 unsigned DstSize= li_->getInterval(DstReg).getSize() / InstrSlots::NUM;
548 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
549 unsigned Threshold = allocatableRCRegs_[RC].count();
550 // Be conservative. If both sides are virtual registers, do not coalesce
551 // if this will cause a high use density interval to target a smaller set
553 if (DstSize > Threshold || SrcSize > Threshold) {
554 LiveVariables::VarInfo &svi = lv_->getVarInfo(SrcReg);
555 LiveVariables::VarInfo &dvi = lv_->getVarInfo(DstReg);
556 if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) {
557 Again = true; // May be possible to coalesce later.
562 } else if (differingRegisterClasses(SrcReg, DstReg)) {
563 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
564 // with another? If it's the resulting destination register, then
565 // the subidx must be propagated to uses (but only those defined
566 // by the EXTRACT_SUBREG). If it's being coalesced into another
567 // register, it should be safe because register is assumed to have
568 // the register class of the super-register.
570 // If they are not of the same register class, we cannot join them.
571 DOUT << "\tSrc/Dest are different register classes.\n";
572 // Allow the coalescer to try again in case either side gets coalesced to
573 // a physical register that's compatible with the other side. e.g.
574 // r1024 = MOV32to32_ r1025
575 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
576 Again = true; // May be possible to coalesce later.
580 LiveInterval &SrcInt = li_->getInterval(SrcReg);
581 LiveInterval &DstInt = li_->getInterval(DstReg);
582 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
583 "Register mapping is horribly broken!");
585 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
586 DOUT << " and "; DstInt.print(DOUT, tri_);
589 // Check if it is necessary to propagate "isDead" property before intervals
591 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
592 bool isDead = mopd->isDead();
593 bool isShorten = false;
594 unsigned SrcStart = 0, RemoveStart = 0;
595 unsigned SrcEnd = 0, RemoveEnd = 0;
597 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
598 LiveInterval::iterator SrcLR =
599 SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx));
600 RemoveStart = SrcStart = SrcLR->start;
601 RemoveEnd = SrcEnd = SrcLR->end;
602 // The instruction which defines the src is only truly dead if there are
603 // no intermediate uses and there isn't a use beyond the copy.
604 // FIXME: find the last use, mark is kill and shorten the live range.
605 if (SrcEnd > li_->getDefIndex(CopyIdx)) {
609 MachineOperand *LastUse =
610 lastRegisterUse(SrcStart, CopyIdx, SrcReg, LastUseIdx);
612 // Shorten the liveinterval to the end of last use.
613 LastUse->setIsKill();
616 RemoveStart = li_->getDefIndex(LastUseIdx);
619 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
621 MachineOperand *mops = findDefOperand(SrcMI, SrcReg);
623 // A dead def should have a single cycle interval.
630 // We need to be careful about coalescing a source physical register with a
631 // virtual register. Once the coalescing is done, it cannot be broken and
632 // these are not spillable! If the destination interval uses are far away,
633 // think twice about coalescing them!
634 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) {
635 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
636 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
637 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
638 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
639 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
640 if (TheCopy.isBackEdge)
641 Threshold *= 2; // Favors back edge copies.
643 // If the virtual register live interval is long but it has low use desity,
644 // do not join them, instead mark the physical register as its allocation
646 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
647 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
648 if (Length > Threshold &&
649 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
650 JoinVInt.preference = JoinPReg;
652 DOUT << "\tMay tie down a physical register, abort!\n";
653 Again = true; // May be possible to coalesce later.
658 // Okay, attempt to join these two intervals. On failure, this returns false.
659 // Otherwise, if one of the intervals being joined is a physreg, this method
660 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
661 // been modified, so we can use this information below to update aliases.
662 bool Swapped = false;
663 if (JoinIntervals(DstInt, SrcInt, Swapped)) {
665 // Result of the copy is dead. Propagate this property.
667 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
668 "Live-in must be a physical register!");
669 // Live-in to the function but dead. Remove it from entry live-in set.
670 // JoinIntervals may end up swapping the two intervals.
671 mf_->begin()->removeLiveIn(SrcReg);
673 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
675 MachineOperand *mops = findDefOperand(SrcMI, SrcReg);
682 if (isShorten || isDead) {
683 // Shorten the destination live interval.
685 SrcInt.removeRange(RemoveStart, RemoveEnd, true);
688 // Coalescing failed.
690 // If we can eliminate the copy without merging the live ranges, do so now.
692 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
693 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
694 JoinedCopies.insert(CopyMI);
698 // Otherwise, we are unable to join the intervals.
699 DOUT << "Interference!\n";
700 Again = true; // May be possible to coalesce later.
704 LiveInterval *ResSrcInt = &SrcInt;
705 LiveInterval *ResDstInt = &DstInt;
707 std::swap(SrcReg, DstReg);
708 std::swap(ResSrcInt, ResDstInt);
710 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
711 "LiveInterval::join didn't work right!");
713 // If we're about to merge live ranges into a physical register live range,
714 // we have to update any aliased register's live ranges to indicate that they
715 // have clobbered values for this range.
716 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
717 // Unset unnecessary kills.
718 if (!ResDstInt->containsOneValue()) {
719 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
720 E = ResSrcInt->end(); I != E; ++I)
721 unsetRegisterKills(I->start, I->end, DstReg);
724 // If this is a extract_subreg where dst is a physical register, e.g.
725 // cl = EXTRACT_SUBREG reg1024, 1
726 // then create and update the actual physical register allocated to RHS.
728 LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg);
729 SmallSet<const VNInfo*, 4> CopiedValNos;
730 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
731 E = ResSrcInt->ranges.end(); I != E; ++I) {
732 LiveInterval::const_iterator DstLR =
733 ResDstInt->FindLiveRangeContaining(I->start);
734 assert(DstLR != ResDstInt->end() && "Invalid joined interval!");
735 const VNInfo *DstValNo = DstLR->valno;
736 if (CopiedValNos.insert(DstValNo)) {
737 VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->copy,
738 li_->getVNInfoAllocator());
739 ValNo->hasPHIKill = DstValNo->hasPHIKill;
740 RealDstInt.addKills(ValNo, DstValNo->kills);
741 RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
747 // Update the liveintervals of sub-registers.
748 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
749 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
750 li_->getVNInfoAllocator());
752 // Merge use info if the destination is a virtual register.
753 LiveVariables::VarInfo& dVI = lv_->getVarInfo(DstReg);
754 LiveVariables::VarInfo& sVI = lv_->getVarInfo(SrcReg);
755 dVI.NumUses += sVI.NumUses;
758 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
759 // larger super-register.
760 if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
762 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
763 std::swap(SrcReg, DstReg);
764 std::swap(ResSrcInt, ResDstInt);
769 // Add all copies that define val# in the source interval into the queue.
770 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
771 e = ResSrcInt->vni_end(); i != e; ++i) {
772 const VNInfo *vni = *i;
773 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
775 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
776 unsigned NewSrcReg, NewDstReg;
778 JoinedCopies.count(CopyMI) == 0 &&
779 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
780 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
781 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
782 isBackEdgeCopy(CopyMI, DstReg)));
787 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
790 // Remember to delete the copy instruction.
791 JoinedCopies.insert(CopyMI);
793 // Some live range has been lengthened due to colaescing, eliminate the
794 // unnecessary kills.
795 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
796 if (TargetRegisterInfo::isVirtualRegister(DstReg))
797 RemoveUnnecessaryKills(DstReg, *ResDstInt);
799 // SrcReg is guarateed to be the register whose live interval that is
801 li_->removeInterval(SrcReg);
802 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
808 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
809 /// compute what the resultant value numbers for each value in the input two
810 /// ranges will be. This is complicated by copies between the two which can
811 /// and will commonly cause multiple value numbers to be merged into one.
813 /// VN is the value number that we're trying to resolve. InstDefiningValue
814 /// keeps track of the new InstDefiningValue assignment for the result
815 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
816 /// whether a value in this or other is a copy from the opposite set.
817 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
818 /// already been assigned.
820 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
821 /// contains the value number the copy is from.
823 static unsigned ComputeUltimateVN(VNInfo *VNI,
824 SmallVector<VNInfo*, 16> &NewVNInfo,
825 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
826 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
827 SmallVector<int, 16> &ThisValNoAssignments,
828 SmallVector<int, 16> &OtherValNoAssignments) {
829 unsigned VN = VNI->id;
831 // If the VN has already been computed, just return it.
832 if (ThisValNoAssignments[VN] >= 0)
833 return ThisValNoAssignments[VN];
834 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
836 // If this val is not a copy from the other val, then it must be a new value
837 // number in the destination.
838 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
839 if (I == ThisFromOther.end()) {
840 NewVNInfo.push_back(VNI);
841 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
843 VNInfo *OtherValNo = I->second;
845 // Otherwise, this *is* a copy from the RHS. If the other side has already
846 // been computed, return it.
847 if (OtherValNoAssignments[OtherValNo->id] >= 0)
848 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
850 // Mark this value number as currently being computed, then ask what the
851 // ultimate value # of the other value is.
852 ThisValNoAssignments[VN] = -2;
853 unsigned UltimateVN =
854 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
855 OtherValNoAssignments, ThisValNoAssignments);
856 return ThisValNoAssignments[VN] = UltimateVN;
859 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
860 return std::find(V.begin(), V.end(), Val) != V.end();
863 /// SimpleJoin - Attempt to joint the specified interval into this one. The
864 /// caller of this method must guarantee that the RHS only contains a single
865 /// value number and that the RHS is not defined by a copy from this
866 /// interval. This returns false if the intervals are not joinable, or it
867 /// joins them and returns true.
868 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
869 assert(RHS.containsOneValue());
871 // Some number (potentially more than one) value numbers in the current
872 // interval may be defined as copies from the RHS. Scan the overlapping
873 // portions of the LHS and RHS, keeping track of this and looking for
874 // overlapping live ranges that are NOT defined as copies. If these exist, we
877 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
878 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
880 if (LHSIt->start < RHSIt->start) {
881 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
882 if (LHSIt != LHS.begin()) --LHSIt;
883 } else if (RHSIt->start < LHSIt->start) {
884 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
885 if (RHSIt != RHS.begin()) --RHSIt;
888 SmallVector<VNInfo*, 8> EliminatedLHSVals;
891 // Determine if these live intervals overlap.
892 bool Overlaps = false;
893 if (LHSIt->start <= RHSIt->start)
894 Overlaps = LHSIt->end > RHSIt->start;
896 Overlaps = RHSIt->end > LHSIt->start;
898 // If the live intervals overlap, there are two interesting cases: if the
899 // LHS interval is defined by a copy from the RHS, it's ok and we record
900 // that the LHS value # is the same as the RHS. If it's not, then we cannot
901 // coalesce these live ranges and we bail out.
903 // If we haven't already recorded that this value # is safe, check it.
904 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
905 // Copy from the RHS?
906 unsigned SrcReg = li_->getVNInfoSourceReg(LHSIt->valno);
907 if (SrcReg != RHS.reg)
908 return false; // Nope, bail out.
910 EliminatedLHSVals.push_back(LHSIt->valno);
913 // We know this entire LHS live range is okay, so skip it now.
914 if (++LHSIt == LHSEnd) break;
918 if (LHSIt->end < RHSIt->end) {
919 if (++LHSIt == LHSEnd) break;
921 // One interesting case to check here. It's possible that we have
922 // something like "X3 = Y" which defines a new value number in the LHS,
923 // and is the last use of this liverange of the RHS. In this case, we
924 // want to notice this copy (so that it gets coalesced away) even though
925 // the live ranges don't actually overlap.
926 if (LHSIt->start == RHSIt->end) {
927 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
928 // We already know that this value number is going to be merged in
929 // if coalescing succeeds. Just skip the liverange.
930 if (++LHSIt == LHSEnd) break;
932 // Otherwise, if this is a copy from the RHS, mark it as being merged
934 if (li_->getVNInfoSourceReg(LHSIt->valno) == RHS.reg) {
935 EliminatedLHSVals.push_back(LHSIt->valno);
937 // We know this entire LHS live range is okay, so skip it now.
938 if (++LHSIt == LHSEnd) break;
943 if (++RHSIt == RHSEnd) break;
947 // If we got here, we know that the coalescing will be successful and that
948 // the value numbers in EliminatedLHSVals will all be merged together. Since
949 // the most common case is that EliminatedLHSVals has a single number, we
950 // optimize for it: if there is more than one value, we merge them all into
951 // the lowest numbered one, then handle the interval as if we were merging
952 // with one value number.
954 if (EliminatedLHSVals.size() > 1) {
955 // Loop through all the equal value numbers merging them into the smallest
957 VNInfo *Smallest = EliminatedLHSVals[0];
958 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
959 if (EliminatedLHSVals[i]->id < Smallest->id) {
960 // Merge the current notion of the smallest into the smaller one.
961 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
962 Smallest = EliminatedLHSVals[i];
964 // Merge into the smallest.
965 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
970 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
971 LHSValNo = EliminatedLHSVals[0];
974 // Okay, now that there is a single LHS value number that we're merging the
975 // RHS into, update the value number info for the LHS to indicate that the
976 // value number is defined where the RHS value number was.
977 const VNInfo *VNI = RHS.getValNumInfo(0);
978 LHSValNo->def = VNI->def;
979 LHSValNo->copy = VNI->copy;
981 // Okay, the final step is to loop over the RHS live intervals, adding them to
983 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
984 LHS.addKills(LHSValNo, VNI->kills);
985 LHS.MergeRangesInAsValue(RHS, LHSValNo);
986 LHS.weight += RHS.weight;
987 if (RHS.preference && !LHS.preference)
988 LHS.preference = RHS.preference;
993 /// JoinIntervals - Attempt to join these two intervals. On failure, this
994 /// returns false. Otherwise, if one of the intervals being joined is a
995 /// physreg, this method always canonicalizes LHS to be it. The output
996 /// "RHS" will not have been modified, so we can use this information
997 /// below to update aliases.
998 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
999 LiveInterval &RHS, bool &Swapped) {
1000 // Compute the final value assignment, assuming that the live ranges can be
1002 SmallVector<int, 16> LHSValNoAssignments;
1003 SmallVector<int, 16> RHSValNoAssignments;
1004 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1005 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1006 SmallVector<VNInfo*, 16> NewVNInfo;
1008 // If a live interval is a physical register, conservatively check if any
1009 // of its sub-registers is overlapping the live interval of the virtual
1010 // register. If so, do not coalesce.
1011 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1012 *tri_->getSubRegisters(LHS.reg)) {
1013 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1014 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1015 DOUT << "Interfere with sub-register ";
1016 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1019 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1020 *tri_->getSubRegisters(RHS.reg)) {
1021 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1022 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1023 DOUT << "Interfere with sub-register ";
1024 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1029 // Compute ultimate value numbers for the LHS and RHS values.
1030 if (RHS.containsOneValue()) {
1031 // Copies from a liveinterval with a single value are simple to handle and
1032 // very common, handle the special case here. This is important, because
1033 // often RHS is small and LHS is large (e.g. a physreg).
1035 // Find out if the RHS is defined as a copy from some value in the LHS.
1036 int RHSVal0DefinedFromLHS = -1;
1038 VNInfo *RHSValNoInfo = NULL;
1039 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1040 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1041 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1042 // If RHS is not defined as a copy from the LHS, we can use simpler and
1043 // faster checks to see if the live ranges are coalescable. This joiner
1044 // can't swap the LHS/RHS intervals though.
1045 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1046 return SimpleJoin(LHS, RHS);
1048 RHSValNoInfo = RHSValNoInfo0;
1051 // It was defined as a copy from the LHS, find out what value # it is.
1052 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1053 RHSValID = RHSValNoInfo->id;
1054 RHSVal0DefinedFromLHS = RHSValID;
1057 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1058 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1059 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1061 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1062 // should now get updated.
1063 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1066 unsigned VN = VNI->id;
1067 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1068 if (LHSSrcReg != RHS.reg) {
1069 // If this is not a copy from the RHS, its value number will be
1070 // unmodified by the coalescing.
1071 NewVNInfo[VN] = VNI;
1072 LHSValNoAssignments[VN] = VN;
1073 } else if (RHSValID == -1) {
1074 // Otherwise, it is a copy from the RHS, and we don't already have a
1075 // value# for it. Keep the current value number, but remember it.
1076 LHSValNoAssignments[VN] = RHSValID = VN;
1077 NewVNInfo[VN] = RHSValNoInfo;
1078 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1080 // Otherwise, use the specified value #.
1081 LHSValNoAssignments[VN] = RHSValID;
1082 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1083 NewVNInfo[VN] = RHSValNoInfo;
1084 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1088 NewVNInfo[VN] = VNI;
1089 LHSValNoAssignments[VN] = VN;
1093 assert(RHSValID != -1 && "Didn't find value #?");
1094 RHSValNoAssignments[0] = RHSValID;
1095 if (RHSVal0DefinedFromLHS != -1) {
1096 // This path doesn't go through ComputeUltimateVN so just set
1098 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1101 // Loop over the value numbers of the LHS, seeing if any are defined from
1103 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1106 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1109 // DstReg is known to be a register in the LHS interval. If the src is
1110 // from the RHS interval, we can use its value #.
1111 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1114 // Figure out the value # from the RHS.
1115 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1118 // Loop over the value numbers of the RHS, seeing if any are defined from
1120 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1123 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1126 // DstReg is known to be a register in the RHS interval. If the src is
1127 // from the LHS interval, we can use its value #.
1128 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1131 // Figure out the value # from the LHS.
1132 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1135 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1136 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1137 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1139 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1142 unsigned VN = VNI->id;
1143 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1145 ComputeUltimateVN(VNI, NewVNInfo,
1146 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1147 LHSValNoAssignments, RHSValNoAssignments);
1149 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1152 unsigned VN = VNI->id;
1153 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1155 // If this value number isn't a copy from the LHS, it's a new number.
1156 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1157 NewVNInfo.push_back(VNI);
1158 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1162 ComputeUltimateVN(VNI, NewVNInfo,
1163 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1164 RHSValNoAssignments, LHSValNoAssignments);
1168 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1169 // interval lists to see if these intervals are coalescable.
1170 LiveInterval::const_iterator I = LHS.begin();
1171 LiveInterval::const_iterator IE = LHS.end();
1172 LiveInterval::const_iterator J = RHS.begin();
1173 LiveInterval::const_iterator JE = RHS.end();
1175 // Skip ahead until the first place of potential sharing.
1176 if (I->start < J->start) {
1177 I = std::upper_bound(I, IE, J->start);
1178 if (I != LHS.begin()) --I;
1179 } else if (J->start < I->start) {
1180 J = std::upper_bound(J, JE, I->start);
1181 if (J != RHS.begin()) --J;
1185 // Determine if these two live ranges overlap.
1187 if (I->start < J->start) {
1188 Overlaps = I->end > J->start;
1190 Overlaps = J->end > I->start;
1193 // If so, check value # info to determine if they are really different.
1195 // If the live range overlap will map to the same value number in the
1196 // result liverange, we can still coalesce them. If not, we can't.
1197 if (LHSValNoAssignments[I->valno->id] !=
1198 RHSValNoAssignments[J->valno->id])
1202 if (I->end < J->end) {
1211 // Update kill info. Some live ranges are extended due to copy coalescing.
1212 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1213 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1214 VNInfo *VNI = I->first;
1215 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1216 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1217 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1218 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1221 // Update kill info. Some live ranges are extended due to copy coalescing.
1222 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1223 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1224 VNInfo *VNI = I->first;
1225 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1226 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1227 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1228 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1231 // If we get here, we know that we can coalesce the live ranges. Ask the
1232 // intervals to coalesce themselves now.
1233 if ((RHS.ranges.size() > LHS.ranges.size() &&
1234 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1235 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1236 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1239 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1246 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1247 // depth of the basic block (the unsigned), and then on the MBB number.
1248 struct DepthMBBCompare {
1249 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1250 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1251 if (LHS.first > RHS.first) return true; // Deeper loops first
1252 return LHS.first == RHS.first &&
1253 LHS.second->getNumber() < RHS.second->getNumber();
1258 /// getRepIntervalSize - Returns the size of the interval that represents the
1259 /// specified register.
1261 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1262 return Rc->getRepIntervalSize(Reg);
1265 /// CopyRecSort::operator - Join priority queue sorting function.
1267 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1268 // Inner loops first.
1269 if (left.LoopDepth > right.LoopDepth)
1271 else if (left.LoopDepth == right.LoopDepth)
1272 if (left.isBackEdge && !right.isBackEdge)
1277 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1278 std::vector<CopyRec> &TryAgain) {
1279 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1281 std::vector<CopyRec> VirtCopies;
1282 std::vector<CopyRec> PhysCopies;
1283 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1284 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1286 MachineInstr *Inst = MII++;
1288 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1289 unsigned SrcReg, DstReg;
1290 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1291 DstReg = Inst->getOperand(0).getReg();
1292 SrcReg = Inst->getOperand(1).getReg();
1293 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1296 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1297 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1299 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
1301 if (SrcIsPhys || DstIsPhys)
1302 PhysCopies.push_back(CopyRec(Inst, 0, false));
1304 VirtCopies.push_back(CopyRec(Inst, 0, false));
1311 // Try coalescing physical register + virtual register first.
1312 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1313 CopyRec &TheCopy = PhysCopies[i];
1315 if (!JoinCopy(TheCopy, Again))
1317 TryAgain.push_back(TheCopy);
1319 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1320 CopyRec &TheCopy = VirtCopies[i];
1322 if (!JoinCopy(TheCopy, Again))
1324 TryAgain.push_back(TheCopy);
1328 void SimpleRegisterCoalescing::joinIntervals() {
1329 DOUT << "********** JOINING INTERVALS ***********\n";
1332 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1334 std::vector<CopyRec> TryAgainList;
1335 if (loopInfo->begin() == loopInfo->end()) {
1336 // If there are no loops in the function, join intervals in function order.
1337 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1339 CopyCoalesceInMBB(I, TryAgainList);
1341 // Otherwise, join intervals in inner loops before other intervals.
1342 // Unfortunately we can't just iterate over loop hierarchy here because
1343 // there may be more MBB's than BB's. Collect MBB's for sorting.
1345 // Join intervals in the function prolog first. We want to join physical
1346 // registers with virtual registers before the intervals got too long.
1347 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1348 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1349 MachineBasicBlock *MBB = I;
1350 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1353 // Sort by loop depth.
1354 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1356 // Finally, join intervals in loop nest order.
1357 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1358 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1361 // Joining intervals can allow other intervals to be joined. Iteratively join
1362 // until we make no progress.
1364 SmallVector<CopyRec, 16> TryAgain;
1365 bool ProgressMade = true;
1366 while (ProgressMade) {
1367 ProgressMade = false;
1368 while (!JoinQueue->empty()) {
1369 CopyRec R = JoinQueue->pop();
1371 bool Success = JoinCopy(R, Again);
1373 ProgressMade = true;
1375 TryAgain.push_back(R);
1379 while (!TryAgain.empty()) {
1380 JoinQueue->push(TryAgain.back());
1381 TryAgain.pop_back();
1386 bool ProgressMade = true;
1387 while (ProgressMade) {
1388 ProgressMade = false;
1390 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1391 CopyRec &TheCopy = TryAgainList[i];
1394 bool Success = JoinCopy(TheCopy, Again);
1395 if (Success || !Again) {
1396 TheCopy.MI = 0; // Mark this one as done.
1397 ProgressMade = true;
1408 /// Return true if the two specified registers belong to different register
1409 /// classes. The registers may be either phys or virt regs.
1410 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1411 unsigned RegB) const {
1413 // Get the register classes for the first reg.
1414 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1415 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1416 "Shouldn't consider two physregs!");
1417 return !mri_->getRegClass(RegB)->contains(RegA);
1420 // Compare against the regclass for the second reg.
1421 const TargetRegisterClass *RegClass = mri_->getRegClass(RegA);
1422 if (TargetRegisterInfo::isVirtualRegister(RegB))
1423 return RegClass != mri_->getRegClass(RegB);
1425 return !RegClass->contains(RegB);
1428 /// lastRegisterUse - Returns the last use of the specific register between
1429 /// cycles Start and End or NULL if there are no uses.
1431 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
1432 unsigned Reg, unsigned &UseIdx) const{
1434 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1435 MachineOperand *LastUse = NULL;
1436 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
1437 E = mri_->use_end(); I != E; ++I) {
1438 MachineOperand &Use = I.getOperand();
1439 MachineInstr *UseMI = Use.getParent();
1440 unsigned Idx = li_->getInstructionIndex(UseMI);
1441 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1449 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1452 // Skip deleted instructions
1453 MachineInstr *MI = li_->getInstructionFromIndex(e);
1454 while ((e - InstrSlots::NUM) >= s && !MI) {
1455 e -= InstrSlots::NUM;
1456 MI = li_->getInstructionFromIndex(e);
1458 if (e < s || MI == NULL)
1461 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1462 MachineOperand &Use = MI->getOperand(i);
1463 if (Use.isRegister() && Use.isUse() && Use.getReg() &&
1464 tri_->regsOverlap(Use.getReg(), Reg)) {
1470 e -= InstrSlots::NUM;
1477 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1478 /// register. It returns NULL if the def is not found.
1479 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI,
1480 unsigned Reg) const {
1481 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1482 MachineOperand &MO = MI->getOperand(i);
1483 if (MO.isRegister() && MO.isDef() &&
1484 tri_->regsOverlap(MO.getReg(), Reg))
1490 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1491 /// between cycles Start and End.
1492 void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
1494 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1497 // Skip deleted instructions
1498 MachineInstr *MI = li_->getInstructionFromIndex(e);
1499 while ((e - InstrSlots::NUM) >= s && !MI) {
1500 e -= InstrSlots::NUM;
1501 MI = li_->getInstructionFromIndex(e);
1503 if (e < s || MI == NULL)
1506 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1507 MachineOperand &MO = MI->getOperand(i);
1508 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1509 tri_->regsOverlap(MO.getReg(), Reg)) {
1510 MO.setIsKill(false);
1514 e -= InstrSlots::NUM;
1518 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1519 if (TargetRegisterInfo::isPhysicalRegister(reg))
1520 cerr << tri_->getName(reg);
1522 cerr << "%reg" << reg;
1525 void SimpleRegisterCoalescing::releaseMemory() {
1526 JoinedCopies.clear();
1529 static bool isZeroLengthInterval(LiveInterval *li) {
1530 for (LiveInterval::Ranges::const_iterator
1531 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1532 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1537 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1539 mri_ = &fn.getRegInfo();
1540 tm_ = &fn.getTarget();
1541 tri_ = tm_->getRegisterInfo();
1542 tii_ = tm_->getInstrInfo();
1543 li_ = &getAnalysis<LiveIntervals>();
1544 lv_ = &getAnalysis<LiveVariables>();
1545 loopInfo = &getAnalysis<MachineLoopInfo>();
1547 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1548 << "********** Function: "
1549 << ((Value*)mf_->getFunction())->getName() << '\n';
1551 allocatableRegs_ = tri_->getAllocatableSet(fn);
1552 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
1553 E = tri_->regclass_end(); I != E; ++I)
1554 allocatableRCRegs_.insert(std::make_pair(*I,
1555 tri_->getAllocatableSet(fn, *I)));
1557 // Join (coalesce) intervals if requested.
1558 if (EnableJoining) {
1560 DOUT << "********** INTERVALS POST JOINING **********\n";
1561 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
1562 I->second.print(DOUT, tri_);
1566 // Delete all coalesced copies.
1567 for (SmallPtrSet<MachineInstr*,32>::iterator I = JoinedCopies.begin(),
1568 E = JoinedCopies.end(); I != E; ++I) {
1569 li_->RemoveMachineInstrFromMaps(*I);
1570 (*I)->eraseFromParent();
1575 // Perform a final pass over the instructions and compute spill weights
1576 // and remove identity moves.
1577 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1578 mbbi != mbbe; ++mbbi) {
1579 MachineBasicBlock* mbb = mbbi;
1580 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
1582 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1584 // if the move will be an identity move delete it
1585 unsigned srcReg, dstReg;
1586 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) {
1587 // remove from def list
1588 LiveInterval &RegInt = li_->getOrCreateInterval(srcReg);
1589 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1590 // If def of this move instruction is dead, remove its live range from
1591 // the dstination register's live interval.
1593 unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
1594 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
1595 RegInt.removeRange(MLR->start, MoveIdx+1, true);
1597 li_->removeInterval(srcReg);
1599 li_->RemoveMachineInstrFromMaps(mii);
1600 mii = mbbi->erase(mii);
1603 SmallSet<unsigned, 4> UniqueUses;
1604 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
1605 const MachineOperand &mop = mii->getOperand(i);
1606 if (mop.isRegister() && mop.getReg() &&
1607 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
1608 unsigned reg = mop.getReg();
1609 // Multiple uses of reg by the same instruction. It should not
1610 // contribute to spill weight again.
1611 if (UniqueUses.count(reg) != 0)
1613 LiveInterval &RegInt = li_->getInterval(reg);
1615 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
1616 UniqueUses.insert(reg);
1624 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1625 LiveInterval &LI = I->second;
1626 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1627 // If the live interval length is essentially zero, i.e. in every live
1628 // range the use follows def immediately, it doesn't make sense to spill
1629 // it and hope it will be easier to allocate for this li.
1630 if (isZeroLengthInterval(&LI))
1631 LI.weight = HUGE_VALF;
1633 bool isLoad = false;
1634 if (li_->isReMaterializable(LI, isLoad)) {
1635 // If all of the definitions of the interval are re-materializable,
1636 // it is a preferred candidate for spilling. If non of the defs are
1637 // loads, then it's potentially very cheap to re-materialize.
1638 // FIXME: this gets much more complicated once we support non-trivial
1639 // re-materialization.
1647 // Slightly prefer live interval that has been assigned a preferred reg.
1651 // Divide the weight of the interval by its size. This encourages
1652 // spilling of intervals that are large and have few uses, and
1653 // discourages spilling of small intervals with many uses.
1654 LI.weight /= LI.getSize();
1662 /// print - Implement the dump method.
1663 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
1667 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1668 return new SimpleRegisterCoalescing();
1671 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1672 DEFINING_FILE_FOR(SimpleRegisterCoalescing)