1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 char &llvm::SimpleRegisterCoalescingID = SimpleRegisterCoalescing::ID;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP,
103 MachineInstr *CopyMI) {
104 // Bail if there is no dst interval - can happen when merging physical subreg
106 if (!li_->hasInterval(CP.getDstReg()))
110 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
112 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
113 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
115 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
116 // the example above.
117 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
118 if (BLR == IntB.end()) return false;
119 VNInfo *BValNo = BLR->valno;
121 // Get the location that B is defined at. Two options: either this value has
122 // an unknown definition point or it is defined at CopyIdx. If unknown, we
124 if (!BValNo->getCopy()) return false;
125 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
127 // AValNo is the value number in A that defines the copy, A3 in the example.
128 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
129 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
130 // The live range might not exist after fun with physreg coalescing.
131 if (ALR == IntA.end()) return false;
132 VNInfo *AValNo = ALR->valno;
133 // If it's re-defined by an early clobber somewhere in the live range, then
134 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
136 // 172 %ECX<def> = MOV32rr %reg1039<kill>
137 // 180 INLINEASM <es:subl $5,$1
138 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
140 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
141 // 188 %EAX<def> = MOV32rr %EAX<kill>
142 // 196 %ECX<def> = MOV32rr %ECX<kill>
143 // 204 %ECX<def> = MOV32rr %ECX<kill>
144 // 212 %EAX<def> = MOV32rr %EAX<kill>
145 // 220 %EAX<def> = MOV32rr %EAX
146 // 228 %reg1039<def> = MOV32rr %ECX<kill>
147 // The early clobber operand ties ECX input to the ECX def.
149 // The live interval of ECX is represented as this:
150 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
151 // The coalescer has no idea there was a def in the middle of [174,230].
152 if (AValNo->hasRedefByEC())
155 // If AValNo is defined as a copy from IntB, we can potentially process this.
156 // Get the instruction that defines this value number.
157 if (!CP.isCoalescable(AValNo->getCopy()))
160 // Get the LiveRange in IntB that this value number starts with.
161 LiveInterval::iterator ValLR =
162 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
163 if (ValLR == IntB.end())
166 // Make sure that the end of the live range is inside the same block as
168 MachineInstr *ValLREndInst =
169 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
170 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
173 // Okay, we now know that ValLR ends in the same block that the CopyMI
174 // live-range starts. If there are no intervening live ranges between them in
175 // IntB, we can merge them.
176 if (ValLR+1 != BLR) return false;
178 // If a live interval is a physical register, conservatively check if any
179 // of its sub-registers is overlapping the live interval of the virtual
180 // register. If so, do not coalesce.
181 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
182 *tri_->getSubRegisters(IntB.reg)) {
183 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
184 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
186 dbgs() << "\t\tInterfere with sub-register ";
187 li_->getInterval(*SR).print(dbgs(), tri_);
194 dbgs() << "Extending: ";
195 IntB.print(dbgs(), tri_);
198 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
199 // We are about to delete CopyMI, so need to remove it as the 'instruction
200 // that defines this value #'. Update the valnum with the new defining
202 BValNo->def = FillerStart;
205 // Okay, we can merge them. We need to insert a new liverange:
206 // [ValLR.end, BLR.begin) of either value number, then we merge the
207 // two value numbers.
208 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
210 // If the IntB live range is assigned to a physical register, and if that
211 // physreg has sub-registers, update their live intervals as well.
212 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
213 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
214 if (!li_->hasInterval(*SR))
216 LiveInterval &SRLI = li_->getInterval(*SR);
217 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
218 SRLI.getNextValue(FillerStart, 0, true,
219 li_->getVNInfoAllocator())));
223 // Okay, merge "B1" into the same value number as "B0".
224 if (BValNo != ValLR->valno) {
225 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
228 dbgs() << " result = ";
229 IntB.print(dbgs(), tri_);
233 // If the source instruction was killing the source register before the
234 // merge, unset the isKill marker given the live range has been extended.
235 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
237 ValLREndInst->getOperand(UIdx).setIsKill(false);
240 // If the copy instruction was killing the destination register before the
241 // merge, find the last use and trim the live range. That will also add the
243 if (ALR->end == CopyIdx)
244 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
250 /// HasOtherReachingDefs - Return true if there are definitions of IntB
251 /// other than BValNo val# that can reach uses of AValno val# of IntA.
252 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
256 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
258 if (AI->valno != AValNo) continue;
259 LiveInterval::Ranges::iterator BI =
260 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
261 if (BI != IntB.ranges.begin())
263 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
264 if (BI->valno == BValNo)
266 // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
267 if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
269 if (BI->start <= AI->start && BI->end > AI->start)
271 if (BI->start > AI->start && BI->start < AI->end)
279 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
280 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
282 MachineOperand &MO = MI->getOperand(i);
283 if (MO.isReg() && MO.isImplicit())
284 NewMI->addOperand(MO);
288 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
289 /// IntA being the source and IntB being the dest, thus this defines a value
290 /// number in IntB. If the source value number (in IntA) is defined by a
291 /// commutable instruction and its other operand is coalesced to the copy dest
292 /// register, see if we can transform the copy into a noop by commuting the
293 /// definition. For example,
295 /// A3 = op A2 B0<kill>
297 /// B1 = A3 <- this copy
299 /// = op A3 <- more uses
303 /// B2 = op B0 A2<kill>
305 /// B1 = B2 <- now an identify copy
307 /// = op B2 <- more uses
309 /// This returns true if an interval was modified.
311 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
312 MachineInstr *CopyMI) {
313 // FIXME: For now, only eliminate the copy by commuting its def when the
314 // source register is a virtual register. We want to guard against cases
315 // where the copy is a back edge copy and commuting the def lengthen the
316 // live interval of the source register to the entire loop.
317 if (CP.isPhys() && CP.isFlipped())
320 // Bail if there is no dst interval.
321 if (!li_->hasInterval(CP.getDstReg()))
325 li_->getInstructionIndex(CopyMI).getDefIndex();
328 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
330 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
332 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
333 // the example above.
334 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
335 if (BLR == IntB.end()) return false;
336 VNInfo *BValNo = BLR->valno;
338 // Get the location that B is defined at. Two options: either this value has
339 // an unknown definition point or it is defined at CopyIdx. If unknown, we
341 if (!BValNo->getCopy()) return false;
342 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
344 // AValNo is the value number in A that defines the copy, A3 in the example.
345 LiveInterval::iterator ALR =
346 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
348 assert(ALR != IntA.end() && "Live range not found!");
349 VNInfo *AValNo = ALR->valno;
350 // If other defs can reach uses of this def, then it's not safe to perform
351 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
353 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
354 AValNo->isUnused() || AValNo->hasPHIKill())
356 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
359 const TargetInstrDesc &TID = DefMI->getDesc();
360 if (!TID.isCommutable())
362 // If DefMI is a two-address instruction then commuting it will change the
363 // destination register.
364 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
365 assert(DefIdx != -1);
367 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
369 unsigned Op1, Op2, NewDstIdx;
370 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
374 else if (Op2 == UseOpIdx)
379 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
380 unsigned NewReg = NewDstMO.getReg();
381 if (NewReg != IntB.reg || !NewDstMO.isKill())
384 // Make sure there are no other definitions of IntB that would reach the
385 // uses which the new definition can reach.
386 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
389 bool BHasSubRegs = false;
390 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
391 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
393 // Abort if the subregisters of IntB.reg have values that are not simply the
394 // clobbers from the superreg.
396 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
397 if (li_->hasInterval(*SR) &&
398 HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
401 // If some of the uses of IntA.reg is already coalesced away, return false.
402 // It's not possible to determine whether it's safe to perform the coalescing.
403 for (MachineRegisterInfo::use_nodbg_iterator UI =
404 mri_->use_nodbg_begin(IntA.reg),
405 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
406 MachineInstr *UseMI = &*UI;
407 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
408 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
409 if (ULR == IntA.end())
411 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
415 // At this point we have decided that it is legal to do this
416 // transformation. Start by commuting the instruction.
417 MachineBasicBlock *MBB = DefMI->getParent();
418 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
421 if (NewMI != DefMI) {
422 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
423 MBB->insert(DefMI, NewMI);
426 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
427 NewMI->getOperand(OpIdx).setIsKill();
429 bool BHasPHIKill = BValNo->hasPHIKill();
430 SmallVector<VNInfo*, 4> BDeadValNos;
431 std::map<SlotIndex, SlotIndex> BExtend;
433 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
441 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
443 BExtend[ALR->end] = BLR->end;
445 // Update uses of IntA of the specific Val# with IntB.
446 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
447 UE = mri_->use_end(); UI != UE;) {
448 MachineOperand &UseMO = UI.getOperand();
449 MachineInstr *UseMI = &*UI;
451 if (JoinedCopies.count(UseMI))
453 if (UseMI->isDebugValue()) {
454 // FIXME These don't have an instruction index. Not clear we have enough
455 // info to decide whether to do this replacement or not. For now do it.
456 UseMO.setReg(NewReg);
459 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
460 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
461 if (ULR == IntA.end() || ULR->valno != AValNo)
463 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
464 UseMO.substPhysReg(NewReg, *tri_);
466 UseMO.setReg(NewReg);
469 if (UseMO.isKill()) {
471 UseMO.setIsKill(false);
473 if (!UseMI->isCopy())
475 if (UseMI->getOperand(0).getReg() != IntB.reg ||
476 UseMI->getOperand(0).getSubReg())
479 // This copy will become a noop. If it's defining a new val#,
480 // remove that val# as well. However this live range is being
481 // extended to the end of the existing live range defined by the copy.
482 SlotIndex DefIdx = UseIdx.getDefIndex();
483 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
486 BHasPHIKill |= DLR->valno->hasPHIKill();
487 assert(DLR->valno->def == DefIdx);
488 BDeadValNos.push_back(DLR->valno);
489 BExtend[DLR->start] = DLR->end;
490 JoinedCopies.insert(UseMI);
493 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
494 // simply extend BLR if CopyMI doesn't end the range.
496 dbgs() << "Extending: ";
497 IntB.print(dbgs(), tri_);
500 // Remove val#'s defined by copies that will be coalesced away.
501 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
502 VNInfo *DeadVNI = BDeadValNos[i];
504 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
505 if (!li_->hasInterval(*SR))
507 LiveInterval &SRLI = li_->getInterval(*SR);
508 if (const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def))
509 SRLI.removeValNo(SRLR->valno);
512 IntB.removeValNo(BDeadValNos[i]);
515 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
517 VNInfo *ValNo = BValNo;
518 ValNo->def = AValNo->def;
520 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
522 if (AI->valno != AValNo) continue;
523 SlotIndex End = AI->end;
524 std::map<SlotIndex, SlotIndex>::iterator
525 EI = BExtend.find(End);
526 if (EI != BExtend.end())
528 IntB.addRange(LiveRange(AI->start, End, ValNo));
530 ValNo->setHasPHIKill(BHasPHIKill);
533 dbgs() << " result = ";
534 IntB.print(dbgs(), tri_);
535 dbgs() << "\nShortening: ";
536 IntA.print(dbgs(), tri_);
539 IntA.removeValNo(AValNo);
542 dbgs() << " result = ";
543 IntA.print(dbgs(), tri_);
551 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
552 /// fallthoughs to SuccMBB.
553 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
554 MachineBasicBlock *SuccMBB,
555 const TargetInstrInfo *tii_) {
558 MachineBasicBlock *TBB = 0, *FBB = 0;
559 SmallVector<MachineOperand, 4> Cond;
560 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
561 MBB->isSuccessor(SuccMBB);
564 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
565 /// from a physical register live interval as well as from the live intervals
566 /// of its sub-registers.
567 static void removeRange(LiveInterval &li,
568 SlotIndex Start, SlotIndex End,
569 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
570 li.removeRange(Start, End, true);
571 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
572 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
573 if (!li_->hasInterval(*SR))
575 LiveInterval &sli = li_->getInterval(*SR);
576 SlotIndex RemoveStart = Start;
577 SlotIndex RemoveEnd = Start;
579 while (RemoveEnd != End) {
580 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
583 RemoveEnd = (LR->end < End) ? LR->end : End;
584 sli.removeRange(RemoveStart, RemoveEnd, true);
585 RemoveStart = RemoveEnd;
591 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
592 /// as the copy instruction, trim the live interval to the last use and return
595 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
596 MachineBasicBlock *CopyMBB,
598 const LiveRange *LR) {
599 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
600 SlotIndex LastUseIdx;
601 MachineOperand *LastUse =
602 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
604 MachineInstr *LastUseMI = LastUse->getParent();
605 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
612 // r1025<dead> = r1024<kill>
613 if (MBBStart < LR->end)
614 removeRange(li, MBBStart, LR->end, li_, tri_);
618 // There are uses before the copy, just shorten the live range to the end
620 LastUse->setIsKill();
621 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
622 if (LastUseMI->isCopy()) {
623 MachineOperand &DefMO = LastUseMI->getOperand(0);
624 if (DefMO.getReg() == li.reg && !DefMO.getSubReg())
631 if (LR->start <= MBBStart && LR->end > MBBStart) {
632 if (LR->start == li_->getZeroIndex()) {
633 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
634 // Live-in to the function but dead. Remove it from entry live-in set.
635 mf_->begin()->removeLiveIn(li.reg);
637 // FIXME: Shorten intervals in BBs that reaches this BB.
643 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
644 /// computation, replace the copy by rematerialize the definition.
645 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
648 MachineInstr *CopyMI) {
649 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
650 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
651 assert(SrcLR != SrcInt.end() && "Live range not found!");
652 VNInfo *ValNo = SrcLR->valno;
653 // If other defs can reach uses of this def, then it's not safe to perform
654 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
656 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
657 ValNo->isUnused() || ValNo->hasPHIKill())
659 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
660 assert(DefMI && "Defining instruction disappeared");
661 const TargetInstrDesc &TID = DefMI->getDesc();
662 if (!TID.isAsCheapAsAMove())
664 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
666 bool SawStore = false;
667 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
669 if (TID.getNumDefs() != 1)
671 if (!DefMI->isImplicitDef()) {
672 // Make sure the copy destination register class fits the instruction
673 // definition register class. The mismatch can happen as a result of earlier
674 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
675 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
676 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
677 if (mri_->getRegClass(DstReg) != RC)
679 } else if (!RC->contains(DstReg))
683 // If destination register has a sub-register index on it, make sure it mtches
684 // the instruction register class.
686 const TargetInstrDesc &TID = DefMI->getDesc();
687 if (TID.getNumDefs() != 1)
689 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
690 const TargetRegisterClass *DstSubRC =
691 DstRC->getSubRegisterRegClass(DstSubIdx);
692 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
695 else if (DefRC != DstSubRC)
699 RemoveCopyFlag(DstReg, CopyMI);
701 // If copy kills the source register, find the last use and propagate
703 bool checkForDeadDef = false;
704 MachineBasicBlock *MBB = CopyMI->getParent();
705 if (SrcLR->end == CopyIdx.getDefIndex())
706 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
707 checkForDeadDef = true;
710 MachineBasicBlock::iterator MII =
711 llvm::next(MachineBasicBlock::iterator(CopyMI));
712 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_);
713 MachineInstr *NewMI = prior(MII);
715 if (checkForDeadDef) {
716 // PR4090 fix: Trim interval failed because there was no use of the
717 // source interval in this MBB. If the def is in this MBB too then we
718 // should mark it dead:
719 if (DefMI->getParent() == MBB) {
720 DefMI->addRegisterDead(SrcInt.reg, tri_);
721 SrcLR->end = SrcLR->start.getNextSlot();
725 // CopyMI may have implicit operands, transfer them over to the newly
726 // rematerialized instruction. And update implicit def interval valnos.
727 for (unsigned i = CopyMI->getDesc().getNumOperands(),
728 e = CopyMI->getNumOperands(); i != e; ++i) {
729 MachineOperand &MO = CopyMI->getOperand(i);
730 if (MO.isReg() && MO.isImplicit())
731 NewMI->addOperand(MO);
733 RemoveCopyFlag(MO.getReg(), CopyMI);
736 TransferImplicitOps(CopyMI, NewMI);
737 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
738 CopyMI->eraseFromParent();
739 ReMatCopies.insert(CopyMI);
740 ReMatDefs.insert(DefMI);
741 DEBUG(dbgs() << "Remat: " << *NewMI);
746 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
747 /// update the subregister number if it is not zero. If DstReg is a
748 /// physical register and the existing subregister number of the def / use
749 /// being updated is not zero, make sure to set it to the correct physical
752 SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
753 bool DstIsPhys = CP.isPhys();
754 unsigned SrcReg = CP.getSrcReg();
755 unsigned DstReg = CP.getDstReg();
756 unsigned SubIdx = CP.getSubIdx();
758 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg);
759 MachineInstr *UseMI = I.skipInstruction();) {
760 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
763 if (UseMI->isCopy() &&
764 !UseMI->getOperand(1).getSubReg() &&
765 !UseMI->getOperand(0).getSubReg() &&
766 UseMI->getOperand(1).getReg() == SrcReg &&
767 UseMI->getOperand(0).getReg() != SrcReg &&
768 UseMI->getOperand(0).getReg() != DstReg &&
769 !JoinedCopies.count(UseMI) &&
770 ReMaterializeTrivialDef(li_->getInterval(SrcReg),
771 UseMI->getOperand(0).getReg(), 0, UseMI))
775 SmallVector<unsigned,8> Ops;
777 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
778 bool Kills = false, Deads = false;
780 // Replace SrcReg with DstReg in all UseMI operands.
781 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
782 MachineOperand &MO = UseMI->getOperand(Ops[i]);
783 Kills |= MO.isKill();
784 Deads |= MO.isDead();
787 MO.substPhysReg(DstReg, *tri_);
789 MO.substVirtReg(DstReg, SubIdx, *tri_);
792 // This instruction is a copy that will be removed.
793 if (JoinedCopies.count(UseMI))
797 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
798 // read-modify-write of DstReg.
800 UseMI->addRegisterDead(DstReg, tri_);
801 else if (!Reads && Writes)
802 UseMI->addRegisterDefined(DstReg, tri_);
804 // Kill flags apply to the whole physical register.
805 if (DstIsPhys && Kills)
806 UseMI->addRegisterKilled(DstReg, tri_);
810 dbgs() << "\t\tupdated: ";
811 if (!UseMI->isDebugValue())
812 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
818 /// removeIntervalIfEmpty - Check if the live interval of a physical register
819 /// is empty, if so remove it and also remove the empty intervals of its
820 /// sub-registers. Return true if live interval is removed.
821 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
822 const TargetRegisterInfo *tri_) {
824 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
825 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
826 if (!li_->hasInterval(*SR))
828 LiveInterval &sli = li_->getInterval(*SR);
830 li_->removeInterval(*SR);
832 li_->removeInterval(li.reg);
838 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
839 /// Return true if live interval is removed.
840 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
841 MachineInstr *CopyMI) {
842 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
843 LiveInterval::iterator MLR =
844 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
846 return false; // Already removed by ShortenDeadCopySrcLiveRange.
847 SlotIndex RemoveStart = MLR->start;
848 SlotIndex RemoveEnd = MLR->end;
849 SlotIndex DefIdx = CopyIdx.getDefIndex();
850 // Remove the liverange that's defined by this.
851 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
852 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
853 return removeIntervalIfEmpty(li, li_, tri_);
858 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
859 /// the val# it defines. If the live interval becomes empty, remove it as well.
860 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
861 MachineInstr *DefMI) {
862 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
863 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
864 if (DefIdx != MLR->valno->def)
866 li.removeValNo(MLR->valno);
867 return removeIntervalIfEmpty(li, li_, tri_);
870 void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg,
871 const MachineInstr *CopyMI) {
872 SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
873 if (li_->hasInterval(DstReg)) {
874 LiveInterval &LI = li_->getInterval(DstReg);
875 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
876 if (LR->valno->getCopy() == CopyMI)
877 LR->valno->setCopy(0);
879 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
881 for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) {
882 if (!li_->hasInterval(*AS))
884 LiveInterval &LI = li_->getInterval(*AS);
885 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
886 if (LR->valno->getCopy() == CopyMI)
887 LR->valno->setCopy(0);
891 /// PropagateDeadness - Propagate the dead marker to the instruction which
892 /// defines the val#.
893 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
894 SlotIndex &LRStart, LiveIntervals *li_,
895 const TargetRegisterInfo* tri_) {
896 MachineInstr *DefMI =
897 li_->getInstructionFromIndex(LRStart.getDefIndex());
898 if (DefMI && DefMI != CopyMI) {
899 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg);
901 DefMI->getOperand(DeadIdx).setIsDead();
903 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
904 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
905 LRStart = LRStart.getNextSlot();
909 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
910 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
911 /// ends the live range there. If there isn't another use, then this live range
912 /// is dead. Return true if live interval is removed.
914 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
915 MachineInstr *CopyMI) {
916 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
917 if (CopyIdx == SlotIndex()) {
918 // FIXME: special case: function live in. It can be a general case if the
919 // first instruction index starts at > 0 value.
920 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
921 // Live-in to the function but dead. Remove it from entry live-in set.
922 if (mf_->begin()->isLiveIn(li.reg))
923 mf_->begin()->removeLiveIn(li.reg);
924 if (const LiveRange *LR = li.getLiveRangeContaining(CopyIdx))
925 removeRange(li, LR->start, LR->end, li_, tri_);
926 return removeIntervalIfEmpty(li, li_, tri_);
929 LiveInterval::iterator LR =
930 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
932 // Livein but defined by a phi.
935 SlotIndex RemoveStart = LR->start;
936 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
937 if (LR->end > RemoveEnd)
938 // More uses past this copy? Nothing to do.
941 // If there is a last use in the same bb, we can't remove the live range.
942 // Shorten the live interval and return.
943 MachineBasicBlock *CopyMBB = CopyMI->getParent();
944 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
947 // There are other kills of the val#. Nothing to do.
948 if (!li.isOnlyLROfValNo(LR))
951 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
952 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
953 // If the live range starts in another mbb and the copy mbb is not a fall
954 // through mbb, then we can only cut the range from the beginning of the
956 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
958 if (LR->valno->def == RemoveStart) {
959 // If the def MI defines the val# and this copy is the only kill of the
960 // val#, then propagate the dead marker.
961 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
965 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
966 return removeIntervalIfEmpty(li, li_, tri_);
970 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
971 /// two virtual registers from different register classes.
973 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
975 const TargetRegisterClass *SrcRC,
976 const TargetRegisterClass *DstRC,
977 const TargetRegisterClass *NewRC) {
978 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
979 // This heuristics is good enough in practice, but it's obviously not *right*.
980 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
981 // out all but the most restrictive register classes.
982 if (NewRCCount > 4 ||
983 // Early exit if the function is fairly small, coalesce aggressively if
984 // that's the case. For really special register classes with 3 or
985 // fewer registers, be a bit more careful.
986 (li_->getFuncInstructionCount() / NewRCCount) < 8)
988 LiveInterval &SrcInt = li_->getInterval(SrcReg);
989 LiveInterval &DstInt = li_->getInterval(DstReg);
990 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
991 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
992 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
994 // Estimate *register use density*. If it doubles or more, abort.
995 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
996 mri_->use_nodbg_end());
997 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
998 mri_->use_nodbg_end());
999 unsigned NewUses = SrcUses + DstUses;
1000 unsigned NewSize = SrcSize + DstSize;
1001 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1002 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1003 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1006 if (DstRC != NewRC && DstSize > NewRCCount) {
1007 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1008 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1015 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1016 /// which are the src/dst of the copy instruction CopyMI. This returns true
1017 /// if the copy was successfully coalesced away. If it is not currently
1018 /// possible to coalesce this interval, but it may be possible if other
1019 /// things get coalesced, then it returns true by reference in 'Again'.
1020 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1021 MachineInstr *CopyMI = TheCopy.MI;
1024 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1025 return false; // Already done.
1027 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1029 CoalescerPair CP(*tii_, *tri_);
1030 if (!CP.setRegisters(CopyMI)) {
1031 DEBUG(dbgs() << "\tNot coalescable.\n");
1035 // If they are already joined we continue.
1036 if (CP.getSrcReg() == CP.getDstReg()) {
1037 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1038 return false; // Not coalescable.
1041 DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg());
1043 // Enforce policies.
1045 DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n");
1046 // Only coalesce to allocatable physreg.
1047 if (!li_->isAllocatable(CP.getDstReg())) {
1048 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1049 return false; // Not coalescable.
1053 dbgs() << " with reg%" << CP.getDstReg();
1055 dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx());
1056 dbgs() << " to " << CP.getNewRC()->getName() << "\n";
1059 // Avoid constraining virtual register regclass too much.
1060 if (CP.isCrossClass()) {
1061 if (DisableCrossClassJoin) {
1062 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1065 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1066 mri_->getRegClass(CP.getSrcReg()),
1067 mri_->getRegClass(CP.getDstReg()),
1069 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1070 << CP.getNewRC()->getName() << ".\n");
1071 Again = true; // May be possible to coalesce later.
1076 // When possible, let DstReg be the larger interval.
1077 if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
1078 li_->getInterval(CP.getDstReg()).ranges.size())
1082 // We need to be careful about coalescing a source physical register with a
1083 // virtual register. Once the coalescing is done, it cannot be broken and
1084 // these are not spillable! If the destination interval uses are far away,
1085 // think twice about coalescing them!
1086 // FIXME: Why are we skipping this test for partial copies?
1087 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1088 if (!CP.isPartial() && CP.isPhys()) {
1089 LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
1091 // Don't join with physregs that have a ridiculous number of live
1092 // ranges. The data structure performance is really bad when that
1094 if (li_->hasInterval(CP.getDstReg()) &&
1095 li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1098 << "\tPhysical register live interval too complicated, abort!\n");
1102 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
1103 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1104 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1105 if (Length > Threshold &&
1106 std::distance(mri_->use_nodbg_begin(CP.getSrcReg()),
1107 mri_->use_nodbg_end()) * Threshold < Length) {
1108 // Before giving up coalescing, if definition of source is defined by
1109 // trivial computation, try rematerializing it.
1110 if (!CP.isFlipped() &&
1111 ReMaterializeTrivialDef(JoinVInt, CP.getDstReg(), 0, CopyMI))
1115 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1116 Again = true; // May be possible to coalesce later.
1121 // Okay, attempt to join these two intervals. On failure, this returns false.
1122 // Otherwise, if one of the intervals being joined is a physreg, this method
1123 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1124 // been modified, so we can use this information below to update aliases.
1125 if (!JoinIntervals(CP)) {
1126 // Coalescing failed.
1128 // If definition of source is defined by trivial computation, try
1129 // rematerializing it.
1130 if (!CP.isFlipped() &&
1131 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()),
1132 CP.getDstReg(), 0, CopyMI))
1135 // If we can eliminate the copy without merging the live ranges, do so now.
1136 if (!CP.isPartial()) {
1137 if (AdjustCopiesBackFrom(CP, CopyMI) ||
1138 RemoveCopyByCommutingDef(CP, CopyMI)) {
1139 JoinedCopies.insert(CopyMI);
1140 DEBUG(dbgs() << "\tTrivial!\n");
1145 // Otherwise, we are unable to join the intervals.
1146 DEBUG(dbgs() << "\tInterference!\n");
1147 Again = true; // May be possible to coalesce later.
1151 // Coalescing to a virtual register that is of a sub-register class of the
1152 // other. Make sure the resulting register is set to the right register class.
1153 if (CP.isCrossClass()) {
1155 mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
1158 // Remember to delete the copy instruction.
1159 JoinedCopies.insert(CopyMI);
1161 UpdateRegDefsUses(CP);
1163 // If we have extended the live range of a physical register, make sure we
1164 // update live-in lists as well.
1166 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1167 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1168 // ranges for this, and they are preserved.
1169 LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
1170 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1172 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1173 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1174 MachineBasicBlock &block = *BlockSeq[idx];
1175 if (!block.isLiveIn(CP.getDstReg()))
1176 block.addLiveIn(CP.getDstReg());
1182 // SrcReg is guarateed to be the register whose live interval that is
1184 li_->removeInterval(CP.getSrcReg());
1186 // Update regalloc hint.
1187 tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
1190 LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
1191 dbgs() << "\tJoined. Result = ";
1192 DstInt.print(dbgs(), tri_);
1200 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1201 /// compute what the resultant value numbers for each value in the input two
1202 /// ranges will be. This is complicated by copies between the two which can
1203 /// and will commonly cause multiple value numbers to be merged into one.
1205 /// VN is the value number that we're trying to resolve. InstDefiningValue
1206 /// keeps track of the new InstDefiningValue assignment for the result
1207 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1208 /// whether a value in this or other is a copy from the opposite set.
1209 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1210 /// already been assigned.
1212 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1213 /// contains the value number the copy is from.
1215 static unsigned ComputeUltimateVN(VNInfo *VNI,
1216 SmallVector<VNInfo*, 16> &NewVNInfo,
1217 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1218 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1219 SmallVector<int, 16> &ThisValNoAssignments,
1220 SmallVector<int, 16> &OtherValNoAssignments) {
1221 unsigned VN = VNI->id;
1223 // If the VN has already been computed, just return it.
1224 if (ThisValNoAssignments[VN] >= 0)
1225 return ThisValNoAssignments[VN];
1226 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1228 // If this val is not a copy from the other val, then it must be a new value
1229 // number in the destination.
1230 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1231 if (I == ThisFromOther.end()) {
1232 NewVNInfo.push_back(VNI);
1233 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1235 VNInfo *OtherValNo = I->second;
1237 // Otherwise, this *is* a copy from the RHS. If the other side has already
1238 // been computed, return it.
1239 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1240 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1242 // Mark this value number as currently being computed, then ask what the
1243 // ultimate value # of the other value is.
1244 ThisValNoAssignments[VN] = -2;
1245 unsigned UltimateVN =
1246 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1247 OtherValNoAssignments, ThisValNoAssignments);
1248 return ThisValNoAssignments[VN] = UltimateVN;
1251 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1253 bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
1254 LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
1255 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
1257 // If a live interval is a physical register, check for interference with any
1258 // aliases. The interference check implemented here is a bit more conservative
1259 // than the full interfeence check below. We allow overlapping live ranges
1260 // only when one is a copy of the other.
1262 for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){
1263 if (!li_->hasInterval(*AS))
1265 const LiveInterval &LHS = li_->getInterval(*AS);
1266 LiveInterval::const_iterator LI = LHS.begin();
1267 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1269 LI = std::lower_bound(LI, LHS.end(), RI->start);
1270 // Does LHS have an overlapping live range starting before RI?
1271 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1272 (RI->start != RI->valno->def ||
1273 !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) {
1275 dbgs() << "\t\tInterference from alias: ";
1276 LHS.print(dbgs(), tri_);
1277 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1282 // Check that LHS ranges beginning in this range are copies.
1283 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1284 if (LI->start != LI->valno->def ||
1285 !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) {
1287 dbgs() << "\t\tInterference from alias: ";
1288 LHS.print(dbgs(), tri_);
1289 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1298 // Compute the final value assignment, assuming that the live ranges can be
1300 SmallVector<int, 16> LHSValNoAssignments;
1301 SmallVector<int, 16> RHSValNoAssignments;
1302 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1303 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1304 SmallVector<VNInfo*, 16> NewVNInfo;
1306 LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
1307 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
1309 // Loop over the value numbers of the LHS, seeing if any are defined from
1311 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1314 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
1317 // Never join with a register that has EarlyClobber redefs.
1318 if (VNI->hasRedefByEC())
1321 // DstReg is known to be a register in the LHS interval. If the src is
1322 // from the RHS interval, we can use its value #.
1323 if (!CP.isCoalescable(VNI->getCopy()))
1326 // Figure out the value # from the RHS.
1327 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1328 // The copy could be to an aliased physreg.
1330 LHSValsDefinedFromRHS[VNI] = lr->valno;
1333 // Loop over the value numbers of the RHS, seeing if any are defined from
1335 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1338 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
1341 // Never join with a register that has EarlyClobber redefs.
1342 if (VNI->hasRedefByEC())
1345 // DstReg is known to be a register in the RHS interval. If the src is
1346 // from the LHS interval, we can use its value #.
1347 if (!CP.isCoalescable(VNI->getCopy()))
1350 // Figure out the value # from the LHS.
1351 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1352 // The copy could be to an aliased physreg.
1354 RHSValsDefinedFromLHS[VNI] = lr->valno;
1357 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1358 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1359 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1361 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1364 unsigned VN = VNI->id;
1365 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1367 ComputeUltimateVN(VNI, NewVNInfo,
1368 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1369 LHSValNoAssignments, RHSValNoAssignments);
1371 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1374 unsigned VN = VNI->id;
1375 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1377 // If this value number isn't a copy from the LHS, it's a new number.
1378 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1379 NewVNInfo.push_back(VNI);
1380 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1384 ComputeUltimateVN(VNI, NewVNInfo,
1385 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1386 RHSValNoAssignments, LHSValNoAssignments);
1389 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1390 // interval lists to see if these intervals are coalescable.
1391 LiveInterval::const_iterator I = LHS.begin();
1392 LiveInterval::const_iterator IE = LHS.end();
1393 LiveInterval::const_iterator J = RHS.begin();
1394 LiveInterval::const_iterator JE = RHS.end();
1396 // Skip ahead until the first place of potential sharing.
1397 if (I != IE && J != JE) {
1398 if (I->start < J->start) {
1399 I = std::upper_bound(I, IE, J->start);
1400 if (I != LHS.begin()) --I;
1401 } else if (J->start < I->start) {
1402 J = std::upper_bound(J, JE, I->start);
1403 if (J != RHS.begin()) --J;
1407 while (I != IE && J != JE) {
1408 // Determine if these two live ranges overlap.
1410 if (I->start < J->start) {
1411 Overlaps = I->end > J->start;
1413 Overlaps = J->end > I->start;
1416 // If so, check value # info to determine if they are really different.
1418 // If the live range overlap will map to the same value number in the
1419 // result liverange, we can still coalesce them. If not, we can't.
1420 if (LHSValNoAssignments[I->valno->id] !=
1421 RHSValNoAssignments[J->valno->id])
1423 // If it's re-defined by an early clobber somewhere in the live range,
1424 // then conservatively abort coalescing.
1425 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
1429 if (I->end < J->end)
1435 // Update kill info. Some live ranges are extended due to copy coalescing.
1436 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1437 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1438 VNInfo *VNI = I->first;
1439 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1440 if (VNI->hasPHIKill())
1441 NewVNInfo[LHSValID]->setHasPHIKill(true);
1444 // Update kill info. Some live ranges are extended due to copy coalescing.
1445 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1446 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1447 VNInfo *VNI = I->first;
1448 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1449 if (VNI->hasPHIKill())
1450 NewVNInfo[RHSValID]->setHasPHIKill(true);
1453 if (LHSValNoAssignments.empty())
1454 LHSValNoAssignments.push_back(-1);
1455 if (RHSValNoAssignments.empty())
1456 RHSValNoAssignments.push_back(-1);
1458 // If we get here, we know that we can coalesce the live ranges. Ask the
1459 // intervals to coalesce themselves now.
1460 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1466 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1467 // depth of the basic block (the unsigned), and then on the MBB number.
1468 struct DepthMBBCompare {
1469 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1470 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1471 // Deeper loops first
1472 if (LHS.first != RHS.first)
1473 return LHS.first > RHS.first;
1475 // Prefer blocks that are more connected in the CFG. This takes care of
1476 // the most difficult copies first while intervals are short.
1477 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1478 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1482 // As a last resort, sort by block number.
1483 return LHS.second->getNumber() < RHS.second->getNumber();
1488 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1489 std::vector<CopyRec> &TryAgain) {
1490 DEBUG(dbgs() << MBB->getName() << ":\n");
1492 std::vector<CopyRec> VirtCopies;
1493 std::vector<CopyRec> PhysCopies;
1494 std::vector<CopyRec> ImpDefCopies;
1495 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1497 MachineInstr *Inst = MII++;
1499 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1500 unsigned SrcReg, DstReg;
1501 if (Inst->isCopy()) {
1502 DstReg = Inst->getOperand(0).getReg();
1503 SrcReg = Inst->getOperand(1).getReg();
1504 } else if (Inst->isSubregToReg()) {
1505 DstReg = Inst->getOperand(0).getReg();
1506 SrcReg = Inst->getOperand(2).getReg();
1510 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1511 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1512 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1513 ImpDefCopies.push_back(CopyRec(Inst, 0));
1514 else if (SrcIsPhys || DstIsPhys)
1515 PhysCopies.push_back(CopyRec(Inst, 0));
1517 VirtCopies.push_back(CopyRec(Inst, 0));
1520 // Try coalescing implicit copies and insert_subreg <undef> first,
1521 // followed by copies to / from physical registers, then finally copies
1522 // from virtual registers to virtual registers.
1523 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1524 CopyRec &TheCopy = ImpDefCopies[i];
1526 if (!JoinCopy(TheCopy, Again))
1528 TryAgain.push_back(TheCopy);
1530 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1531 CopyRec &TheCopy = PhysCopies[i];
1533 if (!JoinCopy(TheCopy, Again))
1535 TryAgain.push_back(TheCopy);
1537 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1538 CopyRec &TheCopy = VirtCopies[i];
1540 if (!JoinCopy(TheCopy, Again))
1542 TryAgain.push_back(TheCopy);
1546 void SimpleRegisterCoalescing::joinIntervals() {
1547 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1549 std::vector<CopyRec> TryAgainList;
1550 if (loopInfo->empty()) {
1551 // If there are no loops in the function, join intervals in function order.
1552 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1554 CopyCoalesceInMBB(I, TryAgainList);
1556 // Otherwise, join intervals in inner loops before other intervals.
1557 // Unfortunately we can't just iterate over loop hierarchy here because
1558 // there may be more MBB's than BB's. Collect MBB's for sorting.
1560 // Join intervals in the function prolog first. We want to join physical
1561 // registers with virtual registers before the intervals got too long.
1562 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1563 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1564 MachineBasicBlock *MBB = I;
1565 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1568 // Sort by loop depth.
1569 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1571 // Finally, join intervals in loop nest order.
1572 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1573 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1576 // Joining intervals can allow other intervals to be joined. Iteratively join
1577 // until we make no progress.
1578 bool ProgressMade = true;
1579 while (ProgressMade) {
1580 ProgressMade = false;
1582 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1583 CopyRec &TheCopy = TryAgainList[i];
1588 bool Success = JoinCopy(TheCopy, Again);
1589 if (Success || !Again) {
1590 TheCopy.MI = 0; // Mark this one as done.
1591 ProgressMade = true;
1597 /// Return true if the two specified registers belong to different register
1598 /// classes. The registers may be either phys or virt regs.
1600 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1601 unsigned RegB) const {
1602 // Get the register classes for the first reg.
1603 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1604 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1605 "Shouldn't consider two physregs!");
1606 return !mri_->getRegClass(RegB)->contains(RegA);
1609 // Compare against the regclass for the second reg.
1610 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
1611 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
1612 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
1613 return RegClassA != RegClassB;
1615 return !RegClassA->contains(RegB);
1618 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
1619 /// between cycles Start and End or NULL if there are no uses.
1621 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
1624 SlotIndex &UseIdx) const{
1625 UseIdx = SlotIndex();
1626 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1627 MachineOperand *LastUse = NULL;
1628 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
1629 E = mri_->use_nodbg_end(); I != E; ++I) {
1630 MachineOperand &Use = I.getOperand();
1631 MachineInstr *UseMI = Use.getParent();
1632 if (UseMI->isIdentityCopy())
1634 SlotIndex Idx = li_->getInstructionIndex(UseMI);
1635 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
1636 // that compares higher than any other interval.
1637 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1639 UseIdx = Idx.getUseIndex();
1645 SlotIndex s = Start;
1646 SlotIndex e = End.getPrevSlot().getBaseIndex();
1648 // Skip deleted instructions
1649 MachineInstr *MI = li_->getInstructionFromIndex(e);
1650 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
1651 e = e.getPrevIndex();
1652 MI = li_->getInstructionFromIndex(e);
1654 if (e < s || MI == NULL)
1657 // Ignore identity copies.
1658 if (!MI->isIdentityCopy())
1659 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1660 MachineOperand &Use = MI->getOperand(i);
1661 if (Use.isReg() && Use.isUse() && Use.getReg() &&
1662 tri_->regsOverlap(Use.getReg(), Reg)) {
1663 UseIdx = e.getUseIndex();
1668 e = e.getPrevIndex();
1674 void SimpleRegisterCoalescing::releaseMemory() {
1675 JoinedCopies.clear();
1676 ReMatCopies.clear();
1680 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1682 mri_ = &fn.getRegInfo();
1683 tm_ = &fn.getTarget();
1684 tri_ = tm_->getRegisterInfo();
1685 tii_ = tm_->getInstrInfo();
1686 li_ = &getAnalysis<LiveIntervals>();
1687 AA = &getAnalysis<AliasAnalysis>();
1688 loopInfo = &getAnalysis<MachineLoopInfo>();
1690 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1691 << "********** Function: "
1692 << ((Value*)mf_->getFunction())->getName() << '\n');
1694 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
1695 E = tri_->regclass_end(); I != E; ++I)
1696 allocatableRCRegs_.insert(std::make_pair(*I,
1697 tri_->getAllocatableSet(fn, *I)));
1699 // Join (coalesce) intervals if requested.
1700 if (EnableJoining) {
1703 dbgs() << "********** INTERVALS POST JOINING **********\n";
1704 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
1706 I->second->print(dbgs(), tri_);
1712 // Perform a final pass over the instructions and compute spill weights
1713 // and remove identity moves.
1714 SmallVector<unsigned, 4> DeadDefs;
1715 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1716 mbbi != mbbe; ++mbbi) {
1717 MachineBasicBlock* mbb = mbbi;
1718 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1720 MachineInstr *MI = mii;
1721 if (JoinedCopies.count(MI)) {
1722 // Delete all coalesced copies.
1723 bool DoDelete = true;
1724 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1725 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1726 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1727 MI->getNumOperands() > 2)
1728 // Do not delete extract_subreg, insert_subreg of physical
1729 // registers unless the definition is dead. e.g.
1730 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1731 // or else the scavenger may complain. LowerSubregs will
1732 // delete them later.
1735 if (MI->allDefsAreDead()) {
1736 LiveInterval &li = li_->getInterval(SrcReg);
1737 if (!ShortenDeadCopySrcLiveRange(li, MI))
1738 ShortenDeadCopyLiveRange(li, MI);
1742 // We need the instruction to adjust liveness, so make it a KILL.
1743 if (MI->isSubregToReg()) {
1744 MI->RemoveOperand(3);
1745 MI->RemoveOperand(1);
1747 MI->setDesc(tii_->get(TargetOpcode::KILL));
1748 mii = llvm::next(mii);
1750 li_->RemoveMachineInstrFromMaps(MI);
1751 mii = mbbi->erase(mii);
1757 // Now check if this is a remat'ed def instruction which is now dead.
1758 if (ReMatDefs.count(MI)) {
1760 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1761 const MachineOperand &MO = MI->getOperand(i);
1764 unsigned Reg = MO.getReg();
1767 if (TargetRegisterInfo::isVirtualRegister(Reg))
1768 DeadDefs.push_back(Reg);
1771 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1772 !mri_->use_nodbg_empty(Reg)) {
1778 while (!DeadDefs.empty()) {
1779 unsigned DeadDef = DeadDefs.back();
1780 DeadDefs.pop_back();
1781 RemoveDeadDef(li_->getInterval(DeadDef), MI);
1783 li_->RemoveMachineInstrFromMaps(mii);
1784 mii = mbbi->erase(mii);
1790 // If the move will be an identity move delete it
1791 if (MI->isIdentityCopy()) {
1792 unsigned SrcReg = MI->getOperand(1).getReg();
1793 if (li_->hasInterval(SrcReg)) {
1794 LiveInterval &RegInt = li_->getInterval(SrcReg);
1795 // If def of this move instruction is dead, remove its live range
1796 // from the destination register's live interval.
1797 if (MI->allDefsAreDead()) {
1798 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
1799 ShortenDeadCopyLiveRange(RegInt, MI);
1802 li_->RemoveMachineInstrFromMaps(MI);
1803 mii = mbbi->erase(mii);
1810 // Check for now unnecessary kill flags.
1811 if (li_->isNotInMIMap(MI)) continue;
1812 SlotIndex DefIdx = li_->getInstructionIndex(MI).getDefIndex();
1813 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1814 MachineOperand &MO = MI->getOperand(i);
1815 if (!MO.isReg() || !MO.isKill()) continue;
1816 unsigned reg = MO.getReg();
1817 if (!reg || !li_->hasInterval(reg)) continue;
1818 if (!li_->getInterval(reg).killedAt(DefIdx))
1819 MO.setIsKill(false);
1828 /// print - Implement the dump method.
1829 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
1833 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1834 return new SimpleRegisterCoalescing();
1837 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1838 DEFINING_FILE_FOR(SimpleRegisterCoalescing)