1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
104 MachineInstr *CopyMI) {
105 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
107 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
108 // the example above.
109 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
110 assert(BLR != IntB.end() && "Live range not found!");
111 VNInfo *BValNo = BLR->valno;
113 // Get the location that B is defined at. Two options: either this value has
114 // an unknown definition point or it is defined at CopyIdx. If unknown, we
116 if (!BValNo->getCopy()) return false;
117 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
119 // AValNo is the value number in A that defines the copy, A3 in the example.
120 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
121 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
122 assert(ALR != IntA.end() && "Live range not found!");
123 VNInfo *AValNo = ALR->valno;
124 // If it's re-defined by an early clobber somewhere in the live range, then
125 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
127 // 172 %ECX<def> = MOV32rr %reg1039<kill>
128 // 180 INLINEASM <es:subl $5,$1
129 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
131 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
132 // 188 %EAX<def> = MOV32rr %EAX<kill>
133 // 196 %ECX<def> = MOV32rr %ECX<kill>
134 // 204 %ECX<def> = MOV32rr %ECX<kill>
135 // 212 %EAX<def> = MOV32rr %EAX<kill>
136 // 220 %EAX<def> = MOV32rr %EAX
137 // 228 %reg1039<def> = MOV32rr %ECX<kill>
138 // The early clobber operand ties ECX input to the ECX def.
140 // The live interval of ECX is represented as this:
141 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
142 // The coalescer has no idea there was a def in the middle of [174,230].
143 if (AValNo->hasRedefByEC())
146 // If AValNo is defined as a copy from IntB, we can potentially process this.
147 // Get the instruction that defines this value number.
148 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
149 if (!SrcReg) return false; // Not defined by a copy.
151 // If the value number is not defined by a copy instruction, ignore it.
153 // If the source register comes from an interval other than IntB, we can't
155 if (SrcReg != IntB.reg) return false;
157 // Get the LiveRange in IntB that this value number starts with.
158 LiveInterval::iterator ValLR =
159 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
160 assert(ValLR != IntB.end() && "Live range not found!");
162 // Make sure that the end of the live range is inside the same block as
164 MachineInstr *ValLREndInst =
165 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
182 dbgs() << "Interfere with sub-register ";
183 li_->getInterval(*SR).print(dbgs(), tri_);
190 dbgs() << "\nExtending: ";
191 IntB.print(dbgs(), tri_);
194 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
195 // We are about to delete CopyMI, so need to remove it as the 'instruction
196 // that defines this value #'. Update the valnum with the new defining
198 BValNo->def = FillerStart;
201 // Okay, we can merge them. We need to insert a new liverange:
202 // [ValLR.end, BLR.begin) of either value number, then we merge the
203 // two value numbers.
204 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
206 // If the IntB live range is assigned to a physical register, and if that
207 // physreg has sub-registers, update their live intervals as well.
208 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
209 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
210 LiveInterval &SRLI = li_->getInterval(*SR);
211 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
212 SRLI.getNextValue(FillerStart, 0, true,
213 li_->getVNInfoAllocator())));
217 // Okay, merge "B1" into the same value number as "B0".
218 if (BValNo != ValLR->valno) {
219 IntB.addKills(ValLR->valno, BValNo->kills);
220 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
223 dbgs() << " result = ";
224 IntB.print(dbgs(), tri_);
228 // If the source instruction was killing the source register before the
229 // merge, unset the isKill marker given the live range has been extended.
230 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
232 ValLREndInst->getOperand(UIdx).setIsKill(false);
233 ValLR->valno->removeKill(FillerStart);
236 // If the copy instruction was killing the destination register before the
237 // merge, find the last use and trim the live range. That will also add the
239 if (CopyMI->killsRegister(IntA.reg))
240 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
246 /// HasOtherReachingDefs - Return true if there are definitions of IntB
247 /// other than BValNo val# that can reach uses of AValno val# of IntA.
248 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
252 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
254 if (AI->valno != AValNo) continue;
255 LiveInterval::Ranges::iterator BI =
256 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
257 if (BI != IntB.ranges.begin())
259 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
260 if (BI->valno == BValNo)
262 if (BI->start <= AI->start && BI->end > AI->start)
264 if (BI->start > AI->start && BI->start < AI->end)
272 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
273 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
275 MachineOperand &MO = MI->getOperand(i);
276 if (MO.isReg() && MO.isImplicit())
277 NewMI->addOperand(MO);
281 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
282 /// IntA being the source and IntB being the dest, thus this defines a value
283 /// number in IntB. If the source value number (in IntA) is defined by a
284 /// commutable instruction and its other operand is coalesced to the copy dest
285 /// register, see if we can transform the copy into a noop by commuting the
286 /// definition. For example,
288 /// A3 = op A2 B0<kill>
290 /// B1 = A3 <- this copy
292 /// = op A3 <- more uses
296 /// B2 = op B0 A2<kill>
298 /// B1 = B2 <- now an identify copy
300 /// = op B2 <- more uses
302 /// This returns true if an interval was modified.
304 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
306 MachineInstr *CopyMI) {
308 li_->getInstructionIndex(CopyMI).getDefIndex();
310 // FIXME: For now, only eliminate the copy by commuting its def when the
311 // source register is a virtual register. We want to guard against cases
312 // where the copy is a back edge copy and commuting the def lengthen the
313 // live interval of the source register to the entire loop.
314 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
317 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
318 // the example above.
319 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
320 assert(BLR != IntB.end() && "Live range not found!");
321 VNInfo *BValNo = BLR->valno;
323 // Get the location that B is defined at. Two options: either this value has
324 // an unknown definition point or it is defined at CopyIdx. If unknown, we
326 if (!BValNo->getCopy()) return false;
327 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
329 // AValNo is the value number in A that defines the copy, A3 in the example.
330 LiveInterval::iterator ALR =
331 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
333 assert(ALR != IntA.end() && "Live range not found!");
334 VNInfo *AValNo = ALR->valno;
335 // If other defs can reach uses of this def, then it's not safe to perform
336 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
338 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
339 AValNo->isUnused() || AValNo->hasPHIKill())
341 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
342 const TargetInstrDesc &TID = DefMI->getDesc();
343 if (!TID.isCommutable())
345 // If DefMI is a two-address instruction then commuting it will change the
346 // destination register.
347 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
348 assert(DefIdx != -1);
350 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
352 unsigned Op1, Op2, NewDstIdx;
353 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
357 else if (Op2 == UseOpIdx)
362 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
363 unsigned NewReg = NewDstMO.getReg();
364 if (NewReg != IntB.reg || !NewDstMO.isKill())
367 // Make sure there are no other definitions of IntB that would reach the
368 // uses which the new definition can reach.
369 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
372 // If some of the uses of IntA.reg is already coalesced away, return false.
373 // It's not possible to determine whether it's safe to perform the coalescing.
374 for (MachineRegisterInfo::use_nodbg_iterator UI =
375 mri_->use_nodbg_begin(IntA.reg),
376 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
377 MachineInstr *UseMI = &*UI;
378 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
379 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
380 if (ULR == IntA.end())
382 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
386 // At this point we have decided that it is legal to do this
387 // transformation. Start by commuting the instruction.
388 MachineBasicBlock *MBB = DefMI->getParent();
389 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
392 if (NewMI != DefMI) {
393 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
394 MBB->insert(DefMI, NewMI);
397 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
398 NewMI->getOperand(OpIdx).setIsKill();
400 bool BHasPHIKill = BValNo->hasPHIKill();
401 SmallVector<VNInfo*, 4> BDeadValNos;
402 VNInfo::KillSet BKills;
403 std::map<SlotIndex, SlotIndex> BExtend;
405 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
414 // then do not add kills of A to the newly created B interval.
415 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
417 BExtend[ALR->end] = BLR->end;
419 // Update uses of IntA of the specific Val# with IntB.
420 bool BHasSubRegs = false;
421 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
422 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
423 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
424 UE = mri_->use_end(); UI != UE;) {
425 MachineOperand &UseMO = UI.getOperand();
426 MachineInstr *UseMI = &*UI;
428 if (JoinedCopies.count(UseMI))
430 if (UseMI->isDebugValue()) {
431 // FIXME These don't have an instruction index. Not clear we have enough
432 // info to decide whether to do this replacement or not. For now do it.
433 UseMO.setReg(NewReg);
436 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
437 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
438 if (ULR == IntA.end() || ULR->valno != AValNo)
440 UseMO.setReg(NewReg);
443 if (UseMO.isKill()) {
445 UseMO.setIsKill(false);
447 BKills.push_back(UseIdx.getDefIndex());
449 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
450 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
452 if (DstReg == IntB.reg) {
453 // This copy will become a noop. If it's defining a new val#,
454 // remove that val# as well. However this live range is being
455 // extended to the end of the existing live range defined by the copy.
456 SlotIndex DefIdx = UseIdx.getDefIndex();
457 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
458 BHasPHIKill |= DLR->valno->hasPHIKill();
459 assert(DLR->valno->def == DefIdx);
460 BDeadValNos.push_back(DLR->valno);
461 BExtend[DLR->start] = DLR->end;
462 JoinedCopies.insert(UseMI);
463 // If this is a kill but it's going to be removed, the last use
464 // of the same val# is the new kill.
470 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
471 // simply extend BLR if CopyMI doesn't end the range.
473 dbgs() << "\nExtending: ";
474 IntB.print(dbgs(), tri_);
477 // Remove val#'s defined by copies that will be coalesced away.
478 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
479 VNInfo *DeadVNI = BDeadValNos[i];
481 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
482 LiveInterval &SRLI = li_->getInterval(*SR);
483 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
484 SRLI.removeValNo(SRLR->valno);
487 IntB.removeValNo(BDeadValNos[i]);
490 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
491 // is updated. Kills are also updated.
492 VNInfo *ValNo = BValNo;
493 ValNo->def = AValNo->def;
495 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
496 if (ValNo->kills[j] != BLR->end)
497 BKills.push_back(ValNo->kills[j]);
499 ValNo->kills.clear();
500 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
502 if (AI->valno != AValNo) continue;
503 SlotIndex End = AI->end;
504 std::map<SlotIndex, SlotIndex>::iterator
505 EI = BExtend.find(End);
506 if (EI != BExtend.end())
508 IntB.addRange(LiveRange(AI->start, End, ValNo));
510 // If the IntB live range is assigned to a physical register, and if that
511 // physreg has sub-registers, update their live intervals as well.
513 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
514 LiveInterval &SRLI = li_->getInterval(*SR);
515 SRLI.MergeInClobberRange(*li_, AI->start, End,
516 li_->getVNInfoAllocator());
520 IntB.addKills(ValNo, BKills);
521 ValNo->setHasPHIKill(BHasPHIKill);
524 dbgs() << " result = ";
525 IntB.print(dbgs(), tri_);
527 dbgs() << "\nShortening: ";
528 IntA.print(dbgs(), tri_);
531 IntA.removeValNo(AValNo);
534 dbgs() << " result = ";
535 IntA.print(dbgs(), tri_);
543 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
544 /// fallthoughs to SuccMBB.
545 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
546 MachineBasicBlock *SuccMBB,
547 const TargetInstrInfo *tii_) {
550 MachineBasicBlock *TBB = 0, *FBB = 0;
551 SmallVector<MachineOperand, 4> Cond;
552 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
553 MBB->isSuccessor(SuccMBB);
556 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
557 /// from a physical register live interval as well as from the live intervals
558 /// of its sub-registers.
559 static void removeRange(LiveInterval &li,
560 SlotIndex Start, SlotIndex End,
561 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
562 li.removeRange(Start, End, true);
563 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
564 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
565 if (!li_->hasInterval(*SR))
567 LiveInterval &sli = li_->getInterval(*SR);
568 SlotIndex RemoveStart = Start;
569 SlotIndex RemoveEnd = Start;
571 while (RemoveEnd != End) {
572 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
575 RemoveEnd = (LR->end < End) ? LR->end : End;
576 sli.removeRange(RemoveStart, RemoveEnd, true);
577 RemoveStart = RemoveEnd;
583 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
584 /// as the copy instruction, trim the live interval to the last use and return
587 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
588 MachineBasicBlock *CopyMBB,
590 const LiveRange *LR) {
591 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
592 SlotIndex LastUseIdx;
593 MachineOperand *LastUse =
594 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
596 MachineInstr *LastUseMI = LastUse->getParent();
597 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
604 // r1025<dead> = r1024<kill>
605 if (MBBStart < LR->end)
606 removeRange(li, MBBStart, LR->end, li_, tri_);
610 // There are uses before the copy, just shorten the live range to the end
612 LastUse->setIsKill();
613 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
614 LR->valno->addKill(LastUseIdx.getDefIndex());
615 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
616 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
618 // Last use is itself an identity code.
619 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
620 LastUseMI->getOperand(DeadIdx).setIsDead();
626 if (LR->start <= MBBStart && LR->end > MBBStart) {
627 if (LR->start == li_->getZeroIndex()) {
628 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
629 // Live-in to the function but dead. Remove it from entry live-in set.
630 mf_->begin()->removeLiveIn(li.reg);
632 // FIXME: Shorten intervals in BBs that reaches this BB.
638 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
639 /// computation, replace the copy by rematerialize the definition.
640 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
643 MachineInstr *CopyMI) {
644 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
645 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
646 assert(SrcLR != SrcInt.end() && "Live range not found!");
647 VNInfo *ValNo = SrcLR->valno;
648 // If other defs can reach uses of this def, then it's not safe to perform
649 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
651 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
652 ValNo->isUnused() || ValNo->hasPHIKill())
654 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
655 const TargetInstrDesc &TID = DefMI->getDesc();
656 if (!TID.isAsCheapAsAMove())
658 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
660 bool SawStore = false;
661 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
663 if (TID.getNumDefs() != 1)
665 if (!DefMI->isImplicitDef()) {
666 // Make sure the copy destination register class fits the instruction
667 // definition register class. The mismatch can happen as a result of earlier
668 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
669 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
670 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
671 if (mri_->getRegClass(DstReg) != RC)
673 } else if (!RC->contains(DstReg))
677 // If destination register has a sub-register index on it, make sure it mtches
678 // the instruction register class.
680 const TargetInstrDesc &TID = DefMI->getDesc();
681 if (TID.getNumDefs() != 1)
683 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
684 const TargetRegisterClass *DstSubRC =
685 DstRC->getSubRegisterRegClass(DstSubIdx);
686 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
689 else if (DefRC != DstSubRC)
693 SlotIndex DefIdx = CopyIdx.getDefIndex();
694 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
695 DLR->valno->setCopy(0);
696 // Don't forget to update sub-register intervals.
697 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
698 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
699 if (!li_->hasInterval(*SR))
701 const LiveRange *DLR =
702 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
703 if (DLR && DLR->valno->getCopy() == CopyMI)
704 DLR->valno->setCopy(0);
708 // If copy kills the source register, find the last use and propagate
710 bool checkForDeadDef = false;
711 MachineBasicBlock *MBB = CopyMI->getParent();
712 if (CopyMI->killsRegister(SrcInt.reg))
713 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
714 checkForDeadDef = true;
717 MachineBasicBlock::iterator MII =
718 llvm::next(MachineBasicBlock::iterator(CopyMI));
719 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
720 MachineInstr *NewMI = prior(MII);
722 if (checkForDeadDef) {
723 // PR4090 fix: Trim interval failed because there was no use of the
724 // source interval in this MBB. If the def is in this MBB too then we
725 // should mark it dead:
726 if (DefMI->getParent() == MBB) {
727 DefMI->addRegisterDead(SrcInt.reg, tri_);
728 SrcLR->end = SrcLR->start.getNextSlot();
732 // CopyMI may have implicit operands, transfer them over to the newly
733 // rematerialized instruction. And update implicit def interval valnos.
734 for (unsigned i = CopyMI->getDesc().getNumOperands(),
735 e = CopyMI->getNumOperands(); i != e; ++i) {
736 MachineOperand &MO = CopyMI->getOperand(i);
737 if (MO.isReg() && MO.isImplicit())
738 NewMI->addOperand(MO);
739 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
740 unsigned Reg = MO.getReg();
741 const LiveRange *DLR =
742 li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
743 if (DLR && DLR->valno->getCopy() == CopyMI)
744 DLR->valno->setCopy(0);
745 // Handle subregs as well
746 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
747 for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) {
748 if (!li_->hasInterval(*SR))
750 const LiveRange *DLR =
751 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
752 if (DLR && DLR->valno->getCopy() == CopyMI)
753 DLR->valno->setCopy(0);
759 TransferImplicitOps(CopyMI, NewMI);
760 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
761 CopyMI->eraseFromParent();
762 ReMatCopies.insert(CopyMI);
763 ReMatDefs.insert(DefMI);
764 DEBUG(dbgs() << "Remat: " << *NewMI);
769 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
770 /// update the subregister number if it is not zero. If DstReg is a
771 /// physical register and the existing subregister number of the def / use
772 /// being updated is not zero, make sure to set it to the correct physical
775 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
777 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
778 if (DstIsPhys && SubIdx) {
779 // Figure out the real physical register we are updating with.
780 DstReg = tri_->getSubReg(DstReg, SubIdx);
784 // Copy the register use-list before traversing it. We may be adding operands
785 // and invalidating pointers.
786 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
787 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
788 E = mri_->reg_end(); I != E; ++I)
789 reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
791 for (unsigned N=0; N != reglist.size(); ++N) {
792 MachineInstr *UseMI = reglist[N].first;
793 MachineOperand &O = UseMI->getOperand(reglist[N].second);
794 unsigned OldSubIdx = O.getSubReg();
796 unsigned UseDstReg = DstReg;
798 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
800 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
801 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
802 CopySrcSubIdx, CopyDstSubIdx) &&
803 CopySrcReg != CopyDstReg &&
804 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
805 // If the use is a copy and it won't be coalesced away, and its source
806 // is defined by a trivial computation, try to rematerialize it instead.
807 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
808 CopyDstSubIdx, UseMI))
815 // Def and kill of subregister of a virtual register actually defs and
816 // kills the whole register. Add imp-defs and imp-kills as needed.
819 UseMI->addRegisterDead(DstReg, tri_, true);
821 UseMI->addRegisterDefined(DstReg, tri_);
822 } else if (!O.isUndef() &&
824 UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0))))
825 UseMI->addRegisterKilled(DstReg, tri_, true);
830 // Sub-register indexes goes from small to large. e.g.
831 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
832 // EAX: 1 -> AL, 2 -> AX
833 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
834 // sub-register 2 is also AX.
835 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
836 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
839 // Remove would-be duplicated kill marker.
840 if (O.isKill() && UseMI->killsRegister(DstReg))
844 // After updating the operand, check if the machine instruction has
845 // become a copy. If so, update its val# information.
846 if (JoinedCopies.count(UseMI))
849 const TargetInstrDesc &TID = UseMI->getDesc();
850 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
851 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
852 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
853 CopySrcSubIdx, CopyDstSubIdx) &&
854 CopySrcReg != CopyDstReg &&
855 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
856 allocatableRegs_[CopyDstReg])) {
857 LiveInterval &LI = li_->getInterval(CopyDstReg);
859 li_->getInstructionIndex(UseMI).getDefIndex();
860 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
861 if (DLR->valno->def == DefIdx)
862 DLR->valno->setCopy(UseMI);
868 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
869 /// due to live range lengthening as the result of coalescing.
870 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
872 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
873 UE = mri_->use_end(); UI != UE; ++UI) {
874 MachineOperand &UseMO = UI.getOperand();
877 MachineInstr *UseMI = UseMO.getParent();
879 li_->getInstructionIndex(UseMI).getUseIndex();
880 const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
882 (!LR->valno->isKill(UseIdx.getDefIndex()) &&
883 LR->valno->def != UseIdx.getDefIndex())) {
884 // Interesting problem. After coalescing reg1027's def and kill are both
885 // at the same point: %reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
888 // 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
889 // 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
890 // 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
891 // 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
892 // 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
894 // Do not remove the kill marker on t2LDRi12.
895 UseMO.setIsKill(false);
900 /// removeIntervalIfEmpty - Check if the live interval of a physical register
901 /// is empty, if so remove it and also remove the empty intervals of its
902 /// sub-registers. Return true if live interval is removed.
903 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
904 const TargetRegisterInfo *tri_) {
906 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
907 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
908 if (!li_->hasInterval(*SR))
910 LiveInterval &sli = li_->getInterval(*SR);
912 li_->removeInterval(*SR);
914 li_->removeInterval(li.reg);
920 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
921 /// Return true if live interval is removed.
922 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
923 MachineInstr *CopyMI) {
924 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
925 LiveInterval::iterator MLR =
926 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
928 return false; // Already removed by ShortenDeadCopySrcLiveRange.
929 SlotIndex RemoveStart = MLR->start;
930 SlotIndex RemoveEnd = MLR->end;
931 SlotIndex DefIdx = CopyIdx.getDefIndex();
932 // Remove the liverange that's defined by this.
933 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
934 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
935 return removeIntervalIfEmpty(li, li_, tri_);
940 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
941 /// the val# it defines. If the live interval becomes empty, remove it as well.
942 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
943 MachineInstr *DefMI) {
944 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
945 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
946 if (DefIdx != MLR->valno->def)
948 li.removeValNo(MLR->valno);
949 return removeIntervalIfEmpty(li, li_, tri_);
952 /// PropagateDeadness - Propagate the dead marker to the instruction which
953 /// defines the val#.
954 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
955 SlotIndex &LRStart, LiveIntervals *li_,
956 const TargetRegisterInfo* tri_) {
957 MachineInstr *DefMI =
958 li_->getInstructionFromIndex(LRStart.getDefIndex());
959 if (DefMI && DefMI != CopyMI) {
960 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false);
962 DefMI->getOperand(DeadIdx).setIsDead();
964 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
965 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
966 LRStart = LRStart.getNextSlot();
970 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
971 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
972 /// ends the live range there. If there isn't another use, then this live range
973 /// is dead. Return true if live interval is removed.
975 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
976 MachineInstr *CopyMI) {
977 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
978 if (CopyIdx == SlotIndex()) {
979 // FIXME: special case: function live in. It can be a general case if the
980 // first instruction index starts at > 0 value.
981 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
982 // Live-in to the function but dead. Remove it from entry live-in set.
983 if (mf_->begin()->isLiveIn(li.reg))
984 mf_->begin()->removeLiveIn(li.reg);
985 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
986 removeRange(li, LR->start, LR->end, li_, tri_);
987 return removeIntervalIfEmpty(li, li_, tri_);
990 LiveInterval::iterator LR =
991 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
993 // Livein but defined by a phi.
996 SlotIndex RemoveStart = LR->start;
997 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
998 if (LR->end > RemoveEnd)
999 // More uses past this copy? Nothing to do.
1002 // If there is a last use in the same bb, we can't remove the live range.
1003 // Shorten the live interval and return.
1004 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1005 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
1008 // There are other kills of the val#. Nothing to do.
1009 if (!li.isOnlyLROfValNo(LR))
1012 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
1013 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
1014 // If the live range starts in another mbb and the copy mbb is not a fall
1015 // through mbb, then we can only cut the range from the beginning of the
1017 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
1019 if (LR->valno->def == RemoveStart) {
1020 // If the def MI defines the val# and this copy is the only kill of the
1021 // val#, then propagate the dead marker.
1022 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
1025 if (LR->valno->isKill(RemoveEnd))
1026 LR->valno->removeKill(RemoveEnd);
1029 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
1030 return removeIntervalIfEmpty(li, li_, tri_);
1033 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
1034 /// from an implicit def to another register can be coalesced away.
1035 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
1037 LiveInterval &ImpLi) const{
1038 if (!CopyMI->killsRegister(ImpLi.reg))
1040 // Make sure this is the only use.
1041 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
1042 UE = mri_->use_end(); UI != UE;) {
1043 MachineInstr *UseMI = &*UI;
1045 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
1053 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1054 /// a virtual destination register with physical source register.
1056 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1057 MachineBasicBlock *CopyMBB,
1058 LiveInterval &DstInt,
1059 LiveInterval &SrcInt) {
1060 // If the virtual register live interval is long but it has low use desity,
1061 // do not join them, instead mark the physical register as its allocation
1063 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1064 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1065 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1066 if (Length > Threshold &&
1067 (((float)std::distance(mri_->use_nodbg_begin(DstInt.reg),
1068 mri_->use_nodbg_end()) / Length) <
1072 // If the virtual register live interval extends into a loop, turn down
1075 li_->getInstructionIndex(CopyMI).getDefIndex();
1076 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1078 // Let's see if the virtual register live interval extends into the loop.
1079 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1080 assert(DLR != DstInt.end() && "Live range not found!");
1081 DLR = DstInt.FindLiveRangeContaining(DLR->end.getNextSlot());
1082 if (DLR != DstInt.end()) {
1083 CopyMBB = li_->getMBBFromIndex(DLR->start);
1084 L = loopInfo->getLoopFor(CopyMBB);
1088 if (!L || Length <= Threshold)
1091 SlotIndex UseIdx = CopyIdx.getUseIndex();
1092 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1093 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1094 if (loopInfo->getLoopFor(SMBB) != L) {
1095 if (!loopInfo->isLoopHeader(CopyMBB))
1097 // If vr's live interval extends pass the loop header, do not join.
1098 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1099 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1100 MachineBasicBlock *SuccMBB = *SI;
1101 if (SuccMBB == CopyMBB)
1103 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1104 li_->getMBBEndIdx(SuccMBB)))
1111 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1112 /// copy from a virtual source register to a physical destination register.
1114 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1115 MachineBasicBlock *CopyMBB,
1116 LiveInterval &DstInt,
1117 LiveInterval &SrcInt) {
1118 // If the virtual register live interval is long but it has low use density,
1119 // do not join them, instead mark the physical register as its allocation
1121 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1122 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1123 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1124 if (Length > Threshold &&
1125 (((float)std::distance(mri_->use_nodbg_begin(SrcInt.reg),
1126 mri_->use_nodbg_end()) / Length) <
1131 // Must be implicit_def.
1134 // If the virtual register live interval is defined or cross a loop, turn
1135 // down aggressiveness.
1137 li_->getInstructionIndex(CopyMI).getDefIndex();
1138 SlotIndex UseIdx = CopyIdx.getUseIndex();
1139 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1140 assert(SLR != SrcInt.end() && "Live range not found!");
1141 SLR = SrcInt.FindLiveRangeContaining(SLR->start.getPrevSlot());
1142 if (SLR == SrcInt.end())
1144 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1145 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1147 if (!L || Length <= Threshold)
1150 if (loopInfo->getLoopFor(CopyMBB) != L) {
1151 if (SMBB != L->getLoopLatch())
1153 // If vr's live interval is extended from before the loop latch, do not
1155 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1156 PE = SMBB->pred_end(); PI != PE; ++PI) {
1157 MachineBasicBlock *PredMBB = *PI;
1158 if (PredMBB == SMBB)
1160 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1161 li_->getMBBEndIdx(PredMBB)))
1168 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1169 /// two virtual registers from different register classes.
1171 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
1173 unsigned Threshold) {
1174 // Then make sure the intervals are *short*.
1175 LiveInterval &LargeInt = li_->getInterval(LargeReg);
1176 LiveInterval &SmallInt = li_->getInterval(SmallReg);
1177 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
1178 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
1179 if (LargeSize > Threshold) {
1180 unsigned SmallUses = std::distance(mri_->use_nodbg_begin(SmallReg),
1181 mri_->use_nodbg_end());
1182 unsigned LargeUses = std::distance(mri_->use_nodbg_begin(LargeReg),
1183 mri_->use_nodbg_end());
1184 if (SmallUses*LargeSize < LargeUses*SmallSize)
1190 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1191 /// register with a physical register, check if any of the virtual register
1192 /// operand is a sub-register use or def. If so, make sure it won't result
1193 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1194 /// vr1024 = extract_subreg vr1025, 1
1196 /// vr1024 = mov8rr AH
1197 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1198 /// AH does not have a super-reg whose sub-register 1 is AH.
1200 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1203 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1204 E = mri_->reg_end(); I != E; ++I) {
1205 MachineOperand &O = I.getOperand();
1208 MachineInstr *MI = &*I;
1209 if (MI == CopyMI || JoinedCopies.count(MI))
1211 unsigned SubIdx = O.getSubReg();
1212 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1214 if (MI->isExtractSubreg()) {
1215 SubIdx = MI->getOperand(2).getImm();
1216 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1219 unsigned SrcReg = MI->getOperand(1).getReg();
1220 const TargetRegisterClass *RC =
1221 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1222 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1223 : mri_->getRegClass(SrcReg);
1224 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1228 if (MI->isInsertSubreg() || MI->isSubregToReg()) {
1229 SubIdx = MI->getOperand(3).getImm();
1230 if (VirtReg == MI->getOperand(0).getReg()) {
1231 if (!tri_->getSubReg(PhysReg, SubIdx))
1234 unsigned DstReg = MI->getOperand(0).getReg();
1235 const TargetRegisterClass *RC =
1236 TargetRegisterInfo::isPhysicalRegister(DstReg)
1237 ? tri_->getPhysicalRegisterRegClass(DstReg)
1238 : mri_->getRegClass(DstReg);
1239 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1248 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1249 /// an extract_subreg where dst is a physical register, e.g.
1250 /// cl = EXTRACT_SUBREG reg1024, 1
1252 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1253 unsigned SrcReg, unsigned SubIdx,
1254 unsigned &RealDstReg) {
1255 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1256 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1257 assert(RealDstReg && "Invalid extract_subreg instruction!");
1259 LiveInterval &RHS = li_->getInterval(SrcReg);
1260 // For this type of EXTRACT_SUBREG, conservatively
1261 // check if the live interval of the source register interfere with the
1262 // actual super physical register we are trying to coalesce with.
1263 if (li_->hasInterval(RealDstReg) &&
1264 RHS.overlaps(li_->getInterval(RealDstReg))) {
1266 dbgs() << "Interfere with register ";
1267 li_->getInterval(RealDstReg).print(dbgs(), tri_);
1269 return false; // Not coalescable
1271 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1272 // Do not check DstReg or its sub-register. JoinIntervals() will take care
1274 if (*SR != DstReg &&
1275 !tri_->isSubRegister(DstReg, *SR) &&
1276 li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1278 dbgs() << "Interfere with sub-register ";
1279 li_->getInterval(*SR).print(dbgs(), tri_);
1281 return false; // Not coalescable
1286 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1287 /// an insert_subreg where src is a physical register, e.g.
1288 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1290 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1291 unsigned SrcReg, unsigned SubIdx,
1292 unsigned &RealSrcReg) {
1293 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1294 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1295 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1297 LiveInterval &LHS = li_->getInterval(DstReg);
1298 if (li_->hasInterval(RealSrcReg) &&
1299 LHS.overlaps(li_->getInterval(RealSrcReg))) {
1301 dbgs() << "Interfere with register ";
1302 li_->getInterval(RealSrcReg).print(dbgs(), tri_);
1304 return false; // Not coalescable
1306 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1307 // Do not check SrcReg or its sub-register. JoinIntervals() will take care
1309 if (*SR != SrcReg &&
1310 !tri_->isSubRegister(SrcReg, *SR) &&
1311 li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1313 dbgs() << "Interfere with sub-register ";
1314 li_->getInterval(*SR).print(dbgs(), tri_);
1316 return false; // Not coalescable
1321 /// getRegAllocPreference - Return register allocation preference register.
1323 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1324 MachineRegisterInfo *MRI,
1325 const TargetRegisterInfo *TRI) {
1326 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1328 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1329 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1332 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1333 /// which are the src/dst of the copy instruction CopyMI. This returns true
1334 /// if the copy was successfully coalesced away. If it is not currently
1335 /// possible to coalesce this interval, but it may be possible if other
1336 /// things get coalesced, then it returns true by reference in 'Again'.
1337 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1338 MachineInstr *CopyMI = TheCopy.MI;
1341 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1342 return false; // Already done.
1344 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1346 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1347 bool isExtSubReg = CopyMI->isExtractSubreg();
1348 bool isInsSubReg = CopyMI->isInsertSubreg();
1349 bool isSubRegToReg = CopyMI->isSubregToReg();
1350 unsigned SubIdx = 0;
1352 DstReg = CopyMI->getOperand(0).getReg();
1353 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1354 SrcReg = CopyMI->getOperand(1).getReg();
1355 SrcSubIdx = CopyMI->getOperand(2).getImm();
1356 } else if (isInsSubReg || isSubRegToReg) {
1357 DstReg = CopyMI->getOperand(0).getReg();
1358 DstSubIdx = CopyMI->getOperand(3).getImm();
1359 SrcReg = CopyMI->getOperand(2).getReg();
1360 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1361 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1362 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1363 // coalesced to a larger register so the subreg indices cancel out.
1364 DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
1365 "coalesced to another register.\n");
1366 return false; // Not coalescable.
1368 } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1369 if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
1370 // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
1372 return false; // Not coalescable.
1375 llvm_unreachable("Unrecognized copy instruction!");
1378 // If they are already joined we continue.
1379 if (SrcReg == DstReg) {
1380 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1381 return false; // Not coalescable.
1384 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1385 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1387 // If they are both physical registers, we cannot join them.
1388 if (SrcIsPhys && DstIsPhys) {
1389 DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
1390 return false; // Not coalescable.
1393 // We only join virtual registers with allocatable physical registers.
1394 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1395 DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
1396 return false; // Not coalescable.
1398 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1399 DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
1400 return false; // Not coalescable.
1403 // Check that a physical source register is compatible with dst regclass
1405 unsigned SrcSubReg = SrcSubIdx ?
1406 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1407 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1408 const TargetRegisterClass *DstSubRC = DstRC;
1410 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1411 assert(DstSubRC && "Illegal subregister index");
1412 if (!DstSubRC->contains(SrcSubReg)) {
1413 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1414 << tri_->getName(SrcSubReg) << " not in "
1415 << DstSubRC->getName() << ".\n");
1416 return false; // Not coalescable.
1420 // Check that a physical dst register is compatible with source regclass
1422 unsigned DstSubReg = DstSubIdx ?
1423 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1424 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1425 const TargetRegisterClass *SrcSubRC = SrcRC;
1427 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1428 assert(SrcSubRC && "Illegal subregister index");
1429 if (!SrcSubRC->contains(DstSubReg)) {
1430 DEBUG(dbgs() << "\tIncompatible source regclass: "
1431 << tri_->getName(DstSubReg) << " not in "
1432 << SrcSubRC->getName() << ".\n");
1434 return false; // Not coalescable.
1438 // Should be non-null only when coalescing to a sub-register class.
1439 bool CrossRC = false;
1440 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1441 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1442 const TargetRegisterClass *NewRC = NULL;
1443 unsigned RealDstReg = 0;
1444 unsigned RealSrcReg = 0;
1445 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1446 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1447 if (SrcIsPhys && isExtSubReg) {
1448 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1449 // coalesced with AX.
1450 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1452 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1453 // coalesced to a larger register so the subreg indices cancel out.
1454 if (DstSubIdx != SubIdx) {
1455 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1456 return false; // Not coalescable.
1459 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1461 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1462 // EAX = INSERT_SUBREG EAX, r1024, 0
1463 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1465 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1466 // coalesced to a larger register so the subreg indices cancel out.
1467 if (SrcSubIdx != SubIdx) {
1468 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1469 return false; // Not coalescable.
1472 DstReg = tri_->getSubReg(DstReg, SubIdx);
1474 } else if ((DstIsPhys && isExtSubReg) ||
1475 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1476 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1477 DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
1478 << " of a super-class.\n");
1479 return false; // Not coalescable.
1482 // FIXME: The following checks are somewhat conservative. Perhaps a better
1483 // way to implement this is to treat this as coalescing a vr with the
1484 // super physical register.
1486 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1487 return false; // Not coalescable
1489 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1490 return false; // Not coalescable
1494 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1495 : CopyMI->getOperand(2).getSubReg();
1497 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1498 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1499 // coalesced to a larger register so the subreg indices cancel out.
1500 // Also check if the other larger register is of the same register
1501 // class as the would be resulting register.
1504 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1505 return false; // Not coalescable.
1509 if (!DstIsPhys && !SrcIsPhys) {
1510 if (isInsSubReg || isSubRegToReg) {
1511 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1512 } else // extract_subreg {
1513 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1516 DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
1517 return false; // Not coalescable
1520 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1521 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1522 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1523 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1524 Again = true; // May be possible to coalesce later.
1529 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1530 if (DisableCrossClassJoin)
1534 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1535 // with another? If it's the resulting destination register, then
1536 // the subidx must be propagated to uses (but only those defined
1537 // by the EXTRACT_SUBREG). If it's being coalesced into another
1538 // register, it should be safe because register is assumed to have
1539 // the register class of the super-register.
1541 // Process moves where one of the registers have a sub-register index.
1542 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1543 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1544 SubIdx = DstMO->getSubReg();
1546 if (SrcMO->getSubReg())
1547 // FIXME: can we handle this?
1549 // This is not an insert_subreg but it looks like one.
1550 // e.g. %reg1024:4 = MOV32rr %EAX
1553 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1554 return false; // Not coalescable
1558 SubIdx = SrcMO->getSubReg();
1560 // This is not a extract_subreg but it looks like one.
1561 // e.g. %cl = MOV16rr %reg1024:1
1564 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1565 return false; // Not coalescable
1571 unsigned LargeReg = SrcReg;
1572 unsigned SmallReg = DstReg;
1574 // Now determine the register class of the joined register.
1576 if (SubIdx && DstRC && DstRC->isASubClass()) {
1577 // This is a move to a sub-register class. However, the source is a
1578 // sub-register of a larger register class. We don't know what should
1579 // the register class be. FIXME.
1583 if (!DstIsPhys && !SrcIsPhys)
1585 } else if (!SrcIsPhys && !DstIsPhys) {
1586 NewRC = getCommonSubClass(SrcRC, DstRC);
1588 DEBUG(dbgs() << "\tDisjoint regclasses: "
1589 << SrcRC->getName() << ", "
1590 << DstRC->getName() << ".\n");
1591 return false; // Not coalescable.
1593 if (DstRC->getSize() > SrcRC->getSize())
1594 std::swap(LargeReg, SmallReg);
1597 // If we are joining two virtual registers and the resulting register
1598 // class is more restrictive (fewer register, smaller size). Check if it's
1599 // worth doing the merge.
1600 if (!SrcIsPhys && !DstIsPhys &&
1601 (isExtSubReg || DstRC->isASubClass()) &&
1602 !isWinToJoinCrossClass(LargeReg, SmallReg,
1603 allocatableRCRegs_[NewRC].count())) {
1604 DEBUG(dbgs() << "\tSrc/Dest are different register classes: "
1605 << SrcRC->getName() << "/"
1606 << DstRC->getName() << " -> "
1607 << NewRC->getName() << ".\n");
1608 // Allow the coalescer to try again in case either side gets coalesced to
1609 // a physical register that's compatible with the other side. e.g.
1610 // r1024 = MOV32to32_ r1025
1611 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1612 Again = true; // May be possible to coalesce later.
1617 // Will it create illegal extract_subreg / insert_subreg?
1618 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1620 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1623 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1624 LiveInterval &DstInt = li_->getInterval(DstReg);
1625 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1626 "Register mapping is horribly broken!");
1629 dbgs() << "\t\tInspecting "; SrcInt.print(dbgs(), tri_);
1630 dbgs() << " and "; DstInt.print(dbgs(), tri_);
1634 // Save a copy of the virtual register live interval. We'll manually
1635 // merge this into the "real" physical register live interval this is
1637 OwningPtr<LiveInterval> SavedLI;
1639 SavedLI.reset(li_->dupInterval(&SrcInt));
1640 else if (RealSrcReg)
1641 SavedLI.reset(li_->dupInterval(&DstInt));
1643 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1644 // Check if it is necessary to propagate "isDead" property.
1645 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1646 bool isDead = mopd->isDead();
1648 // We need to be careful about coalescing a source physical register with a
1649 // virtual register. Once the coalescing is done, it cannot be broken and
1650 // these are not spillable! If the destination interval uses are far away,
1651 // think twice about coalescing them!
1652 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1653 // If the virtual register live interval is long but it has low use
1654 // density, do not join them, instead mark the physical register as its
1655 // allocation preference.
1656 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1657 LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
1658 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1659 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1661 // Don't join with physregs that have a ridiculous number of live
1662 // ranges. The data structure performance is really bad when that
1664 if (JoinPInt.ranges.size() > 1000) {
1665 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1668 << "\tPhysical register live interval too complicated, abort!\n");
1672 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1673 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1674 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1675 float Ratio = 1.0 / Threshold;
1676 if (Length > Threshold &&
1677 (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
1678 mri_->use_nodbg_end()) / Length) < Ratio)) {
1679 // Before giving up coalescing, if definition of source is defined by
1680 // trivial computation, try rematerializing it.
1681 if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1684 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1686 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1687 Again = true; // May be possible to coalesce later.
1693 // Okay, attempt to join these two intervals. On failure, this returns false.
1694 // Otherwise, if one of the intervals being joined is a physreg, this method
1695 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1696 // been modified, so we can use this information below to update aliases.
1697 bool Swapped = false;
1698 // If SrcInt is implicitly defined, it's safe to coalesce.
1699 if (SrcInt.empty()) {
1700 if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1701 // Only coalesce an empty interval (defined by implicit_def) with
1702 // another interval which has a valno defined by the CopyMI and the CopyMI
1703 // is a kill of the implicit def.
1704 DEBUG(dbgs() << "Not profitable!\n");
1707 } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) {
1708 // Coalescing failed.
1710 // If definition of source is defined by trivial computation, try
1711 // rematerializing it.
1712 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1713 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1716 // If we can eliminate the copy without merging the live ranges, do so now.
1717 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1718 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1719 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1720 JoinedCopies.insert(CopyMI);
1721 DEBUG(dbgs() << "Trivial!\n");
1725 // Otherwise, we are unable to join the intervals.
1726 DEBUG(dbgs() << "Interference!\n");
1727 Again = true; // May be possible to coalesce later.
1731 LiveInterval *ResSrcInt = &SrcInt;
1732 LiveInterval *ResDstInt = &DstInt;
1734 std::swap(SrcReg, DstReg);
1735 std::swap(ResSrcInt, ResDstInt);
1737 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1738 "LiveInterval::join didn't work right!");
1740 // If we're about to merge live ranges into a physical register live interval,
1741 // we have to update any aliased register's live ranges to indicate that they
1742 // have clobbered values for this range.
1743 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1744 // If this is a extract_subreg where dst is a physical register, e.g.
1745 // cl = EXTRACT_SUBREG reg1024, 1
1746 // then create and update the actual physical register allocated to RHS.
1747 if (RealDstReg || RealSrcReg) {
1748 LiveInterval &RealInt =
1749 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1750 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1751 E = SavedLI->vni_end(); I != E; ++I) {
1752 const VNInfo *ValNo = *I;
1753 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
1754 false, // updated at *
1755 li_->getVNInfoAllocator());
1756 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1757 RealInt.addKills(NewValNo, ValNo->kills);
1758 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1760 RealInt.weight += SavedLI->weight;
1761 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1764 // Update the liveintervals of sub-registers.
1765 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1766 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
1767 li_->getVNInfoAllocator());
1770 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1771 // larger super-register.
1772 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1773 !SrcIsPhys && !DstIsPhys) {
1774 if ((isExtSubReg && !Swapped) ||
1775 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1776 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1777 std::swap(SrcReg, DstReg);
1778 std::swap(ResSrcInt, ResDstInt);
1782 // Coalescing to a virtual register that is of a sub-register class of the
1783 // other. Make sure the resulting register is set to the right register class.
1787 // This may happen even if it's cross-rc coalescing. e.g.
1788 // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
1789 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1790 // be allocate a register from GR64_ABCD.
1792 mri_->setRegClass(DstReg, NewRC);
1794 // Remember to delete the copy instruction.
1795 JoinedCopies.insert(CopyMI);
1797 // Some live range has been lengthened due to colaescing, eliminate the
1798 // unnecessary kills.
1799 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1800 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1801 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1803 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1805 // If we have extended the live range of a physical register, make sure we
1806 // update live-in lists as well.
1807 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1808 const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
1809 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1810 for (LiveInterval::const_iterator I = VRegInterval.begin(),
1811 E = VRegInterval.end(); I != E; ++I ) {
1812 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1813 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1814 MachineBasicBlock &block = *BlockSeq[idx];
1815 if (!block.isLiveIn(DstReg))
1816 block.addLiveIn(DstReg);
1822 // SrcReg is guarateed to be the register whose live interval that is
1824 li_->removeInterval(SrcReg);
1826 // Update regalloc hint.
1827 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1829 // Manually deleted the live interval copy.
1835 // If resulting interval has a preference that no longer fits because of subreg
1836 // coalescing, just clear the preference.
1837 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1838 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1839 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1840 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1841 if (!RC->contains(Preference))
1842 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1846 dbgs() << "\n\t\tJoined. Result = ";
1847 ResDstInt->print(dbgs(), tri_);
1855 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1856 /// compute what the resultant value numbers for each value in the input two
1857 /// ranges will be. This is complicated by copies between the two which can
1858 /// and will commonly cause multiple value numbers to be merged into one.
1860 /// VN is the value number that we're trying to resolve. InstDefiningValue
1861 /// keeps track of the new InstDefiningValue assignment for the result
1862 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1863 /// whether a value in this or other is a copy from the opposite set.
1864 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1865 /// already been assigned.
1867 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1868 /// contains the value number the copy is from.
1870 static unsigned ComputeUltimateVN(VNInfo *VNI,
1871 SmallVector<VNInfo*, 16> &NewVNInfo,
1872 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1873 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1874 SmallVector<int, 16> &ThisValNoAssignments,
1875 SmallVector<int, 16> &OtherValNoAssignments) {
1876 unsigned VN = VNI->id;
1878 // If the VN has already been computed, just return it.
1879 if (ThisValNoAssignments[VN] >= 0)
1880 return ThisValNoAssignments[VN];
1881 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1883 // If this val is not a copy from the other val, then it must be a new value
1884 // number in the destination.
1885 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1886 if (I == ThisFromOther.end()) {
1887 NewVNInfo.push_back(VNI);
1888 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1890 VNInfo *OtherValNo = I->second;
1892 // Otherwise, this *is* a copy from the RHS. If the other side has already
1893 // been computed, return it.
1894 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1895 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1897 // Mark this value number as currently being computed, then ask what the
1898 // ultimate value # of the other value is.
1899 ThisValNoAssignments[VN] = -2;
1900 unsigned UltimateVN =
1901 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1902 OtherValNoAssignments, ThisValNoAssignments);
1903 return ThisValNoAssignments[VN] = UltimateVN;
1906 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1907 return std::find(V.begin(), V.end(), Val) != V.end();
1910 static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
1911 const TargetInstrInfo *TII,
1912 const TargetRegisterInfo *TRI) {
1913 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1914 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1916 else if (MI->isExtractSubreg()) {
1917 DstReg = MI->getOperand(0).getReg();
1918 SrcReg = MI->getOperand(1).getReg();
1919 } else if (MI->isSubregToReg() ||
1920 MI->isInsertSubreg()) {
1921 DstReg = MI->getOperand(0).getReg();
1922 SrcReg = MI->getOperand(2).getReg();
1925 return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
1926 (DstReg == DR || TRI->isSuperRegister(DR, DstReg));
1929 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1930 /// the specified live interval is defined by a copy from the specified
1932 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1935 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1938 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1939 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1940 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1941 *tri_->getSuperRegisters(li.reg)) {
1942 // It's a sub-register live interval, we may not have precise information.
1944 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1945 if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
1946 // Cache computed info.
1947 LR->valno->def = LR->start;
1948 LR->valno->setCopy(DefMI);
1956 /// ValueLiveAt - Return true if the LiveRange pointed to by the given
1957 /// iterator, or any subsequent range with the same value number,
1958 /// is live at the given point.
1959 bool SimpleRegisterCoalescing::ValueLiveAt(LiveInterval::iterator LRItr,
1960 LiveInterval::iterator LREnd,
1961 SlotIndex defPoint) const {
1962 for (const VNInfo *valno = LRItr->valno;
1963 (LRItr != LREnd) && (LRItr->valno == valno); ++LRItr) {
1964 if (LRItr->contains(defPoint))
1972 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1973 /// caller of this method must guarantee that the RHS only contains a single
1974 /// value number and that the RHS is not defined by a copy from this
1975 /// interval. This returns false if the intervals are not joinable, or it
1976 /// joins them and returns true.
1977 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1978 assert(RHS.containsOneValue());
1980 // Some number (potentially more than one) value numbers in the current
1981 // interval may be defined as copies from the RHS. Scan the overlapping
1982 // portions of the LHS and RHS, keeping track of this and looking for
1983 // overlapping live ranges that are NOT defined as copies. If these exist, we
1986 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1987 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1989 if (LHSIt->start < RHSIt->start) {
1990 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1991 if (LHSIt != LHS.begin()) --LHSIt;
1992 } else if (RHSIt->start < LHSIt->start) {
1993 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1994 if (RHSIt != RHS.begin()) --RHSIt;
1997 SmallVector<VNInfo*, 8> EliminatedLHSVals;
2000 // Determine if these live intervals overlap.
2001 bool Overlaps = false;
2002 if (LHSIt->start <= RHSIt->start)
2003 Overlaps = LHSIt->end > RHSIt->start;
2005 Overlaps = RHSIt->end > LHSIt->start;
2007 // If the live intervals overlap, there are two interesting cases: if the
2008 // LHS interval is defined by a copy from the RHS, it's ok and we record
2009 // that the LHS value # is the same as the RHS. If it's not, then we cannot
2010 // coalesce these live ranges and we bail out.
2012 // If we haven't already recorded that this value # is safe, check it.
2013 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
2014 // If it's re-defined by an early clobber somewhere in the live range,
2015 // then conservatively abort coalescing.
2016 if (LHSIt->valno->hasRedefByEC())
2018 // Copy from the RHS?
2019 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
2020 return false; // Nope, bail out.
2022 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2023 // Here is an interesting situation:
2025 // vr1025 = copy vr1024
2030 // Even though vr1025 is copied from vr1024, it's not safe to
2031 // coalesce them since the live range of vr1025 intersects the
2032 // def of vr1024. This happens because vr1025 is assigned the
2033 // value of the previous iteration of vr1024.
2035 EliminatedLHSVals.push_back(LHSIt->valno);
2038 // We know this entire LHS live range is okay, so skip it now.
2039 if (++LHSIt == LHSEnd) break;
2043 if (LHSIt->end < RHSIt->end) {
2044 if (++LHSIt == LHSEnd) break;
2046 // One interesting case to check here. It's possible that we have
2047 // something like "X3 = Y" which defines a new value number in the LHS,
2048 // and is the last use of this liverange of the RHS. In this case, we
2049 // want to notice this copy (so that it gets coalesced away) even though
2050 // the live ranges don't actually overlap.
2051 if (LHSIt->start == RHSIt->end) {
2052 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2053 // We already know that this value number is going to be merged in
2054 // if coalescing succeeds. Just skip the liverange.
2055 if (++LHSIt == LHSEnd) break;
2057 // If it's re-defined by an early clobber somewhere in the live range,
2058 // then conservatively abort coalescing.
2059 if (LHSIt->valno->hasRedefByEC())
2061 // Otherwise, if this is a copy from the RHS, mark it as being merged
2063 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2064 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2065 // Here is an interesting situation:
2067 // vr1025 = copy vr1024
2072 // Even though vr1025 is copied from vr1024, it's not safe to
2073 // coalesced them since live range of vr1025 intersects the
2074 // def of vr1024. This happens because vr1025 is assigned the
2075 // value of the previous iteration of vr1024.
2077 EliminatedLHSVals.push_back(LHSIt->valno);
2079 // We know this entire LHS live range is okay, so skip it now.
2080 if (++LHSIt == LHSEnd) break;
2085 if (++RHSIt == RHSEnd) break;
2089 // If we got here, we know that the coalescing will be successful and that
2090 // the value numbers in EliminatedLHSVals will all be merged together. Since
2091 // the most common case is that EliminatedLHSVals has a single number, we
2092 // optimize for it: if there is more than one value, we merge them all into
2093 // the lowest numbered one, then handle the interval as if we were merging
2094 // with one value number.
2095 VNInfo *LHSValNo = NULL;
2096 if (EliminatedLHSVals.size() > 1) {
2097 // Loop through all the equal value numbers merging them into the smallest
2099 VNInfo *Smallest = EliminatedLHSVals[0];
2100 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2101 if (EliminatedLHSVals[i]->id < Smallest->id) {
2102 // Merge the current notion of the smallest into the smaller one.
2103 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2104 Smallest = EliminatedLHSVals[i];
2106 // Merge into the smallest.
2107 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2110 LHSValNo = Smallest;
2111 } else if (EliminatedLHSVals.empty()) {
2112 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2113 *tri_->getSuperRegisters(LHS.reg))
2114 // Imprecise sub-register information. Can't handle it.
2116 llvm_unreachable("No copies from the RHS?");
2118 LHSValNo = EliminatedLHSVals[0];
2121 // Okay, now that there is a single LHS value number that we're merging the
2122 // RHS into, update the value number info for the LHS to indicate that the
2123 // value number is defined where the RHS value number was.
2124 const VNInfo *VNI = RHS.getValNumInfo(0);
2125 LHSValNo->def = VNI->def;
2126 LHSValNo->setCopy(VNI->getCopy());
2128 // Okay, the final step is to loop over the RHS live intervals, adding them to
2130 if (VNI->hasPHIKill())
2131 LHSValNo->setHasPHIKill(true);
2132 LHS.addKills(LHSValNo, VNI->kills);
2133 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2135 LHS.ComputeJoinedWeight(RHS);
2137 // Update regalloc hint if both are virtual registers.
2138 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2139 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2140 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2141 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2142 if (RHSPref != LHSPref)
2143 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2146 // Update the liveintervals of sub-registers.
2147 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2148 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2149 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, LHS,
2150 li_->getVNInfoAllocator());
2155 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2156 /// returns false. Otherwise, if one of the intervals being joined is a
2157 /// physreg, this method always canonicalizes LHS to be it. The output
2158 /// "RHS" will not have been modified, so we can use this information
2159 /// below to update aliases.
2161 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2163 // Compute the final value assignment, assuming that the live ranges can be
2165 SmallVector<int, 16> LHSValNoAssignments;
2166 SmallVector<int, 16> RHSValNoAssignments;
2167 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2168 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2169 SmallVector<VNInfo*, 16> NewVNInfo;
2171 // If a live interval is a physical register, conservatively check if any
2172 // of its sub-registers is overlapping the live interval of the virtual
2173 // register. If so, do not coalesce.
2174 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2175 *tri_->getSubRegisters(LHS.reg)) {
2176 // If it's coalescing a virtual register to a physical register, estimate
2177 // its live interval length. This is the *cost* of scanning an entire live
2178 // interval. If the cost is low, we'll do an exhaustive check instead.
2180 // If this is something like this:
2188 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2189 // less conservative check. It's possible a sub-register is defined before
2190 // v1024 (or live in) and live out of BB1.
2191 if (RHS.containsOneValue() &&
2192 li_->intervalIsInOneMBB(RHS) &&
2193 li_->getApproximateInstructionCount(RHS) <= 10) {
2194 // Perform a more exhaustive check for some common cases.
2195 if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2198 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2199 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2201 dbgs() << "Interfere with sub-register ";
2202 li_->getInterval(*SR).print(dbgs(), tri_);
2207 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2208 *tri_->getSubRegisters(RHS.reg)) {
2209 if (LHS.containsOneValue() &&
2210 li_->getApproximateInstructionCount(LHS) <= 10) {
2211 // Perform a more exhaustive check for some common cases.
2212 if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2215 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2216 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2218 dbgs() << "Interfere with sub-register ";
2219 li_->getInterval(*SR).print(dbgs(), tri_);
2226 // Compute ultimate value numbers for the LHS and RHS values.
2227 if (RHS.containsOneValue()) {
2228 // Copies from a liveinterval with a single value are simple to handle and
2229 // very common, handle the special case here. This is important, because
2230 // often RHS is small and LHS is large (e.g. a physreg).
2232 // Find out if the RHS is defined as a copy from some value in the LHS.
2233 int RHSVal0DefinedFromLHS = -1;
2235 VNInfo *RHSValNoInfo = NULL;
2236 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2237 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2238 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2239 // If RHS is not defined as a copy from the LHS, we can use simpler and
2240 // faster checks to see if the live ranges are coalescable. This joiner
2241 // can't swap the LHS/RHS intervals though.
2242 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2243 return SimpleJoin(LHS, RHS);
2245 RHSValNoInfo = RHSValNoInfo0;
2248 // It was defined as a copy from the LHS, find out what value # it is.
2250 LHS.getLiveRangeContaining(RHSValNoInfo0->def.getPrevSlot())->valno;
2251 RHSValID = RHSValNoInfo->id;
2252 RHSVal0DefinedFromLHS = RHSValID;
2255 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2256 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2257 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2259 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2260 // should now get updated.
2261 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2264 unsigned VN = VNI->id;
2265 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2266 if (LHSSrcReg != RHS.reg) {
2267 // If this is not a copy from the RHS, its value number will be
2268 // unmodified by the coalescing.
2269 NewVNInfo[VN] = VNI;
2270 LHSValNoAssignments[VN] = VN;
2271 } else if (RHSValID == -1) {
2272 // Otherwise, it is a copy from the RHS, and we don't already have a
2273 // value# for it. Keep the current value number, but remember it.
2274 LHSValNoAssignments[VN] = RHSValID = VN;
2275 NewVNInfo[VN] = RHSValNoInfo;
2276 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2278 // Otherwise, use the specified value #.
2279 LHSValNoAssignments[VN] = RHSValID;
2280 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2281 NewVNInfo[VN] = RHSValNoInfo;
2282 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2286 NewVNInfo[VN] = VNI;
2287 LHSValNoAssignments[VN] = VN;
2291 assert(RHSValID != -1 && "Didn't find value #?");
2292 RHSValNoAssignments[0] = RHSValID;
2293 if (RHSVal0DefinedFromLHS != -1) {
2294 // This path doesn't go through ComputeUltimateVN so just set
2296 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2299 // Loop over the value numbers of the LHS, seeing if any are defined from
2301 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2304 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2307 // DstReg is known to be a register in the LHS interval. If the src is
2308 // from the RHS interval, we can use its value #.
2309 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2312 // Figure out the value # from the RHS.
2313 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2314 assert(lr && "Cannot find live range");
2315 LHSValsDefinedFromRHS[VNI] = lr->valno;
2318 // Loop over the value numbers of the RHS, seeing if any are defined from
2320 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2323 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2326 // DstReg is known to be a register in the RHS interval. If the src is
2327 // from the LHS interval, we can use its value #.
2328 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2331 // Figure out the value # from the LHS.
2332 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2333 assert(lr && "Cannot find live range");
2334 RHSValsDefinedFromLHS[VNI] = lr->valno;
2337 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2338 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2339 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2341 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2344 unsigned VN = VNI->id;
2345 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2347 ComputeUltimateVN(VNI, NewVNInfo,
2348 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2349 LHSValNoAssignments, RHSValNoAssignments);
2351 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2354 unsigned VN = VNI->id;
2355 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2357 // If this value number isn't a copy from the LHS, it's a new number.
2358 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2359 NewVNInfo.push_back(VNI);
2360 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2364 ComputeUltimateVN(VNI, NewVNInfo,
2365 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2366 RHSValNoAssignments, LHSValNoAssignments);
2370 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2371 // interval lists to see if these intervals are coalescable.
2372 LiveInterval::const_iterator I = LHS.begin();
2373 LiveInterval::const_iterator IE = LHS.end();
2374 LiveInterval::const_iterator J = RHS.begin();
2375 LiveInterval::const_iterator JE = RHS.end();
2377 // Skip ahead until the first place of potential sharing.
2378 if (I->start < J->start) {
2379 I = std::upper_bound(I, IE, J->start);
2380 if (I != LHS.begin()) --I;
2381 } else if (J->start < I->start) {
2382 J = std::upper_bound(J, JE, I->start);
2383 if (J != RHS.begin()) --J;
2387 // Determine if these two live ranges overlap.
2389 if (I->start < J->start) {
2390 Overlaps = I->end > J->start;
2392 Overlaps = J->end > I->start;
2395 // If so, check value # info to determine if they are really different.
2397 // If the live range overlap will map to the same value number in the
2398 // result liverange, we can still coalesce them. If not, we can't.
2399 if (LHSValNoAssignments[I->valno->id] !=
2400 RHSValNoAssignments[J->valno->id])
2402 // If it's re-defined by an early clobber somewhere in the live range,
2403 // then conservatively abort coalescing.
2404 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
2408 if (I->end < J->end) {
2417 // Update kill info. Some live ranges are extended due to copy coalescing.
2418 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2419 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2420 VNInfo *VNI = I->first;
2421 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2422 NewVNInfo[LHSValID]->removeKill(VNI->def);
2423 if (VNI->hasPHIKill())
2424 NewVNInfo[LHSValID]->setHasPHIKill(true);
2425 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2428 // Update kill info. Some live ranges are extended due to copy coalescing.
2429 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2430 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2431 VNInfo *VNI = I->first;
2432 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2433 NewVNInfo[RHSValID]->removeKill(VNI->def);
2434 if (VNI->hasPHIKill())
2435 NewVNInfo[RHSValID]->setHasPHIKill(true);
2436 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2439 // If we get here, we know that we can coalesce the live ranges. Ask the
2440 // intervals to coalesce themselves now.
2441 if ((RHS.ranges.size() > LHS.ranges.size() &&
2442 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2443 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2444 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2448 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2456 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2457 // depth of the basic block (the unsigned), and then on the MBB number.
2458 struct DepthMBBCompare {
2459 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2460 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2461 // Deeper loops first
2462 if (LHS.first != RHS.first)
2463 return LHS.first > RHS.first;
2465 // Prefer blocks that are more connected in the CFG. This takes care of
2466 // the most difficult copies first while intervals are short.
2467 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
2468 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
2472 // As a last resort, sort by block number.
2473 return LHS.second->getNumber() < RHS.second->getNumber();
2478 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2479 std::vector<CopyRec> &TryAgain) {
2480 DEBUG(dbgs() << MBB->getName() << ":\n");
2482 std::vector<CopyRec> VirtCopies;
2483 std::vector<CopyRec> PhysCopies;
2484 std::vector<CopyRec> ImpDefCopies;
2485 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2487 MachineInstr *Inst = MII++;
2489 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2490 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2491 bool isInsUndef = false;
2492 if (Inst->isExtractSubreg()) {
2493 DstReg = Inst->getOperand(0).getReg();
2494 SrcReg = Inst->getOperand(1).getReg();
2495 } else if (Inst->isInsertSubreg()) {
2496 DstReg = Inst->getOperand(0).getReg();
2497 SrcReg = Inst->getOperand(2).getReg();
2498 if (Inst->getOperand(1).isUndef())
2500 } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
2501 DstReg = Inst->getOperand(0).getReg();
2502 SrcReg = Inst->getOperand(2).getReg();
2503 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2506 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2507 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2509 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
2510 ImpDefCopies.push_back(CopyRec(Inst, 0));
2511 else if (SrcIsPhys || DstIsPhys)
2512 PhysCopies.push_back(CopyRec(Inst, 0));
2514 VirtCopies.push_back(CopyRec(Inst, 0));
2517 // Try coalescing implicit copies and insert_subreg <undef> first,
2518 // followed by copies to / from physical registers, then finally copies
2519 // from virtual registers to virtual registers.
2520 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2521 CopyRec &TheCopy = ImpDefCopies[i];
2523 if (!JoinCopy(TheCopy, Again))
2525 TryAgain.push_back(TheCopy);
2527 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2528 CopyRec &TheCopy = PhysCopies[i];
2530 if (!JoinCopy(TheCopy, Again))
2532 TryAgain.push_back(TheCopy);
2534 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2535 CopyRec &TheCopy = VirtCopies[i];
2537 if (!JoinCopy(TheCopy, Again))
2539 TryAgain.push_back(TheCopy);
2543 void SimpleRegisterCoalescing::joinIntervals() {
2544 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2546 std::vector<CopyRec> TryAgainList;
2547 if (loopInfo->empty()) {
2548 // If there are no loops in the function, join intervals in function order.
2549 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2551 CopyCoalesceInMBB(I, TryAgainList);
2553 // Otherwise, join intervals in inner loops before other intervals.
2554 // Unfortunately we can't just iterate over loop hierarchy here because
2555 // there may be more MBB's than BB's. Collect MBB's for sorting.
2557 // Join intervals in the function prolog first. We want to join physical
2558 // registers with virtual registers before the intervals got too long.
2559 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2560 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2561 MachineBasicBlock *MBB = I;
2562 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2565 // Sort by loop depth.
2566 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2568 // Finally, join intervals in loop nest order.
2569 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2570 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2573 // Joining intervals can allow other intervals to be joined. Iteratively join
2574 // until we make no progress.
2575 bool ProgressMade = true;
2576 while (ProgressMade) {
2577 ProgressMade = false;
2579 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2580 CopyRec &TheCopy = TryAgainList[i];
2585 bool Success = JoinCopy(TheCopy, Again);
2586 if (Success || !Again) {
2587 TheCopy.MI = 0; // Mark this one as done.
2588 ProgressMade = true;
2594 /// Return true if the two specified registers belong to different register
2595 /// classes. The registers may be either phys or virt regs.
2597 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2598 unsigned RegB) const {
2599 // Get the register classes for the first reg.
2600 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2601 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2602 "Shouldn't consider two physregs!");
2603 return !mri_->getRegClass(RegB)->contains(RegA);
2606 // Compare against the regclass for the second reg.
2607 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2608 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2609 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2610 return RegClassA != RegClassB;
2612 return !RegClassA->contains(RegB);
2615 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
2616 /// between cycles Start and End or NULL if there are no uses.
2618 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
2621 SlotIndex &UseIdx) const{
2622 UseIdx = SlotIndex();
2623 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2624 MachineOperand *LastUse = NULL;
2625 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
2626 E = mri_->use_nodbg_end(); I != E; ++I) {
2627 MachineOperand &Use = I.getOperand();
2628 MachineInstr *UseMI = Use.getParent();
2629 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2630 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2632 // Ignore identity copies.
2634 SlotIndex Idx = li_->getInstructionIndex(UseMI);
2635 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
2636 // that compares higher than any other interval.
2637 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2639 UseIdx = Idx.getUseIndex();
2645 SlotIndex s = Start;
2646 SlotIndex e = End.getPrevSlot().getBaseIndex();
2648 // Skip deleted instructions
2649 MachineInstr *MI = li_->getInstructionFromIndex(e);
2650 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
2651 e = e.getPrevIndex();
2652 MI = li_->getInstructionFromIndex(e);
2654 if (e < s || MI == NULL)
2657 // Ignore identity copies.
2658 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2659 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2661 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2662 MachineOperand &Use = MI->getOperand(i);
2663 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2664 tri_->regsOverlap(Use.getReg(), Reg)) {
2665 UseIdx = e.getUseIndex();
2670 e = e.getPrevIndex();
2676 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2677 if (TargetRegisterInfo::isPhysicalRegister(reg))
2678 dbgs() << tri_->getName(reg);
2680 dbgs() << "%reg" << reg;
2683 void SimpleRegisterCoalescing::releaseMemory() {
2684 JoinedCopies.clear();
2685 ReMatCopies.clear();
2689 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2691 mri_ = &fn.getRegInfo();
2692 tm_ = &fn.getTarget();
2693 tri_ = tm_->getRegisterInfo();
2694 tii_ = tm_->getInstrInfo();
2695 li_ = &getAnalysis<LiveIntervals>();
2696 AA = &getAnalysis<AliasAnalysis>();
2697 loopInfo = &getAnalysis<MachineLoopInfo>();
2699 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2700 << "********** Function: "
2701 << ((Value*)mf_->getFunction())->getName() << '\n');
2703 allocatableRegs_ = tri_->getAllocatableSet(fn);
2704 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2705 E = tri_->regclass_end(); I != E; ++I)
2706 allocatableRCRegs_.insert(std::make_pair(*I,
2707 tri_->getAllocatableSet(fn, *I)));
2709 // Join (coalesce) intervals if requested.
2710 if (EnableJoining) {
2713 dbgs() << "********** INTERVALS POST JOINING **********\n";
2714 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
2716 I->second->print(dbgs(), tri_);
2722 // Perform a final pass over the instructions and compute spill weights
2723 // and remove identity moves.
2724 SmallVector<unsigned, 4> DeadDefs;
2725 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2726 mbbi != mbbe; ++mbbi) {
2727 MachineBasicBlock* mbb = mbbi;
2728 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2730 MachineInstr *MI = mii;
2731 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2732 if (JoinedCopies.count(MI)) {
2733 // Delete all coalesced copies.
2734 bool DoDelete = true;
2735 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2736 assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
2737 MI->isSubregToReg()) && "Unrecognized copy instruction");
2738 DstReg = MI->getOperand(0).getReg();
2739 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2740 // Do not delete extract_subreg, insert_subreg of physical
2741 // registers unless the definition is dead. e.g.
2742 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
2743 // or else the scavenger may complain. LowerSubregs will
2744 // delete them later.
2747 if (MI->allDefsAreDead()) {
2748 LiveInterval &li = li_->getInterval(DstReg);
2749 if (!ShortenDeadCopySrcLiveRange(li, MI))
2750 ShortenDeadCopyLiveRange(li, MI);
2754 mii = llvm::next(mii);
2756 li_->RemoveMachineInstrFromMaps(MI);
2757 mii = mbbi->erase(mii);
2763 // Now check if this is a remat'ed def instruction which is now dead.
2764 if (ReMatDefs.count(MI)) {
2766 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2767 const MachineOperand &MO = MI->getOperand(i);
2770 unsigned Reg = MO.getReg();
2773 if (TargetRegisterInfo::isVirtualRegister(Reg))
2774 DeadDefs.push_back(Reg);
2777 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2778 !mri_->use_nodbg_empty(Reg)) {
2784 while (!DeadDefs.empty()) {
2785 unsigned DeadDef = DeadDefs.back();
2786 DeadDefs.pop_back();
2787 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2789 li_->RemoveMachineInstrFromMaps(mii);
2790 mii = mbbi->erase(mii);
2796 // If the move will be an identity move delete it
2797 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2798 if (isMove && SrcReg == DstReg) {
2799 if (li_->hasInterval(SrcReg)) {
2800 LiveInterval &RegInt = li_->getInterval(SrcReg);
2801 // If def of this move instruction is dead, remove its live range
2802 // from the dstination register's live interval.
2803 if (MI->registerDefIsDead(DstReg)) {
2804 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2805 ShortenDeadCopyLiveRange(RegInt, MI);
2808 li_->RemoveMachineInstrFromMaps(MI);
2809 mii = mbbi->erase(mii);
2821 /// print - Implement the dump method.
2822 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
2826 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2827 return new SimpleRegisterCoalescing();
2830 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2831 DEFINING_FILE_FOR(SimpleRegisterCoalescing)