1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numCrossRCs , "Number of cross class joins performed");
40 STATISTIC(numCommutes , "Number of instruction commuting performed");
41 STATISTIC(numExtends , "Number of copies extended");
42 STATISTIC(NumReMats , "Number of instructions re-materialized");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numAborts , "Number of times interval joining aborted");
46 char SimpleRegisterCoalescing::ID = 0;
48 EnableJoining("join-liveintervals",
49 cl::desc("Coalesce copies (default=true)"),
53 NewHeuristic("new-coalescer-heuristic",
54 cl::desc("Use new coalescer heuristic"),
55 cl::init(false), cl::Hidden);
58 CrossClassJoin("join-cross-class-copies",
59 cl::desc("Coalesce cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<LiveIntervals>();
72 AU.addPreserved<LiveIntervals>();
73 AU.addRequired<MachineLoopInfo>();
74 AU.addPreserved<MachineLoopInfo>();
75 AU.addPreservedID(MachineDominatorsID);
77 AU.addPreservedID(StrongPHIEliminationID);
79 AU.addPreservedID(PHIEliminationID);
80 AU.addPreservedID(TwoAddressInstructionPassID);
81 MachineFunctionPass::getAnalysisUsage(AU);
84 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
85 /// being the source and IntB being the dest, thus this defines a value number
86 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
87 /// see if we can merge these two pieces of B into a single value number,
88 /// eliminating a copy. For example:
92 /// B1 = A3 <- this copy
94 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
95 /// value number to be replaced with B0 (which simplifies the B liveinterval).
97 /// This returns true if an interval was modified.
99 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
101 MachineInstr *CopyMI) {
102 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
104 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
105 // the example above.
106 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
107 assert(BLR != IntB.end() && "Live range not found!");
108 VNInfo *BValNo = BLR->valno;
110 // Get the location that B is defined at. Two options: either this value has
111 // an unknown definition point or it is defined at CopyIdx. If unknown, we
113 if (!BValNo->copy) return false;
114 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
116 // AValNo is the value number in A that defines the copy, A3 in the example.
117 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
118 assert(ALR != IntA.end() && "Live range not found!");
119 VNInfo *AValNo = ALR->valno;
120 // If it's re-defined by an early clobber somewhere in the live range, then
121 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
123 // 172 %ECX<def> = MOV32rr %reg1039<kill>
124 // 180 INLINEASM <es:subl $5,$1
125 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
126 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
127 // 188 %EAX<def> = MOV32rr %EAX<kill>
128 // 196 %ECX<def> = MOV32rr %ECX<kill>
129 // 204 %ECX<def> = MOV32rr %ECX<kill>
130 // 212 %EAX<def> = MOV32rr %EAX<kill>
131 // 220 %EAX<def> = MOV32rr %EAX
132 // 228 %reg1039<def> = MOV32rr %ECX<kill>
133 // The early clobber operand ties ECX input to the ECX def.
135 // The live interval of ECX is represented as this:
136 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
137 // The coalescer has no idea there was a def in the middle of [174,230].
138 if (AValNo->redefByEC)
141 // If AValNo is defined as a copy from IntB, we can potentially process this.
142 // Get the instruction that defines this value number.
143 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
144 if (!SrcReg) return false; // Not defined by a copy.
146 // If the value number is not defined by a copy instruction, ignore it.
148 // If the source register comes from an interval other than IntB, we can't
150 if (SrcReg != IntB.reg) return false;
152 // Get the LiveRange in IntB that this value number starts with.
153 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
154 assert(ValLR != IntB.end() && "Live range not found!");
156 // Make sure that the end of the live range is inside the same block as
158 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
160 ValLREndInst->getParent() != CopyMI->getParent()) return false;
162 // Okay, we now know that ValLR ends in the same block that the CopyMI
163 // live-range starts. If there are no intervening live ranges between them in
164 // IntB, we can merge them.
165 if (ValLR+1 != BLR) return false;
167 // If a live interval is a physical register, conservatively check if any
168 // of its sub-registers is overlapping the live interval of the virtual
169 // register. If so, do not coalesce.
170 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
171 *tri_->getSubRegisters(IntB.reg)) {
172 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
173 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
174 DOUT << "Interfere with sub-register ";
175 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
180 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
182 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
183 // We are about to delete CopyMI, so need to remove it as the 'instruction
184 // that defines this value #'. Update the the valnum with the new defining
186 BValNo->def = FillerStart;
189 // Okay, we can merge them. We need to insert a new liverange:
190 // [ValLR.end, BLR.begin) of either value number, then we merge the
191 // two value numbers.
192 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
194 // If the IntB live range is assigned to a physical register, and if that
195 // physreg has aliases,
196 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
197 // Update the liveintervals of sub-registers.
198 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
199 LiveInterval &AliasLI = li_->getInterval(*AS);
200 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
201 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
205 // Okay, merge "B1" into the same value number as "B0".
206 if (BValNo != ValLR->valno) {
207 IntB.addKills(ValLR->valno, BValNo->kills);
208 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
210 DOUT << " result = "; IntB.print(DOUT, tri_);
213 // If the source instruction was killing the source register before the
214 // merge, unset the isKill marker given the live range has been extended.
215 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
217 ValLREndInst->getOperand(UIdx).setIsKill(false);
218 IntB.removeKill(ValLR->valno, FillerStart);
225 /// HasOtherReachingDefs - Return true if there are definitions of IntB
226 /// other than BValNo val# that can reach uses of AValno val# of IntA.
227 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
231 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
233 if (AI->valno != AValNo) continue;
234 LiveInterval::Ranges::iterator BI =
235 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
236 if (BI != IntB.ranges.begin())
238 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
239 if (BI->valno == BValNo)
241 if (BI->start <= AI->start && BI->end > AI->start)
243 if (BI->start > AI->start && BI->start < AI->end)
250 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
251 /// being the source and IntB being the dest, thus this defines a value number
252 /// in IntB. If the source value number (in IntA) is defined by a commutable
253 /// instruction and its other operand is coalesced to the copy dest register,
254 /// see if we can transform the copy into a noop by commuting the definition. For
257 /// A3 = op A2 B0<kill>
259 /// B1 = A3 <- this copy
261 /// = op A3 <- more uses
265 /// B2 = op B0 A2<kill>
267 /// B1 = B2 <- now an identify copy
269 /// = op B2 <- more uses
271 /// This returns true if an interval was modified.
273 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
275 MachineInstr *CopyMI) {
276 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
278 // FIXME: For now, only eliminate the copy by commuting its def when the
279 // source register is a virtual register. We want to guard against cases
280 // where the copy is a back edge copy and commuting the def lengthen the
281 // live interval of the source register to the entire loop.
282 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
285 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
286 // the example above.
287 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
288 assert(BLR != IntB.end() && "Live range not found!");
289 VNInfo *BValNo = BLR->valno;
291 // Get the location that B is defined at. Two options: either this value has
292 // an unknown definition point or it is defined at CopyIdx. If unknown, we
294 if (!BValNo->copy) return false;
295 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
297 // AValNo is the value number in A that defines the copy, A3 in the example.
298 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
299 assert(ALR != IntA.end() && "Live range not found!");
300 VNInfo *AValNo = ALR->valno;
301 // If other defs can reach uses of this def, then it's not safe to perform
303 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
305 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
306 const TargetInstrDesc &TID = DefMI->getDesc();
308 if (!TID.isCommutable() ||
309 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
312 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
313 unsigned NewReg = NewDstMO.getReg();
314 if (NewReg != IntB.reg || !NewDstMO.isKill())
317 // Make sure there are no other definitions of IntB that would reach the
318 // uses which the new definition can reach.
319 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
322 // If some of the uses of IntA.reg is already coalesced away, return false.
323 // It's not possible to determine whether it's safe to perform the coalescing.
324 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
325 UE = mri_->use_end(); UI != UE; ++UI) {
326 MachineInstr *UseMI = &*UI;
327 unsigned UseIdx = li_->getInstructionIndex(UseMI);
328 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
329 if (ULR == IntA.end())
331 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
335 // At this point we have decided that it is legal to do this
336 // transformation. Start by commuting the instruction.
337 MachineBasicBlock *MBB = DefMI->getParent();
338 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
341 if (NewMI != DefMI) {
342 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
343 MBB->insert(DefMI, NewMI);
346 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
347 NewMI->getOperand(OpIdx).setIsKill();
349 bool BHasPHIKill = BValNo->hasPHIKill;
350 SmallVector<VNInfo*, 4> BDeadValNos;
351 SmallVector<unsigned, 4> BKills;
352 std::map<unsigned, unsigned> BExtend;
354 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
363 // then do not add kills of A to the newly created B interval.
364 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
366 BExtend[ALR->end] = BLR->end;
368 // Update uses of IntA of the specific Val# with IntB.
369 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
370 UE = mri_->use_end(); UI != UE;) {
371 MachineOperand &UseMO = UI.getOperand();
372 MachineInstr *UseMI = &*UI;
374 if (JoinedCopies.count(UseMI))
376 unsigned UseIdx = li_->getInstructionIndex(UseMI);
377 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
378 if (ULR == IntA.end() || ULR->valno != AValNo)
380 UseMO.setReg(NewReg);
383 if (UseMO.isKill()) {
385 UseMO.setIsKill(false);
387 BKills.push_back(li_->getUseIndex(UseIdx)+1);
389 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
390 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
392 if (DstReg == IntB.reg) {
393 // This copy will become a noop. If it's defining a new val#,
394 // remove that val# as well. However this live range is being
395 // extended to the end of the existing live range defined by the copy.
396 unsigned DefIdx = li_->getDefIndex(UseIdx);
397 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
398 BHasPHIKill |= DLR->valno->hasPHIKill;
399 assert(DLR->valno->def == DefIdx);
400 BDeadValNos.push_back(DLR->valno);
401 BExtend[DLR->start] = DLR->end;
402 JoinedCopies.insert(UseMI);
403 // If this is a kill but it's going to be removed, the last use
404 // of the same val# is the new kill.
410 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
411 // simply extend BLR if CopyMI doesn't end the range.
412 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
414 // Remove val#'s defined by copies that will be coalesced away.
415 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
416 IntB.removeValNo(BDeadValNos[i]);
418 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
419 // is updated. Kills are also updated.
420 VNInfo *ValNo = BValNo;
421 ValNo->def = AValNo->def;
423 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
424 unsigned Kill = ValNo->kills[j];
425 if (Kill != BLR->end)
426 BKills.push_back(Kill);
428 ValNo->kills.clear();
429 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
431 if (AI->valno != AValNo) continue;
432 unsigned End = AI->end;
433 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
434 if (EI != BExtend.end())
436 IntB.addRange(LiveRange(AI->start, End, ValNo));
438 IntB.addKills(ValNo, BKills);
439 ValNo->hasPHIKill = BHasPHIKill;
441 DOUT << " result = "; IntB.print(DOUT, tri_);
444 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
445 IntA.removeValNo(AValNo);
446 DOUT << " result = "; IntA.print(DOUT, tri_);
453 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
454 /// fallthoughs to SuccMBB.
455 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
456 MachineBasicBlock *SuccMBB,
457 const TargetInstrInfo *tii_) {
460 MachineBasicBlock *TBB = 0, *FBB = 0;
461 SmallVector<MachineOperand, 4> Cond;
462 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
463 MBB->isSuccessor(SuccMBB);
466 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
467 /// from a physical register live interval as well as from the live intervals
468 /// of its sub-registers.
469 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
470 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
471 li.removeRange(Start, End, true);
472 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
473 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
474 if (!li_->hasInterval(*SR))
476 LiveInterval &sli = li_->getInterval(*SR);
477 unsigned RemoveEnd = Start;
478 while (RemoveEnd != End) {
479 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
482 RemoveEnd = (LR->end < End) ? LR->end : End;
483 sli.removeRange(Start, RemoveEnd, true);
490 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
491 /// as the copy instruction, trim the ive interval to the last use and return
494 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
495 MachineBasicBlock *CopyMBB,
497 const LiveRange *LR) {
498 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
500 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
503 MachineInstr *LastUseMI = LastUse->getParent();
504 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
511 // r1025<dead> = r1024<kill>
512 if (MBBStart < LR->end)
513 removeRange(li, MBBStart, LR->end, li_, tri_);
517 // There are uses before the copy, just shorten the live range to the end
519 LastUse->setIsKill();
520 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
521 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
522 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
524 // Last use is itself an identity code.
525 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
526 LastUseMI->getOperand(DeadIdx).setIsDead();
532 if (LR->start <= MBBStart && LR->end > MBBStart) {
533 if (LR->start == 0) {
534 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
535 // Live-in to the function but dead. Remove it from entry live-in set.
536 mf_->begin()->removeLiveIn(li.reg);
538 // FIXME: Shorten intervals in BBs that reaches this BB.
544 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
545 /// computation, replace the copy by rematerialize the definition.
546 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
548 MachineInstr *CopyMI) {
549 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
550 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
551 assert(SrcLR != SrcInt.end() && "Live range not found!");
552 VNInfo *ValNo = SrcLR->valno;
553 // If other defs can reach uses of this def, then it's not safe to perform
555 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
557 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
558 const TargetInstrDesc &TID = DefMI->getDesc();
559 if (!TID.isAsCheapAsAMove())
561 bool SawStore = false;
562 if (!DefMI->isSafeToMove(tii_, SawStore))
565 unsigned DefIdx = li_->getDefIndex(CopyIdx);
566 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
567 DLR->valno->copy = NULL;
568 // Don't forget to update sub-register intervals.
569 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
570 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
571 if (!li_->hasInterval(*SR))
573 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
574 if (DLR && DLR->valno->copy == CopyMI)
575 DLR->valno->copy = NULL;
579 // If copy kills the source register, find the last use and propagate
581 MachineBasicBlock *MBB = CopyMI->getParent();
582 if (CopyMI->killsRegister(SrcInt.reg))
583 TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR);
585 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
586 CopyMI->removeFromParent();
587 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
588 MachineInstr *NewMI = prior(MII);
589 // CopyMI may have implicit operands, transfer them over to the newly
590 // rematerialized instruction. And update implicit def interval valnos.
591 for (unsigned i = CopyMI->getDesc().getNumOperands(),
592 e = CopyMI->getNumOperands(); i != e; ++i) {
593 MachineOperand &MO = CopyMI->getOperand(i);
594 if (MO.isReg() && MO.isImplicit())
595 NewMI->addOperand(MO);
596 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
597 unsigned Reg = MO.getReg();
598 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
599 if (DLR && DLR->valno->copy == CopyMI)
600 DLR->valno->copy = NULL;
604 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
605 MBB->getParent()->DeleteMachineInstr(CopyMI);
606 ReMatCopies.insert(CopyMI);
607 ReMatDefs.insert(DefMI);
612 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
614 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
615 unsigned DstReg) const {
616 MachineBasicBlock *MBB = CopyMI->getParent();
617 const MachineLoop *L = loopInfo->getLoopFor(MBB);
620 if (MBB != L->getLoopLatch())
623 LiveInterval &LI = li_->getInterval(DstReg);
624 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
625 LiveInterval::const_iterator DstLR =
626 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
627 if (DstLR == LI.end())
629 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
630 if (DstLR->valno->kills.size() == 1 &&
631 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
636 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
637 /// update the subregister number if it is not zero. If DstReg is a
638 /// physical register and the existing subregister number of the def / use
639 /// being updated is not zero, make sure to set it to the correct physical
642 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
644 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
645 if (DstIsPhys && SubIdx) {
646 // Figure out the real physical register we are updating with.
647 DstReg = tri_->getSubReg(DstReg, SubIdx);
651 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
652 E = mri_->reg_end(); I != E; ) {
653 MachineOperand &O = I.getOperand();
654 MachineInstr *UseMI = &*I;
656 unsigned OldSubIdx = O.getSubReg();
658 unsigned UseDstReg = DstReg;
660 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
662 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
663 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
664 CopySrcSubIdx, CopyDstSubIdx) &&
665 CopySrcReg != CopyDstReg &&
666 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
667 // If the use is a copy and it won't be coalesced away, and its source
668 // is defined by a trivial computation, try to rematerialize it instead.
669 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
678 // Sub-register indexes goes from small to large. e.g.
679 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
680 // EAX: 1 -> AL, 2 -> AX
681 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
682 // sub-register 2 is also AX.
683 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
684 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
687 // Remove would-be duplicated kill marker.
688 if (O.isKill() && UseMI->killsRegister(DstReg))
692 // After updating the operand, check if the machine instruction has
693 // become a copy. If so, update its val# information.
694 const TargetInstrDesc &TID = UseMI->getDesc();
695 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
696 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
697 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
698 CopySrcSubIdx, CopyDstSubIdx) &&
699 CopySrcReg != CopyDstReg &&
700 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
701 allocatableRegs_[CopyDstReg])) {
702 LiveInterval &LI = li_->getInterval(CopyDstReg);
703 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
704 const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
705 if (DLR->valno->def == DefIdx)
706 DLR->valno->copy = UseMI;
711 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
712 /// registers due to insert_subreg coalescing. e.g.
714 /// r1025 = implicit_def
715 /// r1025 = insert_subreg r1025, r1024
719 /// r1025 = implicit_def
720 /// r1025 = insert_subreg r1025, r1025
723 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
724 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
725 E = mri_->reg_end(); I != E; ) {
726 MachineOperand &O = I.getOperand();
727 MachineInstr *DefMI = &*I;
731 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
733 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
735 li_->RemoveMachineInstrFromMaps(DefMI);
736 DefMI->eraseFromParent();
740 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
741 /// due to live range lengthening as the result of coalescing.
742 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
744 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
745 UE = mri_->use_end(); UI != UE; ++UI) {
746 MachineOperand &UseMO = UI.getOperand();
747 if (UseMO.isKill()) {
748 MachineInstr *UseMI = UseMO.getParent();
749 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
750 if (JoinedCopies.count(UseMI))
752 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
753 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
754 UseMO.setIsKill(false);
759 /// removeIntervalIfEmpty - Check if the live interval of a physical register
760 /// is empty, if so remove it and also remove the empty intervals of its
761 /// sub-registers. Return true if live interval is removed.
762 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
763 const TargetRegisterInfo *tri_) {
765 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
766 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
767 if (!li_->hasInterval(*SR))
769 LiveInterval &sli = li_->getInterval(*SR);
771 li_->removeInterval(*SR);
773 li_->removeInterval(li.reg);
779 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
780 /// Return true if live interval is removed.
781 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
782 MachineInstr *CopyMI) {
783 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
784 LiveInterval::iterator MLR =
785 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
787 return false; // Already removed by ShortenDeadCopySrcLiveRange.
788 unsigned RemoveStart = MLR->start;
789 unsigned RemoveEnd = MLR->end;
790 // Remove the liverange that's defined by this.
791 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
792 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
793 return removeIntervalIfEmpty(li, li_, tri_);
798 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
799 /// the val# it defines. If the live interval becomes empty, remove it as well.
800 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
801 MachineInstr *DefMI) {
802 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
803 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
804 if (DefIdx != MLR->valno->def)
806 li.removeValNo(MLR->valno);
807 return removeIntervalIfEmpty(li, li_, tri_);
810 /// PropagateDeadness - Propagate the dead marker to the instruction which
811 /// defines the val#.
812 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
813 unsigned &LRStart, LiveIntervals *li_,
814 const TargetRegisterInfo* tri_) {
815 MachineInstr *DefMI =
816 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
817 if (DefMI && DefMI != CopyMI) {
818 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
820 DefMI->getOperand(DeadIdx).setIsDead();
821 // A dead def should have a single cycle interval.
827 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
828 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
829 /// ends the live range there. If there isn't another use, then this live range
830 /// is dead. Return true if live interval is removed.
832 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
833 MachineInstr *CopyMI) {
834 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
836 // FIXME: special case: function live in. It can be a general case if the
837 // first instruction index starts at > 0 value.
838 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
839 // Live-in to the function but dead. Remove it from entry live-in set.
840 if (mf_->begin()->isLiveIn(li.reg))
841 mf_->begin()->removeLiveIn(li.reg);
842 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
843 removeRange(li, LR->start, LR->end, li_, tri_);
844 return removeIntervalIfEmpty(li, li_, tri_);
847 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
849 // Livein but defined by a phi.
852 unsigned RemoveStart = LR->start;
853 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
854 if (LR->end > RemoveEnd)
855 // More uses past this copy? Nothing to do.
858 // If there is a last use in the same bb, we can't remove the live range.
859 // Shorten the live interval and return.
860 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMI->getParent(), li, LR))
863 if (LR->valno->def == RemoveStart)
864 // If the def MI defines the val#, propagate the dead marker.
865 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
867 removeRange(li, RemoveStart, LR->end, li_, tri_);
868 return removeIntervalIfEmpty(li, li_, tri_);
871 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
872 /// from an implicit def to another register can be coalesced away.
873 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
875 LiveInterval &ImpLi) const{
876 if (!CopyMI->killsRegister(ImpLi.reg))
878 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
879 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
882 if (LR->valno->hasPHIKill)
884 if (LR->valno->def != CopyIdx)
886 // Make sure all of val# uses are copies.
887 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
888 UE = mri_->use_end(); UI != UE;) {
889 MachineInstr *UseMI = &*UI;
891 if (JoinedCopies.count(UseMI))
893 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
894 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
895 if (ULR == li.end() || ULR->valno != LR->valno)
897 // If the use is not a use, then it's not safe to coalesce the move.
898 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
899 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
900 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
901 UseMI->getOperand(1).getReg() == li.reg)
910 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
911 /// def and it is being removed. Turn all copies from this value# into
912 /// identity copies so they will be removed.
913 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
915 SmallVector<MachineInstr*, 4> ImpDefs;
916 MachineOperand *LastUse = NULL;
917 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
918 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
919 RE = mri_->reg_end(); RI != RE;) {
920 MachineOperand *MO = &RI.getOperand();
921 MachineInstr *MI = &*RI;
924 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
925 ImpDefs.push_back(MI);
929 if (JoinedCopies.count(MI))
931 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
932 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
933 if (ULR == li.end() || ULR->valno != VNI)
935 // If the use is a copy, turn it into an identity copy.
936 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
937 if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
939 // Each use MI may have multiple uses of this register. Change them all.
940 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
941 MachineOperand &MO = MI->getOperand(i);
942 if (MO.isReg() && MO.getReg() == li.reg)
945 JoinedCopies.insert(MI);
946 } else if (UseIdx > LastUseIdx) {
952 LastUse->setIsKill();
954 // Remove dead implicit_def's.
955 while (!ImpDefs.empty()) {
956 MachineInstr *ImpDef = ImpDefs.back();
958 li_->RemoveMachineInstrFromMaps(ImpDef);
959 ImpDef->eraseFromParent();
964 /// getMatchingSuperReg - Return a super-register of the specified register
965 /// Reg so its sub-register of index SubIdx is Reg.
966 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
967 const TargetRegisterClass *RC,
968 const TargetRegisterInfo* TRI) {
969 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
970 unsigned SR = *SRs; ++SRs)
971 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
976 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
977 /// two virtual registers from different register classes.
979 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
981 unsigned Threshold) {
982 // Then make sure the intervals are *short*.
983 LiveInterval &LargeInt = li_->getInterval(LargeReg);
984 LiveInterval &SmallInt = li_->getInterval(SmallReg);
985 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
986 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
987 if (SmallSize > Threshold || LargeSize > Threshold)
988 if ((float)std::distance(mri_->use_begin(SmallReg),
989 mri_->use_end()) / SmallSize <
990 (float)std::distance(mri_->use_begin(LargeReg),
991 mri_->use_end()) / LargeSize)
996 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
997 /// register with a physical register, check if any of the virtual register
998 /// operand is a sub-register use or def. If so, make sure it won't result
999 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1000 /// vr1024 = extract_subreg vr1025, 1
1002 /// vr1024 = mov8rr AH
1003 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1004 /// AH does not have a super-reg whose sub-register 1 is AH.
1006 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1009 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1010 E = mri_->reg_end(); I != E; ++I) {
1011 MachineOperand &O = I.getOperand();
1012 MachineInstr *MI = &*I;
1013 if (MI == CopyMI || JoinedCopies.count(MI))
1015 unsigned SubIdx = O.getSubReg();
1016 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1018 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1019 SubIdx = MI->getOperand(2).getImm();
1020 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1023 unsigned SrcReg = MI->getOperand(1).getReg();
1024 const TargetRegisterClass *RC =
1025 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1026 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1027 : mri_->getRegClass(SrcReg);
1028 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1032 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1033 SubIdx = MI->getOperand(3).getImm();
1034 if (VirtReg == MI->getOperand(0).getReg()) {
1035 if (!tri_->getSubReg(PhysReg, SubIdx))
1038 unsigned DstReg = MI->getOperand(0).getReg();
1039 const TargetRegisterClass *RC =
1040 TargetRegisterInfo::isPhysicalRegister(DstReg)
1041 ? tri_->getPhysicalRegisterRegClass(DstReg)
1042 : mri_->getRegClass(DstReg);
1043 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1052 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1053 /// an extract_subreg where dst is a physical register, e.g.
1054 /// cl = EXTRACT_SUBREG reg1024, 1
1056 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1057 unsigned SrcReg, unsigned SubIdx,
1058 unsigned &RealDstReg) {
1059 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1060 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
1061 assert(RealDstReg && "Invalid extract_subreg instruction!");
1063 // For this type of EXTRACT_SUBREG, conservatively
1064 // check if the live interval of the source register interfere with the
1065 // actual super physical register we are trying to coalesce with.
1066 LiveInterval &RHS = li_->getInterval(SrcReg);
1067 if (li_->hasInterval(RealDstReg) &&
1068 RHS.overlaps(li_->getInterval(RealDstReg))) {
1069 DOUT << "Interfere with register ";
1070 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
1071 return false; // Not coalescable
1073 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1074 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1075 DOUT << "Interfere with sub-register ";
1076 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1077 return false; // Not coalescable
1082 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1083 /// an insert_subreg where src is a physical register, e.g.
1084 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1086 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1087 unsigned SrcReg, unsigned SubIdx,
1088 unsigned &RealSrcReg) {
1089 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1090 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
1091 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1093 LiveInterval &RHS = li_->getInterval(DstReg);
1094 if (li_->hasInterval(RealSrcReg) &&
1095 RHS.overlaps(li_->getInterval(RealSrcReg))) {
1096 DOUT << "Interfere with register ";
1097 DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
1098 return false; // Not coalescable
1100 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1101 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1102 DOUT << "Interfere with sub-register ";
1103 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1104 return false; // Not coalescable
1109 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1110 /// which are the src/dst of the copy instruction CopyMI. This returns true
1111 /// if the copy was successfully coalesced away. If it is not currently
1112 /// possible to coalesce this interval, but it may be possible if other
1113 /// things get coalesced, then it returns true by reference in 'Again'.
1114 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1115 MachineInstr *CopyMI = TheCopy.MI;
1118 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1119 return false; // Already done.
1121 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1123 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1124 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1125 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1126 unsigned SubIdx = 0;
1128 DstReg = CopyMI->getOperand(0).getReg();
1129 SrcReg = CopyMI->getOperand(1).getReg();
1130 } else if (isInsSubReg) {
1131 if (CopyMI->getOperand(2).getSubReg()) {
1132 DOUT << "\tSource of insert_subreg is already coalesced "
1133 << "to another register.\n";
1134 return false; // Not coalescable.
1136 DstReg = CopyMI->getOperand(0).getReg();
1137 SrcReg = CopyMI->getOperand(2).getReg();
1138 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
1139 assert(0 && "Unrecognized copy instruction!");
1143 // If they are already joined we continue.
1144 if (SrcReg == DstReg) {
1145 DOUT << "\tCopy already coalesced.\n";
1146 return false; // Not coalescable.
1149 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1150 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1152 // If they are both physical registers, we cannot join them.
1153 if (SrcIsPhys && DstIsPhys) {
1154 DOUT << "\tCan not coalesce physregs.\n";
1155 return false; // Not coalescable.
1158 // We only join virtual registers with allocatable physical registers.
1159 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1160 DOUT << "\tSrc reg is unallocatable physreg.\n";
1161 return false; // Not coalescable.
1163 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1164 DOUT << "\tDst reg is unallocatable physreg.\n";
1165 return false; // Not coalescable.
1168 // Should be non-null only when coalescing to a sub-register class.
1169 bool CrossRC = false;
1170 const TargetRegisterClass *NewRC = NULL;
1171 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1172 unsigned RealDstReg = 0;
1173 unsigned RealSrcReg = 0;
1174 if (isExtSubReg || isInsSubReg) {
1175 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1176 if (SrcIsPhys && isExtSubReg) {
1177 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1178 // coalesced with AX.
1179 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1181 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1182 // coalesced to a larger register so the subreg indices cancel out.
1183 if (DstSubIdx != SubIdx) {
1184 DOUT << "\t Sub-register indices mismatch.\n";
1185 return false; // Not coalescable.
1188 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1190 } else if (DstIsPhys && isInsSubReg) {
1191 // EAX = INSERT_SUBREG EAX, r1024, 0
1192 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1194 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1195 // coalesced to a larger register so the subreg indices cancel out.
1196 if (SrcSubIdx != SubIdx) {
1197 DOUT << "\t Sub-register indices mismatch.\n";
1198 return false; // Not coalescable.
1201 DstReg = tri_->getSubReg(DstReg, SubIdx);
1203 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
1204 if (CopyMI->getOperand(1).getSubReg()) {
1205 DOUT << "\tSrc of extract_subreg already coalesced with reg"
1206 << " of a super-class.\n";
1207 return false; // Not coalescable.
1211 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1212 return false; // Not coalescable
1214 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1215 return false; // Not coalescable
1219 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1220 : CopyMI->getOperand(2).getSubReg();
1222 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1223 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1224 // coalesced to a larger register so the subreg indices cancel out.
1225 // Also check if the other larger register is of the same register
1226 // class as the would be resulting register.
1229 DOUT << "\t Sub-register indices mismatch.\n";
1230 return false; // Not coalescable.
1234 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1235 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1236 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1237 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1238 Again = true; // May be possible to coalesce later.
1243 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1244 if (!CrossClassJoin)
1248 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1249 // with another? If it's the resulting destination register, then
1250 // the subidx must be propagated to uses (but only those defined
1251 // by the EXTRACT_SUBREG). If it's being coalesced into another
1252 // register, it should be safe because register is assumed to have
1253 // the register class of the super-register.
1255 // Process moves where one of the registers have a sub-register index.
1256 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1257 if (DstMO->getSubReg())
1258 // FIXME: Can we handle this?
1260 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1261 SubIdx = SrcMO->getSubReg();
1263 // This is not a extract_subreg but it looks like one.
1264 // e.g. %cl = MOV16rr %reg1024:2
1267 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1268 return false; // Not coalescable
1273 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1274 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1275 unsigned LargeReg = SrcReg;
1276 unsigned SmallReg = DstReg;
1279 // Now determine the register class of the joined register.
1281 if (SubIdx && DstRC && DstRC->isASubClass()) {
1282 // This is a move to a sub-register class. However, the source is a
1283 // sub-register of a larger register class. We don't know what should
1284 // the register class be. FIXME.
1288 Limit = allocatableRCRegs_[DstRC].count();
1289 } else if (!SrcIsPhys && !SrcIsPhys) {
1290 unsigned SrcSize = SrcRC->getSize();
1291 unsigned DstSize = DstRC->getSize();
1292 if (SrcSize < DstSize)
1293 // For example X86::MOVSD2PDrr copies from FR64 to VR128.
1295 else if (DstSize > SrcSize) {
1297 std::swap(LargeReg, SmallReg);
1299 unsigned SrcNumRegs = SrcRC->getNumRegs();
1300 unsigned DstNumRegs = DstRC->getNumRegs();
1301 if (DstNumRegs < SrcNumRegs)
1302 // Sub-register class?
1304 else if (SrcNumRegs < DstNumRegs) {
1306 std::swap(LargeReg, SmallReg);
1308 // No idea what's the right register class to use.
1313 // If we are joining two virtual registers and the resulting register
1314 // class is more restrictive (fewer register, smaller size). Check if it's
1315 // worth doing the merge.
1316 if (!SrcIsPhys && !DstIsPhys &&
1317 (isExtSubReg || DstRC->isASubClass()) &&
1318 !isWinToJoinCrossClass(LargeReg, SmallReg,
1319 allocatableRCRegs_[NewRC].count())) {
1320 DOUT << "\tSrc/Dest are different register classes.\n";
1321 // Allow the coalescer to try again in case either side gets coalesced to
1322 // a physical register that's compatible with the other side. e.g.
1323 // r1024 = MOV32to32_ r1025
1324 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1325 Again = true; // May be possible to coalesce later.
1330 // Will it create illegal extract_subreg / insert_subreg?
1331 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1333 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1336 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1337 LiveInterval &DstInt = li_->getInterval(DstReg);
1338 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1339 "Register mapping is horribly broken!");
1341 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1342 DOUT << " and "; DstInt.print(DOUT, tri_);
1345 // Check if it is necessary to propagate "isDead" property.
1346 if (!isExtSubReg && !isInsSubReg) {
1347 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1348 bool isDead = mopd->isDead();
1350 // We need to be careful about coalescing a source physical register with a
1351 // virtual register. Once the coalescing is done, it cannot be broken and
1352 // these are not spillable! If the destination interval uses are far away,
1353 // think twice about coalescing them!
1354 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1355 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1356 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1357 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1358 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1359 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1360 if (TheCopy.isBackEdge)
1361 Threshold *= 2; // Favors back edge copies.
1363 // If the virtual register live interval is long but it has low use desity,
1364 // do not join them, instead mark the physical register as its allocation
1366 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1367 if (Length > Threshold &&
1368 (((float)std::distance(mri_->use_begin(JoinVReg), mri_->use_end())
1369 / Length) < (1.0 / Threshold))) {
1370 JoinVInt.preference = JoinPReg;
1372 DOUT << "\tMay tie down a physical register, abort!\n";
1373 Again = true; // May be possible to coalesce later.
1379 // Okay, attempt to join these two intervals. On failure, this returns false.
1380 // Otherwise, if one of the intervals being joined is a physreg, this method
1381 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1382 // been modified, so we can use this information below to update aliases.
1383 bool Swapped = false;
1384 // If SrcInt is implicitly defined, it's safe to coalesce.
1385 bool isEmpty = SrcInt.empty();
1386 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1387 // Only coalesce an empty interval (defined by implicit_def) with
1388 // another interval which has a valno defined by the CopyMI and the CopyMI
1389 // is a kill of the implicit def.
1390 DOUT << "Not profitable!\n";
1394 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1395 // Coalescing failed.
1397 // If definition of source is defined by trivial computation, try
1398 // rematerializing it.
1399 if (!isExtSubReg && !isInsSubReg &&
1400 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1403 // If we can eliminate the copy without merging the live ranges, do so now.
1404 if (!isExtSubReg && !isInsSubReg &&
1405 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1406 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1407 JoinedCopies.insert(CopyMI);
1411 // Otherwise, we are unable to join the intervals.
1412 DOUT << "Interference!\n";
1413 Again = true; // May be possible to coalesce later.
1417 LiveInterval *ResSrcInt = &SrcInt;
1418 LiveInterval *ResDstInt = &DstInt;
1420 std::swap(SrcReg, DstReg);
1421 std::swap(ResSrcInt, ResDstInt);
1423 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1424 "LiveInterval::join didn't work right!");
1426 // If we're about to merge live ranges into a physical register live interval,
1427 // we have to update any aliased register's live ranges to indicate that they
1428 // have clobbered values for this range.
1429 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1430 // If this is a extract_subreg where dst is a physical register, e.g.
1431 // cl = EXTRACT_SUBREG reg1024, 1
1432 // then create and update the actual physical register allocated to RHS.
1433 if (RealDstReg || RealSrcReg) {
1434 LiveInterval &RealInt =
1435 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1436 SmallSet<const VNInfo*, 4> CopiedValNos;
1437 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1438 E = ResSrcInt->ranges.end(); I != E; ++I) {
1439 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1440 assert(DstLR && "Invalid joined interval!");
1441 const VNInfo *DstValNo = DstLR->valno;
1442 if (CopiedValNos.insert(DstValNo)) {
1443 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1444 li_->getVNInfoAllocator());
1445 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1446 RealInt.addKills(ValNo, DstValNo->kills);
1447 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1451 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1454 // Update the liveintervals of sub-registers.
1455 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1456 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1457 li_->getVNInfoAllocator());
1460 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1461 // larger super-register.
1462 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1463 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1464 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1465 std::swap(SrcReg, DstReg);
1466 std::swap(ResSrcInt, ResDstInt);
1470 // Coalescing to a virtual register that is of a sub-register class of the
1471 // other. Make sure the resulting register is set to the right register class.
1475 mri_->setRegClass(DstReg, NewRC);
1479 // Add all copies that define val# in the source interval into the queue.
1480 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1481 e = ResSrcInt->vni_end(); i != e; ++i) {
1482 const VNInfo *vni = *i;
1483 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1485 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1486 unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
1488 JoinedCopies.count(CopyMI) == 0 &&
1489 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
1490 NewSrcSubIdx, NewDstSubIdx)) {
1491 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1492 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1493 isBackEdgeCopy(CopyMI, DstReg)));
1498 // Remember to delete the copy instruction.
1499 JoinedCopies.insert(CopyMI);
1501 // Some live range has been lengthened due to colaescing, eliminate the
1502 // unnecessary kills.
1503 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1504 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1505 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1510 // r1024 = implicit_def
1513 RemoveDeadImpDef(DstReg, *ResDstInt);
1514 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1516 // SrcReg is guarateed to be the register whose live interval that is
1518 li_->removeInterval(SrcReg);
1521 // Now the copy is being coalesced away, the val# previously defined
1522 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1523 // length interval. Remove the val#.
1524 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1525 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1526 VNInfo *ImpVal = LR->valno;
1527 assert(ImpVal->def == CopyIdx);
1528 unsigned NextDef = LR->end;
1529 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1530 ResDstInt->removeValNo(ImpVal);
1531 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1532 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1533 // Special case: vr1024 = implicit_def
1534 // vr1024 = insert_subreg vr1024, vr1025, c
1535 // The insert_subreg becomes a "copy" that defines a val# which can itself
1536 // be coalesced away.
1537 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1538 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1539 LR->valno->copy = DefMI;
1543 // If resulting interval has a preference that no longer fits because of subreg
1544 // coalescing, just clear the preference.
1545 if (ResDstInt->preference && (isExtSubReg || isInsSubReg) &&
1546 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1547 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1548 if (!RC->contains(ResDstInt->preference))
1549 ResDstInt->preference = 0;
1552 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1559 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1560 /// compute what the resultant value numbers for each value in the input two
1561 /// ranges will be. This is complicated by copies between the two which can
1562 /// and will commonly cause multiple value numbers to be merged into one.
1564 /// VN is the value number that we're trying to resolve. InstDefiningValue
1565 /// keeps track of the new InstDefiningValue assignment for the result
1566 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1567 /// whether a value in this or other is a copy from the opposite set.
1568 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1569 /// already been assigned.
1571 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1572 /// contains the value number the copy is from.
1574 static unsigned ComputeUltimateVN(VNInfo *VNI,
1575 SmallVector<VNInfo*, 16> &NewVNInfo,
1576 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1577 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1578 SmallVector<int, 16> &ThisValNoAssignments,
1579 SmallVector<int, 16> &OtherValNoAssignments) {
1580 unsigned VN = VNI->id;
1582 // If the VN has already been computed, just return it.
1583 if (ThisValNoAssignments[VN] >= 0)
1584 return ThisValNoAssignments[VN];
1585 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1587 // If this val is not a copy from the other val, then it must be a new value
1588 // number in the destination.
1589 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1590 if (I == ThisFromOther.end()) {
1591 NewVNInfo.push_back(VNI);
1592 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1594 VNInfo *OtherValNo = I->second;
1596 // Otherwise, this *is* a copy from the RHS. If the other side has already
1597 // been computed, return it.
1598 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1599 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1601 // Mark this value number as currently being computed, then ask what the
1602 // ultimate value # of the other value is.
1603 ThisValNoAssignments[VN] = -2;
1604 unsigned UltimateVN =
1605 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1606 OtherValNoAssignments, ThisValNoAssignments);
1607 return ThisValNoAssignments[VN] = UltimateVN;
1610 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1611 return std::find(V.begin(), V.end(), Val) != V.end();
1614 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1615 /// the specified live interval is defined by a copy from the specified
1617 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1620 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1623 if (LR->valno->def == ~0U &&
1624 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1625 *tri_->getSuperRegisters(li.reg)) {
1626 // It's a sub-register live interval, we may not have precise information.
1628 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1629 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1631 tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1632 DstReg == li.reg && SrcReg == Reg) {
1633 // Cache computed info.
1634 LR->valno->def = LR->start;
1635 LR->valno->copy = DefMI;
1642 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1643 /// caller of this method must guarantee that the RHS only contains a single
1644 /// value number and that the RHS is not defined by a copy from this
1645 /// interval. This returns false if the intervals are not joinable, or it
1646 /// joins them and returns true.
1647 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1648 assert(RHS.containsOneValue());
1650 // Some number (potentially more than one) value numbers in the current
1651 // interval may be defined as copies from the RHS. Scan the overlapping
1652 // portions of the LHS and RHS, keeping track of this and looking for
1653 // overlapping live ranges that are NOT defined as copies. If these exist, we
1656 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1657 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1659 if (LHSIt->start < RHSIt->start) {
1660 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1661 if (LHSIt != LHS.begin()) --LHSIt;
1662 } else if (RHSIt->start < LHSIt->start) {
1663 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1664 if (RHSIt != RHS.begin()) --RHSIt;
1667 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1670 // Determine if these live intervals overlap.
1671 bool Overlaps = false;
1672 if (LHSIt->start <= RHSIt->start)
1673 Overlaps = LHSIt->end > RHSIt->start;
1675 Overlaps = RHSIt->end > LHSIt->start;
1677 // If the live intervals overlap, there are two interesting cases: if the
1678 // LHS interval is defined by a copy from the RHS, it's ok and we record
1679 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1680 // coalesce these live ranges and we bail out.
1682 // If we haven't already recorded that this value # is safe, check it.
1683 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1684 // Copy from the RHS?
1685 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1686 return false; // Nope, bail out.
1688 if (LHSIt->contains(RHSIt->valno->def))
1689 // Here is an interesting situation:
1691 // vr1025 = copy vr1024
1696 // Even though vr1025 is copied from vr1024, it's not safe to
1697 // coalesced them since live range of vr1025 intersects the
1698 // def of vr1024. This happens because vr1025 is assigned the
1699 // value of the previous iteration of vr1024.
1701 EliminatedLHSVals.push_back(LHSIt->valno);
1704 // We know this entire LHS live range is okay, so skip it now.
1705 if (++LHSIt == LHSEnd) break;
1709 if (LHSIt->end < RHSIt->end) {
1710 if (++LHSIt == LHSEnd) break;
1712 // One interesting case to check here. It's possible that we have
1713 // something like "X3 = Y" which defines a new value number in the LHS,
1714 // and is the last use of this liverange of the RHS. In this case, we
1715 // want to notice this copy (so that it gets coalesced away) even though
1716 // the live ranges don't actually overlap.
1717 if (LHSIt->start == RHSIt->end) {
1718 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1719 // We already know that this value number is going to be merged in
1720 // if coalescing succeeds. Just skip the liverange.
1721 if (++LHSIt == LHSEnd) break;
1723 // Otherwise, if this is a copy from the RHS, mark it as being merged
1725 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1726 if (LHSIt->contains(RHSIt->valno->def))
1727 // Here is an interesting situation:
1729 // vr1025 = copy vr1024
1734 // Even though vr1025 is copied from vr1024, it's not safe to
1735 // coalesced them since live range of vr1025 intersects the
1736 // def of vr1024. This happens because vr1025 is assigned the
1737 // value of the previous iteration of vr1024.
1739 EliminatedLHSVals.push_back(LHSIt->valno);
1741 // We know this entire LHS live range is okay, so skip it now.
1742 if (++LHSIt == LHSEnd) break;
1747 if (++RHSIt == RHSEnd) break;
1751 // If we got here, we know that the coalescing will be successful and that
1752 // the value numbers in EliminatedLHSVals will all be merged together. Since
1753 // the most common case is that EliminatedLHSVals has a single number, we
1754 // optimize for it: if there is more than one value, we merge them all into
1755 // the lowest numbered one, then handle the interval as if we were merging
1756 // with one value number.
1757 VNInfo *LHSValNo = NULL;
1758 if (EliminatedLHSVals.size() > 1) {
1759 // Loop through all the equal value numbers merging them into the smallest
1761 VNInfo *Smallest = EliminatedLHSVals[0];
1762 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1763 if (EliminatedLHSVals[i]->id < Smallest->id) {
1764 // Merge the current notion of the smallest into the smaller one.
1765 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1766 Smallest = EliminatedLHSVals[i];
1768 // Merge into the smallest.
1769 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1772 LHSValNo = Smallest;
1773 } else if (EliminatedLHSVals.empty()) {
1774 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1775 *tri_->getSuperRegisters(LHS.reg))
1776 // Imprecise sub-register information. Can't handle it.
1778 assert(0 && "No copies from the RHS?");
1780 LHSValNo = EliminatedLHSVals[0];
1783 // Okay, now that there is a single LHS value number that we're merging the
1784 // RHS into, update the value number info for the LHS to indicate that the
1785 // value number is defined where the RHS value number was.
1786 const VNInfo *VNI = RHS.getValNumInfo(0);
1787 LHSValNo->def = VNI->def;
1788 LHSValNo->copy = VNI->copy;
1790 // Okay, the final step is to loop over the RHS live intervals, adding them to
1792 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1793 LHS.addKills(LHSValNo, VNI->kills);
1794 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1795 LHS.weight += RHS.weight;
1796 if (RHS.preference && !LHS.preference)
1797 LHS.preference = RHS.preference;
1802 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1803 /// returns false. Otherwise, if one of the intervals being joined is a
1804 /// physreg, this method always canonicalizes LHS to be it. The output
1805 /// "RHS" will not have been modified, so we can use this information
1806 /// below to update aliases.
1808 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
1810 // Compute the final value assignment, assuming that the live ranges can be
1812 SmallVector<int, 16> LHSValNoAssignments;
1813 SmallVector<int, 16> RHSValNoAssignments;
1814 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1815 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1816 SmallVector<VNInfo*, 16> NewVNInfo;
1818 // If a live interval is a physical register, conservatively check if any
1819 // of its sub-registers is overlapping the live interval of the virtual
1820 // register. If so, do not coalesce.
1821 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1822 *tri_->getSubRegisters(LHS.reg)) {
1823 // If it's coalescing a virtual register to a physical register, estimate
1824 // its live interval length. This is the *cost* of scanning an entire live
1825 // interval. If the cost is low, we'll do an exhaustive check instead.
1827 // If this is something like this:
1835 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
1836 // less conservative check. It's possible a sub-register is defined before
1837 // v1024 (or live in) and live out of BB1.
1838 if (RHS.containsOneValue() &&
1839 li_->intervalIsInOneMBB(RHS) &&
1840 li_->getApproximateInstructionCount(RHS) <= 10) {
1841 // Perform a more exhaustive check for some common cases.
1842 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
1845 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1846 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1847 DOUT << "Interfere with sub-register ";
1848 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1852 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1853 *tri_->getSubRegisters(RHS.reg)) {
1854 if (LHS.containsOneValue() &&
1855 li_->getApproximateInstructionCount(LHS) <= 10) {
1856 // Perform a more exhaustive check for some common cases.
1857 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
1860 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1861 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1862 DOUT << "Interfere with sub-register ";
1863 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1869 // Compute ultimate value numbers for the LHS and RHS values.
1870 if (RHS.containsOneValue()) {
1871 // Copies from a liveinterval with a single value are simple to handle and
1872 // very common, handle the special case here. This is important, because
1873 // often RHS is small and LHS is large (e.g. a physreg).
1875 // Find out if the RHS is defined as a copy from some value in the LHS.
1876 int RHSVal0DefinedFromLHS = -1;
1878 VNInfo *RHSValNoInfo = NULL;
1879 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1880 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1881 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
1882 // If RHS is not defined as a copy from the LHS, we can use simpler and
1883 // faster checks to see if the live ranges are coalescable. This joiner
1884 // can't swap the LHS/RHS intervals though.
1885 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1886 return SimpleJoin(LHS, RHS);
1888 RHSValNoInfo = RHSValNoInfo0;
1891 // It was defined as a copy from the LHS, find out what value # it is.
1892 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1893 RHSValID = RHSValNoInfo->id;
1894 RHSVal0DefinedFromLHS = RHSValID;
1897 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1898 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1899 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1901 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1902 // should now get updated.
1903 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1906 unsigned VN = VNI->id;
1907 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1908 if (LHSSrcReg != RHS.reg) {
1909 // If this is not a copy from the RHS, its value number will be
1910 // unmodified by the coalescing.
1911 NewVNInfo[VN] = VNI;
1912 LHSValNoAssignments[VN] = VN;
1913 } else if (RHSValID == -1) {
1914 // Otherwise, it is a copy from the RHS, and we don't already have a
1915 // value# for it. Keep the current value number, but remember it.
1916 LHSValNoAssignments[VN] = RHSValID = VN;
1917 NewVNInfo[VN] = RHSValNoInfo;
1918 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1920 // Otherwise, use the specified value #.
1921 LHSValNoAssignments[VN] = RHSValID;
1922 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1923 NewVNInfo[VN] = RHSValNoInfo;
1924 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1928 NewVNInfo[VN] = VNI;
1929 LHSValNoAssignments[VN] = VN;
1933 assert(RHSValID != -1 && "Didn't find value #?");
1934 RHSValNoAssignments[0] = RHSValID;
1935 if (RHSVal0DefinedFromLHS != -1) {
1936 // This path doesn't go through ComputeUltimateVN so just set
1938 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1941 // Loop over the value numbers of the LHS, seeing if any are defined from
1943 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1946 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1949 // DstReg is known to be a register in the LHS interval. If the src is
1950 // from the RHS interval, we can use its value #.
1951 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1954 // Figure out the value # from the RHS.
1955 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1958 // Loop over the value numbers of the RHS, seeing if any are defined from
1960 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1963 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1966 // DstReg is known to be a register in the RHS interval. If the src is
1967 // from the LHS interval, we can use its value #.
1968 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1971 // Figure out the value # from the LHS.
1972 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1975 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1976 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1977 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1979 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1982 unsigned VN = VNI->id;
1983 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1985 ComputeUltimateVN(VNI, NewVNInfo,
1986 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1987 LHSValNoAssignments, RHSValNoAssignments);
1989 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1992 unsigned VN = VNI->id;
1993 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1995 // If this value number isn't a copy from the LHS, it's a new number.
1996 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1997 NewVNInfo.push_back(VNI);
1998 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2002 ComputeUltimateVN(VNI, NewVNInfo,
2003 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2004 RHSValNoAssignments, LHSValNoAssignments);
2008 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2009 // interval lists to see if these intervals are coalescable.
2010 LiveInterval::const_iterator I = LHS.begin();
2011 LiveInterval::const_iterator IE = LHS.end();
2012 LiveInterval::const_iterator J = RHS.begin();
2013 LiveInterval::const_iterator JE = RHS.end();
2015 // Skip ahead until the first place of potential sharing.
2016 if (I->start < J->start) {
2017 I = std::upper_bound(I, IE, J->start);
2018 if (I != LHS.begin()) --I;
2019 } else if (J->start < I->start) {
2020 J = std::upper_bound(J, JE, I->start);
2021 if (J != RHS.begin()) --J;
2025 // Determine if these two live ranges overlap.
2027 if (I->start < J->start) {
2028 Overlaps = I->end > J->start;
2030 Overlaps = J->end > I->start;
2033 // If so, check value # info to determine if they are really different.
2035 // If the live range overlap will map to the same value number in the
2036 // result liverange, we can still coalesce them. If not, we can't.
2037 if (LHSValNoAssignments[I->valno->id] !=
2038 RHSValNoAssignments[J->valno->id])
2042 if (I->end < J->end) {
2051 // Update kill info. Some live ranges are extended due to copy coalescing.
2052 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2053 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2054 VNInfo *VNI = I->first;
2055 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2056 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
2057 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
2058 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2061 // Update kill info. Some live ranges are extended due to copy coalescing.
2062 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2063 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2064 VNInfo *VNI = I->first;
2065 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2066 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
2067 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
2068 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2071 // If we get here, we know that we can coalesce the live ranges. Ask the
2072 // intervals to coalesce themselves now.
2073 if ((RHS.ranges.size() > LHS.ranges.size() &&
2074 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2075 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2076 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
2079 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
2086 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2087 // depth of the basic block (the unsigned), and then on the MBB number.
2088 struct DepthMBBCompare {
2089 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2090 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2091 if (LHS.first > RHS.first) return true; // Deeper loops first
2092 return LHS.first == RHS.first &&
2093 LHS.second->getNumber() < RHS.second->getNumber();
2098 /// getRepIntervalSize - Returns the size of the interval that represents the
2099 /// specified register.
2101 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2102 return Rc->getRepIntervalSize(Reg);
2105 /// CopyRecSort::operator - Join priority queue sorting function.
2107 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2108 // Inner loops first.
2109 if (left.LoopDepth > right.LoopDepth)
2111 else if (left.LoopDepth == right.LoopDepth)
2112 if (left.isBackEdge && !right.isBackEdge)
2117 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2118 std::vector<CopyRec> &TryAgain) {
2119 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2121 std::vector<CopyRec> VirtCopies;
2122 std::vector<CopyRec> PhysCopies;
2123 std::vector<CopyRec> ImpDefCopies;
2124 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2125 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2127 MachineInstr *Inst = MII++;
2129 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2130 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2131 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2132 DstReg = Inst->getOperand(0).getReg();
2133 SrcReg = Inst->getOperand(1).getReg();
2134 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
2135 DstReg = Inst->getOperand(0).getReg();
2136 SrcReg = Inst->getOperand(2).getReg();
2137 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2140 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2141 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2143 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2145 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2146 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2147 else if (SrcIsPhys || DstIsPhys)
2148 PhysCopies.push_back(CopyRec(Inst, 0, false));
2150 VirtCopies.push_back(CopyRec(Inst, 0, false));
2157 // Try coalescing implicit copies first, followed by copies to / from
2158 // physical registers, then finally copies from virtual registers to
2159 // virtual registers.
2160 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2161 CopyRec &TheCopy = ImpDefCopies[i];
2163 if (!JoinCopy(TheCopy, Again))
2165 TryAgain.push_back(TheCopy);
2167 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2168 CopyRec &TheCopy = PhysCopies[i];
2170 if (!JoinCopy(TheCopy, Again))
2172 TryAgain.push_back(TheCopy);
2174 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2175 CopyRec &TheCopy = VirtCopies[i];
2177 if (!JoinCopy(TheCopy, Again))
2179 TryAgain.push_back(TheCopy);
2183 void SimpleRegisterCoalescing::joinIntervals() {
2184 DOUT << "********** JOINING INTERVALS ***********\n";
2187 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2189 std::vector<CopyRec> TryAgainList;
2190 if (loopInfo->empty()) {
2191 // If there are no loops in the function, join intervals in function order.
2192 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2194 CopyCoalesceInMBB(I, TryAgainList);
2196 // Otherwise, join intervals in inner loops before other intervals.
2197 // Unfortunately we can't just iterate over loop hierarchy here because
2198 // there may be more MBB's than BB's. Collect MBB's for sorting.
2200 // Join intervals in the function prolog first. We want to join physical
2201 // registers with virtual registers before the intervals got too long.
2202 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2203 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2204 MachineBasicBlock *MBB = I;
2205 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2208 // Sort by loop depth.
2209 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2211 // Finally, join intervals in loop nest order.
2212 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2213 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2216 // Joining intervals can allow other intervals to be joined. Iteratively join
2217 // until we make no progress.
2219 SmallVector<CopyRec, 16> TryAgain;
2220 bool ProgressMade = true;
2221 while (ProgressMade) {
2222 ProgressMade = false;
2223 while (!JoinQueue->empty()) {
2224 CopyRec R = JoinQueue->pop();
2226 bool Success = JoinCopy(R, Again);
2228 ProgressMade = true;
2230 TryAgain.push_back(R);
2234 while (!TryAgain.empty()) {
2235 JoinQueue->push(TryAgain.back());
2236 TryAgain.pop_back();
2241 bool ProgressMade = true;
2242 while (ProgressMade) {
2243 ProgressMade = false;
2245 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2246 CopyRec &TheCopy = TryAgainList[i];
2249 bool Success = JoinCopy(TheCopy, Again);
2250 if (Success || !Again) {
2251 TheCopy.MI = 0; // Mark this one as done.
2252 ProgressMade = true;
2263 /// Return true if the two specified registers belong to different register
2264 /// classes. The registers may be either phys or virt regs.
2266 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2267 unsigned RegB) const {
2268 // Get the register classes for the first reg.
2269 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2270 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2271 "Shouldn't consider two physregs!");
2272 return !mri_->getRegClass(RegB)->contains(RegA);
2275 // Compare against the regclass for the second reg.
2276 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2277 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2278 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2279 return RegClassA != RegClassB;
2281 return !RegClassA->contains(RegB);
2284 /// lastRegisterUse - Returns the last use of the specific register between
2285 /// cycles Start and End or NULL if there are no uses.
2287 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2288 unsigned Reg, unsigned &UseIdx) const{
2290 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2291 MachineOperand *LastUse = NULL;
2292 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2293 E = mri_->use_end(); I != E; ++I) {
2294 MachineOperand &Use = I.getOperand();
2295 MachineInstr *UseMI = Use.getParent();
2296 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2297 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2299 // Ignore identity copies.
2301 unsigned Idx = li_->getInstructionIndex(UseMI);
2302 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2310 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2313 // Skip deleted instructions
2314 MachineInstr *MI = li_->getInstructionFromIndex(e);
2315 while ((e - InstrSlots::NUM) >= s && !MI) {
2316 e -= InstrSlots::NUM;
2317 MI = li_->getInstructionFromIndex(e);
2319 if (e < s || MI == NULL)
2322 // Ignore identity copies.
2323 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2324 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2326 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2327 MachineOperand &Use = MI->getOperand(i);
2328 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2329 tri_->regsOverlap(Use.getReg(), Reg)) {
2335 e -= InstrSlots::NUM;
2342 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2343 if (TargetRegisterInfo::isPhysicalRegister(reg))
2344 cerr << tri_->getName(reg);
2346 cerr << "%reg" << reg;
2349 void SimpleRegisterCoalescing::releaseMemory() {
2350 JoinedCopies.clear();
2351 ReMatCopies.clear();
2355 static bool isZeroLengthInterval(LiveInterval *li) {
2356 for (LiveInterval::Ranges::const_iterator
2357 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2358 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
2363 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2364 /// turn the copy into an implicit def.
2366 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2367 MachineBasicBlock *MBB,
2368 unsigned DstReg, unsigned SrcReg) {
2369 MachineInstr *CopyMI = &*I;
2370 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2371 if (!li_->hasInterval(SrcReg))
2373 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2374 if (!SrcInt.empty())
2376 if (!li_->hasInterval(DstReg))
2378 LiveInterval &DstInt = li_->getInterval(DstReg);
2379 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2380 DstInt.removeValNo(DstLR->valno);
2381 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2382 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2383 CopyMI->RemoveOperand(i);
2384 bool NoUse = mri_->use_empty(SrcReg);
2386 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2387 E = mri_->reg_end(); I != E; ) {
2388 assert(I.getOperand().isDef());
2389 MachineInstr *DefMI = &*I;
2391 // The implicit_def source has no other uses, delete it.
2392 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2393 li_->RemoveMachineInstrFromMaps(DefMI);
2394 DefMI->eraseFromParent();
2402 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2404 mri_ = &fn.getRegInfo();
2405 tm_ = &fn.getTarget();
2406 tri_ = tm_->getRegisterInfo();
2407 tii_ = tm_->getInstrInfo();
2408 li_ = &getAnalysis<LiveIntervals>();
2409 loopInfo = &getAnalysis<MachineLoopInfo>();
2411 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2412 << "********** Function: "
2413 << ((Value*)mf_->getFunction())->getName() << '\n';
2415 allocatableRegs_ = tri_->getAllocatableSet(fn);
2416 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2417 E = tri_->regclass_end(); I != E; ++I)
2418 allocatableRCRegs_.insert(std::make_pair(*I,
2419 tri_->getAllocatableSet(fn, *I)));
2421 // Join (coalesce) intervals if requested.
2422 if (EnableJoining) {
2425 DOUT << "********** INTERVALS POST JOINING **********\n";
2426 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2427 I->second->print(DOUT, tri_);
2433 // Perform a final pass over the instructions and compute spill weights
2434 // and remove identity moves.
2435 SmallVector<unsigned, 4> DeadDefs;
2436 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2437 mbbi != mbbe; ++mbbi) {
2438 MachineBasicBlock* mbb = mbbi;
2439 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2441 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2443 MachineInstr *MI = mii;
2444 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2445 if (JoinedCopies.count(MI)) {
2446 // Delete all coalesced copies.
2447 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2448 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2449 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2450 "Unrecognized copy instruction");
2451 DstReg = MI->getOperand(0).getReg();
2453 if (MI->registerDefIsDead(DstReg)) {
2454 LiveInterval &li = li_->getInterval(DstReg);
2455 if (!ShortenDeadCopySrcLiveRange(li, MI))
2456 ShortenDeadCopyLiveRange(li, MI);
2458 li_->RemoveMachineInstrFromMaps(MI);
2459 mii = mbbi->erase(mii);
2464 // Now check if this is a remat'ed def instruction which is now dead.
2465 if (ReMatDefs.count(MI)) {
2467 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2468 const MachineOperand &MO = MI->getOperand(i);
2471 unsigned Reg = MO.getReg();
2474 if (TargetRegisterInfo::isVirtualRegister(Reg))
2475 DeadDefs.push_back(Reg);
2478 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2479 !mri_->use_empty(Reg)) {
2485 while (!DeadDefs.empty()) {
2486 unsigned DeadDef = DeadDefs.back();
2487 DeadDefs.pop_back();
2488 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2490 li_->RemoveMachineInstrFromMaps(mii);
2491 mii = mbbi->erase(mii);
2497 // If the move will be an identity move delete it
2498 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2499 if (isMove && SrcReg == DstReg) {
2500 if (li_->hasInterval(SrcReg)) {
2501 LiveInterval &RegInt = li_->getInterval(SrcReg);
2502 // If def of this move instruction is dead, remove its live range
2503 // from the dstination register's live interval.
2504 if (MI->registerDefIsDead(DstReg)) {
2505 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2506 ShortenDeadCopyLiveRange(RegInt, MI);
2509 li_->RemoveMachineInstrFromMaps(MI);
2510 mii = mbbi->erase(mii);
2512 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2513 SmallSet<unsigned, 4> UniqueUses;
2514 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2515 const MachineOperand &mop = MI->getOperand(i);
2516 if (mop.isReg() && mop.getReg() &&
2517 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2518 unsigned reg = mop.getReg();
2519 // Multiple uses of reg by the same instruction. It should not
2520 // contribute to spill weight again.
2521 if (UniqueUses.count(reg) != 0)
2523 LiveInterval &RegInt = li_->getInterval(reg);
2525 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2526 UniqueUses.insert(reg);
2534 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2535 LiveInterval &LI = *I->second;
2536 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2537 // If the live interval length is essentially zero, i.e. in every live
2538 // range the use follows def immediately, it doesn't make sense to spill
2539 // it and hope it will be easier to allocate for this li.
2540 if (isZeroLengthInterval(&LI))
2541 LI.weight = HUGE_VALF;
2543 bool isLoad = false;
2544 SmallVector<LiveInterval*, 4> SpillIs;
2545 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2546 // If all of the definitions of the interval are re-materializable,
2547 // it is a preferred candidate for spilling. If non of the defs are
2548 // loads, then it's potentially very cheap to re-materialize.
2549 // FIXME: this gets much more complicated once we support non-trivial
2550 // re-materialization.
2558 // Slightly prefer live interval that has been assigned a preferred reg.
2562 // Divide the weight of the interval by its size. This encourages
2563 // spilling of intervals that are large and have few uses, and
2564 // discourages spilling of small intervals with many uses.
2565 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2573 /// print - Implement the dump method.
2574 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2578 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2579 return new SimpleRegisterCoalescing();
2582 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2583 DEFINING_FILE_FOR(SimpleRegisterCoalescing)