1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP,
103 MachineInstr *CopyMI) {
104 // Bail if there is no dst interval - can happen when merging physical subreg
106 if (!li_->hasInterval(CP.getDstReg()))
110 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
112 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
113 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
115 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
116 // the example above.
117 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
118 if (BLR == IntB.end()) return false;
119 VNInfo *BValNo = BLR->valno;
121 // Get the location that B is defined at. Two options: either this value has
122 // an unknown definition point or it is defined at CopyIdx. If unknown, we
124 if (!BValNo->getCopy()) return false;
125 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
127 // AValNo is the value number in A that defines the copy, A3 in the example.
128 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
129 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
130 // The live range might not exist after fun with physreg coalescing.
131 if (ALR == IntA.end()) return false;
132 VNInfo *AValNo = ALR->valno;
133 // If it's re-defined by an early clobber somewhere in the live range, then
134 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
136 // 172 %ECX<def> = MOV32rr %reg1039<kill>
137 // 180 INLINEASM <es:subl $5,$1
138 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
140 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
141 // 188 %EAX<def> = MOV32rr %EAX<kill>
142 // 196 %ECX<def> = MOV32rr %ECX<kill>
143 // 204 %ECX<def> = MOV32rr %ECX<kill>
144 // 212 %EAX<def> = MOV32rr %EAX<kill>
145 // 220 %EAX<def> = MOV32rr %EAX
146 // 228 %reg1039<def> = MOV32rr %ECX<kill>
147 // The early clobber operand ties ECX input to the ECX def.
149 // The live interval of ECX is represented as this:
150 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
151 // The coalescer has no idea there was a def in the middle of [174,230].
152 if (AValNo->hasRedefByEC())
155 // If AValNo is defined as a copy from IntB, we can potentially process this.
156 // Get the instruction that defines this value number.
157 if (!CP.isCoalescable(AValNo->getCopy()))
160 // Get the LiveRange in IntB that this value number starts with.
161 LiveInterval::iterator ValLR =
162 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
163 if (ValLR == IntB.end())
166 // Make sure that the end of the live range is inside the same block as
168 MachineInstr *ValLREndInst =
169 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
170 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
173 // Okay, we now know that ValLR ends in the same block that the CopyMI
174 // live-range starts. If there are no intervening live ranges between them in
175 // IntB, we can merge them.
176 if (ValLR+1 != BLR) return false;
178 // If a live interval is a physical register, conservatively check if any
179 // of its sub-registers is overlapping the live interval of the virtual
180 // register. If so, do not coalesce.
181 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
182 *tri_->getSubRegisters(IntB.reg)) {
183 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
184 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
186 dbgs() << "\t\tInterfere with sub-register ";
187 li_->getInterval(*SR).print(dbgs(), tri_);
194 dbgs() << "Extending: ";
195 IntB.print(dbgs(), tri_);
198 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
199 // We are about to delete CopyMI, so need to remove it as the 'instruction
200 // that defines this value #'. Update the valnum with the new defining
202 BValNo->def = FillerStart;
205 // Okay, we can merge them. We need to insert a new liverange:
206 // [ValLR.end, BLR.begin) of either value number, then we merge the
207 // two value numbers.
208 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
210 // If the IntB live range is assigned to a physical register, and if that
211 // physreg has sub-registers, update their live intervals as well.
212 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
213 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
214 if (!li_->hasInterval(*SR))
216 LiveInterval &SRLI = li_->getInterval(*SR);
217 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
218 SRLI.getNextValue(FillerStart, 0, true,
219 li_->getVNInfoAllocator())));
223 // Okay, merge "B1" into the same value number as "B0".
224 if (BValNo != ValLR->valno) {
225 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
228 dbgs() << " result = ";
229 IntB.print(dbgs(), tri_);
233 // If the source instruction was killing the source register before the
234 // merge, unset the isKill marker given the live range has been extended.
235 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
237 ValLREndInst->getOperand(UIdx).setIsKill(false);
240 // If the copy instruction was killing the destination register before the
241 // merge, find the last use and trim the live range. That will also add the
243 if (ALR->end == CopyIdx)
244 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
250 /// HasOtherReachingDefs - Return true if there are definitions of IntB
251 /// other than BValNo val# that can reach uses of AValno val# of IntA.
252 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
256 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
258 if (AI->valno != AValNo) continue;
259 LiveInterval::Ranges::iterator BI =
260 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
261 if (BI != IntB.ranges.begin())
263 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
264 if (BI->valno == BValNo)
266 // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
267 if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
269 if (BI->start <= AI->start && BI->end > AI->start)
271 if (BI->start > AI->start && BI->start < AI->end)
279 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
280 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
282 MachineOperand &MO = MI->getOperand(i);
283 if (MO.isReg() && MO.isImplicit())
284 NewMI->addOperand(MO);
288 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
289 /// IntA being the source and IntB being the dest, thus this defines a value
290 /// number in IntB. If the source value number (in IntA) is defined by a
291 /// commutable instruction and its other operand is coalesced to the copy dest
292 /// register, see if we can transform the copy into a noop by commuting the
293 /// definition. For example,
295 /// A3 = op A2 B0<kill>
297 /// B1 = A3 <- this copy
299 /// = op A3 <- more uses
303 /// B2 = op B0 A2<kill>
305 /// B1 = B2 <- now an identify copy
307 /// = op B2 <- more uses
309 /// This returns true if an interval was modified.
311 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
312 MachineInstr *CopyMI) {
313 // FIXME: For now, only eliminate the copy by commuting its def when the
314 // source register is a virtual register. We want to guard against cases
315 // where the copy is a back edge copy and commuting the def lengthen the
316 // live interval of the source register to the entire loop.
317 if (CP.isPhys() && CP.isFlipped())
320 // Bail if there is no dst interval.
321 if (!li_->hasInterval(CP.getDstReg()))
325 li_->getInstructionIndex(CopyMI).getDefIndex();
328 li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
330 li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
332 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
333 // the example above.
334 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
335 if (BLR == IntB.end()) return false;
336 VNInfo *BValNo = BLR->valno;
338 // Get the location that B is defined at. Two options: either this value has
339 // an unknown definition point or it is defined at CopyIdx. If unknown, we
341 if (!BValNo->getCopy()) return false;
342 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
344 // AValNo is the value number in A that defines the copy, A3 in the example.
345 LiveInterval::iterator ALR =
346 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
348 assert(ALR != IntA.end() && "Live range not found!");
349 VNInfo *AValNo = ALR->valno;
350 // If other defs can reach uses of this def, then it's not safe to perform
351 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
353 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
354 AValNo->isUnused() || AValNo->hasPHIKill())
356 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
359 const TargetInstrDesc &TID = DefMI->getDesc();
360 if (!TID.isCommutable())
362 // If DefMI is a two-address instruction then commuting it will change the
363 // destination register.
364 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
365 assert(DefIdx != -1);
367 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
369 unsigned Op1, Op2, NewDstIdx;
370 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
374 else if (Op2 == UseOpIdx)
379 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
380 unsigned NewReg = NewDstMO.getReg();
381 if (NewReg != IntB.reg || !NewDstMO.isKill())
384 // Make sure there are no other definitions of IntB that would reach the
385 // uses which the new definition can reach.
386 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
389 bool BHasSubRegs = false;
390 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
391 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
393 // Abort if the subregisters of IntB.reg have values that are not simply the
394 // clobbers from the superreg.
396 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
397 if (li_->hasInterval(*SR) &&
398 HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
401 // If some of the uses of IntA.reg is already coalesced away, return false.
402 // It's not possible to determine whether it's safe to perform the coalescing.
403 for (MachineRegisterInfo::use_nodbg_iterator UI =
404 mri_->use_nodbg_begin(IntA.reg),
405 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
406 MachineInstr *UseMI = &*UI;
407 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
408 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
409 if (ULR == IntA.end())
411 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
415 // At this point we have decided that it is legal to do this
416 // transformation. Start by commuting the instruction.
417 MachineBasicBlock *MBB = DefMI->getParent();
418 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
421 if (NewMI != DefMI) {
422 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
423 MBB->insert(DefMI, NewMI);
426 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
427 NewMI->getOperand(OpIdx).setIsKill();
429 bool BHasPHIKill = BValNo->hasPHIKill();
430 SmallVector<VNInfo*, 4> BDeadValNos;
431 std::map<SlotIndex, SlotIndex> BExtend;
433 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
441 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
443 BExtend[ALR->end] = BLR->end;
445 // Update uses of IntA of the specific Val# with IntB.
446 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
447 UE = mri_->use_end(); UI != UE;) {
448 MachineOperand &UseMO = UI.getOperand();
449 MachineInstr *UseMI = &*UI;
451 if (JoinedCopies.count(UseMI))
453 if (UseMI->isDebugValue()) {
454 // FIXME These don't have an instruction index. Not clear we have enough
455 // info to decide whether to do this replacement or not. For now do it.
456 UseMO.setReg(NewReg);
459 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
460 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
461 if (ULR == IntA.end() || ULR->valno != AValNo)
463 UseMO.setReg(NewReg);
466 if (UseMO.isKill()) {
468 UseMO.setIsKill(false);
470 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
471 if (UseMI->isCopy()) {
472 if (UseMI->getOperand(0).getReg() != IntB.reg ||
473 UseMI->getOperand(0).getSubReg())
475 } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
476 if (DstReg != IntB.reg || DstSubIdx)
480 // This copy will become a noop. If it's defining a new val#,
481 // remove that val# as well. However this live range is being
482 // extended to the end of the existing live range defined by the copy.
483 SlotIndex DefIdx = UseIdx.getDefIndex();
484 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
485 BHasPHIKill |= DLR->valno->hasPHIKill();
486 assert(DLR->valno->def == DefIdx);
487 BDeadValNos.push_back(DLR->valno);
488 BExtend[DLR->start] = DLR->end;
489 JoinedCopies.insert(UseMI);
492 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
493 // simply extend BLR if CopyMI doesn't end the range.
495 dbgs() << "Extending: ";
496 IntB.print(dbgs(), tri_);
499 // Remove val#'s defined by copies that will be coalesced away.
500 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
501 VNInfo *DeadVNI = BDeadValNos[i];
503 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
504 if (!li_->hasInterval(*SR))
506 LiveInterval &SRLI = li_->getInterval(*SR);
507 if (const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def))
508 SRLI.removeValNo(SRLR->valno);
511 IntB.removeValNo(BDeadValNos[i]);
514 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
516 VNInfo *ValNo = BValNo;
517 ValNo->def = AValNo->def;
519 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
521 if (AI->valno != AValNo) continue;
522 SlotIndex End = AI->end;
523 std::map<SlotIndex, SlotIndex>::iterator
524 EI = BExtend.find(End);
525 if (EI != BExtend.end())
527 IntB.addRange(LiveRange(AI->start, End, ValNo));
529 ValNo->setHasPHIKill(BHasPHIKill);
532 dbgs() << " result = ";
533 IntB.print(dbgs(), tri_);
534 dbgs() << "\nShortening: ";
535 IntA.print(dbgs(), tri_);
538 IntA.removeValNo(AValNo);
541 dbgs() << " result = ";
542 IntA.print(dbgs(), tri_);
550 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
551 /// fallthoughs to SuccMBB.
552 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
553 MachineBasicBlock *SuccMBB,
554 const TargetInstrInfo *tii_) {
557 MachineBasicBlock *TBB = 0, *FBB = 0;
558 SmallVector<MachineOperand, 4> Cond;
559 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
560 MBB->isSuccessor(SuccMBB);
563 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
564 /// from a physical register live interval as well as from the live intervals
565 /// of its sub-registers.
566 static void removeRange(LiveInterval &li,
567 SlotIndex Start, SlotIndex End,
568 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
569 li.removeRange(Start, End, true);
570 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
571 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
572 if (!li_->hasInterval(*SR))
574 LiveInterval &sli = li_->getInterval(*SR);
575 SlotIndex RemoveStart = Start;
576 SlotIndex RemoveEnd = Start;
578 while (RemoveEnd != End) {
579 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
582 RemoveEnd = (LR->end < End) ? LR->end : End;
583 sli.removeRange(RemoveStart, RemoveEnd, true);
584 RemoveStart = RemoveEnd;
590 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
591 /// as the copy instruction, trim the live interval to the last use and return
594 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
595 MachineBasicBlock *CopyMBB,
597 const LiveRange *LR) {
598 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
599 SlotIndex LastUseIdx;
600 MachineOperand *LastUse =
601 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
603 MachineInstr *LastUseMI = LastUse->getParent();
604 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
611 // r1025<dead> = r1024<kill>
612 if (MBBStart < LR->end)
613 removeRange(li, MBBStart, LR->end, li_, tri_);
617 // There are uses before the copy, just shorten the live range to the end
619 LastUse->setIsKill();
620 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
621 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
622 if ((LastUseMI->isCopy() && !LastUseMI->getOperand(0).getSubReg()) ||
623 (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
624 DstReg == li.reg && DstSubIdx == 0)) {
625 // Last use is itself an identity code.
626 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
628 LastUseMI->getOperand(DeadIdx).setIsDead();
634 if (LR->start <= MBBStart && LR->end > MBBStart) {
635 if (LR->start == li_->getZeroIndex()) {
636 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
637 // Live-in to the function but dead. Remove it from entry live-in set.
638 mf_->begin()->removeLiveIn(li.reg);
640 // FIXME: Shorten intervals in BBs that reaches this BB.
646 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
647 /// computation, replace the copy by rematerialize the definition.
648 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
651 MachineInstr *CopyMI) {
652 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
653 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
654 assert(SrcLR != SrcInt.end() && "Live range not found!");
655 VNInfo *ValNo = SrcLR->valno;
656 // If other defs can reach uses of this def, then it's not safe to perform
657 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
659 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
660 ValNo->isUnused() || ValNo->hasPHIKill())
662 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
663 assert(DefMI && "Defining instruction disappeared");
664 const TargetInstrDesc &TID = DefMI->getDesc();
665 if (!TID.isAsCheapAsAMove())
667 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
669 bool SawStore = false;
670 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
672 if (TID.getNumDefs() != 1)
674 if (!DefMI->isImplicitDef()) {
675 // Make sure the copy destination register class fits the instruction
676 // definition register class. The mismatch can happen as a result of earlier
677 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
678 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
679 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
680 if (mri_->getRegClass(DstReg) != RC)
682 } else if (!RC->contains(DstReg))
686 // If destination register has a sub-register index on it, make sure it mtches
687 // the instruction register class.
689 const TargetInstrDesc &TID = DefMI->getDesc();
690 if (TID.getNumDefs() != 1)
692 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
693 const TargetRegisterClass *DstSubRC =
694 DstRC->getSubRegisterRegClass(DstSubIdx);
695 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
698 else if (DefRC != DstSubRC)
702 RemoveCopyFlag(DstReg, CopyMI);
704 // If copy kills the source register, find the last use and propagate
706 bool checkForDeadDef = false;
707 MachineBasicBlock *MBB = CopyMI->getParent();
708 if (SrcLR->end == CopyIdx.getDefIndex())
709 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
710 checkForDeadDef = true;
713 MachineBasicBlock::iterator MII =
714 llvm::next(MachineBasicBlock::iterator(CopyMI));
715 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_);
716 MachineInstr *NewMI = prior(MII);
718 if (checkForDeadDef) {
719 // PR4090 fix: Trim interval failed because there was no use of the
720 // source interval in this MBB. If the def is in this MBB too then we
721 // should mark it dead:
722 if (DefMI->getParent() == MBB) {
723 DefMI->addRegisterDead(SrcInt.reg, tri_);
724 SrcLR->end = SrcLR->start.getNextSlot();
728 // CopyMI may have implicit operands, transfer them over to the newly
729 // rematerialized instruction. And update implicit def interval valnos.
730 for (unsigned i = CopyMI->getDesc().getNumOperands(),
731 e = CopyMI->getNumOperands(); i != e; ++i) {
732 MachineOperand &MO = CopyMI->getOperand(i);
733 if (MO.isReg() && MO.isImplicit())
734 NewMI->addOperand(MO);
736 RemoveCopyFlag(MO.getReg(), CopyMI);
739 TransferImplicitOps(CopyMI, NewMI);
740 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
741 CopyMI->eraseFromParent();
742 ReMatCopies.insert(CopyMI);
743 ReMatDefs.insert(DefMI);
744 DEBUG(dbgs() << "Remat: " << *NewMI);
749 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
750 /// update the subregister number if it is not zero. If DstReg is a
751 /// physical register and the existing subregister number of the def / use
752 /// being updated is not zero, make sure to set it to the correct physical
755 SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
756 bool DstIsPhys = CP.isPhys();
757 unsigned SrcReg = CP.getSrcReg();
758 unsigned DstReg = CP.getDstReg();
759 unsigned SubIdx = CP.getSubIdx();
761 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg);
762 MachineInstr *UseMI = I.skipInstruction();) {
763 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
766 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
767 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
768 CopySrcSubIdx, CopyDstSubIdx) &&
769 CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
770 CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
771 CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
772 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
777 SmallVector<unsigned,8> Ops;
779 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
780 bool Kills = false, Deads = false;
782 // Replace SrcReg with DstReg in all UseMI operands.
783 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
784 MachineOperand &MO = UseMI->getOperand(Ops[i]);
785 Kills |= MO.isKill();
786 Deads |= MO.isDead();
789 MO.substPhysReg(DstReg, *tri_);
791 MO.substVirtReg(DstReg, SubIdx, *tri_);
794 // This instruction is a copy that will be removed.
795 if (JoinedCopies.count(UseMI))
799 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
800 // read-modify-write of DstReg.
802 UseMI->addRegisterDead(DstReg, tri_);
803 else if (!Reads && Writes)
804 UseMI->addRegisterDefined(DstReg, tri_);
806 // Kill flags apply to the whole physical register.
807 if (DstIsPhys && Kills)
808 UseMI->addRegisterKilled(DstReg, tri_);
812 dbgs() << "\t\tupdated: ";
813 if (!UseMI->isDebugValue())
814 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
819 // After updating the operand, check if the machine instruction has
820 // become a copy. If so, update its val# information.
821 const TargetInstrDesc &TID = UseMI->getDesc();
822 if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
825 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
826 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
827 CopySrcSubIdx, CopyDstSubIdx) &&
828 CopySrcReg != CopyDstReg &&
829 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
830 allocatableRegs_[CopyDstReg])) {
831 LiveInterval &LI = li_->getInterval(CopyDstReg);
833 li_->getInstructionIndex(UseMI).getDefIndex();
834 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
835 if (DLR->valno->def == DefIdx)
836 DLR->valno->setCopy(UseMI);
842 /// removeIntervalIfEmpty - Check if the live interval of a physical register
843 /// is empty, if so remove it and also remove the empty intervals of its
844 /// sub-registers. Return true if live interval is removed.
845 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
846 const TargetRegisterInfo *tri_) {
848 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
849 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
850 if (!li_->hasInterval(*SR))
852 LiveInterval &sli = li_->getInterval(*SR);
854 li_->removeInterval(*SR);
856 li_->removeInterval(li.reg);
862 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
863 /// Return true if live interval is removed.
864 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
865 MachineInstr *CopyMI) {
866 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
867 LiveInterval::iterator MLR =
868 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
870 return false; // Already removed by ShortenDeadCopySrcLiveRange.
871 SlotIndex RemoveStart = MLR->start;
872 SlotIndex RemoveEnd = MLR->end;
873 SlotIndex DefIdx = CopyIdx.getDefIndex();
874 // Remove the liverange that's defined by this.
875 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
876 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
877 return removeIntervalIfEmpty(li, li_, tri_);
882 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
883 /// the val# it defines. If the live interval becomes empty, remove it as well.
884 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
885 MachineInstr *DefMI) {
886 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
887 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
888 if (DefIdx != MLR->valno->def)
890 li.removeValNo(MLR->valno);
891 return removeIntervalIfEmpty(li, li_, tri_);
894 void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg,
895 const MachineInstr *CopyMI) {
896 SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
897 if (li_->hasInterval(DstReg)) {
898 LiveInterval &LI = li_->getInterval(DstReg);
899 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
900 if (LR->valno->getCopy() == CopyMI)
901 LR->valno->setCopy(0);
903 if (!TargetRegisterInfo::isPhysicalRegister(DstReg))
905 for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) {
906 if (!li_->hasInterval(*AS))
908 LiveInterval &LI = li_->getInterval(*AS);
909 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx))
910 if (LR->valno->getCopy() == CopyMI)
911 LR->valno->setCopy(0);
915 /// PropagateDeadness - Propagate the dead marker to the instruction which
916 /// defines the val#.
917 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
918 SlotIndex &LRStart, LiveIntervals *li_,
919 const TargetRegisterInfo* tri_) {
920 MachineInstr *DefMI =
921 li_->getInstructionFromIndex(LRStart.getDefIndex());
922 if (DefMI && DefMI != CopyMI) {
923 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg);
925 DefMI->getOperand(DeadIdx).setIsDead();
927 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
928 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
929 LRStart = LRStart.getNextSlot();
933 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
934 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
935 /// ends the live range there. If there isn't another use, then this live range
936 /// is dead. Return true if live interval is removed.
938 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
939 MachineInstr *CopyMI) {
940 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
941 if (CopyIdx == SlotIndex()) {
942 // FIXME: special case: function live in. It can be a general case if the
943 // first instruction index starts at > 0 value.
944 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
945 // Live-in to the function but dead. Remove it from entry live-in set.
946 if (mf_->begin()->isLiveIn(li.reg))
947 mf_->begin()->removeLiveIn(li.reg);
948 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
949 removeRange(li, LR->start, LR->end, li_, tri_);
950 return removeIntervalIfEmpty(li, li_, tri_);
953 LiveInterval::iterator LR =
954 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
956 // Livein but defined by a phi.
959 SlotIndex RemoveStart = LR->start;
960 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
961 if (LR->end > RemoveEnd)
962 // More uses past this copy? Nothing to do.
965 // If there is a last use in the same bb, we can't remove the live range.
966 // Shorten the live interval and return.
967 MachineBasicBlock *CopyMBB = CopyMI->getParent();
968 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
971 // There are other kills of the val#. Nothing to do.
972 if (!li.isOnlyLROfValNo(LR))
975 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
976 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
977 // If the live range starts in another mbb and the copy mbb is not a fall
978 // through mbb, then we can only cut the range from the beginning of the
980 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
982 if (LR->valno->def == RemoveStart) {
983 // If the def MI defines the val# and this copy is the only kill of the
984 // val#, then propagate the dead marker.
985 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
989 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
990 return removeIntervalIfEmpty(li, li_, tri_);
994 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
995 /// two virtual registers from different register classes.
997 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
999 const TargetRegisterClass *SrcRC,
1000 const TargetRegisterClass *DstRC,
1001 const TargetRegisterClass *NewRC) {
1002 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
1003 // This heuristics is good enough in practice, but it's obviously not *right*.
1004 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1005 // out all but the most restrictive register classes.
1006 if (NewRCCount > 4 ||
1007 // Early exit if the function is fairly small, coalesce aggressively if
1008 // that's the case. For really special register classes with 3 or
1009 // fewer registers, be a bit more careful.
1010 (li_->getFuncInstructionCount() / NewRCCount) < 8)
1012 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1013 LiveInterval &DstInt = li_->getInterval(DstReg);
1014 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
1015 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
1016 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
1018 // Estimate *register use density*. If it doubles or more, abort.
1019 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
1020 mri_->use_nodbg_end());
1021 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
1022 mri_->use_nodbg_end());
1023 unsigned NewUses = SrcUses + DstUses;
1024 unsigned NewSize = SrcSize + DstSize;
1025 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1026 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1027 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1030 if (DstRC != NewRC && DstSize > NewRCCount) {
1031 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1032 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1039 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1040 /// which are the src/dst of the copy instruction CopyMI. This returns true
1041 /// if the copy was successfully coalesced away. If it is not currently
1042 /// possible to coalesce this interval, but it may be possible if other
1043 /// things get coalesced, then it returns true by reference in 'Again'.
1044 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1045 MachineInstr *CopyMI = TheCopy.MI;
1048 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1049 return false; // Already done.
1051 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1053 CoalescerPair CP(*tii_, *tri_);
1054 if (!CP.setRegisters(CopyMI)) {
1055 DEBUG(dbgs() << "\tNot coalescable.\n");
1059 // If they are already joined we continue.
1060 if (CP.getSrcReg() == CP.getDstReg()) {
1061 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1062 return false; // Not coalescable.
1065 DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg());
1067 // Enforce policies.
1069 DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n");
1070 // Only coalesce to allocatable physreg.
1071 if (!allocatableRegs_[CP.getDstReg()]) {
1072 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1073 return false; // Not coalescable.
1077 dbgs() << " with reg%" << CP.getDstReg();
1079 dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx());
1080 dbgs() << " to " << CP.getNewRC()->getName() << "\n";
1083 // Avoid constraining virtual register regclass too much.
1084 if (CP.isCrossClass()) {
1085 if (DisableCrossClassJoin) {
1086 DEBUG(dbgs() << "\tCross-class joins disabled.\n");
1089 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
1090 mri_->getRegClass(CP.getSrcReg()),
1091 mri_->getRegClass(CP.getDstReg()),
1093 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1094 << CP.getNewRC()->getName() << ".\n");
1095 Again = true; // May be possible to coalesce later.
1100 // When possible, let DstReg be the larger interval.
1101 if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
1102 li_->getInterval(CP.getDstReg()).ranges.size())
1106 // We need to be careful about coalescing a source physical register with a
1107 // virtual register. Once the coalescing is done, it cannot be broken and
1108 // these are not spillable! If the destination interval uses are far away,
1109 // think twice about coalescing them!
1110 // FIXME: Why are we skipping this test for partial copies?
1111 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1112 if (!CP.isPartial() && CP.isPhys()) {
1113 LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
1115 // Don't join with physregs that have a ridiculous number of live
1116 // ranges. The data structure performance is really bad when that
1118 if (li_->hasInterval(CP.getDstReg()) &&
1119 li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1120 mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
1123 << "\tPhysical register live interval too complicated, abort!\n");
1127 const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
1128 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1129 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1130 if (Length > Threshold &&
1131 std::distance(mri_->use_nodbg_begin(CP.getSrcReg()),
1132 mri_->use_nodbg_end()) * Threshold < Length) {
1133 // Before giving up coalescing, if definition of source is defined by
1134 // trivial computation, try rematerializing it.
1135 if (!CP.isFlipped() &&
1136 ReMaterializeTrivialDef(JoinVInt, CP.getDstReg(), 0, CopyMI))
1139 mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
1141 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1142 Again = true; // May be possible to coalesce later.
1147 // Okay, attempt to join these two intervals. On failure, this returns false.
1148 // Otherwise, if one of the intervals being joined is a physreg, this method
1149 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1150 // been modified, so we can use this information below to update aliases.
1151 if (!JoinIntervals(CP)) {
1152 // Coalescing failed.
1154 // If definition of source is defined by trivial computation, try
1155 // rematerializing it.
1156 if (!CP.isFlipped() &&
1157 ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()),
1158 CP.getDstReg(), 0, CopyMI))
1161 // If we can eliminate the copy without merging the live ranges, do so now.
1162 if (!CP.isPartial()) {
1163 if (AdjustCopiesBackFrom(CP, CopyMI) ||
1164 RemoveCopyByCommutingDef(CP, CopyMI)) {
1165 JoinedCopies.insert(CopyMI);
1166 DEBUG(dbgs() << "\tTrivial!\n");
1171 // Otherwise, we are unable to join the intervals.
1172 DEBUG(dbgs() << "\tInterference!\n");
1173 Again = true; // May be possible to coalesce later.
1177 // Coalescing to a virtual register that is of a sub-register class of the
1178 // other. Make sure the resulting register is set to the right register class.
1179 if (CP.isCrossClass()) {
1181 mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
1184 // Remember to delete the copy instruction.
1185 JoinedCopies.insert(CopyMI);
1187 UpdateRegDefsUses(CP);
1189 // If we have extended the live range of a physical register, make sure we
1190 // update live-in lists as well.
1192 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1193 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
1194 // ranges for this, and they are preserved.
1195 LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
1196 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1198 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1199 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1200 MachineBasicBlock &block = *BlockSeq[idx];
1201 if (!block.isLiveIn(CP.getDstReg()))
1202 block.addLiveIn(CP.getDstReg());
1208 // SrcReg is guarateed to be the register whose live interval that is
1210 li_->removeInterval(CP.getSrcReg());
1212 // Update regalloc hint.
1213 tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
1216 LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
1217 dbgs() << "\tJoined. Result = ";
1218 DstInt.print(dbgs(), tri_);
1226 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1227 /// compute what the resultant value numbers for each value in the input two
1228 /// ranges will be. This is complicated by copies between the two which can
1229 /// and will commonly cause multiple value numbers to be merged into one.
1231 /// VN is the value number that we're trying to resolve. InstDefiningValue
1232 /// keeps track of the new InstDefiningValue assignment for the result
1233 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1234 /// whether a value in this or other is a copy from the opposite set.
1235 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1236 /// already been assigned.
1238 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1239 /// contains the value number the copy is from.
1241 static unsigned ComputeUltimateVN(VNInfo *VNI,
1242 SmallVector<VNInfo*, 16> &NewVNInfo,
1243 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1244 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1245 SmallVector<int, 16> &ThisValNoAssignments,
1246 SmallVector<int, 16> &OtherValNoAssignments) {
1247 unsigned VN = VNI->id;
1249 // If the VN has already been computed, just return it.
1250 if (ThisValNoAssignments[VN] >= 0)
1251 return ThisValNoAssignments[VN];
1252 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1254 // If this val is not a copy from the other val, then it must be a new value
1255 // number in the destination.
1256 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1257 if (I == ThisFromOther.end()) {
1258 NewVNInfo.push_back(VNI);
1259 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1261 VNInfo *OtherValNo = I->second;
1263 // Otherwise, this *is* a copy from the RHS. If the other side has already
1264 // been computed, return it.
1265 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1266 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1268 // Mark this value number as currently being computed, then ask what the
1269 // ultimate value # of the other value is.
1270 ThisValNoAssignments[VN] = -2;
1271 unsigned UltimateVN =
1272 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1273 OtherValNoAssignments, ThisValNoAssignments);
1274 return ThisValNoAssignments[VN] = UltimateVN;
1277 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1279 bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
1280 LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
1281 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
1283 // If a live interval is a physical register, check for interference with any
1284 // aliases. The interference check implemented here is a bit more conservative
1285 // than the full interfeence check below. We allow overlapping live ranges
1286 // only when one is a copy of the other.
1288 for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){
1289 if (!li_->hasInterval(*AS))
1291 const LiveInterval &LHS = li_->getInterval(*AS);
1292 LiveInterval::const_iterator LI = LHS.begin();
1293 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1295 LI = std::lower_bound(LI, LHS.end(), RI->start);
1296 // Does LHS have an overlapping live range starting before RI?
1297 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1298 (RI->start != RI->valno->def ||
1299 !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) {
1301 dbgs() << "\t\tInterference from alias: ";
1302 LHS.print(dbgs(), tri_);
1303 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1308 // Check that LHS ranges beginning in this range are copies.
1309 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1310 if (LI->start != LI->valno->def ||
1311 !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) {
1313 dbgs() << "\t\tInterference from alias: ";
1314 LHS.print(dbgs(), tri_);
1315 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1324 // Compute the final value assignment, assuming that the live ranges can be
1326 SmallVector<int, 16> LHSValNoAssignments;
1327 SmallVector<int, 16> RHSValNoAssignments;
1328 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1329 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1330 SmallVector<VNInfo*, 16> NewVNInfo;
1332 LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
1333 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
1335 // Loop over the value numbers of the LHS, seeing if any are defined from
1337 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1340 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
1343 // Never join with a register that has EarlyClobber redefs.
1344 if (VNI->hasRedefByEC())
1347 // DstReg is known to be a register in the LHS interval. If the src is
1348 // from the RHS interval, we can use its value #.
1349 if (!CP.isCoalescable(VNI->getCopy()))
1352 // Figure out the value # from the RHS.
1353 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1354 // The copy could be to an aliased physreg.
1356 LHSValsDefinedFromRHS[VNI] = lr->valno;
1359 // Loop over the value numbers of the RHS, seeing if any are defined from
1361 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1364 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
1367 // Never join with a register that has EarlyClobber redefs.
1368 if (VNI->hasRedefByEC())
1371 // DstReg is known to be a register in the RHS interval. If the src is
1372 // from the LHS interval, we can use its value #.
1373 if (!CP.isCoalescable(VNI->getCopy()))
1376 // Figure out the value # from the LHS.
1377 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1378 // The copy could be to an aliased physreg.
1380 RHSValsDefinedFromLHS[VNI] = lr->valno;
1383 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1384 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1385 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1387 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1390 unsigned VN = VNI->id;
1391 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1393 ComputeUltimateVN(VNI, NewVNInfo,
1394 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1395 LHSValNoAssignments, RHSValNoAssignments);
1397 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1400 unsigned VN = VNI->id;
1401 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1403 // If this value number isn't a copy from the LHS, it's a new number.
1404 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1405 NewVNInfo.push_back(VNI);
1406 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1410 ComputeUltimateVN(VNI, NewVNInfo,
1411 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1412 RHSValNoAssignments, LHSValNoAssignments);
1415 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1416 // interval lists to see if these intervals are coalescable.
1417 LiveInterval::const_iterator I = LHS.begin();
1418 LiveInterval::const_iterator IE = LHS.end();
1419 LiveInterval::const_iterator J = RHS.begin();
1420 LiveInterval::const_iterator JE = RHS.end();
1422 // Skip ahead until the first place of potential sharing.
1423 if (I != IE && J != JE) {
1424 if (I->start < J->start) {
1425 I = std::upper_bound(I, IE, J->start);
1426 if (I != LHS.begin()) --I;
1427 } else if (J->start < I->start) {
1428 J = std::upper_bound(J, JE, I->start);
1429 if (J != RHS.begin()) --J;
1433 while (I != IE && J != JE) {
1434 // Determine if these two live ranges overlap.
1436 if (I->start < J->start) {
1437 Overlaps = I->end > J->start;
1439 Overlaps = J->end > I->start;
1442 // If so, check value # info to determine if they are really different.
1444 // If the live range overlap will map to the same value number in the
1445 // result liverange, we can still coalesce them. If not, we can't.
1446 if (LHSValNoAssignments[I->valno->id] !=
1447 RHSValNoAssignments[J->valno->id])
1449 // If it's re-defined by an early clobber somewhere in the live range,
1450 // then conservatively abort coalescing.
1451 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
1455 if (I->end < J->end)
1461 // Update kill info. Some live ranges are extended due to copy coalescing.
1462 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1463 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1464 VNInfo *VNI = I->first;
1465 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1466 if (VNI->hasPHIKill())
1467 NewVNInfo[LHSValID]->setHasPHIKill(true);
1470 // Update kill info. Some live ranges are extended due to copy coalescing.
1471 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1472 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1473 VNInfo *VNI = I->first;
1474 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1475 if (VNI->hasPHIKill())
1476 NewVNInfo[RHSValID]->setHasPHIKill(true);
1479 if (LHSValNoAssignments.empty())
1480 LHSValNoAssignments.push_back(-1);
1481 if (RHSValNoAssignments.empty())
1482 RHSValNoAssignments.push_back(-1);
1484 // If we get here, we know that we can coalesce the live ranges. Ask the
1485 // intervals to coalesce themselves now.
1486 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1492 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1493 // depth of the basic block (the unsigned), and then on the MBB number.
1494 struct DepthMBBCompare {
1495 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1496 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1497 // Deeper loops first
1498 if (LHS.first != RHS.first)
1499 return LHS.first > RHS.first;
1501 // Prefer blocks that are more connected in the CFG. This takes care of
1502 // the most difficult copies first while intervals are short.
1503 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1504 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1508 // As a last resort, sort by block number.
1509 return LHS.second->getNumber() < RHS.second->getNumber();
1514 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1515 std::vector<CopyRec> &TryAgain) {
1516 DEBUG(dbgs() << MBB->getName() << ":\n");
1518 std::vector<CopyRec> VirtCopies;
1519 std::vector<CopyRec> PhysCopies;
1520 std::vector<CopyRec> ImpDefCopies;
1521 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1523 MachineInstr *Inst = MII++;
1525 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1526 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1527 bool isInsUndef = false;
1528 if (Inst->isCopy()) {
1529 DstReg = Inst->getOperand(0).getReg();
1530 SrcReg = Inst->getOperand(1).getReg();
1531 } else if (Inst->isSubregToReg()) {
1532 DstReg = Inst->getOperand(0).getReg();
1533 SrcReg = Inst->getOperand(2).getReg();
1534 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1537 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1538 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1540 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
1541 ImpDefCopies.push_back(CopyRec(Inst, 0));
1542 else if (SrcIsPhys || DstIsPhys)
1543 PhysCopies.push_back(CopyRec(Inst, 0));
1545 VirtCopies.push_back(CopyRec(Inst, 0));
1548 // Try coalescing implicit copies and insert_subreg <undef> first,
1549 // followed by copies to / from physical registers, then finally copies
1550 // from virtual registers to virtual registers.
1551 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1552 CopyRec &TheCopy = ImpDefCopies[i];
1554 if (!JoinCopy(TheCopy, Again))
1556 TryAgain.push_back(TheCopy);
1558 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1559 CopyRec &TheCopy = PhysCopies[i];
1561 if (!JoinCopy(TheCopy, Again))
1563 TryAgain.push_back(TheCopy);
1565 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1566 CopyRec &TheCopy = VirtCopies[i];
1568 if (!JoinCopy(TheCopy, Again))
1570 TryAgain.push_back(TheCopy);
1574 void SimpleRegisterCoalescing::joinIntervals() {
1575 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1577 std::vector<CopyRec> TryAgainList;
1578 if (loopInfo->empty()) {
1579 // If there are no loops in the function, join intervals in function order.
1580 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1582 CopyCoalesceInMBB(I, TryAgainList);
1584 // Otherwise, join intervals in inner loops before other intervals.
1585 // Unfortunately we can't just iterate over loop hierarchy here because
1586 // there may be more MBB's than BB's. Collect MBB's for sorting.
1588 // Join intervals in the function prolog first. We want to join physical
1589 // registers with virtual registers before the intervals got too long.
1590 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1591 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1592 MachineBasicBlock *MBB = I;
1593 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1596 // Sort by loop depth.
1597 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1599 // Finally, join intervals in loop nest order.
1600 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1601 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1604 // Joining intervals can allow other intervals to be joined. Iteratively join
1605 // until we make no progress.
1606 bool ProgressMade = true;
1607 while (ProgressMade) {
1608 ProgressMade = false;
1610 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1611 CopyRec &TheCopy = TryAgainList[i];
1616 bool Success = JoinCopy(TheCopy, Again);
1617 if (Success || !Again) {
1618 TheCopy.MI = 0; // Mark this one as done.
1619 ProgressMade = true;
1625 /// Return true if the two specified registers belong to different register
1626 /// classes. The registers may be either phys or virt regs.
1628 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1629 unsigned RegB) const {
1630 // Get the register classes for the first reg.
1631 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1632 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1633 "Shouldn't consider two physregs!");
1634 return !mri_->getRegClass(RegB)->contains(RegA);
1637 // Compare against the regclass for the second reg.
1638 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
1639 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
1640 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
1641 return RegClassA != RegClassB;
1643 return !RegClassA->contains(RegB);
1646 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
1647 /// between cycles Start and End or NULL if there are no uses.
1649 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
1652 SlotIndex &UseIdx) const{
1653 UseIdx = SlotIndex();
1654 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1655 MachineOperand *LastUse = NULL;
1656 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
1657 E = mri_->use_nodbg_end(); I != E; ++I) {
1658 MachineOperand &Use = I.getOperand();
1659 MachineInstr *UseMI = Use.getParent();
1660 if (UseMI->isIdentityCopy())
1662 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1663 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1664 SrcReg == DstReg && SrcSubIdx == DstSubIdx)
1665 // Ignore identity copies.
1667 SlotIndex Idx = li_->getInstructionIndex(UseMI);
1668 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
1669 // that compares higher than any other interval.
1670 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1672 UseIdx = Idx.getUseIndex();
1678 SlotIndex s = Start;
1679 SlotIndex e = End.getPrevSlot().getBaseIndex();
1681 // Skip deleted instructions
1682 MachineInstr *MI = li_->getInstructionFromIndex(e);
1683 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
1684 e = e.getPrevIndex();
1685 MI = li_->getInstructionFromIndex(e);
1687 if (e < s || MI == NULL)
1690 // Ignore identity copies.
1691 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1692 if (!MI->isIdentityCopy() &&
1693 !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1694 SrcReg == DstReg && SrcSubIdx == DstSubIdx))
1695 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1696 MachineOperand &Use = MI->getOperand(i);
1697 if (Use.isReg() && Use.isUse() && Use.getReg() &&
1698 tri_->regsOverlap(Use.getReg(), Reg)) {
1699 UseIdx = e.getUseIndex();
1704 e = e.getPrevIndex();
1710 void SimpleRegisterCoalescing::releaseMemory() {
1711 JoinedCopies.clear();
1712 ReMatCopies.clear();
1716 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1718 mri_ = &fn.getRegInfo();
1719 tm_ = &fn.getTarget();
1720 tri_ = tm_->getRegisterInfo();
1721 tii_ = tm_->getInstrInfo();
1722 li_ = &getAnalysis<LiveIntervals>();
1723 AA = &getAnalysis<AliasAnalysis>();
1724 loopInfo = &getAnalysis<MachineLoopInfo>();
1726 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1727 << "********** Function: "
1728 << ((Value*)mf_->getFunction())->getName() << '\n');
1730 allocatableRegs_ = tri_->getAllocatableSet(fn);
1731 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
1732 E = tri_->regclass_end(); I != E; ++I)
1733 allocatableRCRegs_.insert(std::make_pair(*I,
1734 tri_->getAllocatableSet(fn, *I)));
1736 // Join (coalesce) intervals if requested.
1737 if (EnableJoining) {
1740 dbgs() << "********** INTERVALS POST JOINING **********\n";
1741 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
1743 I->second->print(dbgs(), tri_);
1749 // Perform a final pass over the instructions and compute spill weights
1750 // and remove identity moves.
1751 SmallVector<unsigned, 4> DeadDefs;
1752 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1753 mbbi != mbbe; ++mbbi) {
1754 MachineBasicBlock* mbb = mbbi;
1755 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1757 MachineInstr *MI = mii;
1758 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1759 if (JoinedCopies.count(MI)) {
1760 // Delete all coalesced copies.
1761 bool DoDelete = true;
1762 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1763 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1764 SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1765 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1766 // Do not delete extract_subreg, insert_subreg of physical
1767 // registers unless the definition is dead. e.g.
1768 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1769 // or else the scavenger may complain. LowerSubregs will
1770 // delete them later.
1773 if (MI->allDefsAreDead()) {
1774 LiveInterval &li = li_->getInterval(SrcReg);
1775 if (!ShortenDeadCopySrcLiveRange(li, MI))
1776 ShortenDeadCopyLiveRange(li, MI);
1780 mii = llvm::next(mii);
1782 li_->RemoveMachineInstrFromMaps(MI);
1783 mii = mbbi->erase(mii);
1789 // Now check if this is a remat'ed def instruction which is now dead.
1790 if (ReMatDefs.count(MI)) {
1792 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1793 const MachineOperand &MO = MI->getOperand(i);
1796 unsigned Reg = MO.getReg();
1799 if (TargetRegisterInfo::isVirtualRegister(Reg))
1800 DeadDefs.push_back(Reg);
1803 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1804 !mri_->use_nodbg_empty(Reg)) {
1810 while (!DeadDefs.empty()) {
1811 unsigned DeadDef = DeadDefs.back();
1812 DeadDefs.pop_back();
1813 RemoveDeadDef(li_->getInterval(DeadDef), MI);
1815 li_->RemoveMachineInstrFromMaps(mii);
1816 mii = mbbi->erase(mii);
1822 // If the move will be an identity move delete it
1823 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
1824 if (MI->isIdentityCopy() ||
1825 (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
1826 if (li_->hasInterval(SrcReg)) {
1827 LiveInterval &RegInt = li_->getInterval(SrcReg);
1828 // If def of this move instruction is dead, remove its live range
1829 // from the destination register's live interval.
1830 if (MI->allDefsAreDead()) {
1831 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
1832 ShortenDeadCopyLiveRange(RegInt, MI);
1835 li_->RemoveMachineInstrFromMaps(MI);
1836 mii = mbbi->erase(mii);
1843 // Check for now unnecessary kill flags.
1844 if (li_->isNotInMIMap(MI)) continue;
1845 SlotIndex DefIdx = li_->getInstructionIndex(MI).getDefIndex();
1846 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1847 MachineOperand &MO = MI->getOperand(i);
1848 if (!MO.isReg() || !MO.isKill()) continue;
1849 unsigned reg = MO.getReg();
1850 if (!reg || !li_->hasInterval(reg)) continue;
1851 if (!li_->getInterval(reg).killedAt(DefIdx))
1852 MO.setIsKill(false);
1861 /// print - Implement the dump method.
1862 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
1866 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1867 return new SimpleRegisterCoalescing();
1870 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1871 DEFINING_FILE_FOR(SimpleRegisterCoalescing)