1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "llvm/CodeGen/SimpleRegisterCoalescing.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "VirtRegMap.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
46 EnableJoining("join-liveintervals",
47 cl::desc("Coalesce copies (default=true)"),
50 RegisterPass<SimpleRegisterCoalescing>
51 X("simple-register-coalescing", "Simple Register Coalescing");
53 // Declare that we implement the RegisterCoalescer interface
54 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
57 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
59 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
60 //AU.addPreserved<LiveVariables>();
61 AU.addPreserved<LiveIntervals>();
62 AU.addPreservedID(PHIEliminationID);
63 AU.addPreservedID(TwoAddressInstructionPassID);
64 AU.addRequired<LiveVariables>();
65 AU.addRequired<LiveIntervals>();
66 AU.addRequired<LoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
71 /// being the source and IntB being the dest, thus this defines a value number
72 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
73 /// see if we can merge these two pieces of B into a single value number,
74 /// eliminating a copy. For example:
78 /// B1 = A3 <- this copy
80 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
81 /// value number to be replaced with B0 (which simplifies the B liveinterval).
83 /// This returns true if an interval was modified.
85 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
86 MachineInstr *CopyMI) {
87 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
89 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
91 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
92 VNInfo *BValNo = BLR->valno;
94 // Get the location that B is defined at. Two options: either this value has
95 // an unknown definition point or it is defined at CopyIdx. If unknown, we
97 if (!BValNo->reg) return false;
98 assert(BValNo->def == CopyIdx &&
99 "Copy doesn't define the value?");
101 // AValNo is the value number in A that defines the copy, A0 in the example.
102 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
103 VNInfo *AValNo = AValLR->valno;
105 // If AValNo is defined as a copy from IntB, we can potentially process this.
107 // Get the instruction that defines this value number.
108 unsigned SrcReg = AValNo->reg;
109 if (!SrcReg) return false; // Not defined by a copy.
111 // If the value number is not defined by a copy instruction, ignore it.
113 // If the source register comes from an interval other than IntB, we can't
115 if (rep(SrcReg) != IntB.reg) return false;
117 // Get the LiveRange in IntB that this value number starts with.
118 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
120 // Make sure that the end of the live range is inside the same block as
122 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
124 ValLREndInst->getParent() != CopyMI->getParent()) return false;
126 // Okay, we now know that ValLR ends in the same block that the CopyMI
127 // live-range starts. If there are no intervening live ranges between them in
128 // IntB, we can merge them.
129 if (ValLR+1 != BLR) return false;
131 // If a live interval is a physical register, conservatively check if any
132 // of its sub-registers is overlapping the live interval of the virtual
133 // register. If so, do not coalesce.
134 if (MRegisterInfo::isPhysicalRegister(IntB.reg) &&
135 *mri_->getSubRegisters(IntB.reg)) {
136 for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR)
137 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
138 DOUT << "Interfere with sub-register ";
139 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
144 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
146 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
147 // We are about to delete CopyMI, so need to remove it as the 'instruction
148 // that defines this value #'. Update the the valnum with the new defining
150 BValNo->def = FillerStart;
153 // Okay, we can merge them. We need to insert a new liverange:
154 // [ValLR.end, BLR.begin) of either value number, then we merge the
155 // two value numbers.
156 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
158 // If the IntB live range is assigned to a physical register, and if that
159 // physreg has aliases,
160 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
161 // Update the liveintervals of sub-registers.
162 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
163 LiveInterval &AliasLI = li_->getInterval(*AS);
164 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
165 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
169 // Okay, merge "B1" into the same value number as "B0".
170 if (BValNo != ValLR->valno)
171 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
172 DOUT << " result = "; IntB.print(DOUT, mri_);
175 // If the source instruction was killing the source register before the
176 // merge, unset the isKill marker given the live range has been extended.
177 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
179 ValLREndInst->getOperand(UIdx).unsetIsKill();
181 // Finally, delete the copy instruction.
182 li_->RemoveMachineInstrFromMaps(CopyMI);
183 CopyMI->eraseFromParent();
188 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
189 /// which are the src/dst of the copy instruction CopyMI. This returns true
190 /// if the copy was successfully coalesced away, or if it is never possible
191 /// to coalesce this copy, due to register constraints. It returns
192 /// false if it is not currently possible to coalesce this interval, but
193 /// it may be possible if other things get coalesced.
194 bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI,
195 unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
196 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
198 // Get representative registers.
199 unsigned repSrcReg = rep(SrcReg);
200 unsigned repDstReg = rep(DstReg);
202 // If they are already joined we continue.
203 if (repSrcReg == repDstReg) {
204 DOUT << "\tCopy already coalesced.\n";
205 return true; // Not coalescable.
208 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
209 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
210 if (PhysOnly && !SrcIsPhys && !DstIsPhys)
211 // Only joining physical registers with virtual registers in this round.
214 // If they are both physical registers, we cannot join them.
215 if (SrcIsPhys && DstIsPhys) {
216 DOUT << "\tCan not coalesce physregs.\n";
217 return true; // Not coalescable.
220 // We only join virtual registers with allocatable physical registers.
221 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
222 DOUT << "\tSrc reg is unallocatable physreg.\n";
223 return true; // Not coalescable.
225 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
226 DOUT << "\tDst reg is unallocatable physreg.\n";
227 return true; // Not coalescable.
230 // If they are not of the same register class, we cannot join them.
231 if (differingRegisterClasses(repSrcReg, repDstReg)) {
232 DOUT << "\tSrc/Dest are different register classes.\n";
233 return true; // Not coalescable.
236 LiveInterval &SrcInt = li_->getInterval(repSrcReg);
237 LiveInterval &DstInt = li_->getInterval(repDstReg);
238 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
239 "Register mapping is horribly broken!");
241 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
242 DOUT << " and "; DstInt.print(DOUT, mri_);
245 // Check if it is necessary to propagate "isDead" property before intervals
247 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
248 bool isDead = mopd->isDead();
249 bool isShorten = false;
250 unsigned SrcStart = 0, RemoveStart = 0;
251 unsigned SrcEnd = 0, RemoveEnd = 0;
253 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
254 LiveInterval::iterator SrcLR =
255 SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx));
256 RemoveStart = SrcStart = SrcLR->start;
257 RemoveEnd = SrcEnd = SrcLR->end;
258 // The instruction which defines the src is only truly dead if there are
259 // no intermediate uses and there isn't a use beyond the copy.
260 // FIXME: find the last use, mark is kill and shorten the live range.
261 if (SrcEnd > li_->getDefIndex(CopyIdx)) {
265 MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
267 // Shorten the liveinterval to the end of last use.
271 RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse));
274 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
276 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
278 // A dead def should have a single cycle interval.
285 // We need to be careful about coalescing a source physical register with a
286 // virtual register. Once the coalescing is done, it cannot be broken and
287 // these are not spillable! If the destination interval uses are far away,
288 // think twice about coalescing them!
289 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys)) {
290 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
291 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
292 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
293 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
294 unsigned Threshold = allocatableRCRegs_[RC].count();
296 // If the virtual register live interval is long has it has low use desity,
297 // do not join them, instead mark the physical register as its allocation
299 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
300 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
301 if (Length > Threshold &&
302 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
303 JoinVInt.preference = JoinPReg;
305 DOUT << "\tMay tie down a physical register, abort!\n";
310 // Okay, attempt to join these two intervals. On failure, this returns false.
311 // Otherwise, if one of the intervals being joined is a physreg, this method
312 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
313 // been modified, so we can use this information below to update aliases.
314 bool Swapped = false;
315 if (JoinIntervals(DstInt, SrcInt, Swapped)) {
317 // Result of the copy is dead. Propagate this property.
319 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
320 "Live-in must be a physical register!");
321 // Live-in to the function but dead. Remove it from entry live-in set.
322 // JoinIntervals may end up swapping the two intervals.
323 mf_->begin()->removeLiveIn(repSrcReg);
325 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
327 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
334 if (isShorten || isDead) {
335 // Shorten the destination live interval.
337 SrcInt.removeRange(RemoveStart, RemoveEnd);
340 // Coalescing failed.
342 // If we can eliminate the copy without merging the live ranges, do so now.
343 if (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI))
346 // Otherwise, we are unable to join the intervals.
347 DOUT << "Interference!\n";
351 LiveInterval *ResSrcInt = &SrcInt;
352 LiveInterval *ResDstInt = &DstInt;
354 std::swap(repSrcReg, repDstReg);
355 std::swap(ResSrcInt, ResDstInt);
357 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
358 "LiveInterval::join didn't work right!");
360 // If we're about to merge live ranges into a physical register live range,
361 // we have to update any aliased register's live ranges to indicate that they
362 // have clobbered values for this range.
363 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
364 // Unset unnecessary kills.
365 if (!ResDstInt->containsOneValue()) {
366 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
367 E = ResSrcInt->end(); I != E; ++I)
368 unsetRegisterKills(I->start, I->end, repDstReg);
371 // Update the liveintervals of sub-registers.
372 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
373 li_->getInterval(*AS).MergeInClobberRanges(*ResSrcInt,
374 li_->getVNInfoAllocator());
376 // Merge use info if the destination is a virtual register.
377 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
378 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
379 dVI.NumUses += sVI.NumUses;
382 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
385 // Remember these liveintervals have been joined.
386 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
387 if (MRegisterInfo::isVirtualRegister(repDstReg))
388 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
390 // repSrcReg is guarateed to be the register whose live interval that is
392 li_->removeInterval(repSrcReg);
393 r2rMap_[repSrcReg] = repDstReg;
395 // Finally, delete the copy instruction.
396 li_->RemoveMachineInstrFromMaps(CopyMI);
397 CopyMI->eraseFromParent();
403 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
404 /// compute what the resultant value numbers for each value in the input two
405 /// ranges will be. This is complicated by copies between the two which can
406 /// and will commonly cause multiple value numbers to be merged into one.
408 /// VN is the value number that we're trying to resolve. InstDefiningValue
409 /// keeps track of the new InstDefiningValue assignment for the result
410 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
411 /// whether a value in this or other is a copy from the opposite set.
412 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
413 /// already been assigned.
415 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
416 /// contains the value number the copy is from.
418 static unsigned ComputeUltimateVN(VNInfo *VNI,
419 SmallVector<VNInfo*, 16> &NewVNInfo,
420 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
421 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
422 SmallVector<int, 16> &ThisValNoAssignments,
423 SmallVector<int, 16> &OtherValNoAssignments) {
424 unsigned VN = VNI->id;
426 // If the VN has already been computed, just return it.
427 if (ThisValNoAssignments[VN] >= 0)
428 return ThisValNoAssignments[VN];
429 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
431 // If this val is not a copy from the other val, then it must be a new value
432 // number in the destination.
433 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
434 if (I == ThisFromOther.end()) {
435 NewVNInfo.push_back(VNI);
436 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
438 VNInfo *OtherValNo = I->second;
440 // Otherwise, this *is* a copy from the RHS. If the other side has already
441 // been computed, return it.
442 if (OtherValNoAssignments[OtherValNo->id] >= 0)
443 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
445 // Mark this value number as currently being computed, then ask what the
446 // ultimate value # of the other value is.
447 ThisValNoAssignments[VN] = -2;
448 unsigned UltimateVN =
449 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
450 OtherValNoAssignments, ThisValNoAssignments);
451 return ThisValNoAssignments[VN] = UltimateVN;
454 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
455 return std::find(V.begin(), V.end(), Val) != V.end();
458 /// SimpleJoin - Attempt to joint the specified interval into this one. The
459 /// caller of this method must guarantee that the RHS only contains a single
460 /// value number and that the RHS is not defined by a copy from this
461 /// interval. This returns false if the intervals are not joinable, or it
462 /// joins them and returns true.
463 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
464 assert(RHS.containsOneValue());
466 // Some number (potentially more than one) value numbers in the current
467 // interval may be defined as copies from the RHS. Scan the overlapping
468 // portions of the LHS and RHS, keeping track of this and looking for
469 // overlapping live ranges that are NOT defined as copies. If these exist, we
472 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
473 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
475 if (LHSIt->start < RHSIt->start) {
476 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
477 if (LHSIt != LHS.begin()) --LHSIt;
478 } else if (RHSIt->start < LHSIt->start) {
479 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
480 if (RHSIt != RHS.begin()) --RHSIt;
483 SmallVector<VNInfo*, 8> EliminatedLHSVals;
486 // Determine if these live intervals overlap.
487 bool Overlaps = false;
488 if (LHSIt->start <= RHSIt->start)
489 Overlaps = LHSIt->end > RHSIt->start;
491 Overlaps = RHSIt->end > LHSIt->start;
493 // If the live intervals overlap, there are two interesting cases: if the
494 // LHS interval is defined by a copy from the RHS, it's ok and we record
495 // that the LHS value # is the same as the RHS. If it's not, then we cannot
496 // coalesce these live ranges and we bail out.
498 // If we haven't already recorded that this value # is safe, check it.
499 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
500 // Copy from the RHS?
501 unsigned SrcReg = LHSIt->valno->reg;
502 if (rep(SrcReg) != RHS.reg)
503 return false; // Nope, bail out.
505 EliminatedLHSVals.push_back(LHSIt->valno);
508 // We know this entire LHS live range is okay, so skip it now.
509 if (++LHSIt == LHSEnd) break;
513 if (LHSIt->end < RHSIt->end) {
514 if (++LHSIt == LHSEnd) break;
516 // One interesting case to check here. It's possible that we have
517 // something like "X3 = Y" which defines a new value number in the LHS,
518 // and is the last use of this liverange of the RHS. In this case, we
519 // want to notice this copy (so that it gets coalesced away) even though
520 // the live ranges don't actually overlap.
521 if (LHSIt->start == RHSIt->end) {
522 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
523 // We already know that this value number is going to be merged in
524 // if coalescing succeeds. Just skip the liverange.
525 if (++LHSIt == LHSEnd) break;
527 // Otherwise, if this is a copy from the RHS, mark it as being merged
529 if (rep(LHSIt->valno->reg) == RHS.reg) {
530 EliminatedLHSVals.push_back(LHSIt->valno);
532 // We know this entire LHS live range is okay, so skip it now.
533 if (++LHSIt == LHSEnd) break;
538 if (++RHSIt == RHSEnd) break;
542 // If we got here, we know that the coalescing will be successful and that
543 // the value numbers in EliminatedLHSVals will all be merged together. Since
544 // the most common case is that EliminatedLHSVals has a single number, we
545 // optimize for it: if there is more than one value, we merge them all into
546 // the lowest numbered one, then handle the interval as if we were merging
547 // with one value number.
549 if (EliminatedLHSVals.size() > 1) {
550 // Loop through all the equal value numbers merging them into the smallest
552 VNInfo *Smallest = EliminatedLHSVals[0];
553 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
554 if (EliminatedLHSVals[i]->id < Smallest->id) {
555 // Merge the current notion of the smallest into the smaller one.
556 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
557 Smallest = EliminatedLHSVals[i];
559 // Merge into the smallest.
560 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
565 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
566 LHSValNo = EliminatedLHSVals[0];
569 // Okay, now that there is a single LHS value number that we're merging the
570 // RHS into, update the value number info for the LHS to indicate that the
571 // value number is defined where the RHS value number was.
572 const VNInfo *VNI = RHS.getValNumInfo(0);
573 LHSValNo->def = VNI->def;
574 LHSValNo->reg = VNI->reg;
576 // Okay, the final step is to loop over the RHS live intervals, adding them to
578 LHS.addKills(LHSValNo, VNI->kills);
579 LHS.MergeRangesInAsValue(RHS, LHSValNo);
580 LHS.weight += RHS.weight;
581 if (RHS.preference && !LHS.preference)
582 LHS.preference = RHS.preference;
587 /// JoinIntervals - Attempt to join these two intervals. On failure, this
588 /// returns false. Otherwise, if one of the intervals being joined is a
589 /// physreg, this method always canonicalizes LHS to be it. The output
590 /// "RHS" will not have been modified, so we can use this information
591 /// below to update aliases.
592 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
593 LiveInterval &RHS, bool &Swapped) {
594 // Compute the final value assignment, assuming that the live ranges can be
596 SmallVector<int, 16> LHSValNoAssignments;
597 SmallVector<int, 16> RHSValNoAssignments;
598 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
599 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
600 SmallVector<VNInfo*, 16> NewVNInfo;
602 // If a live interval is a physical register, conservatively check if any
603 // of its sub-registers is overlapping the live interval of the virtual
604 // register. If so, do not coalesce.
605 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
606 *mri_->getSubRegisters(LHS.reg)) {
607 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
608 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
609 DOUT << "Interfere with sub-register ";
610 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
613 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
614 *mri_->getSubRegisters(RHS.reg)) {
615 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
616 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
617 DOUT << "Interfere with sub-register ";
618 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
623 // Compute ultimate value numbers for the LHS and RHS values.
624 if (RHS.containsOneValue()) {
625 // Copies from a liveinterval with a single value are simple to handle and
626 // very common, handle the special case here. This is important, because
627 // often RHS is small and LHS is large (e.g. a physreg).
629 // Find out if the RHS is defined as a copy from some value in the LHS.
630 int RHSVal0DefinedFromLHS = -1;
632 VNInfo *RHSValNoInfo = NULL;
633 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
634 unsigned RHSSrcReg = RHSValNoInfo0->reg;
635 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
636 // If RHS is not defined as a copy from the LHS, we can use simpler and
637 // faster checks to see if the live ranges are coalescable. This joiner
638 // can't swap the LHS/RHS intervals though.
639 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
640 return SimpleJoin(LHS, RHS);
642 RHSValNoInfo = RHSValNoInfo0;
645 // It was defined as a copy from the LHS, find out what value # it is.
646 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
647 RHSValID = RHSValNoInfo->id;
648 RHSVal0DefinedFromLHS = RHSValID;
651 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
652 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
653 NewVNInfo.resize(LHS.getNumValNums(), NULL);
655 // Okay, *all* of the values in LHS that are defined as a copy from RHS
656 // should now get updated.
657 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
660 unsigned VN = VNI->id;
661 if (unsigned LHSSrcReg = VNI->reg) {
662 if (rep(LHSSrcReg) != RHS.reg) {
663 // If this is not a copy from the RHS, its value number will be
664 // unmodified by the coalescing.
666 LHSValNoAssignments[VN] = VN;
667 } else if (RHSValID == -1) {
668 // Otherwise, it is a copy from the RHS, and we don't already have a
669 // value# for it. Keep the current value number, but remember it.
670 LHSValNoAssignments[VN] = RHSValID = VN;
671 NewVNInfo[VN] = RHSValNoInfo;
672 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
674 // Otherwise, use the specified value #.
675 LHSValNoAssignments[VN] = RHSValID;
676 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
677 NewVNInfo[VN] = RHSValNoInfo;
678 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
683 LHSValNoAssignments[VN] = VN;
687 assert(RHSValID != -1 && "Didn't find value #?");
688 RHSValNoAssignments[0] = RHSValID;
689 if (RHSVal0DefinedFromLHS != -1) {
690 // This path doesn't go through ComputeUltimateVN so just set
692 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
695 // Loop over the value numbers of the LHS, seeing if any are defined from
697 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
700 unsigned ValSrcReg = VNI->reg;
701 if (ValSrcReg == 0) // Src not defined by a copy?
704 // DstReg is known to be a register in the LHS interval. If the src is
705 // from the RHS interval, we can use its value #.
706 if (rep(ValSrcReg) != RHS.reg)
709 // Figure out the value # from the RHS.
710 LHSValsDefinedFromRHS[VNI] = RHS.getLiveRangeContaining(VNI->def-1)->valno;
713 // Loop over the value numbers of the RHS, seeing if any are defined from
715 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
718 unsigned ValSrcReg = VNI->reg;
719 if (ValSrcReg == 0) // Src not defined by a copy?
722 // DstReg is known to be a register in the RHS interval. If the src is
723 // from the LHS interval, we can use its value #.
724 if (rep(ValSrcReg) != LHS.reg)
727 // Figure out the value # from the LHS.
728 RHSValsDefinedFromLHS[VNI]= LHS.getLiveRangeContaining(VNI->def-1)->valno;
731 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
732 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
733 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
735 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
738 unsigned VN = VNI->id;
739 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
741 ComputeUltimateVN(VNI, NewVNInfo,
742 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
743 LHSValNoAssignments, RHSValNoAssignments);
745 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
748 unsigned VN = VNI->id;
749 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
751 // If this value number isn't a copy from the LHS, it's a new number.
752 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
753 NewVNInfo.push_back(VNI);
754 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
758 ComputeUltimateVN(VNI, NewVNInfo,
759 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
760 RHSValNoAssignments, LHSValNoAssignments);
764 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
765 // interval lists to see if these intervals are coalescable.
766 LiveInterval::const_iterator I = LHS.begin();
767 LiveInterval::const_iterator IE = LHS.end();
768 LiveInterval::const_iterator J = RHS.begin();
769 LiveInterval::const_iterator JE = RHS.end();
771 // Skip ahead until the first place of potential sharing.
772 if (I->start < J->start) {
773 I = std::upper_bound(I, IE, J->start);
774 if (I != LHS.begin()) --I;
775 } else if (J->start < I->start) {
776 J = std::upper_bound(J, JE, I->start);
777 if (J != RHS.begin()) --J;
781 // Determine if these two live ranges overlap.
783 if (I->start < J->start) {
784 Overlaps = I->end > J->start;
786 Overlaps = J->end > I->start;
789 // If so, check value # info to determine if they are really different.
791 // If the live range overlap will map to the same value number in the
792 // result liverange, we can still coalesce them. If not, we can't.
793 if (LHSValNoAssignments[I->valno->id] !=
794 RHSValNoAssignments[J->valno->id])
798 if (I->end < J->end) {
807 // If we get here, we know that we can coalesce the live ranges. Ask the
808 // intervals to coalesce themselves now.
809 if ((RHS.ranges.size() > LHS.ranges.size() &&
810 MRegisterInfo::isVirtualRegister(LHS.reg)) ||
811 MRegisterInfo::isPhysicalRegister(RHS.reg)) {
812 // Update kill info. Some live ranges are extended due to copy coalescing.
813 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
814 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
815 VNInfo *VNI = I->first;
816 unsigned LHSValID = LHSValNoAssignments[VNI->id];
817 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
818 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
821 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
824 // Update kill info. Some live ranges are extended due to copy coalescing.
825 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
826 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
827 VNInfo *VNI = I->first;
828 unsigned RHSValID = RHSValNoAssignments[VNI->id];
829 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
830 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
833 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
840 // DepthMBBCompare - Comparison predicate that sort first based on the loop
841 // depth of the basic block (the unsigned), and then on the MBB number.
842 struct DepthMBBCompare {
843 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
844 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
845 if (LHS.first > RHS.first) return true; // Deeper loops first
846 return LHS.first == RHS.first &&
847 LHS.second->getNumber() < RHS.second->getNumber();
852 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
853 std::vector<CopyRec> *TryAgain, bool PhysOnly) {
854 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
856 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
858 MachineInstr *Inst = MII++;
860 // If this isn't a copy, we can't join intervals.
861 unsigned SrcReg, DstReg;
862 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
864 bool Done = JoinCopy(Inst, SrcReg, DstReg, PhysOnly);
865 if (TryAgain && !Done)
866 TryAgain->push_back(getCopyRec(Inst, SrcReg, DstReg));
870 void SimpleRegisterCoalescing::joinIntervals() {
871 DOUT << "********** JOINING INTERVALS ***********\n";
873 JoinedLIs.resize(li_->getNumIntervals());
876 std::vector<CopyRec> TryAgainList;
877 const LoopInfo &LI = getAnalysis<LoopInfo>();
878 if (LI.begin() == LI.end()) {
879 // If there are no loops in the function, join intervals in function order.
880 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
882 CopyCoalesceInMBB(I, &TryAgainList);
884 // Otherwise, join intervals in inner loops before other intervals.
885 // Unfortunately we can't just iterate over loop hierarchy here because
886 // there may be more MBB's than BB's. Collect MBB's for sorting.
888 // Join intervals in the function prolog first. We want to join physical
889 // registers with virtual registers before the intervals got too long.
890 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
891 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
892 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
894 // Sort by loop depth.
895 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
897 // Finally, join intervals in loop nest order.
898 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
899 CopyCoalesceInMBB(MBBs[i].second, NULL, true);
900 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
901 CopyCoalesceInMBB(MBBs[i].second, &TryAgainList, false);
904 // Joining intervals can allow other intervals to be joined. Iteratively join
905 // until we make no progress.
906 bool ProgressMade = true;
907 while (ProgressMade) {
908 ProgressMade = false;
910 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
911 CopyRec &TheCopy = TryAgainList[i];
913 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
914 TheCopy.MI = 0; // Mark this one as done.
920 // Some live range has been lengthened due to colaescing, eliminate the
921 // unnecessary kills.
922 int RegNum = JoinedLIs.find_first();
923 while (RegNum != -1) {
924 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
925 unsigned repReg = rep(Reg);
926 LiveInterval &LI = li_->getInterval(repReg);
927 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
928 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
929 MachineInstr *Kill = svi.Kills[i];
930 // Suppose vr1 = op vr2, x
931 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
932 // unless it is a two-address operand.
933 if (li_->isRemoved(Kill) || hasRegisterDef(Kill, repReg))
935 if (LI.liveAt(li_->getInstructionIndex(Kill) + InstrSlots::NUM))
936 unsetRegisterKill(Kill, repReg);
938 RegNum = JoinedLIs.find_next(RegNum);
941 DOUT << "*** Register mapping ***\n";
942 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
944 DOUT << " reg " << i << " -> ";
945 DEBUG(printRegName(r2rMap_[i]));
950 /// Return true if the two specified registers belong to different register
951 /// classes. The registers may be either phys or virt regs.
952 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
953 unsigned RegB) const {
955 // Get the register classes for the first reg.
956 if (MRegisterInfo::isPhysicalRegister(RegA)) {
957 assert(MRegisterInfo::isVirtualRegister(RegB) &&
958 "Shouldn't consider two physregs!");
959 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
962 // Compare against the regclass for the second reg.
963 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
964 if (MRegisterInfo::isVirtualRegister(RegB))
965 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
967 return !RegClass->contains(RegB);
970 /// lastRegisterUse - Returns the last use of the specific register between
971 /// cycles Start and End. It also returns the use operand by reference. It
972 /// returns NULL if there are no uses.
974 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
975 MachineOperand *&MOU) {
976 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
979 // Skip deleted instructions
980 MachineInstr *MI = li_->getInstructionFromIndex(e);
981 while ((e - InstrSlots::NUM) >= s && !MI) {
982 e -= InstrSlots::NUM;
983 MI = li_->getInstructionFromIndex(e);
985 if (e < s || MI == NULL)
988 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
989 MachineOperand &MO = MI->getOperand(i);
990 if (MO.isRegister() && MO.isUse() && MO.getReg() &&
991 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
997 e -= InstrSlots::NUM;
1004 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1005 /// register. It returns NULL if the def is not found.
1006 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
1007 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1008 MachineOperand &MO = MI->getOperand(i);
1009 if (MO.isRegister() && MO.isDef() &&
1010 mri_->regsOverlap(rep(MO.getReg()), Reg))
1016 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1017 /// of the specific instruction.
1018 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1019 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1020 MachineOperand &MO = MI->getOperand(i);
1021 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1022 mri_->regsOverlap(rep(MO.getReg()), Reg))
1027 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1028 /// between cycles Start and End.
1029 void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
1031 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1034 // Skip deleted instructions
1035 MachineInstr *MI = li_->getInstructionFromIndex(e);
1036 while ((e - InstrSlots::NUM) >= s && !MI) {
1037 e -= InstrSlots::NUM;
1038 MI = li_->getInstructionFromIndex(e);
1040 if (e < s || MI == NULL)
1043 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1044 MachineOperand &MO = MI->getOperand(i);
1045 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1046 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1051 e -= InstrSlots::NUM;
1055 /// hasRegisterDef - True if the instruction defines the specific register.
1057 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1058 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1059 MachineOperand &MO = MI->getOperand(i);
1060 if (MO.isRegister() && MO.isDef() &&
1061 mri_->regsOverlap(rep(MO.getReg()), Reg))
1067 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1068 if (MRegisterInfo::isPhysicalRegister(reg))
1069 cerr << mri_->getName(reg);
1071 cerr << "%reg" << reg;
1074 void SimpleRegisterCoalescing::releaseMemory() {
1079 static bool isZeroLengthInterval(LiveInterval *li) {
1080 for (LiveInterval::Ranges::const_iterator
1081 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1082 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1087 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1089 tm_ = &fn.getTarget();
1090 mri_ = tm_->getRegisterInfo();
1091 tii_ = tm_->getInstrInfo();
1092 li_ = &getAnalysis<LiveIntervals>();
1093 lv_ = &getAnalysis<LiveVariables>();
1095 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1096 << "********** Function: "
1097 << ((Value*)mf_->getFunction())->getName() << '\n';
1099 allocatableRegs_ = mri_->getAllocatableSet(fn);
1100 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
1101 E = mri_->regclass_end(); I != E; ++I)
1102 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
1104 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
1106 // Join (coalesce) intervals if requested.
1107 if (EnableJoining) {
1109 DOUT << "********** INTERVALS POST JOINING **********\n";
1110 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1111 I->second.print(DOUT, mri_);
1116 // perform a final pass over the instructions and compute spill
1117 // weights, coalesce virtual registers and remove identity moves.
1118 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
1120 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1121 mbbi != mbbe; ++mbbi) {
1122 MachineBasicBlock* mbb = mbbi;
1123 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
1125 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1127 // if the move will be an identity move delete it
1128 unsigned srcReg, dstReg, RegRep;
1129 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
1130 (RegRep = rep(srcReg)) == rep(dstReg)) {
1131 // remove from def list
1132 LiveInterval &RegInt = li_->getOrCreateInterval(RegRep);
1133 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1134 // If def of this move instruction is dead, remove its live range from
1135 // the dstination register's live interval.
1137 unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
1138 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
1139 RegInt.removeRange(MLR->start, MoveIdx+1);
1141 li_->removeInterval(RegRep);
1143 li_->RemoveMachineInstrFromMaps(mii);
1144 mii = mbbi->erase(mii);
1147 SmallSet<unsigned, 4> UniqueUses;
1148 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
1149 const MachineOperand &mop = mii->getOperand(i);
1150 if (mop.isRegister() && mop.getReg() &&
1151 MRegisterInfo::isVirtualRegister(mop.getReg())) {
1152 // replace register with representative register
1153 unsigned reg = rep(mop.getReg());
1154 mii->getOperand(i).setReg(reg);
1156 // Multiple uses of reg by the same instruction. It should not
1157 // contribute to spill weight again.
1158 if (UniqueUses.count(reg) != 0)
1160 LiveInterval &RegInt = li_->getInterval(reg);
1161 float w = (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
1163 UniqueUses.insert(reg);
1171 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1172 LiveInterval &LI = I->second;
1173 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
1174 // If the live interval length is essentially zero, i.e. in every live
1175 // range the use follows def immediately, it doesn't make sense to spill
1176 // it and hope it will be easier to allocate for this li.
1177 if (isZeroLengthInterval(&LI))
1178 LI.weight = HUGE_VALF;
1180 // Slightly prefer live interval that has been assigned a preferred reg.
1184 // Divide the weight of the interval by its size. This encourages
1185 // spilling of intervals that are large and have few uses, and
1186 // discourages spilling of small intervals with many uses.
1187 LI.weight /= LI.getSize();
1195 /// print - Implement the dump method.
1196 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
1200 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1201 return new SimpleRegisterCoalescing();
1204 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1205 DEFINING_FILE_FOR(SimpleRegisterCoalescing)