1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
37 STATISTIC(numJoins , "Number of interval joins performed");
38 STATISTIC(numCommutes , "Number of instruction commuting performed");
39 STATISTIC(numExtends , "Number of copies extended");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
45 EnableJoining("join-liveintervals",
46 cl::desc("Coalesce copies (default=true)"),
50 NewHeuristic("new-coalescer-heuristic",
51 cl::desc("Use new coalescer heuristic"),
54 static RegisterPass<SimpleRegisterCoalescing>
55 X("simple-register-coalescing", "Simple Register Coalescing");
57 // Declare that we implement the RegisterCoalescer interface
58 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
60 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
62 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addPreserved<LiveIntervals>();
64 AU.addPreserved<MachineLoopInfo>();
65 AU.addPreservedID(MachineDominatorsID);
66 AU.addPreservedID(PHIEliminationID);
67 AU.addPreservedID(TwoAddressInstructionPassID);
68 AU.addRequired<LiveIntervals>();
69 AU.addRequired<MachineLoopInfo>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
74 /// being the source and IntB being the dest, thus this defines a value number
75 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
76 /// see if we can merge these two pieces of B into a single value number,
77 /// eliminating a copy. For example:
81 /// B1 = A3 <- this copy
83 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
84 /// value number to be replaced with B0 (which simplifies the B liveinterval).
86 /// This returns true if an interval was modified.
88 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
90 MachineInstr *CopyMI) {
91 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
93 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
95 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
96 if (BLR == IntB.end()) // Should never happen!
98 VNInfo *BValNo = BLR->valno;
100 // Get the location that B is defined at. Two options: either this value has
101 // an unknown definition point or it is defined at CopyIdx. If unknown, we
103 if (!BValNo->copy) return false;
104 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
106 // AValNo is the value number in A that defines the copy, A3 in the example.
107 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
108 if (ALR == IntA.end()) // Should never happen!
110 VNInfo *AValNo = ALR->valno;
112 // If AValNo is defined as a copy from IntB, we can potentially process this.
113 // Get the instruction that defines this value number.
114 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
115 if (!SrcReg) return false; // Not defined by a copy.
117 // If the value number is not defined by a copy instruction, ignore it.
119 // If the source register comes from an interval other than IntB, we can't
121 if (SrcReg != IntB.reg) return false;
123 // Get the LiveRange in IntB that this value number starts with.
124 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
125 if (ValLR == IntB.end()) // Should never happen!
128 // Make sure that the end of the live range is inside the same block as
130 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
132 ValLREndInst->getParent() != CopyMI->getParent()) return false;
134 // Okay, we now know that ValLR ends in the same block that the CopyMI
135 // live-range starts. If there are no intervening live ranges between them in
136 // IntB, we can merge them.
137 if (ValLR+1 != BLR) return false;
139 // If a live interval is a physical register, conservatively check if any
140 // of its sub-registers is overlapping the live interval of the virtual
141 // register. If so, do not coalesce.
142 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
143 *tri_->getSubRegisters(IntB.reg)) {
144 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
145 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
146 DOUT << "Interfere with sub-register ";
147 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
152 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
154 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
155 // We are about to delete CopyMI, so need to remove it as the 'instruction
156 // that defines this value #'. Update the the valnum with the new defining
158 BValNo->def = FillerStart;
161 // Okay, we can merge them. We need to insert a new liverange:
162 // [ValLR.end, BLR.begin) of either value number, then we merge the
163 // two value numbers.
164 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
166 // If the IntB live range is assigned to a physical register, and if that
167 // physreg has aliases,
168 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
169 // Update the liveintervals of sub-registers.
170 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
171 LiveInterval &AliasLI = li_->getInterval(*AS);
172 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
173 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
177 // Okay, merge "B1" into the same value number as "B0".
178 if (BValNo != ValLR->valno)
179 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
180 DOUT << " result = "; IntB.print(DOUT, tri_);
183 // If the source instruction was killing the source register before the
184 // merge, unset the isKill marker given the live range has been extended.
185 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
187 ValLREndInst->getOperand(UIdx).setIsKill(false);
193 /// HasOtherReachingDefs - Return true if there are definitions of IntB
194 /// other than BValNo val# that can reach uses of AValno val# of IntA.
195 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
199 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
201 if (AI->valno != AValNo) continue;
202 LiveInterval::Ranges::iterator BI =
203 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
204 if (BI != IntB.ranges.begin())
206 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
207 if (BI->valno == BValNo)
209 if (BI->start <= AI->start && BI->end > AI->start)
211 if (BI->start > AI->start && BI->start < AI->end)
218 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
219 /// being the source and IntB being the dest, thus this defines a value number
220 /// in IntB. If the source value number (in IntA) is defined by a commutable
221 /// instruction and its other operand is coalesced to the copy dest register,
222 /// see if we can transform the copy into a noop by commuting the definition. For
225 /// A3 = op A2 B0<kill>
227 /// B1 = A3 <- this copy
229 /// = op A3 <- more uses
233 /// B2 = op B0 A2<kill>
235 /// B1 = B2 <- now an identify copy
237 /// = op B2 <- more uses
239 /// This returns true if an interval was modified.
241 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
243 MachineInstr *CopyMI) {
244 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
246 // FIXME: For now, only eliminate the copy by commuting its def when the
247 // source register is a virtual register. We want to guard against cases
248 // where the copy is a back edge copy and commuting the def lengthen the
249 // live interval of the source register to the entire loop.
250 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
253 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
254 // the example above.
255 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
256 if (BLR == IntB.end()) // Should never happen!
258 VNInfo *BValNo = BLR->valno;
260 // Get the location that B is defined at. Two options: either this value has
261 // an unknown definition point or it is defined at CopyIdx. If unknown, we
263 if (!BValNo->copy) return false;
264 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
266 // AValNo is the value number in A that defines the copy, A3 in the example.
267 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
268 if (ALR == IntA.end()) // Should never happen!
270 VNInfo *AValNo = ALR->valno;
271 // If other defs can reach uses of this def, then it's not safe to perform
273 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
275 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
276 const TargetInstrDesc &TID = DefMI->getDesc();
278 if (!TID.isCommutable() ||
279 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
282 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
283 unsigned NewReg = NewDstMO.getReg();
284 if (NewReg != IntB.reg || !NewDstMO.isKill())
287 // Make sure there are no other definitions of IntB that would reach the
288 // uses which the new definition can reach.
289 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
292 // If some of the uses of IntA.reg is already coalesced away, return false.
293 // It's not possible to determine whether it's safe to perform the coalescing.
294 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
295 UE = mri_->use_end(); UI != UE; ++UI) {
296 MachineInstr *UseMI = &*UI;
297 unsigned UseIdx = li_->getInstructionIndex(UseMI);
298 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
299 if (ULR == IntA.end())
301 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
305 // At this point we have decided that it is legal to do this
306 // transformation. Start by commuting the instruction.
307 MachineBasicBlock *MBB = DefMI->getParent();
308 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
311 if (NewMI != DefMI) {
312 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
313 MBB->insert(DefMI, NewMI);
316 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
317 NewMI->getOperand(OpIdx).setIsKill();
319 bool BHasPHIKill = BValNo->hasPHIKill;
320 SmallVector<VNInfo*, 4> BDeadValNos;
321 SmallVector<unsigned, 4> BKills;
322 std::map<unsigned, unsigned> BExtend;
324 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
333 // then do not add kills of A to the newly created B interval.
334 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
336 BExtend[ALR->end] = BLR->end;
338 // Update uses of IntA of the specific Val# with IntB.
339 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
340 UE = mri_->use_end(); UI != UE;) {
341 MachineOperand &UseMO = UI.getOperand();
342 MachineInstr *UseMI = &*UI;
344 if (JoinedCopies.count(UseMI))
346 unsigned UseIdx = li_->getInstructionIndex(UseMI);
347 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
348 if (ULR == IntA.end() || ULR->valno != AValNo)
350 UseMO.setReg(NewReg);
353 if (UseMO.isKill()) {
355 UseMO.setIsKill(false);
357 BKills.push_back(li_->getUseIndex(UseIdx)+1);
359 unsigned SrcReg, DstReg;
360 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
362 if (DstReg == IntB.reg) {
363 // This copy will become a noop. If it's defining a new val#,
364 // remove that val# as well. However this live range is being
365 // extended to the end of the existing live range defined by the copy.
366 unsigned DefIdx = li_->getDefIndex(UseIdx);
367 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
368 BHasPHIKill |= DLR->valno->hasPHIKill;
369 assert(DLR->valno->def == DefIdx);
370 BDeadValNos.push_back(DLR->valno);
371 BExtend[DLR->start] = DLR->end;
372 JoinedCopies.insert(UseMI);
373 // If this is a kill but it's going to be removed, the last use
374 // of the same val# is the new kill.
380 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
381 // simply extend BLR if CopyMI doesn't end the range.
382 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
384 IntB.removeValNo(BValNo);
385 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
386 IntB.removeValNo(BDeadValNos[i]);
387 VNInfo *ValNo = IntB.getNextValue(AValNo->def, 0, li_->getVNInfoAllocator());
388 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
390 if (AI->valno != AValNo) continue;
391 unsigned End = AI->end;
392 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
393 if (EI != BExtend.end())
395 IntB.addRange(LiveRange(AI->start, End, ValNo));
397 IntB.addKills(ValNo, BKills);
398 ValNo->hasPHIKill = BHasPHIKill;
400 DOUT << " result = "; IntB.print(DOUT, tri_);
403 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
404 IntA.removeValNo(AValNo);
405 DOUT << " result = "; IntA.print(DOUT, tri_);
412 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
414 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
415 unsigned DstReg) const {
416 MachineBasicBlock *MBB = CopyMI->getParent();
417 const MachineLoop *L = loopInfo->getLoopFor(MBB);
420 if (MBB != L->getLoopLatch())
423 LiveInterval &LI = li_->getInterval(DstReg);
424 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
425 LiveInterval::const_iterator DstLR =
426 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
427 if (DstLR == LI.end())
429 unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM;
430 if (DstLR->valno->kills.size() == 1 &&
431 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
436 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
437 /// update the subregister number if it is not zero. If DstReg is a
438 /// physical register and the existing subregister number of the def / use
439 /// being updated is not zero, make sure to set it to the correct physical
442 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
444 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
445 if (DstIsPhys && SubIdx) {
446 // Figure out the real physical register we are updating with.
447 DstReg = tri_->getSubReg(DstReg, SubIdx);
451 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
452 E = mri_->reg_end(); I != E; ) {
453 MachineOperand &O = I.getOperand();
454 MachineInstr *UseMI = &*I;
456 unsigned OldSubIdx = O.getSubReg();
458 unsigned UseDstReg = DstReg;
460 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
464 // Sub-register indexes goes from small to large. e.g.
465 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
466 // EAX: 1 -> AL, 2 -> AX
467 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
468 // sub-register 2 is also AX.
469 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
470 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
473 // Remove would-be duplicated kill marker.
474 if (O.isKill() && UseMI->killsRegister(DstReg))
481 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
482 /// registers due to insert_subreg coalescing. e.g.
484 /// r1025 = implicit_def
485 /// r1025 = insert_subreg r1025, r1024
489 /// r1025 = implicit_def
490 /// r1025 = insert_subreg r1025, r1025
493 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
494 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
495 E = mri_->reg_end(); I != E; ) {
496 MachineOperand &O = I.getOperand();
497 MachineInstr *DefMI = &*I;
501 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
503 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
505 li_->RemoveMachineInstrFromMaps(DefMI);
506 DefMI->eraseFromParent();
510 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
511 /// due to live range lengthening as the result of coalescing.
512 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
514 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
515 UE = mri_->use_end(); UI != UE; ++UI) {
516 MachineOperand &UseMO = UI.getOperand();
517 if (UseMO.isKill()) {
518 MachineInstr *UseMI = UseMO.getParent();
520 if (!tii_->isMoveInstr(*UseMI, SReg, DReg))
522 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
523 if (JoinedCopies.count(UseMI))
525 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
526 if (!LI.isKill(UI->valno, UseIdx+1))
527 UseMO.setIsKill(false);
532 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
533 /// from a physical register live interval as well as from the live intervals
534 /// of its sub-registers.
535 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
536 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
537 li.removeRange(Start, End, true);
538 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
539 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
540 if (!li_->hasInterval(*SR))
542 LiveInterval &sli = li_->getInterval(*SR);
543 unsigned RemoveEnd = Start;
544 while (RemoveEnd != End) {
545 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
548 RemoveEnd = (LR->end < End) ? LR->end : End;
549 sli.removeRange(Start, RemoveEnd, true);
556 /// removeIntervalIfEmpty - Check if the live interval of a physical register
557 /// is empty, if so remove it and also remove the empty intervals of its
558 /// sub-registers. Return true if live interval is removed.
559 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
560 const TargetRegisterInfo *tri_) {
562 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
563 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
564 if (!li_->hasInterval(*SR))
566 LiveInterval &sli = li_->getInterval(*SR);
568 li_->removeInterval(*SR);
570 li_->removeInterval(li.reg);
576 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
577 /// Return true if live interval is removed.
578 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
579 MachineInstr *CopyMI) {
580 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
581 LiveInterval::iterator MLR =
582 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
584 return false; // Already removed by ShortenDeadCopySrcLiveRange.
585 unsigned RemoveStart = MLR->start;
586 unsigned RemoveEnd = MLR->end;
587 // Remove the liverange that's defined by this.
588 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
589 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
590 return removeIntervalIfEmpty(li, li_, tri_);
595 /// PropagateDeadness - Propagate the dead marker to the instruction which
596 /// defines the val#.
597 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
598 unsigned &LRStart, LiveIntervals *li_,
599 const TargetRegisterInfo* tri_) {
600 MachineInstr *DefMI =
601 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
602 if (DefMI && DefMI != CopyMI) {
603 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
605 DefMI->getOperand(DeadIdx).setIsDead();
606 // A dead def should have a single cycle interval.
612 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
613 /// fallthoughs to SuccMBB.
614 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
615 MachineBasicBlock *SuccMBB,
616 const TargetInstrInfo *tii_) {
619 MachineBasicBlock *TBB = 0, *FBB = 0;
620 std::vector<MachineOperand> Cond;
621 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
622 MBB->isSuccessor(SuccMBB);
625 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
626 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
627 /// ends the live range there. If there isn't another use, then this live range
628 /// is dead. Return true if live interval is removed.
630 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
631 MachineInstr *CopyMI) {
632 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
634 // FIXME: special case: function live in. It can be a general case if the
635 // first instruction index starts at > 0 value.
636 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
637 // Live-in to the function but dead. Remove it from entry live-in set.
638 if (mf_->begin()->isLiveIn(li.reg))
639 mf_->begin()->removeLiveIn(li.reg);
640 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
641 removeRange(li, LR->start, LR->end, li_, tri_);
642 return removeIntervalIfEmpty(li, li_, tri_);
645 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
647 // Livein but defined by a phi.
650 unsigned RemoveStart = LR->start;
651 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
652 if (LR->end > RemoveEnd)
653 // More uses past this copy? Nothing to do.
656 MachineBasicBlock *CopyMBB = CopyMI->getParent();
657 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
659 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
662 MachineInstr *LastUseMI = LastUse->getParent();
663 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
670 // r1025<dead> = r1024<kill>
671 if (MBBStart < LR->end)
672 removeRange(li, MBBStart, LR->end, li_, tri_);
676 // There are uses before the copy, just shorten the live range to the end
678 LastUse->setIsKill();
679 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
680 unsigned SrcReg, DstReg;
681 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
683 // Last use is itself an identity code.
684 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
685 LastUseMI->getOperand(DeadIdx).setIsDead();
691 if (LR->start <= MBBStart && LR->end > MBBStart) {
692 if (LR->start == 0) {
693 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
694 // Live-in to the function but dead. Remove it from entry live-in set.
695 mf_->begin()->removeLiveIn(li.reg);
697 // FIXME: Shorten intervals in BBs that reaches this BB.
700 if (LR->valno->def == RemoveStart)
701 // If the def MI defines the val#, propagate the dead marker.
702 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
704 removeRange(li, RemoveStart, LR->end, li_, tri_);
705 return removeIntervalIfEmpty(li, li_, tri_);
708 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
709 /// from an implicit def to another register can be coalesced away.
710 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
712 LiveInterval &ImpLi) const{
713 if (!CopyMI->killsRegister(ImpLi.reg))
715 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
716 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
719 if (LR->valno->hasPHIKill)
721 if (LR->valno->def != CopyIdx)
723 // Make sure all of val# uses are copies.
724 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
725 UE = mri_->use_end(); UI != UE;) {
726 MachineInstr *UseMI = &*UI;
728 if (JoinedCopies.count(UseMI))
730 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
731 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
732 if (ULR == li.end() || ULR->valno != LR->valno)
734 // If the use is not a use, then it's not safe to coalesce the move.
735 unsigned SrcReg, DstReg;
736 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
737 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
738 UseMI->getOperand(1).getReg() == li.reg)
747 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
748 /// def and it is being removed. Turn all copies from this value# into
749 /// identity copies so they will be removed.
750 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
752 SmallVector<MachineInstr*, 4> ImpDefs;
753 MachineOperand *LastUse = NULL;
754 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
755 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
756 RE = mri_->reg_end(); RI != RE;) {
757 MachineOperand *MO = &RI.getOperand();
758 MachineInstr *MI = &*RI;
761 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
762 ImpDefs.push_back(MI);
766 if (JoinedCopies.count(MI))
768 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
769 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
770 if (ULR == li.end() || ULR->valno != VNI)
772 // If the use is a copy, turn it into an identity copy.
773 unsigned SrcReg, DstReg;
774 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
775 // Each use MI may have multiple uses of this register. Change them all.
776 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
777 MachineOperand &MO = MI->getOperand(i);
778 if (MO.isReg() && MO.getReg() == li.reg)
781 JoinedCopies.insert(MI);
782 } else if (UseIdx > LastUseIdx) {
788 LastUse->setIsKill();
790 // Remove dead implicit_def's.
791 while (!ImpDefs.empty()) {
792 MachineInstr *ImpDef = ImpDefs.back();
794 li_->RemoveMachineInstrFromMaps(ImpDef);
795 ImpDef->eraseFromParent();
800 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
801 const TargetRegisterClass *RC,
802 const TargetRegisterInfo* TRI) {
803 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
804 unsigned SR = *SRs; ++SRs)
805 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
810 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
811 /// which are the src/dst of the copy instruction CopyMI. This returns true
812 /// if the copy was successfully coalesced away. If it is not currently
813 /// possible to coalesce this interval, but it may be possible if other
814 /// things get coalesced, then it returns true by reference in 'Again'.
815 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
816 MachineInstr *CopyMI = TheCopy.MI;
819 if (JoinedCopies.count(CopyMI))
820 return false; // Already done.
822 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
826 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
827 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
830 DstReg = CopyMI->getOperand(0).getReg();
831 SrcReg = CopyMI->getOperand(1).getReg();
832 } else if (isInsSubReg) {
833 if (CopyMI->getOperand(2).getSubReg()) {
834 DOUT << "\tSource of insert_subreg is already coalesced "
835 << "to another register.\n";
836 return false; // Not coalescable.
838 DstReg = CopyMI->getOperand(0).getReg();
839 SrcReg = CopyMI->getOperand(2).getReg();
840 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
841 assert(0 && "Unrecognized copy instruction!");
845 // If they are already joined we continue.
846 if (SrcReg == DstReg) {
847 DOUT << "\tCopy already coalesced.\n";
848 return false; // Not coalescable.
851 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
852 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
854 // If they are both physical registers, we cannot join them.
855 if (SrcIsPhys && DstIsPhys) {
856 DOUT << "\tCan not coalesce physregs.\n";
857 return false; // Not coalescable.
860 // We only join virtual registers with allocatable physical registers.
861 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
862 DOUT << "\tSrc reg is unallocatable physreg.\n";
863 return false; // Not coalescable.
865 if (DstIsPhys && !allocatableRegs_[DstReg]) {
866 DOUT << "\tDst reg is unallocatable physreg.\n";
867 return false; // Not coalescable.
870 unsigned RealDstReg = 0;
871 unsigned RealSrcReg = 0;
872 if (isExtSubReg || isInsSubReg) {
873 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
874 if (SrcIsPhys && isExtSubReg) {
875 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
876 // coalesced with AX.
877 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
879 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
880 // coalesced to a larger register so the subreg indices cancel out.
881 if (DstSubIdx != SubIdx) {
882 DOUT << "\t Sub-register indices mismatch.\n";
883 return false; // Not coalescable.
886 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
888 } else if (DstIsPhys && isInsSubReg) {
889 // EAX = INSERT_SUBREG EAX, r1024, 0
890 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
892 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
893 // coalesced to a larger register so the subreg indices cancel out.
894 if (SrcSubIdx != SubIdx) {
895 DOUT << "\t Sub-register indices mismatch.\n";
896 return false; // Not coalescable.
899 DstReg = tri_->getSubReg(DstReg, SubIdx);
901 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
902 // If this is a extract_subreg where dst is a physical register, e.g.
903 // cl = EXTRACT_SUBREG reg1024, 1
904 // then create and update the actual physical register allocated to RHS.
906 // reg1024 = INSERT_SUBREG r1024, cl, 1
907 if (CopyMI->getOperand(1).getSubReg()) {
908 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
909 << " of a super-class.\n";
910 return false; // Not coalescable.
912 const TargetRegisterClass *RC =
913 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
915 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
916 assert(RealDstReg && "Invalid extra_subreg instruction!");
918 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
919 assert(RealSrcReg && "Invalid extra_subreg instruction!");
922 // For this type of EXTRACT_SUBREG, conservatively
923 // check if the live interval of the source register interfere with the
924 // actual super physical register we are trying to coalesce with.
925 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
926 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
927 if (li_->hasInterval(PhysReg) &&
928 RHS.overlaps(li_->getInterval(PhysReg))) {
929 DOUT << "Interfere with register ";
930 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
931 return false; // Not coalescable
933 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
934 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
935 DOUT << "Interfere with sub-register ";
936 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
937 return false; // Not coalescable
941 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
942 : CopyMI->getOperand(2).getSubReg();
944 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
945 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
946 // coalesced to a larger register so the subreg indices cancel out.
947 // Also check if the other larger register is of the same register
948 // class as the would be resulting register.
951 DOUT << "\t Sub-register indices mismatch.\n";
952 return false; // Not coalescable.
956 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
957 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
958 unsigned LargeRegSize =
959 li_->getInterval(LargeReg).getSize() / InstrSlots::NUM;
960 unsigned SmallRegSize =
961 li_->getInterval(SmallReg).getSize() / InstrSlots::NUM;
962 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
963 unsigned Threshold = allocatableRCRegs_[RC].count();
964 // Be conservative. If both sides are virtual registers, do not coalesce
965 // if this will cause a high use density interval to target a smaller
967 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
968 if ((float)std::distance(mri_->use_begin(SmallReg),
969 mri_->use_end()) / SmallRegSize <
970 (float)std::distance(mri_->use_begin(LargeReg),
971 mri_->use_end()) / LargeRegSize) {
972 Again = true; // May be possible to coalesce later.
978 } else if (differingRegisterClasses(SrcReg, DstReg)) {
979 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
980 // with another? If it's the resulting destination register, then
981 // the subidx must be propagated to uses (but only those defined
982 // by the EXTRACT_SUBREG). If it's being coalesced into another
983 // register, it should be safe because register is assumed to have
984 // the register class of the super-register.
986 // If they are not of the same register class, we cannot join them.
987 DOUT << "\tSrc/Dest are different register classes.\n";
988 // Allow the coalescer to try again in case either side gets coalesced to
989 // a physical register that's compatible with the other side. e.g.
990 // r1024 = MOV32to32_ r1025
991 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
992 Again = true; // May be possible to coalesce later.
996 LiveInterval &SrcInt = li_->getInterval(SrcReg);
997 LiveInterval &DstInt = li_->getInterval(DstReg);
998 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
999 "Register mapping is horribly broken!");
1001 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1002 DOUT << " and "; DstInt.print(DOUT, tri_);
1005 // Check if it is necessary to propagate "isDead" property.
1006 if (!isExtSubReg && !isInsSubReg) {
1007 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1008 bool isDead = mopd->isDead();
1010 // We need to be careful about coalescing a source physical register with a
1011 // virtual register. Once the coalescing is done, it cannot be broken and
1012 // these are not spillable! If the destination interval uses are far away,
1013 // think twice about coalescing them!
1014 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1015 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1016 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1017 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1018 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1019 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1020 if (TheCopy.isBackEdge)
1021 Threshold *= 2; // Favors back edge copies.
1023 // If the virtual register live interval is long but it has low use desity,
1024 // do not join them, instead mark the physical register as its allocation
1026 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
1027 if (Length > Threshold &&
1028 (((float)std::distance(mri_->use_begin(JoinVReg),
1029 mri_->use_end()) / Length) < (1.0 / Threshold))) {
1030 JoinVInt.preference = JoinPReg;
1032 DOUT << "\tMay tie down a physical register, abort!\n";
1033 Again = true; // May be possible to coalesce later.
1039 // Okay, attempt to join these two intervals. On failure, this returns false.
1040 // Otherwise, if one of the intervals being joined is a physreg, this method
1041 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1042 // been modified, so we can use this information below to update aliases.
1043 bool Swapped = false;
1044 // If SrcInt is implicitly defined, it's safe to coalesce.
1045 bool isEmpty = SrcInt.empty();
1046 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1047 // Only coalesce an empty interval (defined by implicit_def) with
1048 // another interval which has a valno defined by the CopyMI and the CopyMI
1049 // is a kill of the implicit def.
1050 DOUT << "Not profitable!\n";
1054 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1055 // Coalescing failed.
1057 // If we can eliminate the copy without merging the live ranges, do so now.
1058 if (!isExtSubReg && !isInsSubReg &&
1059 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1060 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1061 JoinedCopies.insert(CopyMI);
1065 // Otherwise, we are unable to join the intervals.
1066 DOUT << "Interference!\n";
1067 Again = true; // May be possible to coalesce later.
1071 LiveInterval *ResSrcInt = &SrcInt;
1072 LiveInterval *ResDstInt = &DstInt;
1074 std::swap(SrcReg, DstReg);
1075 std::swap(ResSrcInt, ResDstInt);
1077 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1078 "LiveInterval::join didn't work right!");
1080 // If we're about to merge live ranges into a physical register live range,
1081 // we have to update any aliased register's live ranges to indicate that they
1082 // have clobbered values for this range.
1083 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1084 // If this is a extract_subreg where dst is a physical register, e.g.
1085 // cl = EXTRACT_SUBREG reg1024, 1
1086 // then create and update the actual physical register allocated to RHS.
1087 if (RealDstReg || RealSrcReg) {
1088 LiveInterval &RealInt =
1089 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1090 SmallSet<const VNInfo*, 4> CopiedValNos;
1091 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1092 E = ResSrcInt->ranges.end(); I != E; ++I) {
1093 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1094 assert(DstLR && "Invalid joined interval!");
1095 const VNInfo *DstValNo = DstLR->valno;
1096 if (CopiedValNos.insert(DstValNo)) {
1097 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1098 li_->getVNInfoAllocator());
1099 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1100 RealInt.addKills(ValNo, DstValNo->kills);
1101 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1105 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1108 // Update the liveintervals of sub-registers.
1109 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1110 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1111 li_->getVNInfoAllocator());
1114 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1115 // larger super-register.
1116 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1117 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1118 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1119 std::swap(SrcReg, DstReg);
1120 std::swap(ResSrcInt, ResDstInt);
1125 // Add all copies that define val# in the source interval into the queue.
1126 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1127 e = ResSrcInt->vni_end(); i != e; ++i) {
1128 const VNInfo *vni = *i;
1129 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1131 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1132 unsigned NewSrcReg, NewDstReg;
1134 JoinedCopies.count(CopyMI) == 0 &&
1135 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1136 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
1137 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1138 isBackEdgeCopy(CopyMI, DstReg)));
1143 // Remember to delete the copy instruction.
1144 JoinedCopies.insert(CopyMI);
1146 // Some live range has been lengthened due to colaescing, eliminate the
1147 // unnecessary kills.
1148 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1149 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1150 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1152 // SrcReg is guarateed to be the register whose live interval that is
1154 li_->removeInterval(SrcReg);
1158 // r1024 = implicit_def
1161 RemoveDeadImpDef(DstReg, *ResDstInt);
1162 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1165 // Now the copy is being coalesced away, the val# previously defined
1166 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1167 // length interval. Remove the val#.
1168 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1169 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1170 VNInfo *ImpVal = LR->valno;
1171 assert(ImpVal->def == CopyIdx);
1172 unsigned NextDef = LR->end;
1173 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1174 ResDstInt->removeValNo(ImpVal);
1175 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1176 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1177 // Special case: vr1024 = implicit_def
1178 // vr1024 = insert_subreg vr1024, vr1025, c
1179 // The insert_subreg becomes a "copy" that defines a val# which can itself
1180 // be coalesced away.
1181 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1182 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1183 LR->valno->copy = DefMI;
1187 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1194 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1195 /// compute what the resultant value numbers for each value in the input two
1196 /// ranges will be. This is complicated by copies between the two which can
1197 /// and will commonly cause multiple value numbers to be merged into one.
1199 /// VN is the value number that we're trying to resolve. InstDefiningValue
1200 /// keeps track of the new InstDefiningValue assignment for the result
1201 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1202 /// whether a value in this or other is a copy from the opposite set.
1203 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1204 /// already been assigned.
1206 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1207 /// contains the value number the copy is from.
1209 static unsigned ComputeUltimateVN(VNInfo *VNI,
1210 SmallVector<VNInfo*, 16> &NewVNInfo,
1211 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1212 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1213 SmallVector<int, 16> &ThisValNoAssignments,
1214 SmallVector<int, 16> &OtherValNoAssignments) {
1215 unsigned VN = VNI->id;
1217 // If the VN has already been computed, just return it.
1218 if (ThisValNoAssignments[VN] >= 0)
1219 return ThisValNoAssignments[VN];
1220 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1222 // If this val is not a copy from the other val, then it must be a new value
1223 // number in the destination.
1224 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1225 if (I == ThisFromOther.end()) {
1226 NewVNInfo.push_back(VNI);
1227 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1229 VNInfo *OtherValNo = I->second;
1231 // Otherwise, this *is* a copy from the RHS. If the other side has already
1232 // been computed, return it.
1233 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1234 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1236 // Mark this value number as currently being computed, then ask what the
1237 // ultimate value # of the other value is.
1238 ThisValNoAssignments[VN] = -2;
1239 unsigned UltimateVN =
1240 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1241 OtherValNoAssignments, ThisValNoAssignments);
1242 return ThisValNoAssignments[VN] = UltimateVN;
1245 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1246 return std::find(V.begin(), V.end(), Val) != V.end();
1249 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1250 /// the specified live interval is defined by a copy from the specified
1252 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1255 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1258 if (LR->valno->def == ~0U &&
1259 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1260 *tri_->getSuperRegisters(li.reg)) {
1261 // It's a sub-register live interval, we may not have precise information.
1263 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1264 unsigned SrcReg, DstReg;
1265 if (tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1266 DstReg == li.reg && SrcReg == Reg) {
1267 // Cache computed info.
1268 LR->valno->def = LR->start;
1269 LR->valno->copy = DefMI;
1276 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1277 /// caller of this method must guarantee that the RHS only contains a single
1278 /// value number and that the RHS is not defined by a copy from this
1279 /// interval. This returns false if the intervals are not joinable, or it
1280 /// joins them and returns true.
1281 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1282 assert(RHS.containsOneValue());
1284 // Some number (potentially more than one) value numbers in the current
1285 // interval may be defined as copies from the RHS. Scan the overlapping
1286 // portions of the LHS and RHS, keeping track of this and looking for
1287 // overlapping live ranges that are NOT defined as copies. If these exist, we
1290 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1291 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1293 if (LHSIt->start < RHSIt->start) {
1294 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1295 if (LHSIt != LHS.begin()) --LHSIt;
1296 } else if (RHSIt->start < LHSIt->start) {
1297 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1298 if (RHSIt != RHS.begin()) --RHSIt;
1301 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1304 // Determine if these live intervals overlap.
1305 bool Overlaps = false;
1306 if (LHSIt->start <= RHSIt->start)
1307 Overlaps = LHSIt->end > RHSIt->start;
1309 Overlaps = RHSIt->end > LHSIt->start;
1311 // If the live intervals overlap, there are two interesting cases: if the
1312 // LHS interval is defined by a copy from the RHS, it's ok and we record
1313 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1314 // coalesce these live ranges and we bail out.
1316 // If we haven't already recorded that this value # is safe, check it.
1317 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1318 // Copy from the RHS?
1319 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1320 return false; // Nope, bail out.
1322 if (LHSIt->contains(RHSIt->valno->def))
1323 // Here is an interesting situation:
1325 // vr1025 = copy vr1024
1330 // Even though vr1025 is copied from vr1024, it's not safe to
1331 // coalesced them since live range of vr1025 intersects the
1332 // def of vr1024. This happens because vr1025 is assigned the
1333 // value of the previous iteration of vr1024.
1335 EliminatedLHSVals.push_back(LHSIt->valno);
1338 // We know this entire LHS live range is okay, so skip it now.
1339 if (++LHSIt == LHSEnd) break;
1343 if (LHSIt->end < RHSIt->end) {
1344 if (++LHSIt == LHSEnd) break;
1346 // One interesting case to check here. It's possible that we have
1347 // something like "X3 = Y" which defines a new value number in the LHS,
1348 // and is the last use of this liverange of the RHS. In this case, we
1349 // want to notice this copy (so that it gets coalesced away) even though
1350 // the live ranges don't actually overlap.
1351 if (LHSIt->start == RHSIt->end) {
1352 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1353 // We already know that this value number is going to be merged in
1354 // if coalescing succeeds. Just skip the liverange.
1355 if (++LHSIt == LHSEnd) break;
1357 // Otherwise, if this is a copy from the RHS, mark it as being merged
1359 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1360 if (LHSIt->contains(RHSIt->valno->def))
1361 // Here is an interesting situation:
1363 // vr1025 = copy vr1024
1368 // Even though vr1025 is copied from vr1024, it's not safe to
1369 // coalesced them since live range of vr1025 intersects the
1370 // def of vr1024. This happens because vr1025 is assigned the
1371 // value of the previous iteration of vr1024.
1373 EliminatedLHSVals.push_back(LHSIt->valno);
1375 // We know this entire LHS live range is okay, so skip it now.
1376 if (++LHSIt == LHSEnd) break;
1381 if (++RHSIt == RHSEnd) break;
1385 // If we got here, we know that the coalescing will be successful and that
1386 // the value numbers in EliminatedLHSVals will all be merged together. Since
1387 // the most common case is that EliminatedLHSVals has a single number, we
1388 // optimize for it: if there is more than one value, we merge them all into
1389 // the lowest numbered one, then handle the interval as if we were merging
1390 // with one value number.
1392 if (EliminatedLHSVals.size() > 1) {
1393 // Loop through all the equal value numbers merging them into the smallest
1395 VNInfo *Smallest = EliminatedLHSVals[0];
1396 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1397 if (EliminatedLHSVals[i]->id < Smallest->id) {
1398 // Merge the current notion of the smallest into the smaller one.
1399 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1400 Smallest = EliminatedLHSVals[i];
1402 // Merge into the smallest.
1403 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1406 LHSValNo = Smallest;
1407 } else if (EliminatedLHSVals.empty()) {
1408 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1409 *tri_->getSuperRegisters(LHS.reg))
1410 // Imprecise sub-register information. Can't handle it.
1412 assert(0 && "No copies from the RHS?");
1414 LHSValNo = EliminatedLHSVals[0];
1417 // Okay, now that there is a single LHS value number that we're merging the
1418 // RHS into, update the value number info for the LHS to indicate that the
1419 // value number is defined where the RHS value number was.
1420 const VNInfo *VNI = RHS.getValNumInfo(0);
1421 LHSValNo->def = VNI->def;
1422 LHSValNo->copy = VNI->copy;
1424 // Okay, the final step is to loop over the RHS live intervals, adding them to
1426 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1427 LHS.addKills(LHSValNo, VNI->kills);
1428 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1429 LHS.weight += RHS.weight;
1430 if (RHS.preference && !LHS.preference)
1431 LHS.preference = RHS.preference;
1436 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1437 /// returns false. Otherwise, if one of the intervals being joined is a
1438 /// physreg, this method always canonicalizes LHS to be it. The output
1439 /// "RHS" will not have been modified, so we can use this information
1440 /// below to update aliases.
1441 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
1442 LiveInterval &RHS, bool &Swapped) {
1443 // Compute the final value assignment, assuming that the live ranges can be
1445 SmallVector<int, 16> LHSValNoAssignments;
1446 SmallVector<int, 16> RHSValNoAssignments;
1447 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1448 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1449 SmallVector<VNInfo*, 16> NewVNInfo;
1451 // If a live interval is a physical register, conservatively check if any
1452 // of its sub-registers is overlapping the live interval of the virtual
1453 // register. If so, do not coalesce.
1454 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1455 *tri_->getSubRegisters(LHS.reg)) {
1456 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1457 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1458 DOUT << "Interfere with sub-register ";
1459 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1462 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1463 *tri_->getSubRegisters(RHS.reg)) {
1464 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1465 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1466 DOUT << "Interfere with sub-register ";
1467 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1472 // Compute ultimate value numbers for the LHS and RHS values.
1473 if (RHS.containsOneValue()) {
1474 // Copies from a liveinterval with a single value are simple to handle and
1475 // very common, handle the special case here. This is important, because
1476 // often RHS is small and LHS is large (e.g. a physreg).
1478 // Find out if the RHS is defined as a copy from some value in the LHS.
1479 int RHSVal0DefinedFromLHS = -1;
1481 VNInfo *RHSValNoInfo = NULL;
1482 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1483 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1484 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1485 // If RHS is not defined as a copy from the LHS, we can use simpler and
1486 // faster checks to see if the live ranges are coalescable. This joiner
1487 // can't swap the LHS/RHS intervals though.
1488 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1489 return SimpleJoin(LHS, RHS);
1491 RHSValNoInfo = RHSValNoInfo0;
1494 // It was defined as a copy from the LHS, find out what value # it is.
1495 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1496 RHSValID = RHSValNoInfo->id;
1497 RHSVal0DefinedFromLHS = RHSValID;
1500 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1501 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1502 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1504 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1505 // should now get updated.
1506 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1509 unsigned VN = VNI->id;
1510 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1511 if (LHSSrcReg != RHS.reg) {
1512 // If this is not a copy from the RHS, its value number will be
1513 // unmodified by the coalescing.
1514 NewVNInfo[VN] = VNI;
1515 LHSValNoAssignments[VN] = VN;
1516 } else if (RHSValID == -1) {
1517 // Otherwise, it is a copy from the RHS, and we don't already have a
1518 // value# for it. Keep the current value number, but remember it.
1519 LHSValNoAssignments[VN] = RHSValID = VN;
1520 NewVNInfo[VN] = RHSValNoInfo;
1521 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1523 // Otherwise, use the specified value #.
1524 LHSValNoAssignments[VN] = RHSValID;
1525 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1526 NewVNInfo[VN] = RHSValNoInfo;
1527 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1531 NewVNInfo[VN] = VNI;
1532 LHSValNoAssignments[VN] = VN;
1536 assert(RHSValID != -1 && "Didn't find value #?");
1537 RHSValNoAssignments[0] = RHSValID;
1538 if (RHSVal0DefinedFromLHS != -1) {
1539 // This path doesn't go through ComputeUltimateVN so just set
1541 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1544 // Loop over the value numbers of the LHS, seeing if any are defined from
1546 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1549 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1552 // DstReg is known to be a register in the LHS interval. If the src is
1553 // from the RHS interval, we can use its value #.
1554 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1557 // Figure out the value # from the RHS.
1558 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1561 // Loop over the value numbers of the RHS, seeing if any are defined from
1563 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1566 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1569 // DstReg is known to be a register in the RHS interval. If the src is
1570 // from the LHS interval, we can use its value #.
1571 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1574 // Figure out the value # from the LHS.
1575 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1578 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1579 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1580 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1582 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1585 unsigned VN = VNI->id;
1586 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1588 ComputeUltimateVN(VNI, NewVNInfo,
1589 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1590 LHSValNoAssignments, RHSValNoAssignments);
1592 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1595 unsigned VN = VNI->id;
1596 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1598 // If this value number isn't a copy from the LHS, it's a new number.
1599 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1600 NewVNInfo.push_back(VNI);
1601 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1605 ComputeUltimateVN(VNI, NewVNInfo,
1606 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1607 RHSValNoAssignments, LHSValNoAssignments);
1611 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1612 // interval lists to see if these intervals are coalescable.
1613 LiveInterval::const_iterator I = LHS.begin();
1614 LiveInterval::const_iterator IE = LHS.end();
1615 LiveInterval::const_iterator J = RHS.begin();
1616 LiveInterval::const_iterator JE = RHS.end();
1618 // Skip ahead until the first place of potential sharing.
1619 if (I->start < J->start) {
1620 I = std::upper_bound(I, IE, J->start);
1621 if (I != LHS.begin()) --I;
1622 } else if (J->start < I->start) {
1623 J = std::upper_bound(J, JE, I->start);
1624 if (J != RHS.begin()) --J;
1628 // Determine if these two live ranges overlap.
1630 if (I->start < J->start) {
1631 Overlaps = I->end > J->start;
1633 Overlaps = J->end > I->start;
1636 // If so, check value # info to determine if they are really different.
1638 // If the live range overlap will map to the same value number in the
1639 // result liverange, we can still coalesce them. If not, we can't.
1640 if (LHSValNoAssignments[I->valno->id] !=
1641 RHSValNoAssignments[J->valno->id])
1645 if (I->end < J->end) {
1654 // Update kill info. Some live ranges are extended due to copy coalescing.
1655 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1656 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1657 VNInfo *VNI = I->first;
1658 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1659 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1660 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1661 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1664 // Update kill info. Some live ranges are extended due to copy coalescing.
1665 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1666 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1667 VNInfo *VNI = I->first;
1668 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1669 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1670 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1671 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1674 // If we get here, we know that we can coalesce the live ranges. Ask the
1675 // intervals to coalesce themselves now.
1676 if ((RHS.ranges.size() > LHS.ranges.size() &&
1677 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1678 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1679 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1682 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1689 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1690 // depth of the basic block (the unsigned), and then on the MBB number.
1691 struct DepthMBBCompare {
1692 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1693 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1694 if (LHS.first > RHS.first) return true; // Deeper loops first
1695 return LHS.first == RHS.first &&
1696 LHS.second->getNumber() < RHS.second->getNumber();
1701 /// getRepIntervalSize - Returns the size of the interval that represents the
1702 /// specified register.
1704 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1705 return Rc->getRepIntervalSize(Reg);
1708 /// CopyRecSort::operator - Join priority queue sorting function.
1710 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1711 // Inner loops first.
1712 if (left.LoopDepth > right.LoopDepth)
1714 else if (left.LoopDepth == right.LoopDepth)
1715 if (left.isBackEdge && !right.isBackEdge)
1720 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1721 std::vector<CopyRec> &TryAgain) {
1722 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1724 std::vector<CopyRec> VirtCopies;
1725 std::vector<CopyRec> PhysCopies;
1726 std::vector<CopyRec> ImpDefCopies;
1727 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1728 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1730 MachineInstr *Inst = MII++;
1732 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1733 unsigned SrcReg, DstReg;
1734 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1735 DstReg = Inst->getOperand(0).getReg();
1736 SrcReg = Inst->getOperand(1).getReg();
1737 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1738 DstReg = Inst->getOperand(0).getReg();
1739 SrcReg = Inst->getOperand(2).getReg();
1740 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1743 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1744 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1746 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
1748 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1749 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
1750 else if (SrcIsPhys || DstIsPhys)
1751 PhysCopies.push_back(CopyRec(Inst, 0, false));
1753 VirtCopies.push_back(CopyRec(Inst, 0, false));
1760 // Try coalescing implicit copies first, followed by copies to / from
1761 // physical registers, then finally copies from virtual registers to
1762 // virtual registers.
1763 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1764 CopyRec &TheCopy = ImpDefCopies[i];
1766 if (!JoinCopy(TheCopy, Again))
1768 TryAgain.push_back(TheCopy);
1770 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1771 CopyRec &TheCopy = PhysCopies[i];
1773 if (!JoinCopy(TheCopy, Again))
1775 TryAgain.push_back(TheCopy);
1777 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1778 CopyRec &TheCopy = VirtCopies[i];
1780 if (!JoinCopy(TheCopy, Again))
1782 TryAgain.push_back(TheCopy);
1786 void SimpleRegisterCoalescing::joinIntervals() {
1787 DOUT << "********** JOINING INTERVALS ***********\n";
1790 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1792 std::vector<CopyRec> TryAgainList;
1793 if (loopInfo->begin() == loopInfo->end()) {
1794 // If there are no loops in the function, join intervals in function order.
1795 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1797 CopyCoalesceInMBB(I, TryAgainList);
1799 // Otherwise, join intervals in inner loops before other intervals.
1800 // Unfortunately we can't just iterate over loop hierarchy here because
1801 // there may be more MBB's than BB's. Collect MBB's for sorting.
1803 // Join intervals in the function prolog first. We want to join physical
1804 // registers with virtual registers before the intervals got too long.
1805 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1806 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1807 MachineBasicBlock *MBB = I;
1808 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1811 // Sort by loop depth.
1812 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1814 // Finally, join intervals in loop nest order.
1815 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1816 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1819 // Joining intervals can allow other intervals to be joined. Iteratively join
1820 // until we make no progress.
1822 SmallVector<CopyRec, 16> TryAgain;
1823 bool ProgressMade = true;
1824 while (ProgressMade) {
1825 ProgressMade = false;
1826 while (!JoinQueue->empty()) {
1827 CopyRec R = JoinQueue->pop();
1829 bool Success = JoinCopy(R, Again);
1831 ProgressMade = true;
1833 TryAgain.push_back(R);
1837 while (!TryAgain.empty()) {
1838 JoinQueue->push(TryAgain.back());
1839 TryAgain.pop_back();
1844 bool ProgressMade = true;
1845 while (ProgressMade) {
1846 ProgressMade = false;
1848 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1849 CopyRec &TheCopy = TryAgainList[i];
1852 bool Success = JoinCopy(TheCopy, Again);
1853 if (Success || !Again) {
1854 TheCopy.MI = 0; // Mark this one as done.
1855 ProgressMade = true;
1866 /// Return true if the two specified registers belong to different register
1867 /// classes. The registers may be either phys or virt regs.
1868 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1869 unsigned RegB) const {
1871 // Get the register classes for the first reg.
1872 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1873 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1874 "Shouldn't consider two physregs!");
1875 return !mri_->getRegClass(RegB)->contains(RegA);
1878 // Compare against the regclass for the second reg.
1879 const TargetRegisterClass *RegClass = mri_->getRegClass(RegA);
1880 if (TargetRegisterInfo::isVirtualRegister(RegB))
1881 return RegClass != mri_->getRegClass(RegB);
1883 return !RegClass->contains(RegB);
1886 /// lastRegisterUse - Returns the last use of the specific register between
1887 /// cycles Start and End or NULL if there are no uses.
1889 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
1890 unsigned Reg, unsigned &UseIdx) const{
1892 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1893 MachineOperand *LastUse = NULL;
1894 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
1895 E = mri_->use_end(); I != E; ++I) {
1896 MachineOperand &Use = I.getOperand();
1897 MachineInstr *UseMI = Use.getParent();
1898 unsigned SrcReg, DstReg;
1899 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
1900 // Ignore identity copies.
1902 unsigned Idx = li_->getInstructionIndex(UseMI);
1903 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1911 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1914 // Skip deleted instructions
1915 MachineInstr *MI = li_->getInstructionFromIndex(e);
1916 while ((e - InstrSlots::NUM) >= s && !MI) {
1917 e -= InstrSlots::NUM;
1918 MI = li_->getInstructionFromIndex(e);
1920 if (e < s || MI == NULL)
1923 // Ignore identity copies.
1924 unsigned SrcReg, DstReg;
1925 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
1926 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1927 MachineOperand &Use = MI->getOperand(i);
1928 if (Use.isRegister() && Use.isUse() && Use.getReg() &&
1929 tri_->regsOverlap(Use.getReg(), Reg)) {
1935 e -= InstrSlots::NUM;
1942 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1943 if (TargetRegisterInfo::isPhysicalRegister(reg))
1944 cerr << tri_->getName(reg);
1946 cerr << "%reg" << reg;
1949 void SimpleRegisterCoalescing::releaseMemory() {
1950 JoinedCopies.clear();
1953 static bool isZeroLengthInterval(LiveInterval *li) {
1954 for (LiveInterval::Ranges::const_iterator
1955 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1956 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1961 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
1962 /// turn the copy into an implicit def.
1964 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
1965 MachineBasicBlock *MBB,
1966 unsigned DstReg, unsigned SrcReg) {
1967 MachineInstr *CopyMI = &*I;
1968 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1969 if (!li_->hasInterval(SrcReg))
1971 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1972 if (!SrcInt.empty())
1974 if (!li_->hasInterval(DstReg))
1976 LiveInterval &DstInt = li_->getInterval(DstReg);
1977 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
1978 DstInt.removeValNo(DstLR->valno);
1979 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
1980 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
1981 CopyMI->RemoveOperand(i);
1982 bool NoUse = mri_->use_begin(SrcReg) == mri_->use_end();
1984 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
1985 E = mri_->reg_end(); I != E; ) {
1986 assert(I.getOperand().isDef());
1987 MachineInstr *DefMI = &*I;
1989 // The implicit_def source has no other uses, delete it.
1990 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
1991 li_->RemoveMachineInstrFromMaps(DefMI);
1992 DefMI->eraseFromParent();
2000 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2002 mri_ = &fn.getRegInfo();
2003 tm_ = &fn.getTarget();
2004 tri_ = tm_->getRegisterInfo();
2005 tii_ = tm_->getInstrInfo();
2006 li_ = &getAnalysis<LiveIntervals>();
2007 loopInfo = &getAnalysis<MachineLoopInfo>();
2009 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2010 << "********** Function: "
2011 << ((Value*)mf_->getFunction())->getName() << '\n';
2013 allocatableRegs_ = tri_->getAllocatableSet(fn);
2014 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2015 E = tri_->regclass_end(); I != E; ++I)
2016 allocatableRCRegs_.insert(std::make_pair(*I,
2017 tri_->getAllocatableSet(fn, *I)));
2019 // Join (coalesce) intervals if requested.
2020 if (EnableJoining) {
2022 DOUT << "********** INTERVALS POST JOINING **********\n";
2023 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2024 I->second.print(DOUT, tri_);
2029 // Perform a final pass over the instructions and compute spill weights
2030 // and remove identity moves.
2031 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2032 mbbi != mbbe; ++mbbi) {
2033 MachineBasicBlock* mbb = mbbi;
2034 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2036 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2038 MachineInstr *MI = mii;
2039 unsigned SrcReg, DstReg;
2040 if (JoinedCopies.count(MI)) {
2041 // Delete all coalesced copies.
2042 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) {
2043 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2044 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2045 "Unrecognized copy instruction");
2046 DstReg = MI->getOperand(0).getReg();
2048 if (MI->registerDefIsDead(DstReg)) {
2049 LiveInterval &li = li_->getInterval(DstReg);
2050 if (!ShortenDeadCopySrcLiveRange(li, MI))
2051 ShortenDeadCopyLiveRange(li, MI);
2053 li_->RemoveMachineInstrFromMaps(MI);
2054 mii = mbbi->erase(mii);
2059 // If the move will be an identity move delete it
2060 bool isMove = tii_->isMoveInstr(*mii, SrcReg, DstReg);
2061 if (isMove && SrcReg == DstReg) {
2062 if (li_->hasInterval(SrcReg)) {
2063 LiveInterval &RegInt = li_->getInterval(SrcReg);
2064 // If def of this move instruction is dead, remove its live range
2065 // from the dstination register's live interval.
2066 if (mii->registerDefIsDead(DstReg)) {
2067 if (!ShortenDeadCopySrcLiveRange(RegInt, mii))
2068 ShortenDeadCopyLiveRange(RegInt, mii);
2071 li_->RemoveMachineInstrFromMaps(mii);
2072 mii = mbbi->erase(mii);
2074 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2075 SmallSet<unsigned, 4> UniqueUses;
2076 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
2077 const MachineOperand &mop = mii->getOperand(i);
2078 if (mop.isRegister() && mop.getReg() &&
2079 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2080 unsigned reg = mop.getReg();
2081 // Multiple uses of reg by the same instruction. It should not
2082 // contribute to spill weight again.
2083 if (UniqueUses.count(reg) != 0)
2085 LiveInterval &RegInt = li_->getInterval(reg);
2087 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2088 UniqueUses.insert(reg);
2096 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2097 LiveInterval &LI = I->second;
2098 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2099 // If the live interval length is essentially zero, i.e. in every live
2100 // range the use follows def immediately, it doesn't make sense to spill
2101 // it and hope it will be easier to allocate for this li.
2102 if (isZeroLengthInterval(&LI))
2103 LI.weight = HUGE_VALF;
2105 bool isLoad = false;
2106 if (li_->isReMaterializable(LI, isLoad)) {
2107 // If all of the definitions of the interval are re-materializable,
2108 // it is a preferred candidate for spilling. If non of the defs are
2109 // loads, then it's potentially very cheap to re-materialize.
2110 // FIXME: this gets much more complicated once we support non-trivial
2111 // re-materialization.
2119 // Slightly prefer live interval that has been assigned a preferred reg.
2123 // Divide the weight of the interval by its size. This encourages
2124 // spilling of intervals that are large and have few uses, and
2125 // discourages spilling of small intervals with many uses.
2126 LI.weight /= LI.getSize();
2134 /// print - Implement the dump method.
2135 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2139 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2140 return new SimpleRegisterCoalescing();
2143 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2144 DEFINING_FILE_FOR(SimpleRegisterCoalescing)