1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numSubJoins , "Number of subclass joins performed");
40 STATISTIC(numCommutes , "Number of instruction commuting performed");
41 STATISTIC(numExtends , "Number of copies extended");
42 STATISTIC(NumReMats , "Number of instructions re-materialized");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numAborts , "Number of times interval joining aborted");
46 char SimpleRegisterCoalescing::ID = 0;
48 EnableJoining("join-liveintervals",
49 cl::desc("Coalesce copies (default=true)"),
53 NewHeuristic("new-coalescer-heuristic",
54 cl::desc("Use new coalescer heuristic"),
55 cl::init(false), cl::Hidden);
58 CrossClassJoin("join-subclass-copies",
59 cl::desc("Coalesce copies to sub- register class"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<LiveIntervals>();
72 AU.addPreserved<LiveIntervals>();
73 AU.addRequired<MachineLoopInfo>();
74 AU.addPreserved<MachineLoopInfo>();
75 AU.addPreservedID(MachineDominatorsID);
77 AU.addPreservedID(StrongPHIEliminationID);
79 AU.addPreservedID(PHIEliminationID);
80 AU.addPreservedID(TwoAddressInstructionPassID);
81 MachineFunctionPass::getAnalysisUsage(AU);
84 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
85 /// being the source and IntB being the dest, thus this defines a value number
86 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
87 /// see if we can merge these two pieces of B into a single value number,
88 /// eliminating a copy. For example:
92 /// B1 = A3 <- this copy
94 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
95 /// value number to be replaced with B0 (which simplifies the B liveinterval).
97 /// This returns true if an interval was modified.
99 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
101 MachineInstr *CopyMI) {
102 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
104 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
105 // the example above.
106 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
107 if (BLR == IntB.end()) // Should never happen!
109 VNInfo *BValNo = BLR->valno;
111 // Get the location that B is defined at. Two options: either this value has
112 // an unknown definition point or it is defined at CopyIdx. If unknown, we
114 if (!BValNo->copy) return false;
115 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
117 // AValNo is the value number in A that defines the copy, A3 in the example.
118 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
119 if (ALR == IntA.end()) // Should never happen!
121 VNInfo *AValNo = ALR->valno;
123 // If AValNo is defined as a copy from IntB, we can potentially process this.
124 // Get the instruction that defines this value number.
125 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
126 if (!SrcReg) return false; // Not defined by a copy.
128 // If the value number is not defined by a copy instruction, ignore it.
130 // If the source register comes from an interval other than IntB, we can't
132 if (SrcReg != IntB.reg) return false;
134 // Get the LiveRange in IntB that this value number starts with.
135 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
136 if (ValLR == IntB.end()) // Should never happen!
139 // Make sure that the end of the live range is inside the same block as
141 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
143 ValLREndInst->getParent() != CopyMI->getParent()) return false;
145 // Okay, we now know that ValLR ends in the same block that the CopyMI
146 // live-range starts. If there are no intervening live ranges between them in
147 // IntB, we can merge them.
148 if (ValLR+1 != BLR) return false;
150 // If a live interval is a physical register, conservatively check if any
151 // of its sub-registers is overlapping the live interval of the virtual
152 // register. If so, do not coalesce.
153 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
154 *tri_->getSubRegisters(IntB.reg)) {
155 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
156 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
157 DOUT << "Interfere with sub-register ";
158 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
163 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
165 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
166 // We are about to delete CopyMI, so need to remove it as the 'instruction
167 // that defines this value #'. Update the the valnum with the new defining
169 BValNo->def = FillerStart;
172 // Okay, we can merge them. We need to insert a new liverange:
173 // [ValLR.end, BLR.begin) of either value number, then we merge the
174 // two value numbers.
175 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
177 // If the IntB live range is assigned to a physical register, and if that
178 // physreg has aliases,
179 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
180 // Update the liveintervals of sub-registers.
181 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
182 LiveInterval &AliasLI = li_->getInterval(*AS);
183 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
184 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
188 // Okay, merge "B1" into the same value number as "B0".
189 if (BValNo != ValLR->valno) {
190 IntB.addKills(ValLR->valno, BValNo->kills);
191 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
193 DOUT << " result = "; IntB.print(DOUT, tri_);
196 // If the source instruction was killing the source register before the
197 // merge, unset the isKill marker given the live range has been extended.
198 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
200 ValLREndInst->getOperand(UIdx).setIsKill(false);
201 IntB.removeKill(ValLR->valno, FillerStart);
208 /// HasOtherReachingDefs - Return true if there are definitions of IntB
209 /// other than BValNo val# that can reach uses of AValno val# of IntA.
210 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
214 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
216 if (AI->valno != AValNo) continue;
217 LiveInterval::Ranges::iterator BI =
218 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
219 if (BI != IntB.ranges.begin())
221 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
222 if (BI->valno == BValNo)
224 if (BI->start <= AI->start && BI->end > AI->start)
226 if (BI->start > AI->start && BI->start < AI->end)
233 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
234 /// being the source and IntB being the dest, thus this defines a value number
235 /// in IntB. If the source value number (in IntA) is defined by a commutable
236 /// instruction and its other operand is coalesced to the copy dest register,
237 /// see if we can transform the copy into a noop by commuting the definition. For
240 /// A3 = op A2 B0<kill>
242 /// B1 = A3 <- this copy
244 /// = op A3 <- more uses
248 /// B2 = op B0 A2<kill>
250 /// B1 = B2 <- now an identify copy
252 /// = op B2 <- more uses
254 /// This returns true if an interval was modified.
256 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
258 MachineInstr *CopyMI) {
259 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
261 // FIXME: For now, only eliminate the copy by commuting its def when the
262 // source register is a virtual register. We want to guard against cases
263 // where the copy is a back edge copy and commuting the def lengthen the
264 // live interval of the source register to the entire loop.
265 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
268 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
269 // the example above.
270 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
271 if (BLR == IntB.end()) // Should never happen!
273 VNInfo *BValNo = BLR->valno;
275 // Get the location that B is defined at. Two options: either this value has
276 // an unknown definition point or it is defined at CopyIdx. If unknown, we
278 if (!BValNo->copy) return false;
279 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
281 // AValNo is the value number in A that defines the copy, A3 in the example.
282 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
283 if (ALR == IntA.end()) // Should never happen!
285 VNInfo *AValNo = ALR->valno;
286 // If other defs can reach uses of this def, then it's not safe to perform
288 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
290 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
291 const TargetInstrDesc &TID = DefMI->getDesc();
293 if (!TID.isCommutable() ||
294 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
297 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
298 unsigned NewReg = NewDstMO.getReg();
299 if (NewReg != IntB.reg || !NewDstMO.isKill())
302 // Make sure there are no other definitions of IntB that would reach the
303 // uses which the new definition can reach.
304 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
307 // If some of the uses of IntA.reg is already coalesced away, return false.
308 // It's not possible to determine whether it's safe to perform the coalescing.
309 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
310 UE = mri_->use_end(); UI != UE; ++UI) {
311 MachineInstr *UseMI = &*UI;
312 unsigned UseIdx = li_->getInstructionIndex(UseMI);
313 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
314 if (ULR == IntA.end())
316 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
320 // At this point we have decided that it is legal to do this
321 // transformation. Start by commuting the instruction.
322 MachineBasicBlock *MBB = DefMI->getParent();
323 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
326 if (NewMI != DefMI) {
327 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
328 MBB->insert(DefMI, NewMI);
331 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
332 NewMI->getOperand(OpIdx).setIsKill();
334 bool BHasPHIKill = BValNo->hasPHIKill;
335 SmallVector<VNInfo*, 4> BDeadValNos;
336 SmallVector<unsigned, 4> BKills;
337 std::map<unsigned, unsigned> BExtend;
339 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
348 // then do not add kills of A to the newly created B interval.
349 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
351 BExtend[ALR->end] = BLR->end;
353 // Update uses of IntA of the specific Val# with IntB.
354 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
355 UE = mri_->use_end(); UI != UE;) {
356 MachineOperand &UseMO = UI.getOperand();
357 MachineInstr *UseMI = &*UI;
359 if (JoinedCopies.count(UseMI))
361 unsigned UseIdx = li_->getInstructionIndex(UseMI);
362 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
363 if (ULR == IntA.end() || ULR->valno != AValNo)
365 UseMO.setReg(NewReg);
368 if (UseMO.isKill()) {
370 UseMO.setIsKill(false);
372 BKills.push_back(li_->getUseIndex(UseIdx)+1);
374 unsigned SrcReg, DstReg;
375 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
377 if (DstReg == IntB.reg) {
378 // This copy will become a noop. If it's defining a new val#,
379 // remove that val# as well. However this live range is being
380 // extended to the end of the existing live range defined by the copy.
381 unsigned DefIdx = li_->getDefIndex(UseIdx);
382 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
383 BHasPHIKill |= DLR->valno->hasPHIKill;
384 assert(DLR->valno->def == DefIdx);
385 BDeadValNos.push_back(DLR->valno);
386 BExtend[DLR->start] = DLR->end;
387 JoinedCopies.insert(UseMI);
388 // If this is a kill but it's going to be removed, the last use
389 // of the same val# is the new kill.
395 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
396 // simply extend BLR if CopyMI doesn't end the range.
397 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
399 // Remove val#'s defined by copies that will be coalesced away.
400 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
401 IntB.removeValNo(BDeadValNos[i]);
403 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
404 // is updated. Kills are also updated.
405 VNInfo *ValNo = BValNo;
406 ValNo->def = AValNo->def;
408 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
409 unsigned Kill = ValNo->kills[j];
410 if (Kill != BLR->end)
411 BKills.push_back(Kill);
413 ValNo->kills.clear();
414 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
416 if (AI->valno != AValNo) continue;
417 unsigned End = AI->end;
418 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
419 if (EI != BExtend.end())
421 IntB.addRange(LiveRange(AI->start, End, ValNo));
423 IntB.addKills(ValNo, BKills);
424 ValNo->hasPHIKill = BHasPHIKill;
426 DOUT << " result = "; IntB.print(DOUT, tri_);
429 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
430 IntA.removeValNo(AValNo);
431 DOUT << " result = "; IntA.print(DOUT, tri_);
438 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
439 /// computation, replace the copy by rematerialize the definition.
440 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
442 MachineInstr *CopyMI) {
443 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
444 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
445 if (SrcLR == SrcInt.end()) // Should never happen!
447 VNInfo *ValNo = SrcLR->valno;
448 // If other defs can reach uses of this def, then it's not safe to perform
450 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
452 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
453 const TargetInstrDesc &TID = DefMI->getDesc();
454 if (!TID.isAsCheapAsAMove())
456 bool SawStore = false;
457 if (!DefMI->isSafeToMove(tii_, SawStore))
460 unsigned DefIdx = li_->getDefIndex(CopyIdx);
461 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
462 DLR->valno->copy = NULL;
463 // Don't forget to update sub-register intervals.
464 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
465 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
466 if (!li_->hasInterval(*SR))
468 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
469 if (DLR && DLR->valno->copy == CopyMI)
470 DLR->valno->copy = NULL;
474 MachineBasicBlock *MBB = CopyMI->getParent();
475 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
476 CopyMI->removeFromParent();
477 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
478 MachineInstr *NewMI = prior(MII);
479 // CopyMI may have implicit operands, transfer them over to the newly
480 // rematerialized instruction. And update implicit def interval valnos.
481 for (unsigned i = CopyMI->getDesc().getNumOperands(),
482 e = CopyMI->getNumOperands(); i != e; ++i) {
483 MachineOperand &MO = CopyMI->getOperand(i);
484 if (MO.isReg() && MO.isImplicit())
485 NewMI->addOperand(MO);
486 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
487 unsigned Reg = MO.getReg();
488 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
489 if (DLR && DLR->valno->copy == CopyMI)
490 DLR->valno->copy = NULL;
494 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
495 MBB->getParent()->DeleteMachineInstr(CopyMI);
496 ReMatCopies.insert(CopyMI);
497 ReMatDefs.insert(DefMI);
502 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
504 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
505 unsigned DstReg) const {
506 MachineBasicBlock *MBB = CopyMI->getParent();
507 const MachineLoop *L = loopInfo->getLoopFor(MBB);
510 if (MBB != L->getLoopLatch())
513 LiveInterval &LI = li_->getInterval(DstReg);
514 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
515 LiveInterval::const_iterator DstLR =
516 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
517 if (DstLR == LI.end())
519 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
520 if (DstLR->valno->kills.size() == 1 &&
521 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
526 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
527 /// update the subregister number if it is not zero. If DstReg is a
528 /// physical register and the existing subregister number of the def / use
529 /// being updated is not zero, make sure to set it to the correct physical
532 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
534 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
535 if (DstIsPhys && SubIdx) {
536 // Figure out the real physical register we are updating with.
537 DstReg = tri_->getSubReg(DstReg, SubIdx);
541 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
542 E = mri_->reg_end(); I != E; ) {
543 MachineOperand &O = I.getOperand();
544 MachineInstr *UseMI = &*I;
546 unsigned OldSubIdx = O.getSubReg();
548 unsigned UseDstReg = DstReg;
550 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
552 unsigned CopySrcReg, CopyDstReg;
553 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
554 CopySrcReg != CopyDstReg &&
555 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
556 // If the use is a copy and it won't be coalesced away, and its source
557 // is defined by a trivial computation, try to rematerialize it instead.
558 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
567 // Sub-register indexes goes from small to large. e.g.
568 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
569 // EAX: 1 -> AL, 2 -> AX
570 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
571 // sub-register 2 is also AX.
572 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
573 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
576 // Remove would-be duplicated kill marker.
577 if (O.isKill() && UseMI->killsRegister(DstReg))
581 // After updating the operand, check if the machine instruction has
582 // become a copy. If so, update its val# information.
583 const TargetInstrDesc &TID = UseMI->getDesc();
584 unsigned CopySrcReg, CopyDstReg;
585 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
586 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
587 CopySrcReg != CopyDstReg &&
588 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
589 allocatableRegs_[CopyDstReg])) {
590 LiveInterval &LI = li_->getInterval(CopyDstReg);
591 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
592 const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
593 if (DLR->valno->def == DefIdx)
594 DLR->valno->copy = UseMI;
599 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
600 /// registers due to insert_subreg coalescing. e.g.
602 /// r1025 = implicit_def
603 /// r1025 = insert_subreg r1025, r1024
607 /// r1025 = implicit_def
608 /// r1025 = insert_subreg r1025, r1025
611 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
612 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
613 E = mri_->reg_end(); I != E; ) {
614 MachineOperand &O = I.getOperand();
615 MachineInstr *DefMI = &*I;
619 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
621 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
623 li_->RemoveMachineInstrFromMaps(DefMI);
624 DefMI->eraseFromParent();
628 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
629 /// due to live range lengthening as the result of coalescing.
630 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
632 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
633 UE = mri_->use_end(); UI != UE; ++UI) {
634 MachineOperand &UseMO = UI.getOperand();
635 if (UseMO.isKill()) {
636 MachineInstr *UseMI = UseMO.getParent();
637 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
638 if (JoinedCopies.count(UseMI))
640 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
641 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
642 UseMO.setIsKill(false);
647 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
648 /// from a physical register live interval as well as from the live intervals
649 /// of its sub-registers.
650 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
651 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
652 li.removeRange(Start, End, true);
653 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
654 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
655 if (!li_->hasInterval(*SR))
657 LiveInterval &sli = li_->getInterval(*SR);
658 unsigned RemoveEnd = Start;
659 while (RemoveEnd != End) {
660 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
663 RemoveEnd = (LR->end < End) ? LR->end : End;
664 sli.removeRange(Start, RemoveEnd, true);
671 /// removeIntervalIfEmpty - Check if the live interval of a physical register
672 /// is empty, if so remove it and also remove the empty intervals of its
673 /// sub-registers. Return true if live interval is removed.
674 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
675 const TargetRegisterInfo *tri_) {
677 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
678 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
679 if (!li_->hasInterval(*SR))
681 LiveInterval &sli = li_->getInterval(*SR);
683 li_->removeInterval(*SR);
685 li_->removeInterval(li.reg);
691 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
692 /// Return true if live interval is removed.
693 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
694 MachineInstr *CopyMI) {
695 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
696 LiveInterval::iterator MLR =
697 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
699 return false; // Already removed by ShortenDeadCopySrcLiveRange.
700 unsigned RemoveStart = MLR->start;
701 unsigned RemoveEnd = MLR->end;
702 // Remove the liverange that's defined by this.
703 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
704 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
705 return removeIntervalIfEmpty(li, li_, tri_);
710 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
711 /// the val# it defines. If the live interval becomes empty, remove it as well.
712 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
713 MachineInstr *DefMI) {
714 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
715 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
716 if (DefIdx != MLR->valno->def)
718 li.removeValNo(MLR->valno);
719 return removeIntervalIfEmpty(li, li_, tri_);
722 /// PropagateDeadness - Propagate the dead marker to the instruction which
723 /// defines the val#.
724 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
725 unsigned &LRStart, LiveIntervals *li_,
726 const TargetRegisterInfo* tri_) {
727 MachineInstr *DefMI =
728 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
729 if (DefMI && DefMI != CopyMI) {
730 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
732 DefMI->getOperand(DeadIdx).setIsDead();
733 // A dead def should have a single cycle interval.
739 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
740 /// fallthoughs to SuccMBB.
741 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
742 MachineBasicBlock *SuccMBB,
743 const TargetInstrInfo *tii_) {
746 MachineBasicBlock *TBB = 0, *FBB = 0;
747 SmallVector<MachineOperand, 4> Cond;
748 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
749 MBB->isSuccessor(SuccMBB);
752 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
753 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
754 /// ends the live range there. If there isn't another use, then this live range
755 /// is dead. Return true if live interval is removed.
757 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
758 MachineInstr *CopyMI) {
759 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
761 // FIXME: special case: function live in. It can be a general case if the
762 // first instruction index starts at > 0 value.
763 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
764 // Live-in to the function but dead. Remove it from entry live-in set.
765 if (mf_->begin()->isLiveIn(li.reg))
766 mf_->begin()->removeLiveIn(li.reg);
767 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
768 removeRange(li, LR->start, LR->end, li_, tri_);
769 return removeIntervalIfEmpty(li, li_, tri_);
772 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
774 // Livein but defined by a phi.
777 unsigned RemoveStart = LR->start;
778 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
779 if (LR->end > RemoveEnd)
780 // More uses past this copy? Nothing to do.
783 MachineBasicBlock *CopyMBB = CopyMI->getParent();
784 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
786 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
789 MachineInstr *LastUseMI = LastUse->getParent();
790 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
797 // r1025<dead> = r1024<kill>
798 if (MBBStart < LR->end)
799 removeRange(li, MBBStart, LR->end, li_, tri_);
803 // There are uses before the copy, just shorten the live range to the end
805 LastUse->setIsKill();
806 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
807 unsigned SrcReg, DstReg;
808 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
810 // Last use is itself an identity code.
811 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
812 LastUseMI->getOperand(DeadIdx).setIsDead();
818 if (LR->start <= MBBStart && LR->end > MBBStart) {
819 if (LR->start == 0) {
820 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
821 // Live-in to the function but dead. Remove it from entry live-in set.
822 mf_->begin()->removeLiveIn(li.reg);
824 // FIXME: Shorten intervals in BBs that reaches this BB.
827 if (LR->valno->def == RemoveStart)
828 // If the def MI defines the val#, propagate the dead marker.
829 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
831 removeRange(li, RemoveStart, LR->end, li_, tri_);
832 return removeIntervalIfEmpty(li, li_, tri_);
835 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
836 /// from an implicit def to another register can be coalesced away.
837 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
839 LiveInterval &ImpLi) const{
840 if (!CopyMI->killsRegister(ImpLi.reg))
842 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
843 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
846 if (LR->valno->hasPHIKill)
848 if (LR->valno->def != CopyIdx)
850 // Make sure all of val# uses are copies.
851 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
852 UE = mri_->use_end(); UI != UE;) {
853 MachineInstr *UseMI = &*UI;
855 if (JoinedCopies.count(UseMI))
857 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
858 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
859 if (ULR == li.end() || ULR->valno != LR->valno)
861 // If the use is not a use, then it's not safe to coalesce the move.
862 unsigned SrcReg, DstReg;
863 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
864 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
865 UseMI->getOperand(1).getReg() == li.reg)
874 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
875 /// def and it is being removed. Turn all copies from this value# into
876 /// identity copies so they will be removed.
877 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
879 SmallVector<MachineInstr*, 4> ImpDefs;
880 MachineOperand *LastUse = NULL;
881 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
882 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
883 RE = mri_->reg_end(); RI != RE;) {
884 MachineOperand *MO = &RI.getOperand();
885 MachineInstr *MI = &*RI;
888 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
889 ImpDefs.push_back(MI);
893 if (JoinedCopies.count(MI))
895 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
896 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
897 if (ULR == li.end() || ULR->valno != VNI)
899 // If the use is a copy, turn it into an identity copy.
900 unsigned SrcReg, DstReg;
901 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
902 // Each use MI may have multiple uses of this register. Change them all.
903 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
904 MachineOperand &MO = MI->getOperand(i);
905 if (MO.isReg() && MO.getReg() == li.reg)
908 JoinedCopies.insert(MI);
909 } else if (UseIdx > LastUseIdx) {
915 LastUse->setIsKill();
917 // Remove dead implicit_def's.
918 while (!ImpDefs.empty()) {
919 MachineInstr *ImpDef = ImpDefs.back();
921 li_->RemoveMachineInstrFromMaps(ImpDef);
922 ImpDef->eraseFromParent();
927 /// getMatchingSuperReg - Return a super-register of the specified register
928 /// Reg so its sub-register of index SubIdx is Reg.
929 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
930 const TargetRegisterClass *RC,
931 const TargetRegisterInfo* TRI) {
932 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
933 unsigned SR = *SRs; ++SRs)
934 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
939 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
940 /// a subset of the register class of SrcReg, return true if it's profitable
941 /// to coalesce the two registers.
943 SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg,
945 MachineBasicBlock *MBB){
949 // First let's make sure all uses are in the same MBB.
950 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
951 RE = mri_->reg_end(); RI != RE; ++RI) {
952 MachineInstr &MI = *RI;
953 if (MI.getParent() != MBB)
956 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(DstReg),
957 RE = mri_->reg_end(); RI != RE; ++RI) {
958 MachineInstr &MI = *RI;
959 if (MI.getParent() != MBB)
963 // Then make sure the intervals are *short*.
964 LiveInterval &SrcInt = li_->getInterval(SrcReg);
965 LiveInterval &DstInt = li_->getInterval(DstReg);
966 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
967 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
968 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
969 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
970 return (SrcSize + DstSize) <= Threshold;
973 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
974 /// register with a physical register, check if any of the virtual register
975 /// operand is a sub-register use or def. If so, make sure it won't result
976 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
977 /// vr1024 = extract_subreg vr1025, 1
979 /// vr1024 = mov8rr AH
980 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
981 /// AH does not have a super-reg whose sub-register 1 is AH.
983 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
986 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
987 E = mri_->reg_end(); I != E; ++I) {
988 MachineOperand &O = I.getOperand();
989 MachineInstr *MI = &*I;
990 if (MI == CopyMI || JoinedCopies.count(MI))
992 unsigned SubIdx = O.getSubReg();
993 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
995 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
996 SubIdx = MI->getOperand(2).getImm();
997 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1000 unsigned SrcReg = MI->getOperand(1).getReg();
1001 const TargetRegisterClass *RC =
1002 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1003 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1004 : mri_->getRegClass(SrcReg);
1005 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1009 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1010 SubIdx = MI->getOperand(3).getImm();
1011 if (VirtReg == MI->getOperand(0).getReg()) {
1012 if (!tri_->getSubReg(PhysReg, SubIdx))
1015 unsigned DstReg = MI->getOperand(0).getReg();
1016 const TargetRegisterClass *RC =
1017 TargetRegisterInfo::isPhysicalRegister(DstReg)
1018 ? tri_->getPhysicalRegisterRegClass(DstReg)
1019 : mri_->getRegClass(DstReg);
1020 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1029 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1030 /// which are the src/dst of the copy instruction CopyMI. This returns true
1031 /// if the copy was successfully coalesced away. If it is not currently
1032 /// possible to coalesce this interval, but it may be possible if other
1033 /// things get coalesced, then it returns true by reference in 'Again'.
1034 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1035 MachineInstr *CopyMI = TheCopy.MI;
1038 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1039 return false; // Already done.
1041 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1045 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1046 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1047 unsigned SubIdx = 0;
1049 DstReg = CopyMI->getOperand(0).getReg();
1050 SrcReg = CopyMI->getOperand(1).getReg();
1051 } else if (isInsSubReg) {
1052 if (CopyMI->getOperand(2).getSubReg()) {
1053 DOUT << "\tSource of insert_subreg is already coalesced "
1054 << "to another register.\n";
1055 return false; // Not coalescable.
1057 DstReg = CopyMI->getOperand(0).getReg();
1058 SrcReg = CopyMI->getOperand(2).getReg();
1059 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
1060 assert(0 && "Unrecognized copy instruction!");
1064 // If they are already joined we continue.
1065 if (SrcReg == DstReg) {
1066 DOUT << "\tCopy already coalesced.\n";
1067 return false; // Not coalescable.
1070 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1071 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1073 // If they are both physical registers, we cannot join them.
1074 if (SrcIsPhys && DstIsPhys) {
1075 DOUT << "\tCan not coalesce physregs.\n";
1076 return false; // Not coalescable.
1079 // We only join virtual registers with allocatable physical registers.
1080 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1081 DOUT << "\tSrc reg is unallocatable physreg.\n";
1082 return false; // Not coalescable.
1084 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1085 DOUT << "\tDst reg is unallocatable physreg.\n";
1086 return false; // Not coalescable.
1089 // Should be non-null only when coalescing to a sub-register class.
1090 const TargetRegisterClass *SubRC = NULL;
1091 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1092 unsigned RealDstReg = 0;
1093 unsigned RealSrcReg = 0;
1094 if (isExtSubReg || isInsSubReg) {
1095 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1096 if (SrcIsPhys && isExtSubReg) {
1097 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1098 // coalesced with AX.
1099 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1101 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1102 // coalesced to a larger register so the subreg indices cancel out.
1103 if (DstSubIdx != SubIdx) {
1104 DOUT << "\t Sub-register indices mismatch.\n";
1105 return false; // Not coalescable.
1108 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1110 } else if (DstIsPhys && isInsSubReg) {
1111 // EAX = INSERT_SUBREG EAX, r1024, 0
1112 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1114 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1115 // coalesced to a larger register so the subreg indices cancel out.
1116 if (SrcSubIdx != SubIdx) {
1117 DOUT << "\t Sub-register indices mismatch.\n";
1118 return false; // Not coalescable.
1121 DstReg = tri_->getSubReg(DstReg, SubIdx);
1123 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
1124 // If this is a extract_subreg where dst is a physical register, e.g.
1125 // cl = EXTRACT_SUBREG reg1024, 1
1126 // then create and update the actual physical register allocated to RHS.
1128 // reg1024 = INSERT_SUBREG r1024, cl, 1
1129 if (CopyMI->getOperand(1).getSubReg()) {
1130 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
1131 << " of a super-class.\n";
1132 return false; // Not coalescable.
1134 const TargetRegisterClass *RC =
1135 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
1137 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
1138 assert(RealDstReg && "Invalid extract_subreg instruction!");
1140 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
1141 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1144 // For this type of EXTRACT_SUBREG, conservatively
1145 // check if the live interval of the source register interfere with the
1146 // actual super physical register we are trying to coalesce with.
1147 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
1148 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
1149 if (li_->hasInterval(PhysReg) &&
1150 RHS.overlaps(li_->getInterval(PhysReg))) {
1151 DOUT << "Interfere with register ";
1152 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
1153 return false; // Not coalescable
1155 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
1156 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1157 DOUT << "Interfere with sub-register ";
1158 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1159 return false; // Not coalescable
1163 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1164 : CopyMI->getOperand(2).getSubReg();
1166 if (OldSubIdx == SubIdx &&
1167 !differingRegisterClasses(SrcReg, DstReg, SubRC))
1168 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1169 // coalesced to a larger register so the subreg indices cancel out.
1170 // Also check if the other larger register is of the same register
1171 // class as the would be resulting register.
1174 DOUT << "\t Sub-register indices mismatch.\n";
1175 return false; // Not coalescable.
1179 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1180 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1181 unsigned LargeRegSize =
1182 li_->getApproximateInstructionCount(li_->getInterval(LargeReg));
1183 unsigned SmallRegSize =
1184 li_->getApproximateInstructionCount(li_->getInterval(SmallReg));
1185 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
1186 unsigned Threshold = allocatableRCRegs_[RC].count();
1187 // Be conservative. If both sides are virtual registers, do not coalesce
1188 // if this will cause a high use density interval to target a smaller
1189 // set of registers.
1190 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
1191 if ((float)std::distance(mri_->use_begin(SmallReg),
1192 mri_->use_end()) / SmallRegSize <
1193 (float)std::distance(mri_->use_begin(LargeReg),
1194 mri_->use_end()) / LargeRegSize) {
1195 Again = true; // May be possible to coalesce later.
1201 } else if (differingRegisterClasses(SrcReg, DstReg, SubRC)) {
1202 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
1203 // with another? If it's the resulting destination register, then
1204 // the subidx must be propagated to uses (but only those defined
1205 // by the EXTRACT_SUBREG). If it's being coalesced into another
1206 // register, it should be safe because register is assumed to have
1207 // the register class of the super-register.
1209 if (!SubRC || !isProfitableToCoalesceToSubRC(SrcReg, DstReg, CopyMBB)) {
1210 // If they are not of the same register class, we cannot join them.
1211 DOUT << "\tSrc/Dest are different register classes.\n";
1212 // Allow the coalescer to try again in case either side gets coalesced to
1213 // a physical register that's compatible with the other side. e.g.
1214 // r1024 = MOV32to32_ r1025
1215 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1216 Again = true; // May be possible to coalesce later.
1221 // Will it create illegal extract_subreg / insert_subreg?
1222 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1224 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1227 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1228 LiveInterval &DstInt = li_->getInterval(DstReg);
1229 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1230 "Register mapping is horribly broken!");
1232 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1233 DOUT << " and "; DstInt.print(DOUT, tri_);
1236 // Check if it is necessary to propagate "isDead" property.
1237 if (!isExtSubReg && !isInsSubReg) {
1238 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1239 bool isDead = mopd->isDead();
1241 // We need to be careful about coalescing a source physical register with a
1242 // virtual register. Once the coalescing is done, it cannot be broken and
1243 // these are not spillable! If the destination interval uses are far away,
1244 // think twice about coalescing them!
1245 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1246 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1247 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1248 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1249 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1250 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1251 if (TheCopy.isBackEdge)
1252 Threshold *= 2; // Favors back edge copies.
1254 // If the virtual register live interval is long but it has low use desity,
1255 // do not join them, instead mark the physical register as its allocation
1257 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1258 if (Length > Threshold &&
1259 (((float)std::distance(mri_->use_begin(JoinVReg),
1260 mri_->use_end()) / Length) < (1.0 / Threshold))) {
1261 JoinVInt.preference = JoinPReg;
1263 DOUT << "\tMay tie down a physical register, abort!\n";
1264 Again = true; // May be possible to coalesce later.
1270 // Okay, attempt to join these two intervals. On failure, this returns false.
1271 // Otherwise, if one of the intervals being joined is a physreg, this method
1272 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1273 // been modified, so we can use this information below to update aliases.
1274 bool Swapped = false;
1275 // If SrcInt is implicitly defined, it's safe to coalesce.
1276 bool isEmpty = SrcInt.empty();
1277 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1278 // Only coalesce an empty interval (defined by implicit_def) with
1279 // another interval which has a valno defined by the CopyMI and the CopyMI
1280 // is a kill of the implicit def.
1281 DOUT << "Not profitable!\n";
1285 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1286 // Coalescing failed.
1288 // If definition of source is defined by trivial computation, try
1289 // rematerializing it.
1290 if (!isExtSubReg && !isInsSubReg &&
1291 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1294 // If we can eliminate the copy without merging the live ranges, do so now.
1295 if (!isExtSubReg && !isInsSubReg &&
1296 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1297 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1298 JoinedCopies.insert(CopyMI);
1302 // Otherwise, we are unable to join the intervals.
1303 DOUT << "Interference!\n";
1304 Again = true; // May be possible to coalesce later.
1308 LiveInterval *ResSrcInt = &SrcInt;
1309 LiveInterval *ResDstInt = &DstInt;
1311 std::swap(SrcReg, DstReg);
1312 std::swap(ResSrcInt, ResDstInt);
1314 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1315 "LiveInterval::join didn't work right!");
1317 // If we're about to merge live ranges into a physical register live range,
1318 // we have to update any aliased register's live ranges to indicate that they
1319 // have clobbered values for this range.
1320 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1321 // If this is a extract_subreg where dst is a physical register, e.g.
1322 // cl = EXTRACT_SUBREG reg1024, 1
1323 // then create and update the actual physical register allocated to RHS.
1324 if (RealDstReg || RealSrcReg) {
1325 LiveInterval &RealInt =
1326 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1327 SmallSet<const VNInfo*, 4> CopiedValNos;
1328 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1329 E = ResSrcInt->ranges.end(); I != E; ++I) {
1330 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1331 assert(DstLR && "Invalid joined interval!");
1332 const VNInfo *DstValNo = DstLR->valno;
1333 if (CopiedValNos.insert(DstValNo)) {
1334 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1335 li_->getVNInfoAllocator());
1336 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1337 RealInt.addKills(ValNo, DstValNo->kills);
1338 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1342 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1345 // Update the liveintervals of sub-registers.
1346 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1347 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1348 li_->getVNInfoAllocator());
1351 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1352 // larger super-register.
1353 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1354 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1355 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1356 std::swap(SrcReg, DstReg);
1357 std::swap(ResSrcInt, ResDstInt);
1361 // Coalescing to a virtual register that is of a sub-register class of the
1362 // other. Make sure the resulting register is set to the right register class.
1364 mri_->setRegClass(DstReg, SubRC);
1369 // Add all copies that define val# in the source interval into the queue.
1370 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1371 e = ResSrcInt->vni_end(); i != e; ++i) {
1372 const VNInfo *vni = *i;
1373 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1375 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1376 unsigned NewSrcReg, NewDstReg;
1378 JoinedCopies.count(CopyMI) == 0 &&
1379 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1380 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1381 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1382 isBackEdgeCopy(CopyMI, DstReg)));
1387 // Remember to delete the copy instruction.
1388 JoinedCopies.insert(CopyMI);
1390 // Some live range has been lengthened due to colaescing, eliminate the
1391 // unnecessary kills.
1392 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1393 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1394 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1399 // r1024 = implicit_def
1402 RemoveDeadImpDef(DstReg, *ResDstInt);
1403 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1405 // SrcReg is guarateed to be the register whose live interval that is
1407 li_->removeInterval(SrcReg);
1410 // Now the copy is being coalesced away, the val# previously defined
1411 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1412 // length interval. Remove the val#.
1413 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1414 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1415 VNInfo *ImpVal = LR->valno;
1416 assert(ImpVal->def == CopyIdx);
1417 unsigned NextDef = LR->end;
1418 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1419 ResDstInt->removeValNo(ImpVal);
1420 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1421 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1422 // Special case: vr1024 = implicit_def
1423 // vr1024 = insert_subreg vr1024, vr1025, c
1424 // The insert_subreg becomes a "copy" that defines a val# which can itself
1425 // be coalesced away.
1426 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1427 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1428 LR->valno->copy = DefMI;
1432 // If resulting interval has a preference that no longer fits because of subreg
1433 // coalescing, just clear the preference.
1434 if (ResDstInt->preference && (isExtSubReg || isInsSubReg) &&
1435 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1436 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1437 if (!RC->contains(ResDstInt->preference))
1438 ResDstInt->preference = 0;
1441 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1448 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1449 /// compute what the resultant value numbers for each value in the input two
1450 /// ranges will be. This is complicated by copies between the two which can
1451 /// and will commonly cause multiple value numbers to be merged into one.
1453 /// VN is the value number that we're trying to resolve. InstDefiningValue
1454 /// keeps track of the new InstDefiningValue assignment for the result
1455 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1456 /// whether a value in this or other is a copy from the opposite set.
1457 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1458 /// already been assigned.
1460 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1461 /// contains the value number the copy is from.
1463 static unsigned ComputeUltimateVN(VNInfo *VNI,
1464 SmallVector<VNInfo*, 16> &NewVNInfo,
1465 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1466 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1467 SmallVector<int, 16> &ThisValNoAssignments,
1468 SmallVector<int, 16> &OtherValNoAssignments) {
1469 unsigned VN = VNI->id;
1471 // If the VN has already been computed, just return it.
1472 if (ThisValNoAssignments[VN] >= 0)
1473 return ThisValNoAssignments[VN];
1474 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1476 // If this val is not a copy from the other val, then it must be a new value
1477 // number in the destination.
1478 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1479 if (I == ThisFromOther.end()) {
1480 NewVNInfo.push_back(VNI);
1481 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1483 VNInfo *OtherValNo = I->second;
1485 // Otherwise, this *is* a copy from the RHS. If the other side has already
1486 // been computed, return it.
1487 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1488 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1490 // Mark this value number as currently being computed, then ask what the
1491 // ultimate value # of the other value is.
1492 ThisValNoAssignments[VN] = -2;
1493 unsigned UltimateVN =
1494 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1495 OtherValNoAssignments, ThisValNoAssignments);
1496 return ThisValNoAssignments[VN] = UltimateVN;
1499 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1500 return std::find(V.begin(), V.end(), Val) != V.end();
1503 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1504 /// the specified live interval is defined by a copy from the specified
1506 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1509 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1512 if (LR->valno->def == ~0U &&
1513 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1514 *tri_->getSuperRegisters(li.reg)) {
1515 // It's a sub-register live interval, we may not have precise information.
1517 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1518 unsigned SrcReg, DstReg;
1519 if (DefMI && tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1520 DstReg == li.reg && SrcReg == Reg) {
1521 // Cache computed info.
1522 LR->valno->def = LR->start;
1523 LR->valno->copy = DefMI;
1530 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1531 /// caller of this method must guarantee that the RHS only contains a single
1532 /// value number and that the RHS is not defined by a copy from this
1533 /// interval. This returns false if the intervals are not joinable, or it
1534 /// joins them and returns true.
1535 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1536 assert(RHS.containsOneValue());
1538 // Some number (potentially more than one) value numbers in the current
1539 // interval may be defined as copies from the RHS. Scan the overlapping
1540 // portions of the LHS and RHS, keeping track of this and looking for
1541 // overlapping live ranges that are NOT defined as copies. If these exist, we
1544 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1545 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1547 if (LHSIt->start < RHSIt->start) {
1548 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1549 if (LHSIt != LHS.begin()) --LHSIt;
1550 } else if (RHSIt->start < LHSIt->start) {
1551 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1552 if (RHSIt != RHS.begin()) --RHSIt;
1555 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1558 // Determine if these live intervals overlap.
1559 bool Overlaps = false;
1560 if (LHSIt->start <= RHSIt->start)
1561 Overlaps = LHSIt->end > RHSIt->start;
1563 Overlaps = RHSIt->end > LHSIt->start;
1565 // If the live intervals overlap, there are two interesting cases: if the
1566 // LHS interval is defined by a copy from the RHS, it's ok and we record
1567 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1568 // coalesce these live ranges and we bail out.
1570 // If we haven't already recorded that this value # is safe, check it.
1571 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1572 // Copy from the RHS?
1573 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1574 return false; // Nope, bail out.
1576 if (LHSIt->contains(RHSIt->valno->def))
1577 // Here is an interesting situation:
1579 // vr1025 = copy vr1024
1584 // Even though vr1025 is copied from vr1024, it's not safe to
1585 // coalesced them since live range of vr1025 intersects the
1586 // def of vr1024. This happens because vr1025 is assigned the
1587 // value of the previous iteration of vr1024.
1589 EliminatedLHSVals.push_back(LHSIt->valno);
1592 // We know this entire LHS live range is okay, so skip it now.
1593 if (++LHSIt == LHSEnd) break;
1597 if (LHSIt->end < RHSIt->end) {
1598 if (++LHSIt == LHSEnd) break;
1600 // One interesting case to check here. It's possible that we have
1601 // something like "X3 = Y" which defines a new value number in the LHS,
1602 // and is the last use of this liverange of the RHS. In this case, we
1603 // want to notice this copy (so that it gets coalesced away) even though
1604 // the live ranges don't actually overlap.
1605 if (LHSIt->start == RHSIt->end) {
1606 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1607 // We already know that this value number is going to be merged in
1608 // if coalescing succeeds. Just skip the liverange.
1609 if (++LHSIt == LHSEnd) break;
1611 // Otherwise, if this is a copy from the RHS, mark it as being merged
1613 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1614 if (LHSIt->contains(RHSIt->valno->def))
1615 // Here is an interesting situation:
1617 // vr1025 = copy vr1024
1622 // Even though vr1025 is copied from vr1024, it's not safe to
1623 // coalesced them since live range of vr1025 intersects the
1624 // def of vr1024. This happens because vr1025 is assigned the
1625 // value of the previous iteration of vr1024.
1627 EliminatedLHSVals.push_back(LHSIt->valno);
1629 // We know this entire LHS live range is okay, so skip it now.
1630 if (++LHSIt == LHSEnd) break;
1635 if (++RHSIt == RHSEnd) break;
1639 // If we got here, we know that the coalescing will be successful and that
1640 // the value numbers in EliminatedLHSVals will all be merged together. Since
1641 // the most common case is that EliminatedLHSVals has a single number, we
1642 // optimize for it: if there is more than one value, we merge them all into
1643 // the lowest numbered one, then handle the interval as if we were merging
1644 // with one value number.
1646 if (EliminatedLHSVals.size() > 1) {
1647 // Loop through all the equal value numbers merging them into the smallest
1649 VNInfo *Smallest = EliminatedLHSVals[0];
1650 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1651 if (EliminatedLHSVals[i]->id < Smallest->id) {
1652 // Merge the current notion of the smallest into the smaller one.
1653 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1654 Smallest = EliminatedLHSVals[i];
1656 // Merge into the smallest.
1657 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1660 LHSValNo = Smallest;
1661 } else if (EliminatedLHSVals.empty()) {
1662 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1663 *tri_->getSuperRegisters(LHS.reg))
1664 // Imprecise sub-register information. Can't handle it.
1666 assert(0 && "No copies from the RHS?");
1668 LHSValNo = EliminatedLHSVals[0];
1671 // Okay, now that there is a single LHS value number that we're merging the
1672 // RHS into, update the value number info for the LHS to indicate that the
1673 // value number is defined where the RHS value number was.
1674 const VNInfo *VNI = RHS.getValNumInfo(0);
1675 LHSValNo->def = VNI->def;
1676 LHSValNo->copy = VNI->copy;
1678 // Okay, the final step is to loop over the RHS live intervals, adding them to
1680 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1681 LHS.addKills(LHSValNo, VNI->kills);
1682 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1683 LHS.weight += RHS.weight;
1684 if (RHS.preference && !LHS.preference)
1685 LHS.preference = RHS.preference;
1690 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1691 /// returns false. Otherwise, if one of the intervals being joined is a
1692 /// physreg, this method always canonicalizes LHS to be it. The output
1693 /// "RHS" will not have been modified, so we can use this information
1694 /// below to update aliases.
1695 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
1696 LiveInterval &RHS, bool &Swapped) {
1697 // Compute the final value assignment, assuming that the live ranges can be
1699 SmallVector<int, 16> LHSValNoAssignments;
1700 SmallVector<int, 16> RHSValNoAssignments;
1701 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1702 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1703 SmallVector<VNInfo*, 16> NewVNInfo;
1705 // If a live interval is a physical register, conservatively check if any
1706 // of its sub-registers is overlapping the live interval of the virtual
1707 // register. If so, do not coalesce.
1708 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1709 *tri_->getSubRegisters(LHS.reg)) {
1710 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1711 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1712 DOUT << "Interfere with sub-register ";
1713 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1716 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1717 *tri_->getSubRegisters(RHS.reg)) {
1718 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1719 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1720 DOUT << "Interfere with sub-register ";
1721 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1726 // Compute ultimate value numbers for the LHS and RHS values.
1727 if (RHS.containsOneValue()) {
1728 // Copies from a liveinterval with a single value are simple to handle and
1729 // very common, handle the special case here. This is important, because
1730 // often RHS is small and LHS is large (e.g. a physreg).
1732 // Find out if the RHS is defined as a copy from some value in the LHS.
1733 int RHSVal0DefinedFromLHS = -1;
1735 VNInfo *RHSValNoInfo = NULL;
1736 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1737 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1738 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1739 // If RHS is not defined as a copy from the LHS, we can use simpler and
1740 // faster checks to see if the live ranges are coalescable. This joiner
1741 // can't swap the LHS/RHS intervals though.
1742 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1743 return SimpleJoin(LHS, RHS);
1745 RHSValNoInfo = RHSValNoInfo0;
1748 // It was defined as a copy from the LHS, find out what value # it is.
1749 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1750 RHSValID = RHSValNoInfo->id;
1751 RHSVal0DefinedFromLHS = RHSValID;
1754 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1755 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1756 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1758 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1759 // should now get updated.
1760 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1763 unsigned VN = VNI->id;
1764 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1765 if (LHSSrcReg != RHS.reg) {
1766 // If this is not a copy from the RHS, its value number will be
1767 // unmodified by the coalescing.
1768 NewVNInfo[VN] = VNI;
1769 LHSValNoAssignments[VN] = VN;
1770 } else if (RHSValID == -1) {
1771 // Otherwise, it is a copy from the RHS, and we don't already have a
1772 // value# for it. Keep the current value number, but remember it.
1773 LHSValNoAssignments[VN] = RHSValID = VN;
1774 NewVNInfo[VN] = RHSValNoInfo;
1775 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1777 // Otherwise, use the specified value #.
1778 LHSValNoAssignments[VN] = RHSValID;
1779 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1780 NewVNInfo[VN] = RHSValNoInfo;
1781 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1785 NewVNInfo[VN] = VNI;
1786 LHSValNoAssignments[VN] = VN;
1790 assert(RHSValID != -1 && "Didn't find value #?");
1791 RHSValNoAssignments[0] = RHSValID;
1792 if (RHSVal0DefinedFromLHS != -1) {
1793 // This path doesn't go through ComputeUltimateVN so just set
1795 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1798 // Loop over the value numbers of the LHS, seeing if any are defined from
1800 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1803 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1806 // DstReg is known to be a register in the LHS interval. If the src is
1807 // from the RHS interval, we can use its value #.
1808 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1811 // Figure out the value # from the RHS.
1812 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1815 // Loop over the value numbers of the RHS, seeing if any are defined from
1817 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1820 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1823 // DstReg is known to be a register in the RHS interval. If the src is
1824 // from the LHS interval, we can use its value #.
1825 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1828 // Figure out the value # from the LHS.
1829 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1832 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1833 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1834 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1836 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1839 unsigned VN = VNI->id;
1840 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1842 ComputeUltimateVN(VNI, NewVNInfo,
1843 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1844 LHSValNoAssignments, RHSValNoAssignments);
1846 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1849 unsigned VN = VNI->id;
1850 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1852 // If this value number isn't a copy from the LHS, it's a new number.
1853 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1854 NewVNInfo.push_back(VNI);
1855 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1859 ComputeUltimateVN(VNI, NewVNInfo,
1860 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1861 RHSValNoAssignments, LHSValNoAssignments);
1865 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1866 // interval lists to see if these intervals are coalescable.
1867 LiveInterval::const_iterator I = LHS.begin();
1868 LiveInterval::const_iterator IE = LHS.end();
1869 LiveInterval::const_iterator J = RHS.begin();
1870 LiveInterval::const_iterator JE = RHS.end();
1872 // Skip ahead until the first place of potential sharing.
1873 if (I->start < J->start) {
1874 I = std::upper_bound(I, IE, J->start);
1875 if (I != LHS.begin()) --I;
1876 } else if (J->start < I->start) {
1877 J = std::upper_bound(J, JE, I->start);
1878 if (J != RHS.begin()) --J;
1882 // Determine if these two live ranges overlap.
1884 if (I->start < J->start) {
1885 Overlaps = I->end > J->start;
1887 Overlaps = J->end > I->start;
1890 // If so, check value # info to determine if they are really different.
1892 // If the live range overlap will map to the same value number in the
1893 // result liverange, we can still coalesce them. If not, we can't.
1894 if (LHSValNoAssignments[I->valno->id] !=
1895 RHSValNoAssignments[J->valno->id])
1899 if (I->end < J->end) {
1908 // Update kill info. Some live ranges are extended due to copy coalescing.
1909 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1910 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1911 VNInfo *VNI = I->first;
1912 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1913 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1914 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1915 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1918 // Update kill info. Some live ranges are extended due to copy coalescing.
1919 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1920 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1921 VNInfo *VNI = I->first;
1922 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1923 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1924 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1925 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1928 // If we get here, we know that we can coalesce the live ranges. Ask the
1929 // intervals to coalesce themselves now.
1930 if ((RHS.ranges.size() > LHS.ranges.size() &&
1931 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1932 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1933 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1936 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1943 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1944 // depth of the basic block (the unsigned), and then on the MBB number.
1945 struct DepthMBBCompare {
1946 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1947 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1948 if (LHS.first > RHS.first) return true; // Deeper loops first
1949 return LHS.first == RHS.first &&
1950 LHS.second->getNumber() < RHS.second->getNumber();
1955 /// getRepIntervalSize - Returns the size of the interval that represents the
1956 /// specified register.
1958 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1959 return Rc->getRepIntervalSize(Reg);
1962 /// CopyRecSort::operator - Join priority queue sorting function.
1964 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1965 // Inner loops first.
1966 if (left.LoopDepth > right.LoopDepth)
1968 else if (left.LoopDepth == right.LoopDepth)
1969 if (left.isBackEdge && !right.isBackEdge)
1974 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1975 std::vector<CopyRec> &TryAgain) {
1976 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1978 std::vector<CopyRec> VirtCopies;
1979 std::vector<CopyRec> PhysCopies;
1980 std::vector<CopyRec> ImpDefCopies;
1981 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1982 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1984 MachineInstr *Inst = MII++;
1986 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1987 unsigned SrcReg, DstReg;
1988 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1989 DstReg = Inst->getOperand(0).getReg();
1990 SrcReg = Inst->getOperand(1).getReg();
1991 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1992 DstReg = Inst->getOperand(0).getReg();
1993 SrcReg = Inst->getOperand(2).getReg();
1994 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1997 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1998 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2000 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2002 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2003 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2004 else if (SrcIsPhys || DstIsPhys)
2005 PhysCopies.push_back(CopyRec(Inst, 0, false));
2007 VirtCopies.push_back(CopyRec(Inst, 0, false));
2014 // Try coalescing implicit copies first, followed by copies to / from
2015 // physical registers, then finally copies from virtual registers to
2016 // virtual registers.
2017 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2018 CopyRec &TheCopy = ImpDefCopies[i];
2020 if (!JoinCopy(TheCopy, Again))
2022 TryAgain.push_back(TheCopy);
2024 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2025 CopyRec &TheCopy = PhysCopies[i];
2027 if (!JoinCopy(TheCopy, Again))
2029 TryAgain.push_back(TheCopy);
2031 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2032 CopyRec &TheCopy = VirtCopies[i];
2034 if (!JoinCopy(TheCopy, Again))
2036 TryAgain.push_back(TheCopy);
2040 void SimpleRegisterCoalescing::joinIntervals() {
2041 DOUT << "********** JOINING INTERVALS ***********\n";
2044 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2046 std::vector<CopyRec> TryAgainList;
2047 if (loopInfo->empty()) {
2048 // If there are no loops in the function, join intervals in function order.
2049 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2051 CopyCoalesceInMBB(I, TryAgainList);
2053 // Otherwise, join intervals in inner loops before other intervals.
2054 // Unfortunately we can't just iterate over loop hierarchy here because
2055 // there may be more MBB's than BB's. Collect MBB's for sorting.
2057 // Join intervals in the function prolog first. We want to join physical
2058 // registers with virtual registers before the intervals got too long.
2059 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2060 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2061 MachineBasicBlock *MBB = I;
2062 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2065 // Sort by loop depth.
2066 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2068 // Finally, join intervals in loop nest order.
2069 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2070 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2073 // Joining intervals can allow other intervals to be joined. Iteratively join
2074 // until we make no progress.
2076 SmallVector<CopyRec, 16> TryAgain;
2077 bool ProgressMade = true;
2078 while (ProgressMade) {
2079 ProgressMade = false;
2080 while (!JoinQueue->empty()) {
2081 CopyRec R = JoinQueue->pop();
2083 bool Success = JoinCopy(R, Again);
2085 ProgressMade = true;
2087 TryAgain.push_back(R);
2091 while (!TryAgain.empty()) {
2092 JoinQueue->push(TryAgain.back());
2093 TryAgain.pop_back();
2098 bool ProgressMade = true;
2099 while (ProgressMade) {
2100 ProgressMade = false;
2102 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2103 CopyRec &TheCopy = TryAgainList[i];
2106 bool Success = JoinCopy(TheCopy, Again);
2107 if (Success || !Again) {
2108 TheCopy.MI = 0; // Mark this one as done.
2109 ProgressMade = true;
2120 /// Return true if the two specified registers belong to different register
2121 /// classes. The registers may be either phys or virt regs. In the
2122 /// case where both registers are virtual registers, it would also returns
2123 /// true by reference the RegB register class in SubRC if it is a subset of
2124 /// RegA's register class.
2126 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB,
2127 const TargetRegisterClass *&SubRC) const {
2129 // Get the register classes for the first reg.
2130 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2131 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2132 "Shouldn't consider two physregs!");
2133 return !mri_->getRegClass(RegB)->contains(RegA);
2136 // Compare against the regclass for the second reg.
2137 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2138 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2139 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2140 if (RegClassA == RegClassB)
2142 SubRC = (RegClassA->hasSubClass(RegClassB)) ? RegClassB : NULL;
2145 return !RegClassA->contains(RegB);
2148 /// lastRegisterUse - Returns the last use of the specific register between
2149 /// cycles Start and End or NULL if there are no uses.
2151 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2152 unsigned Reg, unsigned &UseIdx) const{
2154 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2155 MachineOperand *LastUse = NULL;
2156 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2157 E = mri_->use_end(); I != E; ++I) {
2158 MachineOperand &Use = I.getOperand();
2159 MachineInstr *UseMI = Use.getParent();
2160 unsigned SrcReg, DstReg;
2161 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
2162 // Ignore identity copies.
2164 unsigned Idx = li_->getInstructionIndex(UseMI);
2165 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2173 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2176 // Skip deleted instructions
2177 MachineInstr *MI = li_->getInstructionFromIndex(e);
2178 while ((e - InstrSlots::NUM) >= s && !MI) {
2179 e -= InstrSlots::NUM;
2180 MI = li_->getInstructionFromIndex(e);
2182 if (e < s || MI == NULL)
2185 // Ignore identity copies.
2186 unsigned SrcReg, DstReg;
2187 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
2188 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2189 MachineOperand &Use = MI->getOperand(i);
2190 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2191 tri_->regsOverlap(Use.getReg(), Reg)) {
2197 e -= InstrSlots::NUM;
2204 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2205 if (TargetRegisterInfo::isPhysicalRegister(reg))
2206 cerr << tri_->getName(reg);
2208 cerr << "%reg" << reg;
2211 void SimpleRegisterCoalescing::releaseMemory() {
2212 JoinedCopies.clear();
2213 ReMatCopies.clear();
2217 static bool isZeroLengthInterval(LiveInterval *li) {
2218 for (LiveInterval::Ranges::const_iterator
2219 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2220 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
2225 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2226 /// turn the copy into an implicit def.
2228 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2229 MachineBasicBlock *MBB,
2230 unsigned DstReg, unsigned SrcReg) {
2231 MachineInstr *CopyMI = &*I;
2232 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2233 if (!li_->hasInterval(SrcReg))
2235 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2236 if (!SrcInt.empty())
2238 if (!li_->hasInterval(DstReg))
2240 LiveInterval &DstInt = li_->getInterval(DstReg);
2241 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2242 DstInt.removeValNo(DstLR->valno);
2243 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2244 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2245 CopyMI->RemoveOperand(i);
2246 bool NoUse = mri_->use_empty(SrcReg);
2248 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2249 E = mri_->reg_end(); I != E; ) {
2250 assert(I.getOperand().isDef());
2251 MachineInstr *DefMI = &*I;
2253 // The implicit_def source has no other uses, delete it.
2254 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2255 li_->RemoveMachineInstrFromMaps(DefMI);
2256 DefMI->eraseFromParent();
2264 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2266 mri_ = &fn.getRegInfo();
2267 tm_ = &fn.getTarget();
2268 tri_ = tm_->getRegisterInfo();
2269 tii_ = tm_->getInstrInfo();
2270 li_ = &getAnalysis<LiveIntervals>();
2271 loopInfo = &getAnalysis<MachineLoopInfo>();
2273 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2274 << "********** Function: "
2275 << ((Value*)mf_->getFunction())->getName() << '\n';
2277 allocatableRegs_ = tri_->getAllocatableSet(fn);
2278 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2279 E = tri_->regclass_end(); I != E; ++I)
2280 allocatableRCRegs_.insert(std::make_pair(*I,
2281 tri_->getAllocatableSet(fn, *I)));
2283 // Join (coalesce) intervals if requested.
2284 if (EnableJoining) {
2286 DOUT << "********** INTERVALS POST JOINING **********\n";
2287 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2288 I->second->print(DOUT, tri_);
2293 // Perform a final pass over the instructions and compute spill weights
2294 // and remove identity moves.
2295 SmallVector<unsigned, 4> DeadDefs;
2296 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2297 mbbi != mbbe; ++mbbi) {
2298 MachineBasicBlock* mbb = mbbi;
2299 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2301 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2303 MachineInstr *MI = mii;
2304 unsigned SrcReg, DstReg;
2305 if (JoinedCopies.count(MI)) {
2306 // Delete all coalesced copies.
2307 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) {
2308 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2309 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2310 "Unrecognized copy instruction");
2311 DstReg = MI->getOperand(0).getReg();
2313 if (MI->registerDefIsDead(DstReg)) {
2314 LiveInterval &li = li_->getInterval(DstReg);
2315 if (!ShortenDeadCopySrcLiveRange(li, MI))
2316 ShortenDeadCopyLiveRange(li, MI);
2318 li_->RemoveMachineInstrFromMaps(MI);
2319 mii = mbbi->erase(mii);
2324 // Now check if this is a remat'ed def instruction which is now dead.
2325 if (ReMatDefs.count(MI)) {
2327 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2328 const MachineOperand &MO = MI->getOperand(i);
2331 unsigned Reg = MO.getReg();
2332 if (TargetRegisterInfo::isVirtualRegister(Reg))
2333 DeadDefs.push_back(Reg);
2336 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2337 !mri_->use_empty(Reg)) {
2343 while (!DeadDefs.empty()) {
2344 unsigned DeadDef = DeadDefs.back();
2345 DeadDefs.pop_back();
2346 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2348 li_->RemoveMachineInstrFromMaps(mii);
2349 mii = mbbi->erase(mii);
2355 // If the move will be an identity move delete it
2356 bool isMove = tii_->isMoveInstr(*MI, SrcReg, DstReg);
2357 if (isMove && SrcReg == DstReg) {
2358 if (li_->hasInterval(SrcReg)) {
2359 LiveInterval &RegInt = li_->getInterval(SrcReg);
2360 // If def of this move instruction is dead, remove its live range
2361 // from the dstination register's live interval.
2362 if (MI->registerDefIsDead(DstReg)) {
2363 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2364 ShortenDeadCopyLiveRange(RegInt, MI);
2367 li_->RemoveMachineInstrFromMaps(MI);
2368 mii = mbbi->erase(mii);
2370 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2371 SmallSet<unsigned, 4> UniqueUses;
2372 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2373 const MachineOperand &mop = MI->getOperand(i);
2374 if (mop.isReg() && mop.getReg() &&
2375 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2376 unsigned reg = mop.getReg();
2377 // Multiple uses of reg by the same instruction. It should not
2378 // contribute to spill weight again.
2379 if (UniqueUses.count(reg) != 0)
2381 LiveInterval &RegInt = li_->getInterval(reg);
2383 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2384 UniqueUses.insert(reg);
2392 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2393 LiveInterval &LI = *I->second;
2394 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2395 // If the live interval length is essentially zero, i.e. in every live
2396 // range the use follows def immediately, it doesn't make sense to spill
2397 // it and hope it will be easier to allocate for this li.
2398 if (isZeroLengthInterval(&LI))
2399 LI.weight = HUGE_VALF;
2401 bool isLoad = false;
2402 SmallVector<LiveInterval*, 4> SpillIs;
2403 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2404 // If all of the definitions of the interval are re-materializable,
2405 // it is a preferred candidate for spilling. If non of the defs are
2406 // loads, then it's potentially very cheap to re-materialize.
2407 // FIXME: this gets much more complicated once we support non-trivial
2408 // re-materialization.
2416 // Slightly prefer live interval that has been assigned a preferred reg.
2420 // Divide the weight of the interval by its size. This encourages
2421 // spilling of intervals that are large and have few uses, and
2422 // discourages spilling of small intervals with many uses.
2423 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2431 /// print - Implement the dump method.
2432 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2436 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2437 return new SimpleRegisterCoalescing();
2440 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2441 DEFINING_FILE_FOR(SimpleRegisterCoalescing)