1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
37 STATISTIC(numJoins , "Number of interval joins performed");
38 STATISTIC(numSubJoins , "Number of subclass joins performed");
39 STATISTIC(numCommutes , "Number of instruction commuting performed");
40 STATISTIC(numExtends , "Number of copies extended");
41 STATISTIC(NumReMats , "Number of instructions re-materialized");
42 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
43 STATISTIC(numAborts , "Number of times interval joining aborted");
45 char SimpleRegisterCoalescing::ID = 0;
47 EnableJoining("join-liveintervals",
48 cl::desc("Coalesce copies (default=true)"),
52 NewHeuristic("new-coalescer-heuristic",
53 cl::desc("Use new coalescer heuristic"),
54 cl::init(false), cl::Hidden);
57 CrossClassJoin("join-subclass-copies",
58 cl::desc("Coalesce copies to sub- register class"),
59 cl::init(false), cl::Hidden);
61 static RegisterPass<SimpleRegisterCoalescing>
62 X("simple-register-coalescing", "Simple Register Coalescing");
64 // Declare that we implement the RegisterCoalescer interface
65 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
67 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
69 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addPreserved<LiveIntervals>();
71 AU.addPreserved<MachineLoopInfo>();
72 AU.addPreservedID(MachineDominatorsID);
73 AU.addPreservedID(PHIEliminationID);
74 AU.addPreservedID(TwoAddressInstructionPassID);
75 AU.addRequired<LiveIntervals>();
76 AU.addRequired<MachineLoopInfo>();
77 MachineFunctionPass::getAnalysisUsage(AU);
80 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
81 /// being the source and IntB being the dest, thus this defines a value number
82 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
83 /// see if we can merge these two pieces of B into a single value number,
84 /// eliminating a copy. For example:
88 /// B1 = A3 <- this copy
90 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
91 /// value number to be replaced with B0 (which simplifies the B liveinterval).
93 /// This returns true if an interval was modified.
95 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
97 MachineInstr *CopyMI) {
98 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
100 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
101 // the example above.
102 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
103 if (BLR == IntB.end()) // Should never happen!
105 VNInfo *BValNo = BLR->valno;
107 // Get the location that B is defined at. Two options: either this value has
108 // an unknown definition point or it is defined at CopyIdx. If unknown, we
110 if (!BValNo->copy) return false;
111 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
113 // AValNo is the value number in A that defines the copy, A3 in the example.
114 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
115 if (ALR == IntA.end()) // Should never happen!
117 VNInfo *AValNo = ALR->valno;
119 // If AValNo is defined as a copy from IntB, we can potentially process this.
120 // Get the instruction that defines this value number.
121 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
122 if (!SrcReg) return false; // Not defined by a copy.
124 // If the value number is not defined by a copy instruction, ignore it.
126 // If the source register comes from an interval other than IntB, we can't
128 if (SrcReg != IntB.reg) return false;
130 // Get the LiveRange in IntB that this value number starts with.
131 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
132 if (ValLR == IntB.end()) // Should never happen!
135 // Make sure that the end of the live range is inside the same block as
137 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
139 ValLREndInst->getParent() != CopyMI->getParent()) return false;
141 // Okay, we now know that ValLR ends in the same block that the CopyMI
142 // live-range starts. If there are no intervening live ranges between them in
143 // IntB, we can merge them.
144 if (ValLR+1 != BLR) return false;
146 // If a live interval is a physical register, conservatively check if any
147 // of its sub-registers is overlapping the live interval of the virtual
148 // register. If so, do not coalesce.
149 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
150 *tri_->getSubRegisters(IntB.reg)) {
151 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
152 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
153 DOUT << "Interfere with sub-register ";
154 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
159 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
161 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
162 // We are about to delete CopyMI, so need to remove it as the 'instruction
163 // that defines this value #'. Update the the valnum with the new defining
165 BValNo->def = FillerStart;
168 // Okay, we can merge them. We need to insert a new liverange:
169 // [ValLR.end, BLR.begin) of either value number, then we merge the
170 // two value numbers.
171 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
173 // If the IntB live range is assigned to a physical register, and if that
174 // physreg has aliases,
175 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
176 // Update the liveintervals of sub-registers.
177 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
178 LiveInterval &AliasLI = li_->getInterval(*AS);
179 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
180 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
184 // Okay, merge "B1" into the same value number as "B0".
185 if (BValNo != ValLR->valno)
186 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
187 DOUT << " result = "; IntB.print(DOUT, tri_);
190 // If the source instruction was killing the source register before the
191 // merge, unset the isKill marker given the live range has been extended.
192 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
194 ValLREndInst->getOperand(UIdx).setIsKill(false);
200 /// HasOtherReachingDefs - Return true if there are definitions of IntB
201 /// other than BValNo val# that can reach uses of AValno val# of IntA.
202 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
206 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
208 if (AI->valno != AValNo) continue;
209 LiveInterval::Ranges::iterator BI =
210 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
211 if (BI != IntB.ranges.begin())
213 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
214 if (BI->valno == BValNo)
216 if (BI->start <= AI->start && BI->end > AI->start)
218 if (BI->start > AI->start && BI->start < AI->end)
225 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
226 /// being the source and IntB being the dest, thus this defines a value number
227 /// in IntB. If the source value number (in IntA) is defined by a commutable
228 /// instruction and its other operand is coalesced to the copy dest register,
229 /// see if we can transform the copy into a noop by commuting the definition. For
232 /// A3 = op A2 B0<kill>
234 /// B1 = A3 <- this copy
236 /// = op A3 <- more uses
240 /// B2 = op B0 A2<kill>
242 /// B1 = B2 <- now an identify copy
244 /// = op B2 <- more uses
246 /// This returns true if an interval was modified.
248 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
250 MachineInstr *CopyMI) {
251 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
253 // FIXME: For now, only eliminate the copy by commuting its def when the
254 // source register is a virtual register. We want to guard against cases
255 // where the copy is a back edge copy and commuting the def lengthen the
256 // live interval of the source register to the entire loop.
257 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
260 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
261 // the example above.
262 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
263 if (BLR == IntB.end()) // Should never happen!
265 VNInfo *BValNo = BLR->valno;
267 // Get the location that B is defined at. Two options: either this value has
268 // an unknown definition point or it is defined at CopyIdx. If unknown, we
270 if (!BValNo->copy) return false;
271 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
273 // AValNo is the value number in A that defines the copy, A3 in the example.
274 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
275 if (ALR == IntA.end()) // Should never happen!
277 VNInfo *AValNo = ALR->valno;
278 // If other defs can reach uses of this def, then it's not safe to perform
280 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
282 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
283 const TargetInstrDesc &TID = DefMI->getDesc();
285 if (!TID.isCommutable() ||
286 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
289 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
290 unsigned NewReg = NewDstMO.getReg();
291 if (NewReg != IntB.reg || !NewDstMO.isKill())
294 // Make sure there are no other definitions of IntB that would reach the
295 // uses which the new definition can reach.
296 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
299 // If some of the uses of IntA.reg is already coalesced away, return false.
300 // It's not possible to determine whether it's safe to perform the coalescing.
301 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
302 UE = mri_->use_end(); UI != UE; ++UI) {
303 MachineInstr *UseMI = &*UI;
304 unsigned UseIdx = li_->getInstructionIndex(UseMI);
305 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
306 if (ULR == IntA.end())
308 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
312 // At this point we have decided that it is legal to do this
313 // transformation. Start by commuting the instruction.
314 MachineBasicBlock *MBB = DefMI->getParent();
315 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
318 if (NewMI != DefMI) {
319 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
320 MBB->insert(DefMI, NewMI);
323 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
324 NewMI->getOperand(OpIdx).setIsKill();
326 bool BHasPHIKill = BValNo->hasPHIKill;
327 SmallVector<VNInfo*, 4> BDeadValNos;
328 SmallVector<unsigned, 4> BKills;
329 std::map<unsigned, unsigned> BExtend;
331 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
340 // then do not add kills of A to the newly created B interval.
341 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
343 BExtend[ALR->end] = BLR->end;
345 // Update uses of IntA of the specific Val# with IntB.
346 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
347 UE = mri_->use_end(); UI != UE;) {
348 MachineOperand &UseMO = UI.getOperand();
349 MachineInstr *UseMI = &*UI;
351 if (JoinedCopies.count(UseMI))
353 unsigned UseIdx = li_->getInstructionIndex(UseMI);
354 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
355 if (ULR == IntA.end() || ULR->valno != AValNo)
357 UseMO.setReg(NewReg);
360 if (UseMO.isKill()) {
362 UseMO.setIsKill(false);
364 BKills.push_back(li_->getUseIndex(UseIdx)+1);
366 unsigned SrcReg, DstReg;
367 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
369 if (DstReg == IntB.reg) {
370 // This copy will become a noop. If it's defining a new val#,
371 // remove that val# as well. However this live range is being
372 // extended to the end of the existing live range defined by the copy.
373 unsigned DefIdx = li_->getDefIndex(UseIdx);
374 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
375 BHasPHIKill |= DLR->valno->hasPHIKill;
376 assert(DLR->valno->def == DefIdx);
377 BDeadValNos.push_back(DLR->valno);
378 BExtend[DLR->start] = DLR->end;
379 JoinedCopies.insert(UseMI);
380 // If this is a kill but it's going to be removed, the last use
381 // of the same val# is the new kill.
387 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
388 // simply extend BLR if CopyMI doesn't end the range.
389 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
391 // Remove val#'s defined by copies that will be coalesced away.
392 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
393 IntB.removeValNo(BDeadValNos[i]);
395 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
396 // is updated. Kills are also updated.
397 VNInfo *ValNo = BValNo;
398 ValNo->def = AValNo->def;
400 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
401 unsigned Kill = ValNo->kills[j];
402 if (Kill != BLR->end)
403 BKills.push_back(Kill);
405 ValNo->kills.clear();
406 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
408 if (AI->valno != AValNo) continue;
409 unsigned End = AI->end;
410 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
411 if (EI != BExtend.end())
413 IntB.addRange(LiveRange(AI->start, End, ValNo));
415 IntB.addKills(ValNo, BKills);
416 ValNo->hasPHIKill = BHasPHIKill;
418 DOUT << " result = "; IntB.print(DOUT, tri_);
421 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
422 IntA.removeValNo(AValNo);
423 DOUT << " result = "; IntA.print(DOUT, tri_);
430 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
431 /// computation, replace the copy by rematerialize the definition.
432 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
434 MachineInstr *CopyMI) {
435 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
436 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
437 if (SrcLR == SrcInt.end()) // Should never happen!
439 VNInfo *ValNo = SrcLR->valno;
440 // If other defs can reach uses of this def, then it's not safe to perform
442 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
444 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
445 const TargetInstrDesc &TID = DefMI->getDesc();
446 if (!TID.isAsCheapAsAMove())
448 bool SawStore = false;
449 if (!DefMI->isSafeToMove(tii_, SawStore))
452 unsigned DefIdx = li_->getDefIndex(CopyIdx);
453 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
454 DLR->valno->copy = NULL;
456 MachineBasicBlock::iterator MII = CopyMI;
457 MachineBasicBlock *MBB = CopyMI->getParent();
458 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
459 MachineInstr *NewMI = prior(MII);
460 // CopyMI may have implicit instructions, transfer them over to the newly
461 // rematerialized instruction. And update implicit def interval valnos.
462 for (unsigned i = CopyMI->getDesc().getNumOperands(),
463 e = CopyMI->getNumOperands(); i != e; ++i) {
464 MachineOperand &MO = CopyMI->getOperand(i);
465 if (MO.isReg() && MO.isImplicit())
466 NewMI->addOperand(MO);
468 unsigned Reg = MO.getReg();
469 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
470 if (DLR && DLR->valno->copy == CopyMI)
471 DLR->valno->copy = NULL;
475 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
476 CopyMI->eraseFromParent();
477 ReMatCopies.insert(CopyMI);
482 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
484 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
485 unsigned DstReg) const {
486 MachineBasicBlock *MBB = CopyMI->getParent();
487 const MachineLoop *L = loopInfo->getLoopFor(MBB);
490 if (MBB != L->getLoopLatch())
493 LiveInterval &LI = li_->getInterval(DstReg);
494 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
495 LiveInterval::const_iterator DstLR =
496 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
497 if (DstLR == LI.end())
499 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
500 if (DstLR->valno->kills.size() == 1 &&
501 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
506 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
507 /// update the subregister number if it is not zero. If DstReg is a
508 /// physical register and the existing subregister number of the def / use
509 /// being updated is not zero, make sure to set it to the correct physical
512 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
514 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
515 if (DstIsPhys && SubIdx) {
516 // Figure out the real physical register we are updating with.
517 DstReg = tri_->getSubReg(DstReg, SubIdx);
521 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
522 E = mri_->reg_end(); I != E; ) {
523 MachineOperand &O = I.getOperand();
524 MachineInstr *UseMI = &*I;
526 unsigned OldSubIdx = O.getSubReg();
528 unsigned UseDstReg = DstReg;
530 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
532 unsigned CopySrcReg, CopyDstReg;
533 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
534 CopySrcReg != CopyDstReg &&
535 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
536 // If the use is a copy and it won't be coalesced away, and its source
537 // is defined by a trivial computation, try to rematerialize it instead.
538 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
545 // Sub-register indexes goes from small to large. e.g.
546 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
547 // EAX: 1 -> AL, 2 -> AX
548 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
549 // sub-register 2 is also AX.
550 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
551 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
554 // Remove would-be duplicated kill marker.
555 if (O.isKill() && UseMI->killsRegister(DstReg))
562 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
563 /// registers due to insert_subreg coalescing. e.g.
565 /// r1025 = implicit_def
566 /// r1025 = insert_subreg r1025, r1024
570 /// r1025 = implicit_def
571 /// r1025 = insert_subreg r1025, r1025
574 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
575 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
576 E = mri_->reg_end(); I != E; ) {
577 MachineOperand &O = I.getOperand();
578 MachineInstr *DefMI = &*I;
582 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
584 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
586 li_->RemoveMachineInstrFromMaps(DefMI);
587 DefMI->eraseFromParent();
591 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
592 /// due to live range lengthening as the result of coalescing.
593 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
595 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
596 UE = mri_->use_end(); UI != UE; ++UI) {
597 MachineOperand &UseMO = UI.getOperand();
598 if (UseMO.isKill()) {
599 MachineInstr *UseMI = UseMO.getParent();
600 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
601 if (JoinedCopies.count(UseMI))
603 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
604 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
605 UseMO.setIsKill(false);
610 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
611 /// from a physical register live interval as well as from the live intervals
612 /// of its sub-registers.
613 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
614 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
615 li.removeRange(Start, End, true);
616 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
617 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
618 if (!li_->hasInterval(*SR))
620 LiveInterval &sli = li_->getInterval(*SR);
621 unsigned RemoveEnd = Start;
622 while (RemoveEnd != End) {
623 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
626 RemoveEnd = (LR->end < End) ? LR->end : End;
627 sli.removeRange(Start, RemoveEnd, true);
634 /// removeIntervalIfEmpty - Check if the live interval of a physical register
635 /// is empty, if so remove it and also remove the empty intervals of its
636 /// sub-registers. Return true if live interval is removed.
637 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
638 const TargetRegisterInfo *tri_) {
640 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
641 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
642 if (!li_->hasInterval(*SR))
644 LiveInterval &sli = li_->getInterval(*SR);
646 li_->removeInterval(*SR);
648 li_->removeInterval(li.reg);
654 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
655 /// Return true if live interval is removed.
656 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
657 MachineInstr *CopyMI) {
658 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
659 LiveInterval::iterator MLR =
660 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
662 return false; // Already removed by ShortenDeadCopySrcLiveRange.
663 unsigned RemoveStart = MLR->start;
664 unsigned RemoveEnd = MLR->end;
665 // Remove the liverange that's defined by this.
666 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
667 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
668 return removeIntervalIfEmpty(li, li_, tri_);
673 /// PropagateDeadness - Propagate the dead marker to the instruction which
674 /// defines the val#.
675 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
676 unsigned &LRStart, LiveIntervals *li_,
677 const TargetRegisterInfo* tri_) {
678 MachineInstr *DefMI =
679 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
680 if (DefMI && DefMI != CopyMI) {
681 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
683 DefMI->getOperand(DeadIdx).setIsDead();
684 // A dead def should have a single cycle interval.
690 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
691 /// fallthoughs to SuccMBB.
692 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
693 MachineBasicBlock *SuccMBB,
694 const TargetInstrInfo *tii_) {
697 MachineBasicBlock *TBB = 0, *FBB = 0;
698 SmallVector<MachineOperand, 4> Cond;
699 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
700 MBB->isSuccessor(SuccMBB);
703 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
704 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
705 /// ends the live range there. If there isn't another use, then this live range
706 /// is dead. Return true if live interval is removed.
708 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
709 MachineInstr *CopyMI) {
710 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
712 // FIXME: special case: function live in. It can be a general case if the
713 // first instruction index starts at > 0 value.
714 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
715 // Live-in to the function but dead. Remove it from entry live-in set.
716 if (mf_->begin()->isLiveIn(li.reg))
717 mf_->begin()->removeLiveIn(li.reg);
718 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
719 removeRange(li, LR->start, LR->end, li_, tri_);
720 return removeIntervalIfEmpty(li, li_, tri_);
723 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
725 // Livein but defined by a phi.
728 unsigned RemoveStart = LR->start;
729 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
730 if (LR->end > RemoveEnd)
731 // More uses past this copy? Nothing to do.
734 MachineBasicBlock *CopyMBB = CopyMI->getParent();
735 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
737 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
740 MachineInstr *LastUseMI = LastUse->getParent();
741 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
748 // r1025<dead> = r1024<kill>
749 if (MBBStart < LR->end)
750 removeRange(li, MBBStart, LR->end, li_, tri_);
754 // There are uses before the copy, just shorten the live range to the end
756 LastUse->setIsKill();
757 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
758 unsigned SrcReg, DstReg;
759 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
761 // Last use is itself an identity code.
762 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
763 LastUseMI->getOperand(DeadIdx).setIsDead();
769 if (LR->start <= MBBStart && LR->end > MBBStart) {
770 if (LR->start == 0) {
771 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
772 // Live-in to the function but dead. Remove it from entry live-in set.
773 mf_->begin()->removeLiveIn(li.reg);
775 // FIXME: Shorten intervals in BBs that reaches this BB.
778 if (LR->valno->def == RemoveStart)
779 // If the def MI defines the val#, propagate the dead marker.
780 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
782 removeRange(li, RemoveStart, LR->end, li_, tri_);
783 return removeIntervalIfEmpty(li, li_, tri_);
786 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
787 /// from an implicit def to another register can be coalesced away.
788 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
790 LiveInterval &ImpLi) const{
791 if (!CopyMI->killsRegister(ImpLi.reg))
793 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
794 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
797 if (LR->valno->hasPHIKill)
799 if (LR->valno->def != CopyIdx)
801 // Make sure all of val# uses are copies.
802 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
803 UE = mri_->use_end(); UI != UE;) {
804 MachineInstr *UseMI = &*UI;
806 if (JoinedCopies.count(UseMI))
808 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
809 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
810 if (ULR == li.end() || ULR->valno != LR->valno)
812 // If the use is not a use, then it's not safe to coalesce the move.
813 unsigned SrcReg, DstReg;
814 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
815 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
816 UseMI->getOperand(1).getReg() == li.reg)
825 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
826 /// def and it is being removed. Turn all copies from this value# into
827 /// identity copies so they will be removed.
828 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
830 SmallVector<MachineInstr*, 4> ImpDefs;
831 MachineOperand *LastUse = NULL;
832 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
833 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
834 RE = mri_->reg_end(); RI != RE;) {
835 MachineOperand *MO = &RI.getOperand();
836 MachineInstr *MI = &*RI;
839 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
840 ImpDefs.push_back(MI);
844 if (JoinedCopies.count(MI))
846 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
847 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
848 if (ULR == li.end() || ULR->valno != VNI)
850 // If the use is a copy, turn it into an identity copy.
851 unsigned SrcReg, DstReg;
852 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
853 // Each use MI may have multiple uses of this register. Change them all.
854 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
855 MachineOperand &MO = MI->getOperand(i);
856 if (MO.isReg() && MO.getReg() == li.reg)
859 JoinedCopies.insert(MI);
860 } else if (UseIdx > LastUseIdx) {
866 LastUse->setIsKill();
868 // Remove dead implicit_def's.
869 while (!ImpDefs.empty()) {
870 MachineInstr *ImpDef = ImpDefs.back();
872 li_->RemoveMachineInstrFromMaps(ImpDef);
873 ImpDef->eraseFromParent();
878 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
879 const TargetRegisterClass *RC,
880 const TargetRegisterInfo* TRI) {
881 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
882 unsigned SR = *SRs; ++SRs)
883 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
888 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
889 /// a subset of the register class of SrcReg, return true if it's profitable
890 /// to coalesce the two registers.
892 SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg,
894 MachineBasicBlock *MBB){
898 // First let's make sure all uses are in the same MBB.
899 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
900 RE = mri_->reg_end(); RI != RE; ++RI) {
901 MachineInstr &MI = *RI;
902 if (MI.getParent() != MBB)
905 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(DstReg),
906 RE = mri_->reg_end(); RI != RE; ++RI) {
907 MachineInstr &MI = *RI;
908 if (MI.getParent() != MBB)
912 // Then make sure the intervals are *short*.
913 LiveInterval &SrcInt = li_->getInterval(SrcReg);
914 LiveInterval &DstInt = li_->getInterval(DstReg);
915 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
916 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
917 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
918 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
919 return (SrcSize + DstSize) <= Threshold;
923 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
924 /// which are the src/dst of the copy instruction CopyMI. This returns true
925 /// if the copy was successfully coalesced away. If it is not currently
926 /// possible to coalesce this interval, but it may be possible if other
927 /// things get coalesced, then it returns true by reference in 'Again'.
928 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
929 MachineInstr *CopyMI = TheCopy.MI;
932 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
933 return false; // Already done.
935 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
939 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
940 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
943 DstReg = CopyMI->getOperand(0).getReg();
944 SrcReg = CopyMI->getOperand(1).getReg();
945 } else if (isInsSubReg) {
946 if (CopyMI->getOperand(2).getSubReg()) {
947 DOUT << "\tSource of insert_subreg is already coalesced "
948 << "to another register.\n";
949 return false; // Not coalescable.
951 DstReg = CopyMI->getOperand(0).getReg();
952 SrcReg = CopyMI->getOperand(2).getReg();
953 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
954 assert(0 && "Unrecognized copy instruction!");
958 // If they are already joined we continue.
959 if (SrcReg == DstReg) {
960 DOUT << "\tCopy already coalesced.\n";
961 return false; // Not coalescable.
964 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
965 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
967 // If they are both physical registers, we cannot join them.
968 if (SrcIsPhys && DstIsPhys) {
969 DOUT << "\tCan not coalesce physregs.\n";
970 return false; // Not coalescable.
973 // We only join virtual registers with allocatable physical registers.
974 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
975 DOUT << "\tSrc reg is unallocatable physreg.\n";
976 return false; // Not coalescable.
978 if (DstIsPhys && !allocatableRegs_[DstReg]) {
979 DOUT << "\tDst reg is unallocatable physreg.\n";
980 return false; // Not coalescable.
983 // Should be non-null only when coalescing to a sub-register class.
984 const TargetRegisterClass *SubRC = NULL;
985 MachineBasicBlock *CopyMBB = CopyMI->getParent();
986 unsigned RealDstReg = 0;
987 unsigned RealSrcReg = 0;
988 if (isExtSubReg || isInsSubReg) {
989 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
990 if (SrcIsPhys && isExtSubReg) {
991 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
992 // coalesced with AX.
993 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
995 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
996 // coalesced to a larger register so the subreg indices cancel out.
997 if (DstSubIdx != SubIdx) {
998 DOUT << "\t Sub-register indices mismatch.\n";
999 return false; // Not coalescable.
1002 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1004 } else if (DstIsPhys && isInsSubReg) {
1005 // EAX = INSERT_SUBREG EAX, r1024, 0
1006 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1008 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1009 // coalesced to a larger register so the subreg indices cancel out.
1010 if (SrcSubIdx != SubIdx) {
1011 DOUT << "\t Sub-register indices mismatch.\n";
1012 return false; // Not coalescable.
1015 DstReg = tri_->getSubReg(DstReg, SubIdx);
1017 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
1018 // If this is a extract_subreg where dst is a physical register, e.g.
1019 // cl = EXTRACT_SUBREG reg1024, 1
1020 // then create and update the actual physical register allocated to RHS.
1022 // reg1024 = INSERT_SUBREG r1024, cl, 1
1023 if (CopyMI->getOperand(1).getSubReg()) {
1024 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
1025 << " of a super-class.\n";
1026 return false; // Not coalescable.
1028 const TargetRegisterClass *RC =
1029 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
1031 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
1032 assert(RealDstReg && "Invalid extract_subreg instruction!");
1034 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
1035 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1038 // For this type of EXTRACT_SUBREG, conservatively
1039 // check if the live interval of the source register interfere with the
1040 // actual super physical register we are trying to coalesce with.
1041 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
1042 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
1043 if (li_->hasInterval(PhysReg) &&
1044 RHS.overlaps(li_->getInterval(PhysReg))) {
1045 DOUT << "Interfere with register ";
1046 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
1047 return false; // Not coalescable
1049 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
1050 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1051 DOUT << "Interfere with sub-register ";
1052 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1053 return false; // Not coalescable
1057 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1058 : CopyMI->getOperand(2).getSubReg();
1060 if (OldSubIdx == SubIdx &&
1061 !differingRegisterClasses(SrcReg, DstReg, SubRC))
1062 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1063 // coalesced to a larger register so the subreg indices cancel out.
1064 // Also check if the other larger register is of the same register
1065 // class as the would be resulting register.
1068 DOUT << "\t Sub-register indices mismatch.\n";
1069 return false; // Not coalescable.
1073 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1074 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1075 unsigned LargeRegSize =
1076 li_->getApproximateInstructionCount(li_->getInterval(LargeReg));
1077 unsigned SmallRegSize =
1078 li_->getApproximateInstructionCount(li_->getInterval(SmallReg));
1079 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
1080 unsigned Threshold = allocatableRCRegs_[RC].count();
1081 // Be conservative. If both sides are virtual registers, do not coalesce
1082 // if this will cause a high use density interval to target a smaller
1083 // set of registers.
1084 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
1085 if ((float)std::distance(mri_->use_begin(SmallReg),
1086 mri_->use_end()) / SmallRegSize <
1087 (float)std::distance(mri_->use_begin(LargeReg),
1088 mri_->use_end()) / LargeRegSize) {
1089 Again = true; // May be possible to coalesce later.
1095 } else if (differingRegisterClasses(SrcReg, DstReg, SubRC)) {
1096 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
1097 // with another? If it's the resulting destination register, then
1098 // the subidx must be propagated to uses (but only those defined
1099 // by the EXTRACT_SUBREG). If it's being coalesced into another
1100 // register, it should be safe because register is assumed to have
1101 // the register class of the super-register.
1103 if (!SubRC || !isProfitableToCoalesceToSubRC(SrcReg, DstReg, CopyMBB)) {
1104 // If they are not of the same register class, we cannot join them.
1105 DOUT << "\tSrc/Dest are different register classes.\n";
1106 // Allow the coalescer to try again in case either side gets coalesced to
1107 // a physical register that's compatible with the other side. e.g.
1108 // r1024 = MOV32to32_ r1025
1109 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1110 Again = true; // May be possible to coalesce later.
1115 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1116 LiveInterval &DstInt = li_->getInterval(DstReg);
1117 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1118 "Register mapping is horribly broken!");
1120 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1121 DOUT << " and "; DstInt.print(DOUT, tri_);
1124 // Check if it is necessary to propagate "isDead" property.
1125 if (!isExtSubReg && !isInsSubReg) {
1126 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1127 bool isDead = mopd->isDead();
1129 // We need to be careful about coalescing a source physical register with a
1130 // virtual register. Once the coalescing is done, it cannot be broken and
1131 // these are not spillable! If the destination interval uses are far away,
1132 // think twice about coalescing them!
1133 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1134 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1135 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1136 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1137 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1138 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1139 if (TheCopy.isBackEdge)
1140 Threshold *= 2; // Favors back edge copies.
1142 // If the virtual register live interval is long but it has low use desity,
1143 // do not join them, instead mark the physical register as its allocation
1145 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1146 if (Length > Threshold &&
1147 (((float)std::distance(mri_->use_begin(JoinVReg),
1148 mri_->use_end()) / Length) < (1.0 / Threshold))) {
1149 JoinVInt.preference = JoinPReg;
1151 DOUT << "\tMay tie down a physical register, abort!\n";
1152 Again = true; // May be possible to coalesce later.
1158 // Okay, attempt to join these two intervals. On failure, this returns false.
1159 // Otherwise, if one of the intervals being joined is a physreg, this method
1160 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1161 // been modified, so we can use this information below to update aliases.
1162 bool Swapped = false;
1163 // If SrcInt is implicitly defined, it's safe to coalesce.
1164 bool isEmpty = SrcInt.empty();
1165 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1166 // Only coalesce an empty interval (defined by implicit_def) with
1167 // another interval which has a valno defined by the CopyMI and the CopyMI
1168 // is a kill of the implicit def.
1169 DOUT << "Not profitable!\n";
1173 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1174 // Coalescing failed.
1176 // If definition of source is defined by trivial computation, try
1177 // rematerializing it.
1178 if (!isExtSubReg && !isInsSubReg &&
1179 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1182 // If we can eliminate the copy without merging the live ranges, do so now.
1183 if (!isExtSubReg && !isInsSubReg &&
1184 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1185 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1186 JoinedCopies.insert(CopyMI);
1190 // Otherwise, we are unable to join the intervals.
1191 DOUT << "Interference!\n";
1192 Again = true; // May be possible to coalesce later.
1196 LiveInterval *ResSrcInt = &SrcInt;
1197 LiveInterval *ResDstInt = &DstInt;
1199 std::swap(SrcReg, DstReg);
1200 std::swap(ResSrcInt, ResDstInt);
1202 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1203 "LiveInterval::join didn't work right!");
1205 // If we're about to merge live ranges into a physical register live range,
1206 // we have to update any aliased register's live ranges to indicate that they
1207 // have clobbered values for this range.
1208 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1209 // If this is a extract_subreg where dst is a physical register, e.g.
1210 // cl = EXTRACT_SUBREG reg1024, 1
1211 // then create and update the actual physical register allocated to RHS.
1212 if (RealDstReg || RealSrcReg) {
1213 LiveInterval &RealInt =
1214 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1215 SmallSet<const VNInfo*, 4> CopiedValNos;
1216 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1217 E = ResSrcInt->ranges.end(); I != E; ++I) {
1218 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1219 assert(DstLR && "Invalid joined interval!");
1220 const VNInfo *DstValNo = DstLR->valno;
1221 if (CopiedValNos.insert(DstValNo)) {
1222 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1223 li_->getVNInfoAllocator());
1224 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1225 RealInt.addKills(ValNo, DstValNo->kills);
1226 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1230 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1233 // Update the liveintervals of sub-registers.
1234 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1235 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1236 li_->getVNInfoAllocator());
1239 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1240 // larger super-register.
1241 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1242 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1243 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1244 std::swap(SrcReg, DstReg);
1245 std::swap(ResSrcInt, ResDstInt);
1249 // Coalescing to a virtual register that is of a sub-register class of the
1250 // other. Make sure the resulting register is set to the right register class.
1252 mri_->setRegClass(DstReg, SubRC);
1257 // Add all copies that define val# in the source interval into the queue.
1258 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1259 e = ResSrcInt->vni_end(); i != e; ++i) {
1260 const VNInfo *vni = *i;
1261 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1263 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1264 unsigned NewSrcReg, NewDstReg;
1266 JoinedCopies.count(CopyMI) == 0 &&
1267 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1268 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1269 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1270 isBackEdgeCopy(CopyMI, DstReg)));
1275 // Remember to delete the copy instruction.
1276 JoinedCopies.insert(CopyMI);
1278 // Some live range has been lengthened due to colaescing, eliminate the
1279 // unnecessary kills.
1280 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1281 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1282 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1287 // r1024 = implicit_def
1290 RemoveDeadImpDef(DstReg, *ResDstInt);
1291 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1293 // SrcReg is guarateed to be the register whose live interval that is
1295 li_->removeInterval(SrcReg);
1298 // Now the copy is being coalesced away, the val# previously defined
1299 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1300 // length interval. Remove the val#.
1301 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1302 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1303 VNInfo *ImpVal = LR->valno;
1304 assert(ImpVal->def == CopyIdx);
1305 unsigned NextDef = LR->end;
1306 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1307 ResDstInt->removeValNo(ImpVal);
1308 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1309 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1310 // Special case: vr1024 = implicit_def
1311 // vr1024 = insert_subreg vr1024, vr1025, c
1312 // The insert_subreg becomes a "copy" that defines a val# which can itself
1313 // be coalesced away.
1314 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1315 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1316 LR->valno->copy = DefMI;
1320 // If resulting interval has a preference that no longer fits because of subreg
1321 // coalescing, just clear the preference.
1322 if (ResDstInt->preference && (isExtSubReg || isInsSubReg)) {
1323 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1324 if (!RC->contains(ResDstInt->preference))
1325 ResDstInt->preference = 0;
1328 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1335 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1336 /// compute what the resultant value numbers for each value in the input two
1337 /// ranges will be. This is complicated by copies between the two which can
1338 /// and will commonly cause multiple value numbers to be merged into one.
1340 /// VN is the value number that we're trying to resolve. InstDefiningValue
1341 /// keeps track of the new InstDefiningValue assignment for the result
1342 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1343 /// whether a value in this or other is a copy from the opposite set.
1344 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1345 /// already been assigned.
1347 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1348 /// contains the value number the copy is from.
1350 static unsigned ComputeUltimateVN(VNInfo *VNI,
1351 SmallVector<VNInfo*, 16> &NewVNInfo,
1352 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1353 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1354 SmallVector<int, 16> &ThisValNoAssignments,
1355 SmallVector<int, 16> &OtherValNoAssignments) {
1356 unsigned VN = VNI->id;
1358 // If the VN has already been computed, just return it.
1359 if (ThisValNoAssignments[VN] >= 0)
1360 return ThisValNoAssignments[VN];
1361 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1363 // If this val is not a copy from the other val, then it must be a new value
1364 // number in the destination.
1365 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1366 if (I == ThisFromOther.end()) {
1367 NewVNInfo.push_back(VNI);
1368 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1370 VNInfo *OtherValNo = I->second;
1372 // Otherwise, this *is* a copy from the RHS. If the other side has already
1373 // been computed, return it.
1374 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1375 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1377 // Mark this value number as currently being computed, then ask what the
1378 // ultimate value # of the other value is.
1379 ThisValNoAssignments[VN] = -2;
1380 unsigned UltimateVN =
1381 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1382 OtherValNoAssignments, ThisValNoAssignments);
1383 return ThisValNoAssignments[VN] = UltimateVN;
1386 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1387 return std::find(V.begin(), V.end(), Val) != V.end();
1390 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1391 /// the specified live interval is defined by a copy from the specified
1393 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1396 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1399 if (LR->valno->def == ~0U &&
1400 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1401 *tri_->getSuperRegisters(li.reg)) {
1402 // It's a sub-register live interval, we may not have precise information.
1404 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1405 unsigned SrcReg, DstReg;
1406 if (DefMI && tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1407 DstReg == li.reg && SrcReg == Reg) {
1408 // Cache computed info.
1409 LR->valno->def = LR->start;
1410 LR->valno->copy = DefMI;
1417 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1418 /// caller of this method must guarantee that the RHS only contains a single
1419 /// value number and that the RHS is not defined by a copy from this
1420 /// interval. This returns false if the intervals are not joinable, or it
1421 /// joins them and returns true.
1422 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1423 assert(RHS.containsOneValue());
1425 // Some number (potentially more than one) value numbers in the current
1426 // interval may be defined as copies from the RHS. Scan the overlapping
1427 // portions of the LHS and RHS, keeping track of this and looking for
1428 // overlapping live ranges that are NOT defined as copies. If these exist, we
1431 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1432 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1434 if (LHSIt->start < RHSIt->start) {
1435 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1436 if (LHSIt != LHS.begin()) --LHSIt;
1437 } else if (RHSIt->start < LHSIt->start) {
1438 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1439 if (RHSIt != RHS.begin()) --RHSIt;
1442 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1445 // Determine if these live intervals overlap.
1446 bool Overlaps = false;
1447 if (LHSIt->start <= RHSIt->start)
1448 Overlaps = LHSIt->end > RHSIt->start;
1450 Overlaps = RHSIt->end > LHSIt->start;
1452 // If the live intervals overlap, there are two interesting cases: if the
1453 // LHS interval is defined by a copy from the RHS, it's ok and we record
1454 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1455 // coalesce these live ranges and we bail out.
1457 // If we haven't already recorded that this value # is safe, check it.
1458 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1459 // Copy from the RHS?
1460 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1461 return false; // Nope, bail out.
1463 if (LHSIt->contains(RHSIt->valno->def))
1464 // Here is an interesting situation:
1466 // vr1025 = copy vr1024
1471 // Even though vr1025 is copied from vr1024, it's not safe to
1472 // coalesced them since live range of vr1025 intersects the
1473 // def of vr1024. This happens because vr1025 is assigned the
1474 // value of the previous iteration of vr1024.
1476 EliminatedLHSVals.push_back(LHSIt->valno);
1479 // We know this entire LHS live range is okay, so skip it now.
1480 if (++LHSIt == LHSEnd) break;
1484 if (LHSIt->end < RHSIt->end) {
1485 if (++LHSIt == LHSEnd) break;
1487 // One interesting case to check here. It's possible that we have
1488 // something like "X3 = Y" which defines a new value number in the LHS,
1489 // and is the last use of this liverange of the RHS. In this case, we
1490 // want to notice this copy (so that it gets coalesced away) even though
1491 // the live ranges don't actually overlap.
1492 if (LHSIt->start == RHSIt->end) {
1493 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1494 // We already know that this value number is going to be merged in
1495 // if coalescing succeeds. Just skip the liverange.
1496 if (++LHSIt == LHSEnd) break;
1498 // Otherwise, if this is a copy from the RHS, mark it as being merged
1500 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1501 if (LHSIt->contains(RHSIt->valno->def))
1502 // Here is an interesting situation:
1504 // vr1025 = copy vr1024
1509 // Even though vr1025 is copied from vr1024, it's not safe to
1510 // coalesced them since live range of vr1025 intersects the
1511 // def of vr1024. This happens because vr1025 is assigned the
1512 // value of the previous iteration of vr1024.
1514 EliminatedLHSVals.push_back(LHSIt->valno);
1516 // We know this entire LHS live range is okay, so skip it now.
1517 if (++LHSIt == LHSEnd) break;
1522 if (++RHSIt == RHSEnd) break;
1526 // If we got here, we know that the coalescing will be successful and that
1527 // the value numbers in EliminatedLHSVals will all be merged together. Since
1528 // the most common case is that EliminatedLHSVals has a single number, we
1529 // optimize for it: if there is more than one value, we merge them all into
1530 // the lowest numbered one, then handle the interval as if we were merging
1531 // with one value number.
1533 if (EliminatedLHSVals.size() > 1) {
1534 // Loop through all the equal value numbers merging them into the smallest
1536 VNInfo *Smallest = EliminatedLHSVals[0];
1537 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1538 if (EliminatedLHSVals[i]->id < Smallest->id) {
1539 // Merge the current notion of the smallest into the smaller one.
1540 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1541 Smallest = EliminatedLHSVals[i];
1543 // Merge into the smallest.
1544 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1547 LHSValNo = Smallest;
1548 } else if (EliminatedLHSVals.empty()) {
1549 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1550 *tri_->getSuperRegisters(LHS.reg))
1551 // Imprecise sub-register information. Can't handle it.
1553 assert(0 && "No copies from the RHS?");
1555 LHSValNo = EliminatedLHSVals[0];
1558 // Okay, now that there is a single LHS value number that we're merging the
1559 // RHS into, update the value number info for the LHS to indicate that the
1560 // value number is defined where the RHS value number was.
1561 const VNInfo *VNI = RHS.getValNumInfo(0);
1562 LHSValNo->def = VNI->def;
1563 LHSValNo->copy = VNI->copy;
1565 // Okay, the final step is to loop over the RHS live intervals, adding them to
1567 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1568 LHS.addKills(LHSValNo, VNI->kills);
1569 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1570 LHS.weight += RHS.weight;
1571 if (RHS.preference && !LHS.preference)
1572 LHS.preference = RHS.preference;
1577 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1578 /// returns false. Otherwise, if one of the intervals being joined is a
1579 /// physreg, this method always canonicalizes LHS to be it. The output
1580 /// "RHS" will not have been modified, so we can use this information
1581 /// below to update aliases.
1582 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
1583 LiveInterval &RHS, bool &Swapped) {
1584 // Compute the final value assignment, assuming that the live ranges can be
1586 SmallVector<int, 16> LHSValNoAssignments;
1587 SmallVector<int, 16> RHSValNoAssignments;
1588 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1589 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1590 SmallVector<VNInfo*, 16> NewVNInfo;
1592 // If a live interval is a physical register, conservatively check if any
1593 // of its sub-registers is overlapping the live interval of the virtual
1594 // register. If so, do not coalesce.
1595 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1596 *tri_->getSubRegisters(LHS.reg)) {
1597 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1598 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1599 DOUT << "Interfere with sub-register ";
1600 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1603 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1604 *tri_->getSubRegisters(RHS.reg)) {
1605 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1606 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1607 DOUT << "Interfere with sub-register ";
1608 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1613 // Compute ultimate value numbers for the LHS and RHS values.
1614 if (RHS.containsOneValue()) {
1615 // Copies from a liveinterval with a single value are simple to handle and
1616 // very common, handle the special case here. This is important, because
1617 // often RHS is small and LHS is large (e.g. a physreg).
1619 // Find out if the RHS is defined as a copy from some value in the LHS.
1620 int RHSVal0DefinedFromLHS = -1;
1622 VNInfo *RHSValNoInfo = NULL;
1623 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1624 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1625 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1626 // If RHS is not defined as a copy from the LHS, we can use simpler and
1627 // faster checks to see if the live ranges are coalescable. This joiner
1628 // can't swap the LHS/RHS intervals though.
1629 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1630 return SimpleJoin(LHS, RHS);
1632 RHSValNoInfo = RHSValNoInfo0;
1635 // It was defined as a copy from the LHS, find out what value # it is.
1636 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1637 RHSValID = RHSValNoInfo->id;
1638 RHSVal0DefinedFromLHS = RHSValID;
1641 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1642 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1643 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1645 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1646 // should now get updated.
1647 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1650 unsigned VN = VNI->id;
1651 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1652 if (LHSSrcReg != RHS.reg) {
1653 // If this is not a copy from the RHS, its value number will be
1654 // unmodified by the coalescing.
1655 NewVNInfo[VN] = VNI;
1656 LHSValNoAssignments[VN] = VN;
1657 } else if (RHSValID == -1) {
1658 // Otherwise, it is a copy from the RHS, and we don't already have a
1659 // value# for it. Keep the current value number, but remember it.
1660 LHSValNoAssignments[VN] = RHSValID = VN;
1661 NewVNInfo[VN] = RHSValNoInfo;
1662 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1664 // Otherwise, use the specified value #.
1665 LHSValNoAssignments[VN] = RHSValID;
1666 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1667 NewVNInfo[VN] = RHSValNoInfo;
1668 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1672 NewVNInfo[VN] = VNI;
1673 LHSValNoAssignments[VN] = VN;
1677 assert(RHSValID != -1 && "Didn't find value #?");
1678 RHSValNoAssignments[0] = RHSValID;
1679 if (RHSVal0DefinedFromLHS != -1) {
1680 // This path doesn't go through ComputeUltimateVN so just set
1682 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1685 // Loop over the value numbers of the LHS, seeing if any are defined from
1687 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1690 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1693 // DstReg is known to be a register in the LHS interval. If the src is
1694 // from the RHS interval, we can use its value #.
1695 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1698 // Figure out the value # from the RHS.
1699 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1702 // Loop over the value numbers of the RHS, seeing if any are defined from
1704 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1707 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1710 // DstReg is known to be a register in the RHS interval. If the src is
1711 // from the LHS interval, we can use its value #.
1712 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1715 // Figure out the value # from the LHS.
1716 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1719 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1720 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1721 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1723 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1726 unsigned VN = VNI->id;
1727 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1729 ComputeUltimateVN(VNI, NewVNInfo,
1730 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1731 LHSValNoAssignments, RHSValNoAssignments);
1733 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1736 unsigned VN = VNI->id;
1737 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1739 // If this value number isn't a copy from the LHS, it's a new number.
1740 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1741 NewVNInfo.push_back(VNI);
1742 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1746 ComputeUltimateVN(VNI, NewVNInfo,
1747 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1748 RHSValNoAssignments, LHSValNoAssignments);
1752 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1753 // interval lists to see if these intervals are coalescable.
1754 LiveInterval::const_iterator I = LHS.begin();
1755 LiveInterval::const_iterator IE = LHS.end();
1756 LiveInterval::const_iterator J = RHS.begin();
1757 LiveInterval::const_iterator JE = RHS.end();
1759 // Skip ahead until the first place of potential sharing.
1760 if (I->start < J->start) {
1761 I = std::upper_bound(I, IE, J->start);
1762 if (I != LHS.begin()) --I;
1763 } else if (J->start < I->start) {
1764 J = std::upper_bound(J, JE, I->start);
1765 if (J != RHS.begin()) --J;
1769 // Determine if these two live ranges overlap.
1771 if (I->start < J->start) {
1772 Overlaps = I->end > J->start;
1774 Overlaps = J->end > I->start;
1777 // If so, check value # info to determine if they are really different.
1779 // If the live range overlap will map to the same value number in the
1780 // result liverange, we can still coalesce them. If not, we can't.
1781 if (LHSValNoAssignments[I->valno->id] !=
1782 RHSValNoAssignments[J->valno->id])
1786 if (I->end < J->end) {
1795 // Update kill info. Some live ranges are extended due to copy coalescing.
1796 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1797 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1798 VNInfo *VNI = I->first;
1799 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1800 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1801 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1802 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1805 // Update kill info. Some live ranges are extended due to copy coalescing.
1806 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1807 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1808 VNInfo *VNI = I->first;
1809 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1810 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1811 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1812 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1815 // If we get here, we know that we can coalesce the live ranges. Ask the
1816 // intervals to coalesce themselves now.
1817 if ((RHS.ranges.size() > LHS.ranges.size() &&
1818 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1819 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1820 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1823 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1830 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1831 // depth of the basic block (the unsigned), and then on the MBB number.
1832 struct DepthMBBCompare {
1833 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1834 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1835 if (LHS.first > RHS.first) return true; // Deeper loops first
1836 return LHS.first == RHS.first &&
1837 LHS.second->getNumber() < RHS.second->getNumber();
1842 /// getRepIntervalSize - Returns the size of the interval that represents the
1843 /// specified register.
1845 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1846 return Rc->getRepIntervalSize(Reg);
1849 /// CopyRecSort::operator - Join priority queue sorting function.
1851 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1852 // Inner loops first.
1853 if (left.LoopDepth > right.LoopDepth)
1855 else if (left.LoopDepth == right.LoopDepth)
1856 if (left.isBackEdge && !right.isBackEdge)
1861 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1862 std::vector<CopyRec> &TryAgain) {
1863 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1865 std::vector<CopyRec> VirtCopies;
1866 std::vector<CopyRec> PhysCopies;
1867 std::vector<CopyRec> ImpDefCopies;
1868 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1869 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1871 MachineInstr *Inst = MII++;
1873 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1874 unsigned SrcReg, DstReg;
1875 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1876 DstReg = Inst->getOperand(0).getReg();
1877 SrcReg = Inst->getOperand(1).getReg();
1878 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1879 DstReg = Inst->getOperand(0).getReg();
1880 SrcReg = Inst->getOperand(2).getReg();
1881 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1884 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1885 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1887 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
1889 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1890 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
1891 else if (SrcIsPhys || DstIsPhys)
1892 PhysCopies.push_back(CopyRec(Inst, 0, false));
1894 VirtCopies.push_back(CopyRec(Inst, 0, false));
1901 // Try coalescing implicit copies first, followed by copies to / from
1902 // physical registers, then finally copies from virtual registers to
1903 // virtual registers.
1904 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1905 CopyRec &TheCopy = ImpDefCopies[i];
1907 if (!JoinCopy(TheCopy, Again))
1909 TryAgain.push_back(TheCopy);
1911 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1912 CopyRec &TheCopy = PhysCopies[i];
1914 if (!JoinCopy(TheCopy, Again))
1916 TryAgain.push_back(TheCopy);
1918 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1919 CopyRec &TheCopy = VirtCopies[i];
1921 if (!JoinCopy(TheCopy, Again))
1923 TryAgain.push_back(TheCopy);
1927 void SimpleRegisterCoalescing::joinIntervals() {
1928 DOUT << "********** JOINING INTERVALS ***********\n";
1931 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1933 std::vector<CopyRec> TryAgainList;
1934 if (loopInfo->empty()) {
1935 // If there are no loops in the function, join intervals in function order.
1936 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1938 CopyCoalesceInMBB(I, TryAgainList);
1940 // Otherwise, join intervals in inner loops before other intervals.
1941 // Unfortunately we can't just iterate over loop hierarchy here because
1942 // there may be more MBB's than BB's. Collect MBB's for sorting.
1944 // Join intervals in the function prolog first. We want to join physical
1945 // registers with virtual registers before the intervals got too long.
1946 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1947 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1948 MachineBasicBlock *MBB = I;
1949 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1952 // Sort by loop depth.
1953 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1955 // Finally, join intervals in loop nest order.
1956 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1957 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1960 // Joining intervals can allow other intervals to be joined. Iteratively join
1961 // until we make no progress.
1963 SmallVector<CopyRec, 16> TryAgain;
1964 bool ProgressMade = true;
1965 while (ProgressMade) {
1966 ProgressMade = false;
1967 while (!JoinQueue->empty()) {
1968 CopyRec R = JoinQueue->pop();
1970 bool Success = JoinCopy(R, Again);
1972 ProgressMade = true;
1974 TryAgain.push_back(R);
1978 while (!TryAgain.empty()) {
1979 JoinQueue->push(TryAgain.back());
1980 TryAgain.pop_back();
1985 bool ProgressMade = true;
1986 while (ProgressMade) {
1987 ProgressMade = false;
1989 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1990 CopyRec &TheCopy = TryAgainList[i];
1993 bool Success = JoinCopy(TheCopy, Again);
1994 if (Success || !Again) {
1995 TheCopy.MI = 0; // Mark this one as done.
1996 ProgressMade = true;
2007 /// Return true if the two specified registers belong to different register
2008 /// classes. The registers may be either phys or virt regs. In the
2009 /// case where both registers are virtual registers, it would also returns
2010 /// true by reference the RegB register class in SubRC if it is a subset of
2011 /// RegA's register class.
2013 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB,
2014 const TargetRegisterClass *&SubRC) const {
2016 // Get the register classes for the first reg.
2017 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2018 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2019 "Shouldn't consider two physregs!");
2020 return !mri_->getRegClass(RegB)->contains(RegA);
2023 // Compare against the regclass for the second reg.
2024 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2025 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2026 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2027 if (RegClassA == RegClassB)
2029 SubRC = (RegClassA->hasSubClass(RegClassB)) ? RegClassB : NULL;
2032 return !RegClassA->contains(RegB);
2035 /// lastRegisterUse - Returns the last use of the specific register between
2036 /// cycles Start and End or NULL if there are no uses.
2038 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2039 unsigned Reg, unsigned &UseIdx) const{
2041 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2042 MachineOperand *LastUse = NULL;
2043 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2044 E = mri_->use_end(); I != E; ++I) {
2045 MachineOperand &Use = I.getOperand();
2046 MachineInstr *UseMI = Use.getParent();
2047 unsigned SrcReg, DstReg;
2048 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
2049 // Ignore identity copies.
2051 unsigned Idx = li_->getInstructionIndex(UseMI);
2052 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2060 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2063 // Skip deleted instructions
2064 MachineInstr *MI = li_->getInstructionFromIndex(e);
2065 while ((e - InstrSlots::NUM) >= s && !MI) {
2066 e -= InstrSlots::NUM;
2067 MI = li_->getInstructionFromIndex(e);
2069 if (e < s || MI == NULL)
2072 // Ignore identity copies.
2073 unsigned SrcReg, DstReg;
2074 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
2075 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2076 MachineOperand &Use = MI->getOperand(i);
2077 if (Use.isRegister() && Use.isUse() && Use.getReg() &&
2078 tri_->regsOverlap(Use.getReg(), Reg)) {
2084 e -= InstrSlots::NUM;
2091 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2092 if (TargetRegisterInfo::isPhysicalRegister(reg))
2093 cerr << tri_->getName(reg);
2095 cerr << "%reg" << reg;
2098 void SimpleRegisterCoalescing::releaseMemory() {
2099 JoinedCopies.clear();
2100 ReMatCopies.clear();
2103 static bool isZeroLengthInterval(LiveInterval *li) {
2104 for (LiveInterval::Ranges::const_iterator
2105 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2106 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
2111 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2112 /// turn the copy into an implicit def.
2114 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2115 MachineBasicBlock *MBB,
2116 unsigned DstReg, unsigned SrcReg) {
2117 MachineInstr *CopyMI = &*I;
2118 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2119 if (!li_->hasInterval(SrcReg))
2121 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2122 if (!SrcInt.empty())
2124 if (!li_->hasInterval(DstReg))
2126 LiveInterval &DstInt = li_->getInterval(DstReg);
2127 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2128 DstInt.removeValNo(DstLR->valno);
2129 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2130 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2131 CopyMI->RemoveOperand(i);
2132 bool NoUse = mri_->use_empty(SrcReg);
2134 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2135 E = mri_->reg_end(); I != E; ) {
2136 assert(I.getOperand().isDef());
2137 MachineInstr *DefMI = &*I;
2139 // The implicit_def source has no other uses, delete it.
2140 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2141 li_->RemoveMachineInstrFromMaps(DefMI);
2142 DefMI->eraseFromParent();
2150 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2152 mri_ = &fn.getRegInfo();
2153 tm_ = &fn.getTarget();
2154 tri_ = tm_->getRegisterInfo();
2155 tii_ = tm_->getInstrInfo();
2156 li_ = &getAnalysis<LiveIntervals>();
2157 loopInfo = &getAnalysis<MachineLoopInfo>();
2159 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2160 << "********** Function: "
2161 << ((Value*)mf_->getFunction())->getName() << '\n';
2163 allocatableRegs_ = tri_->getAllocatableSet(fn);
2164 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2165 E = tri_->regclass_end(); I != E; ++I)
2166 allocatableRCRegs_.insert(std::make_pair(*I,
2167 tri_->getAllocatableSet(fn, *I)));
2169 // Join (coalesce) intervals if requested.
2170 if (EnableJoining) {
2172 DOUT << "********** INTERVALS POST JOINING **********\n";
2173 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2174 I->second->print(DOUT, tri_);
2179 // Perform a final pass over the instructions and compute spill weights
2180 // and remove identity moves.
2181 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2182 mbbi != mbbe; ++mbbi) {
2183 MachineBasicBlock* mbb = mbbi;
2184 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2186 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2188 MachineInstr *MI = mii;
2189 unsigned SrcReg, DstReg;
2190 if (JoinedCopies.count(MI)) {
2191 // Delete all coalesced copies.
2192 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) {
2193 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2194 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2195 "Unrecognized copy instruction");
2196 DstReg = MI->getOperand(0).getReg();
2198 if (MI->registerDefIsDead(DstReg)) {
2199 LiveInterval &li = li_->getInterval(DstReg);
2200 if (!ShortenDeadCopySrcLiveRange(li, MI))
2201 ShortenDeadCopyLiveRange(li, MI);
2203 li_->RemoveMachineInstrFromMaps(MI);
2204 mii = mbbi->erase(mii);
2209 // If the move will be an identity move delete it
2210 bool isMove = tii_->isMoveInstr(*mii, SrcReg, DstReg);
2211 if (isMove && SrcReg == DstReg) {
2212 if (li_->hasInterval(SrcReg)) {
2213 LiveInterval &RegInt = li_->getInterval(SrcReg);
2214 // If def of this move instruction is dead, remove its live range
2215 // from the dstination register's live interval.
2216 if (mii->registerDefIsDead(DstReg)) {
2217 if (!ShortenDeadCopySrcLiveRange(RegInt, mii))
2218 ShortenDeadCopyLiveRange(RegInt, mii);
2221 li_->RemoveMachineInstrFromMaps(mii);
2222 mii = mbbi->erase(mii);
2224 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2225 SmallSet<unsigned, 4> UniqueUses;
2226 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
2227 const MachineOperand &mop = mii->getOperand(i);
2228 if (mop.isRegister() && mop.getReg() &&
2229 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2230 unsigned reg = mop.getReg();
2231 // Multiple uses of reg by the same instruction. It should not
2232 // contribute to spill weight again.
2233 if (UniqueUses.count(reg) != 0)
2235 LiveInterval &RegInt = li_->getInterval(reg);
2237 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2238 UniqueUses.insert(reg);
2246 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2247 LiveInterval &LI = *I->second;
2248 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2249 // If the live interval length is essentially zero, i.e. in every live
2250 // range the use follows def immediately, it doesn't make sense to spill
2251 // it and hope it will be easier to allocate for this li.
2252 if (isZeroLengthInterval(&LI))
2253 LI.weight = HUGE_VALF;
2255 bool isLoad = false;
2256 if (li_->isReMaterializable(LI, isLoad)) {
2257 // If all of the definitions of the interval are re-materializable,
2258 // it is a preferred candidate for spilling. If non of the defs are
2259 // loads, then it's potentially very cheap to re-materialize.
2260 // FIXME: this gets much more complicated once we support non-trivial
2261 // re-materialization.
2269 // Slightly prefer live interval that has been assigned a preferred reg.
2273 // Divide the weight of the interval by its size. This encourages
2274 // spilling of intervals that are large and have few uses, and
2275 // discourages spilling of small intervals with many uses.
2276 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2284 /// print - Implement the dump method.
2285 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2289 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2290 return new SimpleRegisterCoalescing();
2293 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2294 DEFINING_FILE_FOR(SimpleRegisterCoalescing)