1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
104 MachineInstr *CopyMI) {
105 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
107 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
108 // the example above.
109 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
110 assert(BLR != IntB.end() && "Live range not found!");
111 VNInfo *BValNo = BLR->valno;
113 // Get the location that B is defined at. Two options: either this value has
114 // an unknown definition point or it is defined at CopyIdx. If unknown, we
116 if (!BValNo->getCopy()) return false;
117 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
119 // AValNo is the value number in A that defines the copy, A3 in the example.
120 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
121 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
122 assert(ALR != IntA.end() && "Live range not found!");
123 VNInfo *AValNo = ALR->valno;
124 // If it's re-defined by an early clobber somewhere in the live range, then
125 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
127 // 172 %ECX<def> = MOV32rr %reg1039<kill>
128 // 180 INLINEASM <es:subl $5,$1
129 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
131 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
132 // 188 %EAX<def> = MOV32rr %EAX<kill>
133 // 196 %ECX<def> = MOV32rr %ECX<kill>
134 // 204 %ECX<def> = MOV32rr %ECX<kill>
135 // 212 %EAX<def> = MOV32rr %EAX<kill>
136 // 220 %EAX<def> = MOV32rr %EAX
137 // 228 %reg1039<def> = MOV32rr %ECX<kill>
138 // The early clobber operand ties ECX input to the ECX def.
140 // The live interval of ECX is represented as this:
141 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
142 // The coalescer has no idea there was a def in the middle of [174,230].
143 if (AValNo->hasRedefByEC())
146 // If AValNo is defined as a copy from IntB, we can potentially process this.
147 // Get the instruction that defines this value number.
148 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
149 if (!SrcReg) return false; // Not defined by a copy.
151 // If the value number is not defined by a copy instruction, ignore it.
153 // If the source register comes from an interval other than IntB, we can't
155 if (SrcReg != IntB.reg) return false;
157 // Get the LiveRange in IntB that this value number starts with.
158 LiveInterval::iterator ValLR =
159 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
160 assert(ValLR != IntB.end() && "Live range not found!");
162 // Make sure that the end of the live range is inside the same block as
164 MachineInstr *ValLREndInst =
165 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
182 dbgs() << "\t\tInterfere with sub-register ";
183 li_->getInterval(*SR).print(dbgs(), tri_);
190 dbgs() << "Extending: ";
191 IntB.print(dbgs(), tri_);
194 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
195 // We are about to delete CopyMI, so need to remove it as the 'instruction
196 // that defines this value #'. Update the valnum with the new defining
198 BValNo->def = FillerStart;
201 // Okay, we can merge them. We need to insert a new liverange:
202 // [ValLR.end, BLR.begin) of either value number, then we merge the
203 // two value numbers.
204 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
206 // If the IntB live range is assigned to a physical register, and if that
207 // physreg has sub-registers, update their live intervals as well.
208 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
209 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
210 LiveInterval &SRLI = li_->getInterval(*SR);
211 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
212 SRLI.getNextValue(FillerStart, 0, true,
213 li_->getVNInfoAllocator())));
217 // Okay, merge "B1" into the same value number as "B0".
218 if (BValNo != ValLR->valno) {
219 IntB.addKills(ValLR->valno, BValNo->kills);
220 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
223 dbgs() << " result = ";
224 IntB.print(dbgs(), tri_);
228 // If the source instruction was killing the source register before the
229 // merge, unset the isKill marker given the live range has been extended.
230 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
232 ValLREndInst->getOperand(UIdx).setIsKill(false);
233 ValLR->valno->removeKill(FillerStart);
236 // If the copy instruction was killing the destination register before the
237 // merge, find the last use and trim the live range. That will also add the
239 if (ALR->valno->isKill(CopyIdx))
240 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
246 /// HasOtherReachingDefs - Return true if there are definitions of IntB
247 /// other than BValNo val# that can reach uses of AValno val# of IntA.
248 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
252 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
254 if (AI->valno != AValNo) continue;
255 LiveInterval::Ranges::iterator BI =
256 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
257 if (BI != IntB.ranges.begin())
259 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
260 if (BI->valno == BValNo)
262 if (BI->start <= AI->start && BI->end > AI->start)
264 if (BI->start > AI->start && BI->start < AI->end)
272 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
273 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
275 MachineOperand &MO = MI->getOperand(i);
276 if (MO.isReg() && MO.isImplicit())
277 NewMI->addOperand(MO);
281 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
282 /// IntA being the source and IntB being the dest, thus this defines a value
283 /// number in IntB. If the source value number (in IntA) is defined by a
284 /// commutable instruction and its other operand is coalesced to the copy dest
285 /// register, see if we can transform the copy into a noop by commuting the
286 /// definition. For example,
288 /// A3 = op A2 B0<kill>
290 /// B1 = A3 <- this copy
292 /// = op A3 <- more uses
296 /// B2 = op B0 A2<kill>
298 /// B1 = B2 <- now an identify copy
300 /// = op B2 <- more uses
302 /// This returns true if an interval was modified.
304 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
306 MachineInstr *CopyMI) {
308 li_->getInstructionIndex(CopyMI).getDefIndex();
310 // FIXME: For now, only eliminate the copy by commuting its def when the
311 // source register is a virtual register. We want to guard against cases
312 // where the copy is a back edge copy and commuting the def lengthen the
313 // live interval of the source register to the entire loop.
314 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
317 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
318 // the example above.
319 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
320 assert(BLR != IntB.end() && "Live range not found!");
321 VNInfo *BValNo = BLR->valno;
323 // Get the location that B is defined at. Two options: either this value has
324 // an unknown definition point or it is defined at CopyIdx. If unknown, we
326 if (!BValNo->getCopy()) return false;
327 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
329 // AValNo is the value number in A that defines the copy, A3 in the example.
330 LiveInterval::iterator ALR =
331 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
333 assert(ALR != IntA.end() && "Live range not found!");
334 VNInfo *AValNo = ALR->valno;
335 // If other defs can reach uses of this def, then it's not safe to perform
336 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
338 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
339 AValNo->isUnused() || AValNo->hasPHIKill())
341 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
342 const TargetInstrDesc &TID = DefMI->getDesc();
343 if (!TID.isCommutable())
345 // If DefMI is a two-address instruction then commuting it will change the
346 // destination register.
347 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
348 assert(DefIdx != -1);
350 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
352 unsigned Op1, Op2, NewDstIdx;
353 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
357 else if (Op2 == UseOpIdx)
362 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
363 unsigned NewReg = NewDstMO.getReg();
364 if (NewReg != IntB.reg || !NewDstMO.isKill())
367 // Make sure there are no other definitions of IntB that would reach the
368 // uses which the new definition can reach.
369 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
372 // If some of the uses of IntA.reg is already coalesced away, return false.
373 // It's not possible to determine whether it's safe to perform the coalescing.
374 for (MachineRegisterInfo::use_nodbg_iterator UI =
375 mri_->use_nodbg_begin(IntA.reg),
376 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
377 MachineInstr *UseMI = &*UI;
378 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
379 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
380 if (ULR == IntA.end())
382 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
386 // At this point we have decided that it is legal to do this
387 // transformation. Start by commuting the instruction.
388 MachineBasicBlock *MBB = DefMI->getParent();
389 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
392 if (NewMI != DefMI) {
393 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
394 MBB->insert(DefMI, NewMI);
397 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
398 NewMI->getOperand(OpIdx).setIsKill();
400 bool BHasPHIKill = BValNo->hasPHIKill();
401 SmallVector<VNInfo*, 4> BDeadValNos;
402 VNInfo::KillSet BKills;
403 std::map<SlotIndex, SlotIndex> BExtend;
405 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
414 // then do not add kills of A to the newly created B interval.
415 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
417 BExtend[ALR->end] = BLR->end;
419 // Update uses of IntA of the specific Val# with IntB.
420 bool BHasSubRegs = false;
421 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
422 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
423 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
424 UE = mri_->use_end(); UI != UE;) {
425 MachineOperand &UseMO = UI.getOperand();
426 MachineInstr *UseMI = &*UI;
428 if (JoinedCopies.count(UseMI))
430 if (UseMI->isDebugValue()) {
431 // FIXME These don't have an instruction index. Not clear we have enough
432 // info to decide whether to do this replacement or not. For now do it.
433 UseMO.setReg(NewReg);
436 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
437 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
438 if (ULR == IntA.end() || ULR->valno != AValNo)
440 UseMO.setReg(NewReg);
443 if (UseMO.isKill()) {
445 UseMO.setIsKill(false);
447 BKills.push_back(UseIdx.getDefIndex());
449 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
450 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
452 if (DstReg == IntB.reg) {
453 // This copy will become a noop. If it's defining a new val#,
454 // remove that val# as well. However this live range is being
455 // extended to the end of the existing live range defined by the copy.
456 SlotIndex DefIdx = UseIdx.getDefIndex();
457 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
458 BHasPHIKill |= DLR->valno->hasPHIKill();
459 assert(DLR->valno->def == DefIdx);
460 BDeadValNos.push_back(DLR->valno);
461 BExtend[DLR->start] = DLR->end;
462 JoinedCopies.insert(UseMI);
463 // If this is a kill but it's going to be removed, the last use
464 // of the same val# is the new kill.
470 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
471 // simply extend BLR if CopyMI doesn't end the range.
473 dbgs() << "Extending: ";
474 IntB.print(dbgs(), tri_);
477 // Remove val#'s defined by copies that will be coalesced away.
478 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
479 VNInfo *DeadVNI = BDeadValNos[i];
481 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
482 LiveInterval &SRLI = li_->getInterval(*SR);
483 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
484 SRLI.removeValNo(SRLR->valno);
487 IntB.removeValNo(BDeadValNos[i]);
490 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
491 // is updated. Kills are also updated.
492 VNInfo *ValNo = BValNo;
493 ValNo->def = AValNo->def;
495 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
496 if (ValNo->kills[j] != BLR->end)
497 BKills.push_back(ValNo->kills[j]);
499 ValNo->kills.clear();
500 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
502 if (AI->valno != AValNo) continue;
503 SlotIndex End = AI->end;
504 std::map<SlotIndex, SlotIndex>::iterator
505 EI = BExtend.find(End);
506 if (EI != BExtend.end())
508 IntB.addRange(LiveRange(AI->start, End, ValNo));
510 // If the IntB live range is assigned to a physical register, and if that
511 // physreg has sub-registers, update their live intervals as well.
513 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
514 LiveInterval &SRLI = li_->getInterval(*SR);
515 SRLI.MergeInClobberRange(*li_, AI->start, End,
516 li_->getVNInfoAllocator());
520 IntB.addKills(ValNo, BKills);
521 ValNo->setHasPHIKill(BHasPHIKill);
524 dbgs() << " result = ";
525 IntB.print(dbgs(), tri_);
526 dbgs() << "\nShortening: ";
527 IntA.print(dbgs(), tri_);
530 IntA.removeValNo(AValNo);
533 dbgs() << " result = ";
534 IntA.print(dbgs(), tri_);
542 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
543 /// fallthoughs to SuccMBB.
544 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
545 MachineBasicBlock *SuccMBB,
546 const TargetInstrInfo *tii_) {
549 MachineBasicBlock *TBB = 0, *FBB = 0;
550 SmallVector<MachineOperand, 4> Cond;
551 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
552 MBB->isSuccessor(SuccMBB);
555 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
556 /// from a physical register live interval as well as from the live intervals
557 /// of its sub-registers.
558 static void removeRange(LiveInterval &li,
559 SlotIndex Start, SlotIndex End,
560 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
561 li.removeRange(Start, End, true);
562 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
563 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
564 if (!li_->hasInterval(*SR))
566 LiveInterval &sli = li_->getInterval(*SR);
567 SlotIndex RemoveStart = Start;
568 SlotIndex RemoveEnd = Start;
570 while (RemoveEnd != End) {
571 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
574 RemoveEnd = (LR->end < End) ? LR->end : End;
575 sli.removeRange(RemoveStart, RemoveEnd, true);
576 RemoveStart = RemoveEnd;
582 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
583 /// as the copy instruction, trim the live interval to the last use and return
586 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
587 MachineBasicBlock *CopyMBB,
589 const LiveRange *LR) {
590 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
591 SlotIndex LastUseIdx;
592 MachineOperand *LastUse =
593 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
595 MachineInstr *LastUseMI = LastUse->getParent();
596 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
603 // r1025<dead> = r1024<kill>
604 if (MBBStart < LR->end)
605 removeRange(li, MBBStart, LR->end, li_, tri_);
609 // There are uses before the copy, just shorten the live range to the end
611 LastUse->setIsKill();
612 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
613 LR->valno->addKill(LastUseIdx.getDefIndex());
614 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
615 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
617 // Last use is itself an identity code.
618 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
619 LastUseMI->getOperand(DeadIdx).setIsDead();
625 if (LR->start <= MBBStart && LR->end > MBBStart) {
626 if (LR->start == li_->getZeroIndex()) {
627 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
628 // Live-in to the function but dead. Remove it from entry live-in set.
629 mf_->begin()->removeLiveIn(li.reg);
631 // FIXME: Shorten intervals in BBs that reaches this BB.
637 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
638 /// computation, replace the copy by rematerialize the definition.
639 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
642 MachineInstr *CopyMI) {
643 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
644 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
645 assert(SrcLR != SrcInt.end() && "Live range not found!");
646 VNInfo *ValNo = SrcLR->valno;
647 // If other defs can reach uses of this def, then it's not safe to perform
648 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
650 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
651 ValNo->isUnused() || ValNo->hasPHIKill())
653 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
654 const TargetInstrDesc &TID = DefMI->getDesc();
655 if (!TID.isAsCheapAsAMove())
657 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
659 bool SawStore = false;
660 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
662 if (TID.getNumDefs() != 1)
664 if (!DefMI->isImplicitDef()) {
665 // Make sure the copy destination register class fits the instruction
666 // definition register class. The mismatch can happen as a result of earlier
667 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
668 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
669 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
670 if (mri_->getRegClass(DstReg) != RC)
672 } else if (!RC->contains(DstReg))
676 // If destination register has a sub-register index on it, make sure it mtches
677 // the instruction register class.
679 const TargetInstrDesc &TID = DefMI->getDesc();
680 if (TID.getNumDefs() != 1)
682 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
683 const TargetRegisterClass *DstSubRC =
684 DstRC->getSubRegisterRegClass(DstSubIdx);
685 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
688 else if (DefRC != DstSubRC)
692 SlotIndex DefIdx = CopyIdx.getDefIndex();
693 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
694 DLR->valno->setCopy(0);
695 // Don't forget to update sub-register intervals.
696 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
697 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
698 if (!li_->hasInterval(*SR))
700 const LiveRange *DLR =
701 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
702 if (DLR && DLR->valno->getCopy() == CopyMI)
703 DLR->valno->setCopy(0);
707 // If copy kills the source register, find the last use and propagate
709 bool checkForDeadDef = false;
710 MachineBasicBlock *MBB = CopyMI->getParent();
711 if (SrcLR->valno->isKill(DefIdx))
712 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
713 checkForDeadDef = true;
716 MachineBasicBlock::iterator MII =
717 llvm::next(MachineBasicBlock::iterator(CopyMI));
718 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
719 MachineInstr *NewMI = prior(MII);
721 if (checkForDeadDef) {
722 // PR4090 fix: Trim interval failed because there was no use of the
723 // source interval in this MBB. If the def is in this MBB too then we
724 // should mark it dead:
725 if (DefMI->getParent() == MBB) {
726 DefMI->addRegisterDead(SrcInt.reg, tri_);
727 SrcLR->end = SrcLR->start.getNextSlot();
731 // CopyMI may have implicit operands, transfer them over to the newly
732 // rematerialized instruction. And update implicit def interval valnos.
733 for (unsigned i = CopyMI->getDesc().getNumOperands(),
734 e = CopyMI->getNumOperands(); i != e; ++i) {
735 MachineOperand &MO = CopyMI->getOperand(i);
736 if (MO.isReg() && MO.isImplicit())
737 NewMI->addOperand(MO);
738 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
739 unsigned Reg = MO.getReg();
740 const LiveRange *DLR =
741 li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
742 if (DLR && DLR->valno->getCopy() == CopyMI)
743 DLR->valno->setCopy(0);
744 // Handle subregs as well
745 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
746 for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) {
747 if (!li_->hasInterval(*SR))
749 const LiveRange *DLR =
750 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
751 if (DLR && DLR->valno->getCopy() == CopyMI)
752 DLR->valno->setCopy(0);
758 TransferImplicitOps(CopyMI, NewMI);
759 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
760 CopyMI->eraseFromParent();
761 ReMatCopies.insert(CopyMI);
762 ReMatDefs.insert(DefMI);
763 DEBUG(dbgs() << "Remat: " << *NewMI);
768 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
769 /// update the subregister number if it is not zero. If DstReg is a
770 /// physical register and the existing subregister number of the def / use
771 /// being updated is not zero, make sure to set it to the correct physical
774 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
776 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
777 if (DstIsPhys && SubIdx) {
778 // Figure out the real physical register we are updating with.
779 DstReg = tri_->getSubReg(DstReg, SubIdx);
783 // Copy the register use-list before traversing it. We may be adding operands
784 // and invalidating pointers.
785 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
786 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
787 E = mri_->reg_end(); I != E; ++I)
788 reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
790 for (unsigned N=0; N != reglist.size(); ++N) {
791 MachineInstr *UseMI = reglist[N].first;
792 MachineOperand &O = UseMI->getOperand(reglist[N].second);
793 unsigned OldSubIdx = O.getSubReg();
795 unsigned UseDstReg = DstReg;
797 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
799 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
800 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
801 CopySrcSubIdx, CopyDstSubIdx) &&
802 CopySrcReg != CopyDstReg &&
803 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
804 // If the use is a copy and it won't be coalesced away, and its source
805 // is defined by a trivial computation, try to rematerialize it instead.
806 if (!JoinedCopies.count(UseMI) &&
807 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
808 CopyDstSubIdx, UseMI))
815 // Def and kill of subregister of a virtual register actually defs and
816 // kills the whole register. Add imp-defs and imp-kills as needed.
819 UseMI->addRegisterDead(DstReg, tri_, true);
821 UseMI->addRegisterDefined(DstReg, tri_);
822 } else if (!O.isUndef() &&
824 UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0))))
825 UseMI->addRegisterKilled(DstReg, tri_, true);
827 DEBUG(dbgs() << "\t\tupdated: " << li_->getInstructionIndex(UseMI)
832 // Sub-register indexes goes from small to large. e.g.
833 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
834 // EAX: 1 -> AL, 2 -> AX
835 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
836 // sub-register 2 is also AX.
837 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
838 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
843 DEBUG(dbgs() << "\t\tupdated: " << li_->getInstructionIndex(UseMI)
846 // After updating the operand, check if the machine instruction has
847 // become a copy. If so, update its val# information.
848 if (JoinedCopies.count(UseMI))
851 const TargetInstrDesc &TID = UseMI->getDesc();
852 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
853 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
854 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
855 CopySrcSubIdx, CopyDstSubIdx) &&
856 CopySrcReg != CopyDstReg &&
857 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
858 allocatableRegs_[CopyDstReg])) {
859 LiveInterval &LI = li_->getInterval(CopyDstReg);
861 li_->getInstructionIndex(UseMI).getDefIndex();
862 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
863 if (DLR->valno->def == DefIdx)
864 DLR->valno->setCopy(UseMI);
870 /// removeIntervalIfEmpty - Check if the live interval of a physical register
871 /// is empty, if so remove it and also remove the empty intervals of its
872 /// sub-registers. Return true if live interval is removed.
873 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
874 const TargetRegisterInfo *tri_) {
876 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
877 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
878 if (!li_->hasInterval(*SR))
880 LiveInterval &sli = li_->getInterval(*SR);
882 li_->removeInterval(*SR);
884 li_->removeInterval(li.reg);
890 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
891 /// Return true if live interval is removed.
892 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
893 MachineInstr *CopyMI) {
894 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
895 LiveInterval::iterator MLR =
896 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
898 return false; // Already removed by ShortenDeadCopySrcLiveRange.
899 SlotIndex RemoveStart = MLR->start;
900 SlotIndex RemoveEnd = MLR->end;
901 SlotIndex DefIdx = CopyIdx.getDefIndex();
902 // Remove the liverange that's defined by this.
903 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
904 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
905 return removeIntervalIfEmpty(li, li_, tri_);
910 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
911 /// the val# it defines. If the live interval becomes empty, remove it as well.
912 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
913 MachineInstr *DefMI) {
914 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
915 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
916 if (DefIdx != MLR->valno->def)
918 li.removeValNo(MLR->valno);
919 return removeIntervalIfEmpty(li, li_, tri_);
922 /// PropagateDeadness - Propagate the dead marker to the instruction which
923 /// defines the val#.
924 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
925 SlotIndex &LRStart, LiveIntervals *li_,
926 const TargetRegisterInfo* tri_) {
927 MachineInstr *DefMI =
928 li_->getInstructionFromIndex(LRStart.getDefIndex());
929 if (DefMI && DefMI != CopyMI) {
930 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false);
932 DefMI->getOperand(DeadIdx).setIsDead();
934 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
935 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
936 LRStart = LRStart.getNextSlot();
940 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
941 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
942 /// ends the live range there. If there isn't another use, then this live range
943 /// is dead. Return true if live interval is removed.
945 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
946 MachineInstr *CopyMI) {
947 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
948 if (CopyIdx == SlotIndex()) {
949 // FIXME: special case: function live in. It can be a general case if the
950 // first instruction index starts at > 0 value.
951 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
952 // Live-in to the function but dead. Remove it from entry live-in set.
953 if (mf_->begin()->isLiveIn(li.reg))
954 mf_->begin()->removeLiveIn(li.reg);
955 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
956 removeRange(li, LR->start, LR->end, li_, tri_);
957 return removeIntervalIfEmpty(li, li_, tri_);
960 LiveInterval::iterator LR =
961 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
963 // Livein but defined by a phi.
966 SlotIndex RemoveStart = LR->start;
967 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
968 if (LR->end > RemoveEnd)
969 // More uses past this copy? Nothing to do.
972 // If there is a last use in the same bb, we can't remove the live range.
973 // Shorten the live interval and return.
974 MachineBasicBlock *CopyMBB = CopyMI->getParent();
975 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
978 // There are other kills of the val#. Nothing to do.
979 if (!li.isOnlyLROfValNo(LR))
982 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
983 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
984 // If the live range starts in another mbb and the copy mbb is not a fall
985 // through mbb, then we can only cut the range from the beginning of the
987 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
989 if (LR->valno->def == RemoveStart) {
990 // If the def MI defines the val# and this copy is the only kill of the
991 // val#, then propagate the dead marker.
992 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
995 if (LR->valno->isKill(RemoveEnd))
996 LR->valno->removeKill(RemoveEnd);
999 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
1000 return removeIntervalIfEmpty(li, li_, tri_);
1003 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
1004 /// from an implicit def to another register can be coalesced away.
1005 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
1007 LiveInterval &ImpLi) const{
1008 if (!CopyMI->killsRegister(ImpLi.reg))
1010 // Make sure this is the only use.
1011 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
1012 UE = mri_->use_end(); UI != UE;) {
1013 MachineInstr *UseMI = &*UI;
1015 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
1023 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1024 /// a virtual destination register with physical source register.
1026 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1027 MachineBasicBlock *CopyMBB,
1028 LiveInterval &DstInt,
1029 LiveInterval &SrcInt) {
1030 // If the virtual register live interval is long but it has low use desity,
1031 // do not join them, instead mark the physical register as its allocation
1033 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1034 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1035 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1036 if (Length > Threshold &&
1037 (((float)std::distance(mri_->use_nodbg_begin(DstInt.reg),
1038 mri_->use_nodbg_end()) / Length) <
1042 // If the virtual register live interval extends into a loop, turn down
1045 li_->getInstructionIndex(CopyMI).getDefIndex();
1046 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1048 // Let's see if the virtual register live interval extends into the loop.
1049 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1050 assert(DLR != DstInt.end() && "Live range not found!");
1051 DLR = DstInt.FindLiveRangeContaining(DLR->end.getNextSlot());
1052 if (DLR != DstInt.end()) {
1053 CopyMBB = li_->getMBBFromIndex(DLR->start);
1054 L = loopInfo->getLoopFor(CopyMBB);
1058 if (!L || Length <= Threshold)
1061 SlotIndex UseIdx = CopyIdx.getUseIndex();
1062 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1063 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1064 if (loopInfo->getLoopFor(SMBB) != L) {
1065 if (!loopInfo->isLoopHeader(CopyMBB))
1067 // If vr's live interval extends pass the loop header, do not join.
1068 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1069 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1070 MachineBasicBlock *SuccMBB = *SI;
1071 if (SuccMBB == CopyMBB)
1073 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1074 li_->getMBBEndIdx(SuccMBB)))
1081 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1082 /// copy from a virtual source register to a physical destination register.
1084 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1085 MachineBasicBlock *CopyMBB,
1086 LiveInterval &DstInt,
1087 LiveInterval &SrcInt) {
1088 // If the virtual register live interval is long but it has low use density,
1089 // do not join them, instead mark the physical register as its allocation
1091 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1092 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1093 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1094 if (Length > Threshold &&
1095 (((float)std::distance(mri_->use_nodbg_begin(SrcInt.reg),
1096 mri_->use_nodbg_end()) / Length) <
1101 // Must be implicit_def.
1104 // If the virtual register live interval is defined or cross a loop, turn
1105 // down aggressiveness.
1107 li_->getInstructionIndex(CopyMI).getDefIndex();
1108 SlotIndex UseIdx = CopyIdx.getUseIndex();
1109 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1110 assert(SLR != SrcInt.end() && "Live range not found!");
1111 SLR = SrcInt.FindLiveRangeContaining(SLR->start.getPrevSlot());
1112 if (SLR == SrcInt.end())
1114 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1115 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1117 if (!L || Length <= Threshold)
1120 if (loopInfo->getLoopFor(CopyMBB) != L) {
1121 if (SMBB != L->getLoopLatch())
1123 // If vr's live interval is extended from before the loop latch, do not
1125 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1126 PE = SMBB->pred_end(); PI != PE; ++PI) {
1127 MachineBasicBlock *PredMBB = *PI;
1128 if (PredMBB == SMBB)
1130 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1131 li_->getMBBEndIdx(PredMBB)))
1138 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1139 /// two virtual registers from different register classes.
1141 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
1143 const TargetRegisterClass *SrcRC,
1144 const TargetRegisterClass *DstRC,
1145 const TargetRegisterClass *NewRC) {
1146 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
1147 // This heuristics is good enough in practice, but it's obviously not *right*.
1148 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1149 // out all but the most restrictive register classes.
1150 if (NewRCCount > 4 ||
1151 // Early exit if the function is fairly small, coalesce aggressively if
1152 // that's the case. For really special register classes with 3 or
1153 // fewer registers, be a bit more careful.
1154 (li_->getFuncInstructionCount() / NewRCCount) < 8)
1156 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1157 LiveInterval &DstInt = li_->getInterval(DstReg);
1158 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
1159 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
1160 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
1162 // Estimate *register use density*. If it doubles or more, abort.
1163 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
1164 mri_->use_nodbg_end());
1165 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
1166 mri_->use_nodbg_end());
1167 float NewDensity = ((float)(SrcUses + DstUses) / (SrcSize + DstSize)) /
1169 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1170 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1171 float Density = ((float)SrcUses / SrcSize) / SrcRCCount;
1172 if (NewDensity > Density * 2.0f)
1175 if (DstRC != NewRC && DstSize > NewRCCount) {
1176 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1177 float Density = ((float)DstUses / DstSize) / DstRCCount;
1178 if (NewDensity > Density * 2.0f)
1184 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1185 /// register with a physical register, check if any of the virtual register
1186 /// operand is a sub-register use or def. If so, make sure it won't result
1187 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1188 /// vr1024 = extract_subreg vr1025, 1
1190 /// vr1024 = mov8rr AH
1191 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1192 /// AH does not have a super-reg whose sub-register 1 is AH.
1194 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1197 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1198 E = mri_->reg_end(); I != E; ++I) {
1199 MachineOperand &O = I.getOperand();
1202 MachineInstr *MI = &*I;
1203 if (MI == CopyMI || JoinedCopies.count(MI))
1205 unsigned SubIdx = O.getSubReg();
1206 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1208 if (MI->isExtractSubreg()) {
1209 SubIdx = MI->getOperand(2).getImm();
1210 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1213 unsigned SrcReg = MI->getOperand(1).getReg();
1214 const TargetRegisterClass *RC =
1215 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1216 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1217 : mri_->getRegClass(SrcReg);
1218 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1222 if (MI->isInsertSubreg() || MI->isSubregToReg()) {
1223 SubIdx = MI->getOperand(3).getImm();
1224 if (VirtReg == MI->getOperand(0).getReg()) {
1225 if (!tri_->getSubReg(PhysReg, SubIdx))
1228 unsigned DstReg = MI->getOperand(0).getReg();
1229 const TargetRegisterClass *RC =
1230 TargetRegisterInfo::isPhysicalRegister(DstReg)
1231 ? tri_->getPhysicalRegisterRegClass(DstReg)
1232 : mri_->getRegClass(DstReg);
1233 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1242 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1243 /// an extract_subreg where dst is a physical register, e.g.
1244 /// cl = EXTRACT_SUBREG reg1024, 1
1246 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1247 unsigned SrcReg, unsigned SubIdx,
1248 unsigned &RealDstReg) {
1249 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1250 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1251 assert(RealDstReg && "Invalid extract_subreg instruction!");
1253 LiveInterval &RHS = li_->getInterval(SrcReg);
1254 // For this type of EXTRACT_SUBREG, conservatively
1255 // check if the live interval of the source register interfere with the
1256 // actual super physical register we are trying to coalesce with.
1257 if (li_->hasInterval(RealDstReg) &&
1258 RHS.overlaps(li_->getInterval(RealDstReg))) {
1260 dbgs() << "\t\tInterfere with register ";
1261 li_->getInterval(RealDstReg).print(dbgs(), tri_);
1263 return false; // Not coalescable
1265 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1266 // Do not check DstReg or its sub-register. JoinIntervals() will take care
1268 if (*SR != DstReg &&
1269 !tri_->isSubRegister(DstReg, *SR) &&
1270 li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1272 dbgs() << "\t\tInterfere with sub-register ";
1273 li_->getInterval(*SR).print(dbgs(), tri_);
1275 return false; // Not coalescable
1280 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1281 /// an insert_subreg where src is a physical register, e.g.
1282 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1284 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1285 unsigned SrcReg, unsigned SubIdx,
1286 unsigned &RealSrcReg) {
1287 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1288 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1289 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1291 LiveInterval &LHS = li_->getInterval(DstReg);
1292 if (li_->hasInterval(RealSrcReg) &&
1293 LHS.overlaps(li_->getInterval(RealSrcReg))) {
1295 dbgs() << "\t\tInterfere with register ";
1296 li_->getInterval(RealSrcReg).print(dbgs(), tri_);
1298 return false; // Not coalescable
1300 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1301 // Do not check SrcReg or its sub-register. JoinIntervals() will take care
1303 if (*SR != SrcReg &&
1304 !tri_->isSubRegister(SrcReg, *SR) &&
1305 li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1307 dbgs() << "\t\tInterfere with sub-register ";
1308 li_->getInterval(*SR).print(dbgs(), tri_);
1310 return false; // Not coalescable
1315 /// getRegAllocPreference - Return register allocation preference register.
1317 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1318 MachineRegisterInfo *MRI,
1319 const TargetRegisterInfo *TRI) {
1320 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1322 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1323 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1326 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1327 /// which are the src/dst of the copy instruction CopyMI. This returns true
1328 /// if the copy was successfully coalesced away. If it is not currently
1329 /// possible to coalesce this interval, but it may be possible if other
1330 /// things get coalesced, then it returns true by reference in 'Again'.
1331 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1332 MachineInstr *CopyMI = TheCopy.MI;
1335 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1336 return false; // Already done.
1338 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1340 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1341 bool isExtSubReg = CopyMI->isExtractSubreg();
1342 bool isInsSubReg = CopyMI->isInsertSubreg();
1343 bool isSubRegToReg = CopyMI->isSubregToReg();
1344 unsigned SubIdx = 0;
1346 DstReg = CopyMI->getOperand(0).getReg();
1347 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1348 SrcReg = CopyMI->getOperand(1).getReg();
1349 SrcSubIdx = CopyMI->getOperand(2).getImm();
1350 } else if (isInsSubReg || isSubRegToReg) {
1351 DstReg = CopyMI->getOperand(0).getReg();
1352 DstSubIdx = CopyMI->getOperand(3).getImm();
1353 SrcReg = CopyMI->getOperand(2).getReg();
1354 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1355 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1356 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1357 // coalesced to a larger register so the subreg indices cancel out.
1358 DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
1359 "coalesced to another register.\n");
1360 return false; // Not coalescable.
1362 } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1363 if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
1364 // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
1366 return false; // Not coalescable.
1369 llvm_unreachable("Unrecognized copy instruction!");
1372 // If they are already joined we continue.
1373 if (SrcReg == DstReg) {
1374 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1375 return false; // Not coalescable.
1378 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1379 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1381 // If they are both physical registers, we cannot join them.
1382 if (SrcIsPhys && DstIsPhys) {
1383 DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
1384 return false; // Not coalescable.
1387 // We only join virtual registers with allocatable physical registers.
1388 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1389 DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
1390 return false; // Not coalescable.
1392 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1393 DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
1394 return false; // Not coalescable.
1397 // We cannot handle dual subreg indices and mismatched classes at the same
1399 if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
1400 DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
1404 // Check that a physical source register is compatible with dst regclass
1406 unsigned SrcSubReg = SrcSubIdx ?
1407 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1408 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1409 const TargetRegisterClass *DstSubRC = DstRC;
1411 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1412 assert(DstSubRC && "Illegal subregister index");
1413 if (!DstSubRC->contains(SrcSubReg)) {
1414 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1415 << tri_->getName(SrcSubReg) << " not in "
1416 << DstSubRC->getName() << ".\n");
1417 return false; // Not coalescable.
1421 // Check that a physical dst register is compatible with source regclass
1423 unsigned DstSubReg = DstSubIdx ?
1424 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1425 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1426 const TargetRegisterClass *SrcSubRC = SrcRC;
1428 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1429 assert(SrcSubRC && "Illegal subregister index");
1430 if (!SrcSubRC->contains(DstSubReg)) {
1431 DEBUG(dbgs() << "\tIncompatible source regclass: "
1432 << tri_->getName(DstSubReg) << " not in "
1433 << SrcSubRC->getName() << ".\n");
1435 return false; // Not coalescable.
1439 // Should be non-null only when coalescing to a sub-register class.
1440 bool CrossRC = false;
1441 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1442 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1443 const TargetRegisterClass *NewRC = NULL;
1444 unsigned RealDstReg = 0;
1445 unsigned RealSrcReg = 0;
1446 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1447 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1448 if (SrcIsPhys && isExtSubReg) {
1449 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1450 // coalesced with AX.
1451 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1453 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1454 // coalesced to a larger register so the subreg indices cancel out.
1455 if (DstSubIdx != SubIdx) {
1456 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1457 return false; // Not coalescable.
1460 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1462 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1463 // EAX = INSERT_SUBREG EAX, r1024, 0
1464 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1466 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1467 // coalesced to a larger register so the subreg indices cancel out.
1468 if (SrcSubIdx != SubIdx) {
1469 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1470 return false; // Not coalescable.
1473 DstReg = tri_->getSubReg(DstReg, SubIdx);
1475 } else if ((DstIsPhys && isExtSubReg) ||
1476 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1477 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1478 DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
1479 << " of a super-class.\n");
1480 return false; // Not coalescable.
1483 // FIXME: The following checks are somewhat conservative. Perhaps a better
1484 // way to implement this is to treat this as coalescing a vr with the
1485 // super physical register.
1487 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1488 return false; // Not coalescable
1490 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1491 return false; // Not coalescable
1495 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1496 : CopyMI->getOperand(2).getSubReg();
1498 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1499 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1500 // coalesced to a larger register so the subreg indices cancel out.
1501 // Also check if the other larger register is of the same register
1502 // class as the would be resulting register.
1505 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1506 return false; // Not coalescable.
1510 if (!DstIsPhys && !SrcIsPhys) {
1511 if (isInsSubReg || isSubRegToReg) {
1512 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1513 } else // extract_subreg {
1514 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1517 DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
1518 return false; // Not coalescable
1521 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1522 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1523 << SrcRC->getName() << "/"
1524 << DstRC->getName() << " -> "
1525 << NewRC->getName() << ".\n");
1526 Again = true; // May be possible to coalesce later.
1531 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1532 if (DisableCrossClassJoin)
1536 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1537 // with another? If it's the resulting destination register, then
1538 // the subidx must be propagated to uses (but only those defined
1539 // by the EXTRACT_SUBREG). If it's being coalesced into another
1540 // register, it should be safe because register is assumed to have
1541 // the register class of the super-register.
1543 // Process moves where one of the registers have a sub-register index.
1544 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1545 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1546 SubIdx = DstMO->getSubReg();
1548 if (SrcMO->getSubReg())
1549 // FIXME: can we handle this?
1551 // This is not an insert_subreg but it looks like one.
1552 // e.g. %reg1024:4 = MOV32rr %EAX
1555 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1556 return false; // Not coalescable
1560 SubIdx = SrcMO->getSubReg();
1562 // This is not a extract_subreg but it looks like one.
1563 // e.g. %cl = MOV16rr %reg1024:1
1566 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1567 return false; // Not coalescable
1573 // Now determine the register class of the joined register.
1574 if (!SrcIsPhys && !DstIsPhys) {
1577 SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
1578 } else if (isInsSubReg) {
1580 SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
1582 NewRC = getCommonSubClass(SrcRC, DstRC);
1586 DEBUG(dbgs() << "\tDisjoint regclasses: "
1587 << SrcRC->getName() << ", "
1588 << DstRC->getName() << ".\n");
1589 return false; // Not coalescable.
1592 // If we are joining two virtual registers and the resulting register
1593 // class is more restrictive (fewer register, smaller size). Check if it's
1594 // worth doing the merge.
1595 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1596 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1597 << SrcRC->getName() << "/"
1598 << DstRC->getName() << " -> "
1599 << NewRC->getName() << ".\n");
1600 // Allow the coalescer to try again in case either side gets coalesced to
1601 // a physical register that's compatible with the other side. e.g.
1602 // r1024 = MOV32to32_ r1025
1603 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1604 Again = true; // May be possible to coalesce later.
1610 // Will it create illegal extract_subreg / insert_subreg?
1611 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1613 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1616 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1617 LiveInterval &DstInt = li_->getInterval(DstReg);
1618 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1619 "Register mapping is horribly broken!");
1622 dbgs() << "\t\tInspecting ";
1623 if (SrcRC) dbgs() << SrcRC->getName() << ": ";
1624 SrcInt.print(dbgs(), tri_);
1625 dbgs() << "\n\t\t and ";
1626 if (DstRC) dbgs() << DstRC->getName() << ": ";
1627 DstInt.print(dbgs(), tri_);
1631 // Save a copy of the virtual register live interval. We'll manually
1632 // merge this into the "real" physical register live interval this is
1634 OwningPtr<LiveInterval> SavedLI;
1636 SavedLI.reset(li_->dupInterval(&SrcInt));
1637 else if (RealSrcReg)
1638 SavedLI.reset(li_->dupInterval(&DstInt));
1640 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1641 // Check if it is necessary to propagate "isDead" property.
1642 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1643 bool isDead = mopd->isDead();
1645 // We need to be careful about coalescing a source physical register with a
1646 // virtual register. Once the coalescing is done, it cannot be broken and
1647 // these are not spillable! If the destination interval uses are far away,
1648 // think twice about coalescing them!
1649 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1650 // If the virtual register live interval is long but it has low use
1651 // density, do not join them, instead mark the physical register as its
1652 // allocation preference.
1653 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1654 LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
1655 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1656 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1658 // Don't join with physregs that have a ridiculous number of live
1659 // ranges. The data structure performance is really bad when that
1661 if (JoinPInt.ranges.size() > 1000) {
1662 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1665 << "\tPhysical register live interval too complicated, abort!\n");
1669 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1670 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1671 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1672 float Ratio = 1.0 / Threshold;
1673 if (Length > Threshold &&
1674 (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
1675 mri_->use_nodbg_end()) / Length) < Ratio)) {
1676 // Before giving up coalescing, if definition of source is defined by
1677 // trivial computation, try rematerializing it.
1678 if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1681 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1683 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1684 Again = true; // May be possible to coalesce later.
1690 // Okay, attempt to join these two intervals. On failure, this returns false.
1691 // Otherwise, if one of the intervals being joined is a physreg, this method
1692 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1693 // been modified, so we can use this information below to update aliases.
1694 bool Swapped = false;
1695 // If SrcInt is implicitly defined, it's safe to coalesce.
1696 if (SrcInt.empty()) {
1697 if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1698 // Only coalesce an empty interval (defined by implicit_def) with
1699 // another interval which has a valno defined by the CopyMI and the CopyMI
1700 // is a kill of the implicit def.
1701 DEBUG(dbgs() << "\tNot profitable!\n");
1704 } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) {
1705 // Coalescing failed.
1707 // If definition of source is defined by trivial computation, try
1708 // rematerializing it.
1709 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1710 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1713 // If we can eliminate the copy without merging the live ranges, do so now.
1714 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1715 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1716 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1717 JoinedCopies.insert(CopyMI);
1718 DEBUG(dbgs() << "\tTrivial!\n");
1722 // Otherwise, we are unable to join the intervals.
1723 DEBUG(dbgs() << "\tInterference!\n");
1724 Again = true; // May be possible to coalesce later.
1728 LiveInterval *ResSrcInt = &SrcInt;
1729 LiveInterval *ResDstInt = &DstInt;
1731 std::swap(SrcReg, DstReg);
1732 std::swap(ResSrcInt, ResDstInt);
1734 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1735 "LiveInterval::join didn't work right!");
1737 // If we're about to merge live ranges into a physical register live interval,
1738 // we have to update any aliased register's live ranges to indicate that they
1739 // have clobbered values for this range.
1740 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1741 // If this is a extract_subreg where dst is a physical register, e.g.
1742 // cl = EXTRACT_SUBREG reg1024, 1
1743 // then create and update the actual physical register allocated to RHS.
1744 if (RealDstReg || RealSrcReg) {
1745 LiveInterval &RealInt =
1746 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1747 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1748 E = SavedLI->vni_end(); I != E; ++I) {
1749 const VNInfo *ValNo = *I;
1750 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
1751 false, // updated at *
1752 li_->getVNInfoAllocator());
1753 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1754 RealInt.addKills(NewValNo, ValNo->kills);
1755 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1757 RealInt.weight += SavedLI->weight;
1758 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1761 // Update the liveintervals of sub-registers.
1762 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1763 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
1764 li_->getVNInfoAllocator());
1767 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1768 // larger super-register.
1769 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1770 !SrcIsPhys && !DstIsPhys) {
1771 if ((isExtSubReg && !Swapped) ||
1772 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1773 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1774 std::swap(SrcReg, DstReg);
1775 std::swap(ResSrcInt, ResDstInt);
1779 // Coalescing to a virtual register that is of a sub-register class of the
1780 // other. Make sure the resulting register is set to the right register class.
1784 // This may happen even if it's cross-rc coalescing. e.g.
1785 // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
1786 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1787 // be allocate a register from GR64_ABCD.
1789 mri_->setRegClass(DstReg, NewRC);
1791 // Remember to delete the copy instruction.
1792 JoinedCopies.insert(CopyMI);
1794 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1796 // If we have extended the live range of a physical register, make sure we
1797 // update live-in lists as well.
1798 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1799 const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
1800 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1801 for (LiveInterval::const_iterator I = VRegInterval.begin(),
1802 E = VRegInterval.end(); I != E; ++I ) {
1803 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1804 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1805 MachineBasicBlock &block = *BlockSeq[idx];
1806 if (!block.isLiveIn(DstReg))
1807 block.addLiveIn(DstReg);
1813 // SrcReg is guarateed to be the register whose live interval that is
1815 li_->removeInterval(SrcReg);
1817 // Update regalloc hint.
1818 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1820 // Manually deleted the live interval copy.
1826 // If resulting interval has a preference that no longer fits because of subreg
1827 // coalescing, just clear the preference.
1828 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1829 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1830 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1831 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1832 if (!RC->contains(Preference))
1833 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1837 dbgs() << "\t\tJoined. Result = ";
1838 ResDstInt->print(dbgs(), tri_);
1846 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1847 /// compute what the resultant value numbers for each value in the input two
1848 /// ranges will be. This is complicated by copies between the two which can
1849 /// and will commonly cause multiple value numbers to be merged into one.
1851 /// VN is the value number that we're trying to resolve. InstDefiningValue
1852 /// keeps track of the new InstDefiningValue assignment for the result
1853 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1854 /// whether a value in this or other is a copy from the opposite set.
1855 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1856 /// already been assigned.
1858 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1859 /// contains the value number the copy is from.
1861 static unsigned ComputeUltimateVN(VNInfo *VNI,
1862 SmallVector<VNInfo*, 16> &NewVNInfo,
1863 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1864 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1865 SmallVector<int, 16> &ThisValNoAssignments,
1866 SmallVector<int, 16> &OtherValNoAssignments) {
1867 unsigned VN = VNI->id;
1869 // If the VN has already been computed, just return it.
1870 if (ThisValNoAssignments[VN] >= 0)
1871 return ThisValNoAssignments[VN];
1872 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1874 // If this val is not a copy from the other val, then it must be a new value
1875 // number in the destination.
1876 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1877 if (I == ThisFromOther.end()) {
1878 NewVNInfo.push_back(VNI);
1879 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1881 VNInfo *OtherValNo = I->second;
1883 // Otherwise, this *is* a copy from the RHS. If the other side has already
1884 // been computed, return it.
1885 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1886 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1888 // Mark this value number as currently being computed, then ask what the
1889 // ultimate value # of the other value is.
1890 ThisValNoAssignments[VN] = -2;
1891 unsigned UltimateVN =
1892 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1893 OtherValNoAssignments, ThisValNoAssignments);
1894 return ThisValNoAssignments[VN] = UltimateVN;
1897 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1898 return std::find(V.begin(), V.end(), Val) != V.end();
1901 static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
1902 const TargetInstrInfo *TII,
1903 const TargetRegisterInfo *TRI) {
1904 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1905 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1907 else if (MI->isExtractSubreg()) {
1908 DstReg = MI->getOperand(0).getReg();
1909 SrcReg = MI->getOperand(1).getReg();
1910 } else if (MI->isSubregToReg() ||
1911 MI->isInsertSubreg()) {
1912 DstReg = MI->getOperand(0).getReg();
1913 SrcReg = MI->getOperand(2).getReg();
1916 return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
1917 (DstReg == DR || TRI->isSuperRegister(DR, DstReg));
1920 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1921 /// the specified live interval is defined by a copy from the specified
1923 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1926 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1929 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1930 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1931 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1932 *tri_->getSuperRegisters(li.reg)) {
1933 // It's a sub-register live interval, we may not have precise information.
1935 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1936 if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
1937 // Cache computed info.
1938 LR->valno->def = LR->start;
1939 LR->valno->setCopy(DefMI);
1947 /// ValueLiveAt - Return true if the LiveRange pointed to by the given
1948 /// iterator, or any subsequent range with the same value number,
1949 /// is live at the given point.
1950 bool SimpleRegisterCoalescing::ValueLiveAt(LiveInterval::iterator LRItr,
1951 LiveInterval::iterator LREnd,
1952 SlotIndex defPoint) const {
1953 for (const VNInfo *valno = LRItr->valno;
1954 (LRItr != LREnd) && (LRItr->valno == valno); ++LRItr) {
1955 if (LRItr->contains(defPoint))
1963 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1964 /// caller of this method must guarantee that the RHS only contains a single
1965 /// value number and that the RHS is not defined by a copy from this
1966 /// interval. This returns false if the intervals are not joinable, or it
1967 /// joins them and returns true.
1968 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1969 assert(RHS.containsOneValue());
1971 // Some number (potentially more than one) value numbers in the current
1972 // interval may be defined as copies from the RHS. Scan the overlapping
1973 // portions of the LHS and RHS, keeping track of this and looking for
1974 // overlapping live ranges that are NOT defined as copies. If these exist, we
1977 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1978 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1980 if (LHSIt->start < RHSIt->start) {
1981 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1982 if (LHSIt != LHS.begin()) --LHSIt;
1983 } else if (RHSIt->start < LHSIt->start) {
1984 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1985 if (RHSIt != RHS.begin()) --RHSIt;
1988 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1991 // Determine if these live intervals overlap.
1992 bool Overlaps = false;
1993 if (LHSIt->start <= RHSIt->start)
1994 Overlaps = LHSIt->end > RHSIt->start;
1996 Overlaps = RHSIt->end > LHSIt->start;
1998 // If the live intervals overlap, there are two interesting cases: if the
1999 // LHS interval is defined by a copy from the RHS, it's ok and we record
2000 // that the LHS value # is the same as the RHS. If it's not, then we cannot
2001 // coalesce these live ranges and we bail out.
2003 // If we haven't already recorded that this value # is safe, check it.
2004 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
2005 // If it's re-defined by an early clobber somewhere in the live range,
2006 // then conservatively abort coalescing.
2007 if (LHSIt->valno->hasRedefByEC())
2009 // Copy from the RHS?
2010 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
2011 return false; // Nope, bail out.
2013 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2014 // Here is an interesting situation:
2016 // vr1025 = copy vr1024
2021 // Even though vr1025 is copied from vr1024, it's not safe to
2022 // coalesce them since the live range of vr1025 intersects the
2023 // def of vr1024. This happens because vr1025 is assigned the
2024 // value of the previous iteration of vr1024.
2026 EliminatedLHSVals.push_back(LHSIt->valno);
2029 // We know this entire LHS live range is okay, so skip it now.
2030 if (++LHSIt == LHSEnd) break;
2034 if (LHSIt->end < RHSIt->end) {
2035 if (++LHSIt == LHSEnd) break;
2037 // One interesting case to check here. It's possible that we have
2038 // something like "X3 = Y" which defines a new value number in the LHS,
2039 // and is the last use of this liverange of the RHS. In this case, we
2040 // want to notice this copy (so that it gets coalesced away) even though
2041 // the live ranges don't actually overlap.
2042 if (LHSIt->start == RHSIt->end) {
2043 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2044 // We already know that this value number is going to be merged in
2045 // if coalescing succeeds. Just skip the liverange.
2046 if (++LHSIt == LHSEnd) break;
2048 // If it's re-defined by an early clobber somewhere in the live range,
2049 // then conservatively abort coalescing.
2050 if (LHSIt->valno->hasRedefByEC())
2052 // Otherwise, if this is a copy from the RHS, mark it as being merged
2054 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2055 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2056 // Here is an interesting situation:
2058 // vr1025 = copy vr1024
2063 // Even though vr1025 is copied from vr1024, it's not safe to
2064 // coalesced them since live range of vr1025 intersects the
2065 // def of vr1024. This happens because vr1025 is assigned the
2066 // value of the previous iteration of vr1024.
2068 EliminatedLHSVals.push_back(LHSIt->valno);
2070 // We know this entire LHS live range is okay, so skip it now.
2071 if (++LHSIt == LHSEnd) break;
2076 if (++RHSIt == RHSEnd) break;
2080 // If we got here, we know that the coalescing will be successful and that
2081 // the value numbers in EliminatedLHSVals will all be merged together. Since
2082 // the most common case is that EliminatedLHSVals has a single number, we
2083 // optimize for it: if there is more than one value, we merge them all into
2084 // the lowest numbered one, then handle the interval as if we were merging
2085 // with one value number.
2086 VNInfo *LHSValNo = NULL;
2087 if (EliminatedLHSVals.size() > 1) {
2088 // Loop through all the equal value numbers merging them into the smallest
2090 VNInfo *Smallest = EliminatedLHSVals[0];
2091 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2092 if (EliminatedLHSVals[i]->id < Smallest->id) {
2093 // Merge the current notion of the smallest into the smaller one.
2094 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2095 Smallest = EliminatedLHSVals[i];
2097 // Merge into the smallest.
2098 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2101 LHSValNo = Smallest;
2102 } else if (EliminatedLHSVals.empty()) {
2103 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2104 *tri_->getSuperRegisters(LHS.reg))
2105 // Imprecise sub-register information. Can't handle it.
2107 llvm_unreachable("No copies from the RHS?");
2109 LHSValNo = EliminatedLHSVals[0];
2112 // Okay, now that there is a single LHS value number that we're merging the
2113 // RHS into, update the value number info for the LHS to indicate that the
2114 // value number is defined where the RHS value number was.
2115 const VNInfo *VNI = RHS.getValNumInfo(0);
2116 LHSValNo->def = VNI->def;
2117 LHSValNo->setCopy(VNI->getCopy());
2119 // Okay, the final step is to loop over the RHS live intervals, adding them to
2121 if (VNI->hasPHIKill())
2122 LHSValNo->setHasPHIKill(true);
2123 LHS.addKills(LHSValNo, VNI->kills);
2124 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2126 LHS.ComputeJoinedWeight(RHS);
2128 // Update regalloc hint if both are virtual registers.
2129 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2130 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2131 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2132 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2133 if (RHSPref != LHSPref)
2134 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2137 // Update the liveintervals of sub-registers.
2138 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2139 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2140 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, LHS,
2141 li_->getVNInfoAllocator());
2146 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2147 /// returns false. Otherwise, if one of the intervals being joined is a
2148 /// physreg, this method always canonicalizes LHS to be it. The output
2149 /// "RHS" will not have been modified, so we can use this information
2150 /// below to update aliases.
2152 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2154 // Compute the final value assignment, assuming that the live ranges can be
2156 SmallVector<int, 16> LHSValNoAssignments;
2157 SmallVector<int, 16> RHSValNoAssignments;
2158 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2159 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2160 SmallVector<VNInfo*, 16> NewVNInfo;
2162 // If a live interval is a physical register, conservatively check if any
2163 // of its sub-registers is overlapping the live interval of the virtual
2164 // register. If so, do not coalesce.
2165 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2166 *tri_->getSubRegisters(LHS.reg)) {
2167 // If it's coalescing a virtual register to a physical register, estimate
2168 // its live interval length. This is the *cost* of scanning an entire live
2169 // interval. If the cost is low, we'll do an exhaustive check instead.
2171 // If this is something like this:
2179 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2180 // less conservative check. It's possible a sub-register is defined before
2181 // v1024 (or live in) and live out of BB1.
2182 if (RHS.containsOneValue() &&
2183 li_->intervalIsInOneMBB(RHS) &&
2184 li_->getApproximateInstructionCount(RHS) <= 10) {
2185 // Perform a more exhaustive check for some common cases.
2186 if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2189 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2190 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2192 dbgs() << "\tInterfere with sub-register ";
2193 li_->getInterval(*SR).print(dbgs(), tri_);
2198 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2199 *tri_->getSubRegisters(RHS.reg)) {
2200 if (LHS.containsOneValue() &&
2201 li_->getApproximateInstructionCount(LHS) <= 10) {
2202 // Perform a more exhaustive check for some common cases.
2203 if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2206 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2207 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2209 dbgs() << "\tInterfere with sub-register ";
2210 li_->getInterval(*SR).print(dbgs(), tri_);
2217 // Compute ultimate value numbers for the LHS and RHS values.
2218 if (RHS.containsOneValue()) {
2219 // Copies from a liveinterval with a single value are simple to handle and
2220 // very common, handle the special case here. This is important, because
2221 // often RHS is small and LHS is large (e.g. a physreg).
2223 // Find out if the RHS is defined as a copy from some value in the LHS.
2224 int RHSVal0DefinedFromLHS = -1;
2226 VNInfo *RHSValNoInfo = NULL;
2227 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2228 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2229 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2230 // If RHS is not defined as a copy from the LHS, we can use simpler and
2231 // faster checks to see if the live ranges are coalescable. This joiner
2232 // can't swap the LHS/RHS intervals though.
2233 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2234 return SimpleJoin(LHS, RHS);
2236 RHSValNoInfo = RHSValNoInfo0;
2239 // It was defined as a copy from the LHS, find out what value # it is.
2241 LHS.getLiveRangeContaining(RHSValNoInfo0->def.getPrevSlot())->valno;
2242 RHSValID = RHSValNoInfo->id;
2243 RHSVal0DefinedFromLHS = RHSValID;
2246 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2247 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2248 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2250 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2251 // should now get updated.
2252 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2255 unsigned VN = VNI->id;
2256 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2257 if (LHSSrcReg != RHS.reg) {
2258 // If this is not a copy from the RHS, its value number will be
2259 // unmodified by the coalescing.
2260 NewVNInfo[VN] = VNI;
2261 LHSValNoAssignments[VN] = VN;
2262 } else if (RHSValID == -1) {
2263 // Otherwise, it is a copy from the RHS, and we don't already have a
2264 // value# for it. Keep the current value number, but remember it.
2265 LHSValNoAssignments[VN] = RHSValID = VN;
2266 NewVNInfo[VN] = RHSValNoInfo;
2267 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2269 // Otherwise, use the specified value #.
2270 LHSValNoAssignments[VN] = RHSValID;
2271 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2272 NewVNInfo[VN] = RHSValNoInfo;
2273 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2277 NewVNInfo[VN] = VNI;
2278 LHSValNoAssignments[VN] = VN;
2282 assert(RHSValID != -1 && "Didn't find value #?");
2283 RHSValNoAssignments[0] = RHSValID;
2284 if (RHSVal0DefinedFromLHS != -1) {
2285 // This path doesn't go through ComputeUltimateVN so just set
2287 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2290 // Loop over the value numbers of the LHS, seeing if any are defined from
2292 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2295 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2298 // DstReg is known to be a register in the LHS interval. If the src is
2299 // from the RHS interval, we can use its value #.
2300 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2303 // Figure out the value # from the RHS.
2304 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2305 assert(lr && "Cannot find live range");
2306 LHSValsDefinedFromRHS[VNI] = lr->valno;
2309 // Loop over the value numbers of the RHS, seeing if any are defined from
2311 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2314 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2317 // DstReg is known to be a register in the RHS interval. If the src is
2318 // from the LHS interval, we can use its value #.
2319 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2322 // Figure out the value # from the LHS.
2323 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2324 assert(lr && "Cannot find live range");
2325 RHSValsDefinedFromLHS[VNI] = lr->valno;
2328 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2329 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2330 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2332 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2335 unsigned VN = VNI->id;
2336 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2338 ComputeUltimateVN(VNI, NewVNInfo,
2339 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2340 LHSValNoAssignments, RHSValNoAssignments);
2342 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2345 unsigned VN = VNI->id;
2346 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2348 // If this value number isn't a copy from the LHS, it's a new number.
2349 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2350 NewVNInfo.push_back(VNI);
2351 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2355 ComputeUltimateVN(VNI, NewVNInfo,
2356 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2357 RHSValNoAssignments, LHSValNoAssignments);
2361 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2362 // interval lists to see if these intervals are coalescable.
2363 LiveInterval::const_iterator I = LHS.begin();
2364 LiveInterval::const_iterator IE = LHS.end();
2365 LiveInterval::const_iterator J = RHS.begin();
2366 LiveInterval::const_iterator JE = RHS.end();
2368 // Skip ahead until the first place of potential sharing.
2369 if (I->start < J->start) {
2370 I = std::upper_bound(I, IE, J->start);
2371 if (I != LHS.begin()) --I;
2372 } else if (J->start < I->start) {
2373 J = std::upper_bound(J, JE, I->start);
2374 if (J != RHS.begin()) --J;
2378 // Determine if these two live ranges overlap.
2380 if (I->start < J->start) {
2381 Overlaps = I->end > J->start;
2383 Overlaps = J->end > I->start;
2386 // If so, check value # info to determine if they are really different.
2388 // If the live range overlap will map to the same value number in the
2389 // result liverange, we can still coalesce them. If not, we can't.
2390 if (LHSValNoAssignments[I->valno->id] !=
2391 RHSValNoAssignments[J->valno->id])
2393 // If it's re-defined by an early clobber somewhere in the live range,
2394 // then conservatively abort coalescing.
2395 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
2399 if (I->end < J->end) {
2408 // Update kill info. Some live ranges are extended due to copy coalescing.
2409 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2410 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2411 VNInfo *VNI = I->first;
2412 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2413 NewVNInfo[LHSValID]->removeKill(VNI->def);
2414 if (VNI->hasPHIKill())
2415 NewVNInfo[LHSValID]->setHasPHIKill(true);
2416 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2419 // Update kill info. Some live ranges are extended due to copy coalescing.
2420 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2421 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2422 VNInfo *VNI = I->first;
2423 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2424 NewVNInfo[RHSValID]->removeKill(VNI->def);
2425 if (VNI->hasPHIKill())
2426 NewVNInfo[RHSValID]->setHasPHIKill(true);
2427 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2430 // If we get here, we know that we can coalesce the live ranges. Ask the
2431 // intervals to coalesce themselves now.
2432 if ((RHS.ranges.size() > LHS.ranges.size() &&
2433 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2434 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2435 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2439 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2447 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2448 // depth of the basic block (the unsigned), and then on the MBB number.
2449 struct DepthMBBCompare {
2450 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2451 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2452 // Deeper loops first
2453 if (LHS.first != RHS.first)
2454 return LHS.first > RHS.first;
2456 // Prefer blocks that are more connected in the CFG. This takes care of
2457 // the most difficult copies first while intervals are short.
2458 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
2459 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
2463 // As a last resort, sort by block number.
2464 return LHS.second->getNumber() < RHS.second->getNumber();
2469 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2470 std::vector<CopyRec> &TryAgain) {
2471 DEBUG(dbgs() << MBB->getName() << ":\n");
2473 std::vector<CopyRec> VirtCopies;
2474 std::vector<CopyRec> PhysCopies;
2475 std::vector<CopyRec> ImpDefCopies;
2476 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2478 MachineInstr *Inst = MII++;
2480 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2481 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2482 bool isInsUndef = false;
2483 if (Inst->isExtractSubreg()) {
2484 DstReg = Inst->getOperand(0).getReg();
2485 SrcReg = Inst->getOperand(1).getReg();
2486 } else if (Inst->isInsertSubreg()) {
2487 DstReg = Inst->getOperand(0).getReg();
2488 SrcReg = Inst->getOperand(2).getReg();
2489 if (Inst->getOperand(1).isUndef())
2491 } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
2492 DstReg = Inst->getOperand(0).getReg();
2493 SrcReg = Inst->getOperand(2).getReg();
2494 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2497 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2498 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2500 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
2501 ImpDefCopies.push_back(CopyRec(Inst, 0));
2502 else if (SrcIsPhys || DstIsPhys)
2503 PhysCopies.push_back(CopyRec(Inst, 0));
2505 VirtCopies.push_back(CopyRec(Inst, 0));
2508 // Try coalescing implicit copies and insert_subreg <undef> first,
2509 // followed by copies to / from physical registers, then finally copies
2510 // from virtual registers to virtual registers.
2511 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2512 CopyRec &TheCopy = ImpDefCopies[i];
2514 if (!JoinCopy(TheCopy, Again))
2516 TryAgain.push_back(TheCopy);
2518 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2519 CopyRec &TheCopy = PhysCopies[i];
2521 if (!JoinCopy(TheCopy, Again))
2523 TryAgain.push_back(TheCopy);
2525 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2526 CopyRec &TheCopy = VirtCopies[i];
2528 if (!JoinCopy(TheCopy, Again))
2530 TryAgain.push_back(TheCopy);
2534 void SimpleRegisterCoalescing::joinIntervals() {
2535 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2537 std::vector<CopyRec> TryAgainList;
2538 if (loopInfo->empty()) {
2539 // If there are no loops in the function, join intervals in function order.
2540 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2542 CopyCoalesceInMBB(I, TryAgainList);
2544 // Otherwise, join intervals in inner loops before other intervals.
2545 // Unfortunately we can't just iterate over loop hierarchy here because
2546 // there may be more MBB's than BB's. Collect MBB's for sorting.
2548 // Join intervals in the function prolog first. We want to join physical
2549 // registers with virtual registers before the intervals got too long.
2550 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2551 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2552 MachineBasicBlock *MBB = I;
2553 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2556 // Sort by loop depth.
2557 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2559 // Finally, join intervals in loop nest order.
2560 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2561 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2564 // Joining intervals can allow other intervals to be joined. Iteratively join
2565 // until we make no progress.
2566 bool ProgressMade = true;
2567 while (ProgressMade) {
2568 ProgressMade = false;
2570 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2571 CopyRec &TheCopy = TryAgainList[i];
2576 bool Success = JoinCopy(TheCopy, Again);
2577 if (Success || !Again) {
2578 TheCopy.MI = 0; // Mark this one as done.
2579 ProgressMade = true;
2585 /// Return true if the two specified registers belong to different register
2586 /// classes. The registers may be either phys or virt regs.
2588 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2589 unsigned RegB) const {
2590 // Get the register classes for the first reg.
2591 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2592 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2593 "Shouldn't consider two physregs!");
2594 return !mri_->getRegClass(RegB)->contains(RegA);
2597 // Compare against the regclass for the second reg.
2598 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2599 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2600 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2601 return RegClassA != RegClassB;
2603 return !RegClassA->contains(RegB);
2606 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
2607 /// between cycles Start and End or NULL if there are no uses.
2609 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
2612 SlotIndex &UseIdx) const{
2613 UseIdx = SlotIndex();
2614 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2615 MachineOperand *LastUse = NULL;
2616 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
2617 E = mri_->use_nodbg_end(); I != E; ++I) {
2618 MachineOperand &Use = I.getOperand();
2619 MachineInstr *UseMI = Use.getParent();
2620 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2621 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2623 // Ignore identity copies.
2625 SlotIndex Idx = li_->getInstructionIndex(UseMI);
2626 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
2627 // that compares higher than any other interval.
2628 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2630 UseIdx = Idx.getUseIndex();
2636 SlotIndex s = Start;
2637 SlotIndex e = End.getPrevSlot().getBaseIndex();
2639 // Skip deleted instructions
2640 MachineInstr *MI = li_->getInstructionFromIndex(e);
2641 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
2642 e = e.getPrevIndex();
2643 MI = li_->getInstructionFromIndex(e);
2645 if (e < s || MI == NULL)
2648 // Ignore identity copies.
2649 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2650 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2652 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2653 MachineOperand &Use = MI->getOperand(i);
2654 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2655 tri_->regsOverlap(Use.getReg(), Reg)) {
2656 UseIdx = e.getUseIndex();
2661 e = e.getPrevIndex();
2667 void SimpleRegisterCoalescing::releaseMemory() {
2668 JoinedCopies.clear();
2669 ReMatCopies.clear();
2673 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2675 mri_ = &fn.getRegInfo();
2676 tm_ = &fn.getTarget();
2677 tri_ = tm_->getRegisterInfo();
2678 tii_ = tm_->getInstrInfo();
2679 li_ = &getAnalysis<LiveIntervals>();
2680 AA = &getAnalysis<AliasAnalysis>();
2681 loopInfo = &getAnalysis<MachineLoopInfo>();
2683 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2684 << "********** Function: "
2685 << ((Value*)mf_->getFunction())->getName() << '\n');
2687 allocatableRegs_ = tri_->getAllocatableSet(fn);
2688 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2689 E = tri_->regclass_end(); I != E; ++I)
2690 allocatableRCRegs_.insert(std::make_pair(*I,
2691 tri_->getAllocatableSet(fn, *I)));
2693 // Join (coalesce) intervals if requested.
2694 if (EnableJoining) {
2697 dbgs() << "********** INTERVALS POST JOINING **********\n";
2698 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
2700 I->second->print(dbgs(), tri_);
2706 // Perform a final pass over the instructions and compute spill weights
2707 // and remove identity moves.
2708 SmallVector<unsigned, 4> DeadDefs;
2709 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2710 mbbi != mbbe; ++mbbi) {
2711 MachineBasicBlock* mbb = mbbi;
2712 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2714 MachineInstr *MI = mii;
2715 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2716 if (JoinedCopies.count(MI)) {
2717 // Delete all coalesced copies.
2718 bool DoDelete = true;
2719 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2720 assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
2721 MI->isSubregToReg()) && "Unrecognized copy instruction");
2722 DstReg = MI->getOperand(0).getReg();
2723 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2724 // Do not delete extract_subreg, insert_subreg of physical
2725 // registers unless the definition is dead. e.g.
2726 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
2727 // or else the scavenger may complain. LowerSubregs will
2728 // delete them later.
2731 if (MI->allDefsAreDead()) {
2732 LiveInterval &li = li_->getInterval(DstReg);
2733 if (!ShortenDeadCopySrcLiveRange(li, MI))
2734 ShortenDeadCopyLiveRange(li, MI);
2738 mii = llvm::next(mii);
2740 li_->RemoveMachineInstrFromMaps(MI);
2741 mii = mbbi->erase(mii);
2747 // Now check if this is a remat'ed def instruction which is now dead.
2748 if (ReMatDefs.count(MI)) {
2750 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2751 const MachineOperand &MO = MI->getOperand(i);
2754 unsigned Reg = MO.getReg();
2757 if (TargetRegisterInfo::isVirtualRegister(Reg))
2758 DeadDefs.push_back(Reg);
2761 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2762 !mri_->use_nodbg_empty(Reg)) {
2768 while (!DeadDefs.empty()) {
2769 unsigned DeadDef = DeadDefs.back();
2770 DeadDefs.pop_back();
2771 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2773 li_->RemoveMachineInstrFromMaps(mii);
2774 mii = mbbi->erase(mii);
2780 // If the move will be an identity move delete it
2781 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2782 if (isMove && SrcReg == DstReg) {
2783 if (li_->hasInterval(SrcReg)) {
2784 LiveInterval &RegInt = li_->getInterval(SrcReg);
2785 // If def of this move instruction is dead, remove its live range
2786 // from the dstination register's live interval.
2787 if (MI->registerDefIsDead(DstReg)) {
2788 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2789 ShortenDeadCopyLiveRange(RegInt, MI);
2792 li_->RemoveMachineInstrFromMaps(MI);
2793 mii = mbbi->erase(mii);
2800 // Check for now unnecessary kill flags.
2801 if (li_->isNotInMIMap(MI)) continue;
2802 SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex();
2803 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2804 MachineOperand &MO = MI->getOperand(i);
2805 if (!MO.isReg() || !MO.isKill()) continue;
2806 unsigned reg = MO.getReg();
2807 if (!reg || !li_->hasInterval(reg)) continue;
2808 LiveInterval &LI = li_->getInterval(reg);
2809 const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
2811 (!LR->valno->isKill(UseIdx.getDefIndex()) &&
2812 LR->valno->def != UseIdx.getDefIndex()))
2813 MO.setIsKill(false);
2822 /// print - Implement the dump method.
2823 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
2827 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2828 return new SimpleRegisterCoalescing();
2831 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2832 DEFINING_FILE_FOR(SimpleRegisterCoalescing)