1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
104 MachineInstr *CopyMI) {
105 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
107 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
108 // the example above.
109 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
110 assert(BLR != IntB.end() && "Live range not found!");
111 VNInfo *BValNo = BLR->valno;
113 // Get the location that B is defined at. Two options: either this value has
114 // an unknown definition point or it is defined at CopyIdx. If unknown, we
116 if (!BValNo->getCopy()) return false;
117 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
119 // AValNo is the value number in A that defines the copy, A3 in the example.
120 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
121 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
122 assert(ALR != IntA.end() && "Live range not found!");
123 VNInfo *AValNo = ALR->valno;
124 // If it's re-defined by an early clobber somewhere in the live range, then
125 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
127 // 172 %ECX<def> = MOV32rr %reg1039<kill>
128 // 180 INLINEASM <es:subl $5,$1
129 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
131 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
132 // 188 %EAX<def> = MOV32rr %EAX<kill>
133 // 196 %ECX<def> = MOV32rr %ECX<kill>
134 // 204 %ECX<def> = MOV32rr %ECX<kill>
135 // 212 %EAX<def> = MOV32rr %EAX<kill>
136 // 220 %EAX<def> = MOV32rr %EAX
137 // 228 %reg1039<def> = MOV32rr %ECX<kill>
138 // The early clobber operand ties ECX input to the ECX def.
140 // The live interval of ECX is represented as this:
141 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
142 // The coalescer has no idea there was a def in the middle of [174,230].
143 if (AValNo->hasRedefByEC())
146 // If AValNo is defined as a copy from IntB, we can potentially process this.
147 // Get the instruction that defines this value number.
148 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
149 if (!SrcReg) return false; // Not defined by a copy.
151 // If the value number is not defined by a copy instruction, ignore it.
153 // If the source register comes from an interval other than IntB, we can't
155 if (SrcReg != IntB.reg) return false;
157 // Get the LiveRange in IntB that this value number starts with.
158 LiveInterval::iterator ValLR =
159 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
160 assert(ValLR != IntB.end() && "Live range not found!");
162 // Make sure that the end of the live range is inside the same block as
164 MachineInstr *ValLREndInst =
165 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
182 dbgs() << "\t\tInterfere with sub-register ";
183 li_->getInterval(*SR).print(dbgs(), tri_);
190 dbgs() << "Extending: ";
191 IntB.print(dbgs(), tri_);
194 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
195 // We are about to delete CopyMI, so need to remove it as the 'instruction
196 // that defines this value #'. Update the valnum with the new defining
198 BValNo->def = FillerStart;
201 // Okay, we can merge them. We need to insert a new liverange:
202 // [ValLR.end, BLR.begin) of either value number, then we merge the
203 // two value numbers.
204 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
206 // If the IntB live range is assigned to a physical register, and if that
207 // physreg has sub-registers, update their live intervals as well.
208 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
209 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
210 LiveInterval &SRLI = li_->getInterval(*SR);
211 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
212 SRLI.getNextValue(FillerStart, 0, true,
213 li_->getVNInfoAllocator())));
217 // Okay, merge "B1" into the same value number as "B0".
218 if (BValNo != ValLR->valno) {
219 IntB.addKills(ValLR->valno, BValNo->kills);
220 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
223 dbgs() << " result = ";
224 IntB.print(dbgs(), tri_);
228 // If the source instruction was killing the source register before the
229 // merge, unset the isKill marker given the live range has been extended.
230 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
232 ValLREndInst->getOperand(UIdx).setIsKill(false);
233 ValLR->valno->removeKill(FillerStart);
236 // If the copy instruction was killing the destination register before the
237 // merge, find the last use and trim the live range. That will also add the
239 if (ALR->valno->isKill(CopyIdx))
240 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
246 /// HasOtherReachingDefs - Return true if there are definitions of IntB
247 /// other than BValNo val# that can reach uses of AValno val# of IntA.
248 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
252 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
254 if (AI->valno != AValNo) continue;
255 LiveInterval::Ranges::iterator BI =
256 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
257 if (BI != IntB.ranges.begin())
259 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
260 if (BI->valno == BValNo)
262 // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
263 if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
265 if (BI->start <= AI->start && BI->end > AI->start)
267 if (BI->start > AI->start && BI->start < AI->end)
275 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
276 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
278 MachineOperand &MO = MI->getOperand(i);
279 if (MO.isReg() && MO.isImplicit())
280 NewMI->addOperand(MO);
284 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
285 /// IntA being the source and IntB being the dest, thus this defines a value
286 /// number in IntB. If the source value number (in IntA) is defined by a
287 /// commutable instruction and its other operand is coalesced to the copy dest
288 /// register, see if we can transform the copy into a noop by commuting the
289 /// definition. For example,
291 /// A3 = op A2 B0<kill>
293 /// B1 = A3 <- this copy
295 /// = op A3 <- more uses
299 /// B2 = op B0 A2<kill>
301 /// B1 = B2 <- now an identify copy
303 /// = op B2 <- more uses
305 /// This returns true if an interval was modified.
307 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
309 MachineInstr *CopyMI) {
311 li_->getInstructionIndex(CopyMI).getDefIndex();
313 // FIXME: For now, only eliminate the copy by commuting its def when the
314 // source register is a virtual register. We want to guard against cases
315 // where the copy is a back edge copy and commuting the def lengthen the
316 // live interval of the source register to the entire loop.
317 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
320 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
321 // the example above.
322 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
323 assert(BLR != IntB.end() && "Live range not found!");
324 VNInfo *BValNo = BLR->valno;
326 // Get the location that B is defined at. Two options: either this value has
327 // an unknown definition point or it is defined at CopyIdx. If unknown, we
329 if (!BValNo->getCopy()) return false;
330 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
332 // AValNo is the value number in A that defines the copy, A3 in the example.
333 LiveInterval::iterator ALR =
334 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
336 assert(ALR != IntA.end() && "Live range not found!");
337 VNInfo *AValNo = ALR->valno;
338 // If other defs can reach uses of this def, then it's not safe to perform
339 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
341 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
342 AValNo->isUnused() || AValNo->hasPHIKill())
344 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
345 const TargetInstrDesc &TID = DefMI->getDesc();
346 if (!TID.isCommutable())
348 // If DefMI is a two-address instruction then commuting it will change the
349 // destination register.
350 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
351 assert(DefIdx != -1);
353 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
355 unsigned Op1, Op2, NewDstIdx;
356 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
360 else if (Op2 == UseOpIdx)
365 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
366 unsigned NewReg = NewDstMO.getReg();
367 if (NewReg != IntB.reg || !NewDstMO.isKill())
370 // Make sure there are no other definitions of IntB that would reach the
371 // uses which the new definition can reach.
372 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
375 bool BHasSubRegs = false;
376 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
377 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
379 // Abort if the subregisters of IntB.reg have values that are not simply the
380 // clobbers from the superreg.
382 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
383 if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
386 // If some of the uses of IntA.reg is already coalesced away, return false.
387 // It's not possible to determine whether it's safe to perform the coalescing.
388 for (MachineRegisterInfo::use_nodbg_iterator UI =
389 mri_->use_nodbg_begin(IntA.reg),
390 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
391 MachineInstr *UseMI = &*UI;
392 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
393 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
394 if (ULR == IntA.end())
396 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
400 // At this point we have decided that it is legal to do this
401 // transformation. Start by commuting the instruction.
402 MachineBasicBlock *MBB = DefMI->getParent();
403 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
406 if (NewMI != DefMI) {
407 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
408 MBB->insert(DefMI, NewMI);
411 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
412 NewMI->getOperand(OpIdx).setIsKill();
414 bool BHasPHIKill = BValNo->hasPHIKill();
415 SmallVector<VNInfo*, 4> BDeadValNos;
416 VNInfo::KillSet BKills;
417 std::map<SlotIndex, SlotIndex> BExtend;
419 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
428 // then do not add kills of A to the newly created B interval.
429 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
431 BExtend[ALR->end] = BLR->end;
433 // Update uses of IntA of the specific Val# with IntB.
434 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
435 UE = mri_->use_end(); UI != UE;) {
436 MachineOperand &UseMO = UI.getOperand();
437 MachineInstr *UseMI = &*UI;
439 if (JoinedCopies.count(UseMI))
441 if (UseMI->isDebugValue()) {
442 // FIXME These don't have an instruction index. Not clear we have enough
443 // info to decide whether to do this replacement or not. For now do it.
444 UseMO.setReg(NewReg);
447 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
448 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
449 if (ULR == IntA.end() || ULR->valno != AValNo)
451 UseMO.setReg(NewReg);
454 if (UseMO.isKill()) {
456 UseMO.setIsKill(false);
458 BKills.push_back(UseIdx.getDefIndex());
460 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
461 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
463 if (DstReg == IntB.reg && DstSubIdx == 0) {
464 // This copy will become a noop. If it's defining a new val#,
465 // remove that val# as well. However this live range is being
466 // extended to the end of the existing live range defined by the copy.
467 SlotIndex DefIdx = UseIdx.getDefIndex();
468 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
469 BHasPHIKill |= DLR->valno->hasPHIKill();
470 assert(DLR->valno->def == DefIdx);
471 BDeadValNos.push_back(DLR->valno);
472 BExtend[DLR->start] = DLR->end;
473 JoinedCopies.insert(UseMI);
474 // If this is a kill but it's going to be removed, the last use
475 // of the same val# is the new kill.
481 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
482 // simply extend BLR if CopyMI doesn't end the range.
484 dbgs() << "Extending: ";
485 IntB.print(dbgs(), tri_);
488 // Remove val#'s defined by copies that will be coalesced away.
489 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
490 VNInfo *DeadVNI = BDeadValNos[i];
492 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
493 LiveInterval &SRLI = li_->getInterval(*SR);
494 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
495 SRLI.removeValNo(SRLR->valno);
498 IntB.removeValNo(BDeadValNos[i]);
501 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
502 // is updated. Kills are also updated.
503 VNInfo *ValNo = BValNo;
504 ValNo->def = AValNo->def;
506 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
507 if (ValNo->kills[j] != BLR->end)
508 BKills.push_back(ValNo->kills[j]);
510 ValNo->kills.clear();
511 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
513 if (AI->valno != AValNo) continue;
514 SlotIndex End = AI->end;
515 std::map<SlotIndex, SlotIndex>::iterator
516 EI = BExtend.find(End);
517 if (EI != BExtend.end())
519 IntB.addRange(LiveRange(AI->start, End, ValNo));
521 // If the IntB live range is assigned to a physical register, and if that
522 // physreg has sub-registers, update their live intervals as well.
524 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
525 LiveInterval &SRLI = li_->getInterval(*SR);
526 SRLI.MergeInClobberRange(*li_, AI->start, End,
527 li_->getVNInfoAllocator());
531 IntB.addKills(ValNo, BKills);
532 ValNo->setHasPHIKill(BHasPHIKill);
535 dbgs() << " result = ";
536 IntB.print(dbgs(), tri_);
537 dbgs() << "\nShortening: ";
538 IntA.print(dbgs(), tri_);
541 IntA.removeValNo(AValNo);
544 dbgs() << " result = ";
545 IntA.print(dbgs(), tri_);
553 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
554 /// fallthoughs to SuccMBB.
555 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
556 MachineBasicBlock *SuccMBB,
557 const TargetInstrInfo *tii_) {
560 MachineBasicBlock *TBB = 0, *FBB = 0;
561 SmallVector<MachineOperand, 4> Cond;
562 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
563 MBB->isSuccessor(SuccMBB);
566 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
567 /// from a physical register live interval as well as from the live intervals
568 /// of its sub-registers.
569 static void removeRange(LiveInterval &li,
570 SlotIndex Start, SlotIndex End,
571 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
572 li.removeRange(Start, End, true);
573 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
574 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
575 if (!li_->hasInterval(*SR))
577 LiveInterval &sli = li_->getInterval(*SR);
578 SlotIndex RemoveStart = Start;
579 SlotIndex RemoveEnd = Start;
581 while (RemoveEnd != End) {
582 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
585 RemoveEnd = (LR->end < End) ? LR->end : End;
586 sli.removeRange(RemoveStart, RemoveEnd, true);
587 RemoveStart = RemoveEnd;
593 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
594 /// as the copy instruction, trim the live interval to the last use and return
597 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
598 MachineBasicBlock *CopyMBB,
600 const LiveRange *LR) {
601 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
602 SlotIndex LastUseIdx;
603 MachineOperand *LastUse =
604 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
606 MachineInstr *LastUseMI = LastUse->getParent();
607 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
614 // r1025<dead> = r1024<kill>
615 if (MBBStart < LR->end)
616 removeRange(li, MBBStart, LR->end, li_, tri_);
620 // There are uses before the copy, just shorten the live range to the end
622 LastUse->setIsKill();
623 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
624 LR->valno->addKill(LastUseIdx.getDefIndex());
625 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
626 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
627 DstReg == li.reg && DstSubIdx == 0) {
628 // Last use is itself an identity code.
629 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
630 LastUseMI->getOperand(DeadIdx).setIsDead();
636 if (LR->start <= MBBStart && LR->end > MBBStart) {
637 if (LR->start == li_->getZeroIndex()) {
638 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
639 // Live-in to the function but dead. Remove it from entry live-in set.
640 mf_->begin()->removeLiveIn(li.reg);
642 // FIXME: Shorten intervals in BBs that reaches this BB.
648 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
649 /// computation, replace the copy by rematerialize the definition.
650 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
653 MachineInstr *CopyMI) {
654 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
655 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
656 assert(SrcLR != SrcInt.end() && "Live range not found!");
657 VNInfo *ValNo = SrcLR->valno;
658 // If other defs can reach uses of this def, then it's not safe to perform
659 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
661 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
662 ValNo->isUnused() || ValNo->hasPHIKill())
664 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
665 const TargetInstrDesc &TID = DefMI->getDesc();
666 if (!TID.isAsCheapAsAMove())
668 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
670 bool SawStore = false;
671 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
673 if (TID.getNumDefs() != 1)
675 if (!DefMI->isImplicitDef()) {
676 // Make sure the copy destination register class fits the instruction
677 // definition register class. The mismatch can happen as a result of earlier
678 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
679 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
680 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
681 if (mri_->getRegClass(DstReg) != RC)
683 } else if (!RC->contains(DstReg))
687 // If destination register has a sub-register index on it, make sure it mtches
688 // the instruction register class.
690 const TargetInstrDesc &TID = DefMI->getDesc();
691 if (TID.getNumDefs() != 1)
693 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
694 const TargetRegisterClass *DstSubRC =
695 DstRC->getSubRegisterRegClass(DstSubIdx);
696 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
699 else if (DefRC != DstSubRC)
703 SlotIndex DefIdx = CopyIdx.getDefIndex();
704 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
705 DLR->valno->setCopy(0);
706 // Don't forget to update sub-register intervals.
707 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
708 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
709 if (!li_->hasInterval(*SR))
711 const LiveRange *DLR =
712 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
713 if (DLR && DLR->valno->getCopy() == CopyMI)
714 DLR->valno->setCopy(0);
718 // If copy kills the source register, find the last use and propagate
720 bool checkForDeadDef = false;
721 MachineBasicBlock *MBB = CopyMI->getParent();
722 if (SrcLR->valno->isKill(DefIdx))
723 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
724 checkForDeadDef = true;
727 MachineBasicBlock::iterator MII =
728 llvm::next(MachineBasicBlock::iterator(CopyMI));
729 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
730 MachineInstr *NewMI = prior(MII);
732 if (checkForDeadDef) {
733 // PR4090 fix: Trim interval failed because there was no use of the
734 // source interval in this MBB. If the def is in this MBB too then we
735 // should mark it dead:
736 if (DefMI->getParent() == MBB) {
737 DefMI->addRegisterDead(SrcInt.reg, tri_);
738 SrcLR->end = SrcLR->start.getNextSlot();
742 // CopyMI may have implicit operands, transfer them over to the newly
743 // rematerialized instruction. And update implicit def interval valnos.
744 for (unsigned i = CopyMI->getDesc().getNumOperands(),
745 e = CopyMI->getNumOperands(); i != e; ++i) {
746 MachineOperand &MO = CopyMI->getOperand(i);
747 if (MO.isReg() && MO.isImplicit())
748 NewMI->addOperand(MO);
749 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
750 unsigned Reg = MO.getReg();
751 const LiveRange *DLR =
752 li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
753 if (DLR && DLR->valno->getCopy() == CopyMI)
754 DLR->valno->setCopy(0);
755 // Handle subregs as well
756 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
757 for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) {
758 if (!li_->hasInterval(*SR))
760 const LiveRange *DLR =
761 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
762 if (DLR && DLR->valno->getCopy() == CopyMI)
763 DLR->valno->setCopy(0);
769 TransferImplicitOps(CopyMI, NewMI);
770 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
771 CopyMI->eraseFromParent();
772 ReMatCopies.insert(CopyMI);
773 ReMatDefs.insert(DefMI);
774 DEBUG(dbgs() << "Remat: " << *NewMI);
779 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
780 /// update the subregister number if it is not zero. If DstReg is a
781 /// physical register and the existing subregister number of the def / use
782 /// being updated is not zero, make sure to set it to the correct physical
785 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
787 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
788 if (DstIsPhys && SubIdx) {
789 // Figure out the real physical register we are updating with.
790 DstReg = tri_->getSubReg(DstReg, SubIdx);
794 // Copy the register use-list before traversing it. We may be adding operands
795 // and invalidating pointers.
796 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
797 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
798 E = mri_->reg_end(); I != E; ++I)
799 reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
801 for (unsigned N=0; N != reglist.size(); ++N) {
802 MachineInstr *UseMI = reglist[N].first;
803 MachineOperand &O = UseMI->getOperand(reglist[N].second);
804 unsigned OldSubIdx = O.getSubReg();
806 unsigned UseDstReg = DstReg;
808 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
810 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
811 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
812 CopySrcSubIdx, CopyDstSubIdx) &&
813 CopySrcSubIdx == 0 &&
814 CopyDstSubIdx == 0 &&
815 CopySrcReg != CopyDstReg &&
816 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
817 // If the use is a copy and it won't be coalesced away, and its source
818 // is defined by a trivial computation, try to rematerialize it instead.
819 if (!JoinedCopies.count(UseMI) &&
820 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
821 CopyDstSubIdx, UseMI))
828 // Def and kill of subregister of a virtual register actually defs and
829 // kills the whole register. Add imp-defs and imp-kills as needed.
832 UseMI->addRegisterDead(DstReg, tri_, true);
834 UseMI->addRegisterDefined(DstReg, tri_);
835 } else if (!O.isUndef() &&
837 UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0))))
838 UseMI->addRegisterKilled(DstReg, tri_, true);
842 dbgs() << "\t\tupdated: ";
843 if (!UseMI->isDebugValue())
844 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
850 // Sub-register indexes goes from small to large. e.g.
851 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
852 // EAX: 1 -> AL, 2 -> AX
853 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
854 // sub-register 2 is also AX.
855 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
856 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
862 dbgs() << "\t\tupdated: ";
863 if (!UseMI->isDebugValue())
864 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
868 // After updating the operand, check if the machine instruction has
869 // become a copy. If so, update its val# information.
870 if (JoinedCopies.count(UseMI))
873 const TargetInstrDesc &TID = UseMI->getDesc();
874 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
875 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
876 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
877 CopySrcSubIdx, CopyDstSubIdx) &&
878 CopySrcReg != CopyDstReg &&
879 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
880 allocatableRegs_[CopyDstReg])) {
881 LiveInterval &LI = li_->getInterval(CopyDstReg);
883 li_->getInstructionIndex(UseMI).getDefIndex();
884 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
885 if (DLR->valno->def == DefIdx)
886 DLR->valno->setCopy(UseMI);
892 /// removeIntervalIfEmpty - Check if the live interval of a physical register
893 /// is empty, if so remove it and also remove the empty intervals of its
894 /// sub-registers. Return true if live interval is removed.
895 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
896 const TargetRegisterInfo *tri_) {
898 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
899 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
900 if (!li_->hasInterval(*SR))
902 LiveInterval &sli = li_->getInterval(*SR);
904 li_->removeInterval(*SR);
906 li_->removeInterval(li.reg);
912 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
913 /// Return true if live interval is removed.
914 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
915 MachineInstr *CopyMI) {
916 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
917 LiveInterval::iterator MLR =
918 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
920 return false; // Already removed by ShortenDeadCopySrcLiveRange.
921 SlotIndex RemoveStart = MLR->start;
922 SlotIndex RemoveEnd = MLR->end;
923 SlotIndex DefIdx = CopyIdx.getDefIndex();
924 // Remove the liverange that's defined by this.
925 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
926 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
927 return removeIntervalIfEmpty(li, li_, tri_);
932 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
933 /// the val# it defines. If the live interval becomes empty, remove it as well.
934 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
935 MachineInstr *DefMI) {
936 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
937 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
938 if (DefIdx != MLR->valno->def)
940 li.removeValNo(MLR->valno);
941 return removeIntervalIfEmpty(li, li_, tri_);
944 /// PropagateDeadness - Propagate the dead marker to the instruction which
945 /// defines the val#.
946 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
947 SlotIndex &LRStart, LiveIntervals *li_,
948 const TargetRegisterInfo* tri_) {
949 MachineInstr *DefMI =
950 li_->getInstructionFromIndex(LRStart.getDefIndex());
951 if (DefMI && DefMI != CopyMI) {
952 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false);
954 DefMI->getOperand(DeadIdx).setIsDead();
956 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
957 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
958 LRStart = LRStart.getNextSlot();
962 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
963 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
964 /// ends the live range there. If there isn't another use, then this live range
965 /// is dead. Return true if live interval is removed.
967 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
968 MachineInstr *CopyMI) {
969 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
970 if (CopyIdx == SlotIndex()) {
971 // FIXME: special case: function live in. It can be a general case if the
972 // first instruction index starts at > 0 value.
973 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
974 // Live-in to the function but dead. Remove it from entry live-in set.
975 if (mf_->begin()->isLiveIn(li.reg))
976 mf_->begin()->removeLiveIn(li.reg);
977 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
978 removeRange(li, LR->start, LR->end, li_, tri_);
979 return removeIntervalIfEmpty(li, li_, tri_);
982 LiveInterval::iterator LR =
983 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
985 // Livein but defined by a phi.
988 SlotIndex RemoveStart = LR->start;
989 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
990 if (LR->end > RemoveEnd)
991 // More uses past this copy? Nothing to do.
994 // If there is a last use in the same bb, we can't remove the live range.
995 // Shorten the live interval and return.
996 MachineBasicBlock *CopyMBB = CopyMI->getParent();
997 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
1000 // There are other kills of the val#. Nothing to do.
1001 if (!li.isOnlyLROfValNo(LR))
1004 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
1005 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
1006 // If the live range starts in another mbb and the copy mbb is not a fall
1007 // through mbb, then we can only cut the range from the beginning of the
1009 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
1011 if (LR->valno->def == RemoveStart) {
1012 // If the def MI defines the val# and this copy is the only kill of the
1013 // val#, then propagate the dead marker.
1014 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
1017 if (LR->valno->isKill(RemoveEnd))
1018 LR->valno->removeKill(RemoveEnd);
1021 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
1022 return removeIntervalIfEmpty(li, li_, tri_);
1025 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
1026 /// from an implicit def to another register can be coalesced away.
1027 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
1029 LiveInterval &ImpLi) const{
1030 if (!CopyMI->killsRegister(ImpLi.reg))
1032 // Make sure this is the only use.
1033 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
1034 UE = mri_->use_end(); UI != UE;) {
1035 MachineInstr *UseMI = &*UI;
1037 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
1045 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1046 /// a virtual destination register with physical source register.
1048 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1049 MachineBasicBlock *CopyMBB,
1050 LiveInterval &DstInt,
1051 LiveInterval &SrcInt) {
1052 // If the virtual register live interval is long but it has low use desity,
1053 // do not join them, instead mark the physical register as its allocation
1055 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1056 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1057 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1058 if (Length > Threshold &&
1059 std::distance(mri_->use_nodbg_begin(DstInt.reg),
1060 mri_->use_nodbg_end()) * Threshold < Length)
1063 // If the virtual register live interval extends into a loop, turn down
1066 li_->getInstructionIndex(CopyMI).getDefIndex();
1067 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1069 // Let's see if the virtual register live interval extends into the loop.
1070 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1071 assert(DLR != DstInt.end() && "Live range not found!");
1072 DLR = DstInt.FindLiveRangeContaining(DLR->end.getNextSlot());
1073 if (DLR != DstInt.end()) {
1074 CopyMBB = li_->getMBBFromIndex(DLR->start);
1075 L = loopInfo->getLoopFor(CopyMBB);
1079 if (!L || Length <= Threshold)
1082 SlotIndex UseIdx = CopyIdx.getUseIndex();
1083 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1084 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1085 if (loopInfo->getLoopFor(SMBB) != L) {
1086 if (!loopInfo->isLoopHeader(CopyMBB))
1088 // If vr's live interval extends pass the loop header, do not join.
1089 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1090 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1091 MachineBasicBlock *SuccMBB = *SI;
1092 if (SuccMBB == CopyMBB)
1094 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1095 li_->getMBBEndIdx(SuccMBB)))
1102 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1103 /// copy from a virtual source register to a physical destination register.
1105 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1106 MachineBasicBlock *CopyMBB,
1107 LiveInterval &DstInt,
1108 LiveInterval &SrcInt) {
1109 // If the virtual register live interval is long but it has low use density,
1110 // do not join them, instead mark the physical register as its allocation
1112 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1113 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1114 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1115 if (Length > Threshold &&
1116 std::distance(mri_->use_nodbg_begin(SrcInt.reg),
1117 mri_->use_nodbg_end()) * Threshold < Length)
1121 // Must be implicit_def.
1124 // If the virtual register live interval is defined or cross a loop, turn
1125 // down aggressiveness.
1127 li_->getInstructionIndex(CopyMI).getDefIndex();
1128 SlotIndex UseIdx = CopyIdx.getUseIndex();
1129 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1130 assert(SLR != SrcInt.end() && "Live range not found!");
1131 SLR = SrcInt.FindLiveRangeContaining(SLR->start.getPrevSlot());
1132 if (SLR == SrcInt.end())
1134 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1135 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1137 if (!L || Length <= Threshold)
1140 if (loopInfo->getLoopFor(CopyMBB) != L) {
1141 if (SMBB != L->getLoopLatch())
1143 // If vr's live interval is extended from before the loop latch, do not
1145 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1146 PE = SMBB->pred_end(); PI != PE; ++PI) {
1147 MachineBasicBlock *PredMBB = *PI;
1148 if (PredMBB == SMBB)
1150 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1151 li_->getMBBEndIdx(PredMBB)))
1158 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1159 /// two virtual registers from different register classes.
1161 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
1163 const TargetRegisterClass *SrcRC,
1164 const TargetRegisterClass *DstRC,
1165 const TargetRegisterClass *NewRC) {
1166 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
1167 // This heuristics is good enough in practice, but it's obviously not *right*.
1168 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1169 // out all but the most restrictive register classes.
1170 if (NewRCCount > 4 ||
1171 // Early exit if the function is fairly small, coalesce aggressively if
1172 // that's the case. For really special register classes with 3 or
1173 // fewer registers, be a bit more careful.
1174 (li_->getFuncInstructionCount() / NewRCCount) < 8)
1176 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1177 LiveInterval &DstInt = li_->getInterval(DstReg);
1178 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
1179 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
1180 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
1182 // Estimate *register use density*. If it doubles or more, abort.
1183 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
1184 mri_->use_nodbg_end());
1185 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
1186 mri_->use_nodbg_end());
1187 unsigned NewUses = SrcUses + DstUses;
1188 unsigned NewSize = SrcSize + DstSize;
1189 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1190 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1191 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1194 if (DstRC != NewRC && DstSize > NewRCCount) {
1195 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1196 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1202 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1203 /// register with a physical register, check if any of the virtual register
1204 /// operand is a sub-register use or def. If so, make sure it won't result
1205 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1206 /// vr1024 = extract_subreg vr1025, 1
1208 /// vr1024 = mov8rr AH
1209 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1210 /// AH does not have a super-reg whose sub-register 1 is AH.
1212 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1215 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1216 E = mri_->reg_end(); I != E; ++I) {
1217 MachineOperand &O = I.getOperand();
1220 MachineInstr *MI = &*I;
1221 if (MI == CopyMI || JoinedCopies.count(MI))
1223 unsigned SubIdx = O.getSubReg();
1224 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1226 if (MI->isExtractSubreg()) {
1227 SubIdx = MI->getOperand(2).getImm();
1228 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1231 unsigned SrcReg = MI->getOperand(1).getReg();
1232 const TargetRegisterClass *RC =
1233 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1234 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1235 : mri_->getRegClass(SrcReg);
1236 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1240 if (MI->isInsertSubreg() || MI->isSubregToReg()) {
1241 SubIdx = MI->getOperand(3).getImm();
1242 if (VirtReg == MI->getOperand(0).getReg()) {
1243 if (!tri_->getSubReg(PhysReg, SubIdx))
1246 unsigned DstReg = MI->getOperand(0).getReg();
1247 const TargetRegisterClass *RC =
1248 TargetRegisterInfo::isPhysicalRegister(DstReg)
1249 ? tri_->getPhysicalRegisterRegClass(DstReg)
1250 : mri_->getRegClass(DstReg);
1251 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1260 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1261 /// an extract_subreg where dst is a physical register, e.g.
1262 /// cl = EXTRACT_SUBREG reg1024, 1
1264 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1265 unsigned SrcReg, unsigned SubIdx,
1266 unsigned &RealDstReg) {
1267 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1268 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1270 DEBUG(dbgs() << "\tIncompatible source regclass: "
1271 << "none of the super-registers of " << tri_->getName(DstReg)
1272 << " are in " << RC->getName() << ".\n");
1276 LiveInterval &RHS = li_->getInterval(SrcReg);
1277 // For this type of EXTRACT_SUBREG, conservatively
1278 // check if the live interval of the source register interfere with the
1279 // actual super physical register we are trying to coalesce with.
1280 if (li_->hasInterval(RealDstReg) &&
1281 RHS.overlaps(li_->getInterval(RealDstReg))) {
1283 dbgs() << "\t\tInterfere with register ";
1284 li_->getInterval(RealDstReg).print(dbgs(), tri_);
1286 return false; // Not coalescable
1288 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1289 // Do not check DstReg or its sub-register. JoinIntervals() will take care
1291 if (*SR != DstReg &&
1292 !tri_->isSubRegister(DstReg, *SR) &&
1293 li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1295 dbgs() << "\t\tInterfere with sub-register ";
1296 li_->getInterval(*SR).print(dbgs(), tri_);
1298 return false; // Not coalescable
1303 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1304 /// an insert_subreg where src is a physical register, e.g.
1305 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1307 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1308 unsigned SrcReg, unsigned SubIdx,
1309 unsigned &RealSrcReg) {
1310 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1311 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1313 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1314 << "none of the super-registers of " << tri_->getName(SrcReg)
1315 << " are in " << RC->getName() << ".\n");
1319 LiveInterval &LHS = li_->getInterval(DstReg);
1320 if (li_->hasInterval(RealSrcReg) &&
1321 LHS.overlaps(li_->getInterval(RealSrcReg))) {
1323 dbgs() << "\t\tInterfere with register ";
1324 li_->getInterval(RealSrcReg).print(dbgs(), tri_);
1326 return false; // Not coalescable
1328 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1329 // Do not check SrcReg or its sub-register. JoinIntervals() will take care
1331 if (*SR != SrcReg &&
1332 !tri_->isSubRegister(SrcReg, *SR) &&
1333 li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1335 dbgs() << "\t\tInterfere with sub-register ";
1336 li_->getInterval(*SR).print(dbgs(), tri_);
1338 return false; // Not coalescable
1343 /// getRegAllocPreference - Return register allocation preference register.
1345 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1346 MachineRegisterInfo *MRI,
1347 const TargetRegisterInfo *TRI) {
1348 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1350 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1351 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1354 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1355 /// which are the src/dst of the copy instruction CopyMI. This returns true
1356 /// if the copy was successfully coalesced away. If it is not currently
1357 /// possible to coalesce this interval, but it may be possible if other
1358 /// things get coalesced, then it returns true by reference in 'Again'.
1359 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1360 MachineInstr *CopyMI = TheCopy.MI;
1363 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1364 return false; // Already done.
1366 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1368 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1369 bool isExtSubReg = CopyMI->isExtractSubreg();
1370 bool isInsSubReg = CopyMI->isInsertSubreg();
1371 bool isSubRegToReg = CopyMI->isSubregToReg();
1372 unsigned SubIdx = 0;
1374 DstReg = CopyMI->getOperand(0).getReg();
1375 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1376 SrcReg = CopyMI->getOperand(1).getReg();
1377 SrcSubIdx = CopyMI->getOperand(2).getImm();
1378 } else if (isInsSubReg || isSubRegToReg) {
1379 DstReg = CopyMI->getOperand(0).getReg();
1380 DstSubIdx = CopyMI->getOperand(3).getImm();
1381 SrcReg = CopyMI->getOperand(2).getReg();
1382 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1383 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1384 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1385 // coalesced to a larger register so the subreg indices cancel out.
1386 DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
1387 "coalesced to another register.\n");
1388 return false; // Not coalescable.
1390 } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1391 if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
1392 // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
1394 return false; // Not coalescable.
1397 llvm_unreachable("Unrecognized copy instruction!");
1400 // If they are already joined we continue.
1401 if (SrcReg == DstReg) {
1402 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1403 return false; // Not coalescable.
1406 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1407 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1409 // If they are both physical registers, we cannot join them.
1410 if (SrcIsPhys && DstIsPhys) {
1411 DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
1412 return false; // Not coalescable.
1415 // We only join virtual registers with allocatable physical registers.
1416 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1417 DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
1418 return false; // Not coalescable.
1420 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1421 DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
1422 return false; // Not coalescable.
1425 // We cannot handle dual subreg indices and mismatched classes at the same
1427 if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
1428 DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
1432 // Check that a physical source register is compatible with dst regclass
1434 unsigned SrcSubReg = SrcSubIdx ?
1435 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1436 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1437 const TargetRegisterClass *DstSubRC = DstRC;
1439 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1440 assert(DstSubRC && "Illegal subregister index");
1441 if (!DstSubRC->contains(SrcSubReg)) {
1442 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1443 << "none of the super-registers of "
1444 << tri_->getName(SrcSubReg) << " are in "
1445 << DstSubRC->getName() << ".\n");
1446 return false; // Not coalescable.
1450 // Check that a physical dst register is compatible with source regclass
1452 unsigned DstSubReg = DstSubIdx ?
1453 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1454 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1455 const TargetRegisterClass *SrcSubRC = SrcRC;
1457 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1458 assert(SrcSubRC && "Illegal subregister index");
1459 if (!SrcSubRC->contains(DstSubReg)) {
1460 DEBUG(dbgs() << "\tIncompatible source regclass: "
1461 << "none of the super-registers of "
1462 << tri_->getName(DstSubReg) << " are in "
1463 << SrcSubRC->getName() << ".\n");
1465 return false; // Not coalescable.
1469 // Should be non-null only when coalescing to a sub-register class.
1470 bool CrossRC = false;
1471 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1472 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1473 const TargetRegisterClass *NewRC = NULL;
1474 unsigned RealDstReg = 0;
1475 unsigned RealSrcReg = 0;
1476 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1477 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1478 if (SrcIsPhys && isExtSubReg) {
1479 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1480 // coalesced with AX.
1481 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1483 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1484 // coalesced to a larger register so the subreg indices cancel out.
1485 if (DstSubIdx != SubIdx) {
1486 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1487 return false; // Not coalescable.
1490 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1492 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1493 // EAX = INSERT_SUBREG EAX, r1024, 0
1494 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1496 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1497 // coalesced to a larger register so the subreg indices cancel out.
1498 if (SrcSubIdx != SubIdx) {
1499 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1500 return false; // Not coalescable.
1503 DstReg = tri_->getSubReg(DstReg, SubIdx);
1505 } else if ((DstIsPhys && isExtSubReg) ||
1506 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1507 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1508 DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
1509 << " of a super-class.\n");
1510 return false; // Not coalescable.
1513 // FIXME: The following checks are somewhat conservative. Perhaps a better
1514 // way to implement this is to treat this as coalescing a vr with the
1515 // super physical register.
1517 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1518 return false; // Not coalescable
1520 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1521 return false; // Not coalescable
1525 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1526 : CopyMI->getOperand(2).getSubReg();
1528 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1529 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1530 // coalesced to a larger register so the subreg indices cancel out.
1531 // Also check if the other larger register is of the same register
1532 // class as the would be resulting register.
1535 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1536 return false; // Not coalescable.
1540 if (!DstIsPhys && !SrcIsPhys) {
1541 if (isInsSubReg || isSubRegToReg) {
1542 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1543 } else // extract_subreg {
1544 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1547 DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
1548 return false; // Not coalescable
1551 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1552 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1553 << SrcRC->getName() << "/"
1554 << DstRC->getName() << " -> "
1555 << NewRC->getName() << ".\n");
1556 Again = true; // May be possible to coalesce later.
1561 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1562 if (DisableCrossClassJoin)
1566 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1567 // with another? If it's the resulting destination register, then
1568 // the subidx must be propagated to uses (but only those defined
1569 // by the EXTRACT_SUBREG). If it's being coalesced into another
1570 // register, it should be safe because register is assumed to have
1571 // the register class of the super-register.
1573 // Process moves where one of the registers have a sub-register index.
1574 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1575 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1576 SubIdx = DstMO->getSubReg();
1578 if (SrcMO->getSubReg())
1579 // FIXME: can we handle this?
1581 // This is not an insert_subreg but it looks like one.
1582 // e.g. %reg1024:4 = MOV32rr %EAX
1585 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1586 return false; // Not coalescable
1590 SubIdx = SrcMO->getSubReg();
1592 // This is not a extract_subreg but it looks like one.
1593 // e.g. %cl = MOV16rr %reg1024:1
1596 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1597 return false; // Not coalescable
1603 // Now determine the register class of the joined register.
1604 if (!SrcIsPhys && !DstIsPhys) {
1607 SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
1608 } else if (isInsSubReg) {
1610 SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
1612 NewRC = getCommonSubClass(SrcRC, DstRC);
1616 DEBUG(dbgs() << "\tDisjoint regclasses: "
1617 << SrcRC->getName() << ", "
1618 << DstRC->getName() << ".\n");
1619 return false; // Not coalescable.
1622 // If we are joining two virtual registers and the resulting register
1623 // class is more restrictive (fewer register, smaller size). Check if it's
1624 // worth doing the merge.
1625 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1626 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1627 << SrcRC->getName() << "/"
1628 << DstRC->getName() << " -> "
1629 << NewRC->getName() << ".\n");
1630 // Allow the coalescer to try again in case either side gets coalesced to
1631 // a physical register that's compatible with the other side. e.g.
1632 // r1024 = MOV32to32_ r1025
1633 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1634 Again = true; // May be possible to coalesce later.
1640 // Will it create illegal extract_subreg / insert_subreg?
1641 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1643 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1646 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1647 LiveInterval &DstInt = li_->getInterval(DstReg);
1648 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1649 "Register mapping is horribly broken!");
1652 dbgs() << "\t\tInspecting ";
1653 if (SrcRC) dbgs() << SrcRC->getName() << ": ";
1654 SrcInt.print(dbgs(), tri_);
1655 dbgs() << "\n\t\t and ";
1656 if (DstRC) dbgs() << DstRC->getName() << ": ";
1657 DstInt.print(dbgs(), tri_);
1661 // Save a copy of the virtual register live interval. We'll manually
1662 // merge this into the "real" physical register live interval this is
1664 OwningPtr<LiveInterval> SavedLI;
1666 SavedLI.reset(li_->dupInterval(&SrcInt));
1667 else if (RealSrcReg)
1668 SavedLI.reset(li_->dupInterval(&DstInt));
1670 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1671 // Check if it is necessary to propagate "isDead" property.
1672 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1673 bool isDead = mopd->isDead();
1675 // We need to be careful about coalescing a source physical register with a
1676 // virtual register. Once the coalescing is done, it cannot be broken and
1677 // these are not spillable! If the destination interval uses are far away,
1678 // think twice about coalescing them!
1679 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1680 // If the virtual register live interval is long but it has low use
1681 // density, do not join them, instead mark the physical register as its
1682 // allocation preference.
1683 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1684 LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
1685 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1686 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1688 // Don't join with physregs that have a ridiculous number of live
1689 // ranges. The data structure performance is really bad when that
1691 if (JoinPInt.ranges.size() > 1000) {
1692 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1695 << "\tPhysical register live interval too complicated, abort!\n");
1699 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1700 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1701 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1702 if (Length > Threshold &&
1703 std::distance(mri_->use_nodbg_begin(JoinVReg),
1704 mri_->use_nodbg_end()) * Threshold < Length) {
1705 // Before giving up coalescing, if definition of source is defined by
1706 // trivial computation, try rematerializing it.
1707 if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1710 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1712 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1713 Again = true; // May be possible to coalesce later.
1719 // Okay, attempt to join these two intervals. On failure, this returns false.
1720 // Otherwise, if one of the intervals being joined is a physreg, this method
1721 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1722 // been modified, so we can use this information below to update aliases.
1723 bool Swapped = false;
1724 // If SrcInt is implicitly defined, it's safe to coalesce.
1725 if (SrcInt.empty()) {
1726 if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1727 // Only coalesce an empty interval (defined by implicit_def) with
1728 // another interval which has a valno defined by the CopyMI and the CopyMI
1729 // is a kill of the implicit def.
1730 DEBUG(dbgs() << "\tNot profitable!\n");
1733 } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) {
1734 // Coalescing failed.
1736 // If definition of source is defined by trivial computation, try
1737 // rematerializing it.
1738 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1739 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1742 // If we can eliminate the copy without merging the live ranges, do so now.
1743 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1744 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1745 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1746 JoinedCopies.insert(CopyMI);
1747 DEBUG(dbgs() << "\tTrivial!\n");
1751 // Otherwise, we are unable to join the intervals.
1752 DEBUG(dbgs() << "\tInterference!\n");
1753 Again = true; // May be possible to coalesce later.
1757 LiveInterval *ResSrcInt = &SrcInt;
1758 LiveInterval *ResDstInt = &DstInt;
1760 std::swap(SrcReg, DstReg);
1761 std::swap(ResSrcInt, ResDstInt);
1763 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1764 "LiveInterval::join didn't work right!");
1766 // If we're about to merge live ranges into a physical register live interval,
1767 // we have to update any aliased register's live ranges to indicate that they
1768 // have clobbered values for this range.
1769 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1770 // If this is a extract_subreg where dst is a physical register, e.g.
1771 // cl = EXTRACT_SUBREG reg1024, 1
1772 // then create and update the actual physical register allocated to RHS.
1773 if (RealDstReg || RealSrcReg) {
1774 LiveInterval &RealInt =
1775 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1776 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1777 E = SavedLI->vni_end(); I != E; ++I) {
1778 const VNInfo *ValNo = *I;
1779 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
1780 false, // updated at *
1781 li_->getVNInfoAllocator());
1782 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1783 RealInt.addKills(NewValNo, ValNo->kills);
1784 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1786 RealInt.weight += SavedLI->weight;
1787 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1790 // Update the liveintervals of sub-registers.
1791 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1792 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
1793 li_->getVNInfoAllocator());
1796 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1797 // larger super-register.
1798 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1799 !SrcIsPhys && !DstIsPhys) {
1800 if ((isExtSubReg && !Swapped) ||
1801 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1802 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1803 std::swap(SrcReg, DstReg);
1804 std::swap(ResSrcInt, ResDstInt);
1808 // Coalescing to a virtual register that is of a sub-register class of the
1809 // other. Make sure the resulting register is set to the right register class.
1813 // This may happen even if it's cross-rc coalescing. e.g.
1814 // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
1815 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1816 // be allocate a register from GR64_ABCD.
1818 mri_->setRegClass(DstReg, NewRC);
1820 // Remember to delete the copy instruction.
1821 JoinedCopies.insert(CopyMI);
1823 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1825 // If we have extended the live range of a physical register, make sure we
1826 // update live-in lists as well.
1827 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1828 const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
1829 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1830 for (LiveInterval::const_iterator I = VRegInterval.begin(),
1831 E = VRegInterval.end(); I != E; ++I ) {
1832 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1833 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1834 MachineBasicBlock &block = *BlockSeq[idx];
1835 if (!block.isLiveIn(DstReg))
1836 block.addLiveIn(DstReg);
1842 // SrcReg is guarateed to be the register whose live interval that is
1844 li_->removeInterval(SrcReg);
1846 // Update regalloc hint.
1847 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1849 // Manually deleted the live interval copy.
1855 // If resulting interval has a preference that no longer fits because of subreg
1856 // coalescing, just clear the preference.
1857 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1858 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1859 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1860 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1861 if (!RC->contains(Preference))
1862 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1866 dbgs() << "\t\tJoined. Result = ";
1867 ResDstInt->print(dbgs(), tri_);
1875 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1876 /// compute what the resultant value numbers for each value in the input two
1877 /// ranges will be. This is complicated by copies between the two which can
1878 /// and will commonly cause multiple value numbers to be merged into one.
1880 /// VN is the value number that we're trying to resolve. InstDefiningValue
1881 /// keeps track of the new InstDefiningValue assignment for the result
1882 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1883 /// whether a value in this or other is a copy from the opposite set.
1884 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1885 /// already been assigned.
1887 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1888 /// contains the value number the copy is from.
1890 static unsigned ComputeUltimateVN(VNInfo *VNI,
1891 SmallVector<VNInfo*, 16> &NewVNInfo,
1892 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1893 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1894 SmallVector<int, 16> &ThisValNoAssignments,
1895 SmallVector<int, 16> &OtherValNoAssignments) {
1896 unsigned VN = VNI->id;
1898 // If the VN has already been computed, just return it.
1899 if (ThisValNoAssignments[VN] >= 0)
1900 return ThisValNoAssignments[VN];
1901 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1903 // If this val is not a copy from the other val, then it must be a new value
1904 // number in the destination.
1905 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1906 if (I == ThisFromOther.end()) {
1907 NewVNInfo.push_back(VNI);
1908 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1910 VNInfo *OtherValNo = I->second;
1912 // Otherwise, this *is* a copy from the RHS. If the other side has already
1913 // been computed, return it.
1914 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1915 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1917 // Mark this value number as currently being computed, then ask what the
1918 // ultimate value # of the other value is.
1919 ThisValNoAssignments[VN] = -2;
1920 unsigned UltimateVN =
1921 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1922 OtherValNoAssignments, ThisValNoAssignments);
1923 return ThisValNoAssignments[VN] = UltimateVN;
1926 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1927 return std::find(V.begin(), V.end(), Val) != V.end();
1930 static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
1931 const TargetInstrInfo *TII,
1932 const TargetRegisterInfo *TRI) {
1933 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1934 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1936 else if (MI->isExtractSubreg()) {
1937 DstReg = MI->getOperand(0).getReg();
1938 SrcReg = MI->getOperand(1).getReg();
1939 } else if (MI->isSubregToReg() ||
1940 MI->isInsertSubreg()) {
1941 DstReg = MI->getOperand(0).getReg();
1942 SrcReg = MI->getOperand(2).getReg();
1945 return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
1946 (DstReg == DR || TRI->isSuperRegister(DR, DstReg));
1949 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1950 /// the specified live interval is defined by a copy from the specified
1952 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1955 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1958 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1959 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1960 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1961 *tri_->getSuperRegisters(li.reg)) {
1962 // It's a sub-register live interval, we may not have precise information.
1964 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1965 if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
1966 // Cache computed info.
1967 LR->valno->def = LR->start;
1968 LR->valno->setCopy(DefMI);
1976 /// ValueLiveAt - Return true if the LiveRange pointed to by the given
1977 /// iterator, or any subsequent range with the same value number,
1978 /// is live at the given point.
1979 bool SimpleRegisterCoalescing::ValueLiveAt(LiveInterval::iterator LRItr,
1980 LiveInterval::iterator LREnd,
1981 SlotIndex defPoint) const {
1982 for (const VNInfo *valno = LRItr->valno;
1983 (LRItr != LREnd) && (LRItr->valno == valno); ++LRItr) {
1984 if (LRItr->contains(defPoint))
1992 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1993 /// caller of this method must guarantee that the RHS only contains a single
1994 /// value number and that the RHS is not defined by a copy from this
1995 /// interval. This returns false if the intervals are not joinable, or it
1996 /// joins them and returns true.
1997 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1998 assert(RHS.containsOneValue());
2000 // Some number (potentially more than one) value numbers in the current
2001 // interval may be defined as copies from the RHS. Scan the overlapping
2002 // portions of the LHS and RHS, keeping track of this and looking for
2003 // overlapping live ranges that are NOT defined as copies. If these exist, we
2006 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
2007 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
2009 if (LHSIt->start < RHSIt->start) {
2010 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
2011 if (LHSIt != LHS.begin()) --LHSIt;
2012 } else if (RHSIt->start < LHSIt->start) {
2013 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
2014 if (RHSIt != RHS.begin()) --RHSIt;
2017 SmallVector<VNInfo*, 8> EliminatedLHSVals;
2020 // Determine if these live intervals overlap.
2021 bool Overlaps = false;
2022 if (LHSIt->start <= RHSIt->start)
2023 Overlaps = LHSIt->end > RHSIt->start;
2025 Overlaps = RHSIt->end > LHSIt->start;
2027 // If the live intervals overlap, there are two interesting cases: if the
2028 // LHS interval is defined by a copy from the RHS, it's ok and we record
2029 // that the LHS value # is the same as the RHS. If it's not, then we cannot
2030 // coalesce these live ranges and we bail out.
2032 // If we haven't already recorded that this value # is safe, check it.
2033 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
2034 // If it's re-defined by an early clobber somewhere in the live range,
2035 // then conservatively abort coalescing.
2036 if (LHSIt->valno->hasRedefByEC())
2038 // Copy from the RHS?
2039 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
2040 return false; // Nope, bail out.
2042 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2043 // Here is an interesting situation:
2045 // vr1025 = copy vr1024
2050 // Even though vr1025 is copied from vr1024, it's not safe to
2051 // coalesce them since the live range of vr1025 intersects the
2052 // def of vr1024. This happens because vr1025 is assigned the
2053 // value of the previous iteration of vr1024.
2055 EliminatedLHSVals.push_back(LHSIt->valno);
2058 // We know this entire LHS live range is okay, so skip it now.
2059 if (++LHSIt == LHSEnd) break;
2063 if (LHSIt->end < RHSIt->end) {
2064 if (++LHSIt == LHSEnd) break;
2066 // One interesting case to check here. It's possible that we have
2067 // something like "X3 = Y" which defines a new value number in the LHS,
2068 // and is the last use of this liverange of the RHS. In this case, we
2069 // want to notice this copy (so that it gets coalesced away) even though
2070 // the live ranges don't actually overlap.
2071 if (LHSIt->start == RHSIt->end) {
2072 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2073 // We already know that this value number is going to be merged in
2074 // if coalescing succeeds. Just skip the liverange.
2075 if (++LHSIt == LHSEnd) break;
2077 // If it's re-defined by an early clobber somewhere in the live range,
2078 // then conservatively abort coalescing.
2079 if (LHSIt->valno->hasRedefByEC())
2081 // Otherwise, if this is a copy from the RHS, mark it as being merged
2083 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2084 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2085 // Here is an interesting situation:
2087 // vr1025 = copy vr1024
2092 // Even though vr1025 is copied from vr1024, it's not safe to
2093 // coalesced them since live range of vr1025 intersects the
2094 // def of vr1024. This happens because vr1025 is assigned the
2095 // value of the previous iteration of vr1024.
2097 EliminatedLHSVals.push_back(LHSIt->valno);
2099 // We know this entire LHS live range is okay, so skip it now.
2100 if (++LHSIt == LHSEnd) break;
2105 if (++RHSIt == RHSEnd) break;
2109 // If we got here, we know that the coalescing will be successful and that
2110 // the value numbers in EliminatedLHSVals will all be merged together. Since
2111 // the most common case is that EliminatedLHSVals has a single number, we
2112 // optimize for it: if there is more than one value, we merge them all into
2113 // the lowest numbered one, then handle the interval as if we were merging
2114 // with one value number.
2115 VNInfo *LHSValNo = NULL;
2116 if (EliminatedLHSVals.size() > 1) {
2117 // Loop through all the equal value numbers merging them into the smallest
2119 VNInfo *Smallest = EliminatedLHSVals[0];
2120 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2121 if (EliminatedLHSVals[i]->id < Smallest->id) {
2122 // Merge the current notion of the smallest into the smaller one.
2123 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2124 Smallest = EliminatedLHSVals[i];
2126 // Merge into the smallest.
2127 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2130 LHSValNo = Smallest;
2131 } else if (EliminatedLHSVals.empty()) {
2132 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2133 *tri_->getSuperRegisters(LHS.reg))
2134 // Imprecise sub-register information. Can't handle it.
2136 llvm_unreachable("No copies from the RHS?");
2138 LHSValNo = EliminatedLHSVals[0];
2141 // Okay, now that there is a single LHS value number that we're merging the
2142 // RHS into, update the value number info for the LHS to indicate that the
2143 // value number is defined where the RHS value number was.
2144 const VNInfo *VNI = RHS.getValNumInfo(0);
2145 LHSValNo->def = VNI->def;
2146 LHSValNo->setCopy(VNI->getCopy());
2148 // Okay, the final step is to loop over the RHS live intervals, adding them to
2150 if (VNI->hasPHIKill())
2151 LHSValNo->setHasPHIKill(true);
2152 LHS.addKills(LHSValNo, VNI->kills);
2153 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2155 LHS.ComputeJoinedWeight(RHS);
2157 // Update regalloc hint if both are virtual registers.
2158 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2159 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2160 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2161 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2162 if (RHSPref != LHSPref)
2163 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2166 // Update the liveintervals of sub-registers.
2167 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2168 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2169 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, LHS,
2170 li_->getVNInfoAllocator());
2175 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2176 /// returns false. Otherwise, if one of the intervals being joined is a
2177 /// physreg, this method always canonicalizes LHS to be it. The output
2178 /// "RHS" will not have been modified, so we can use this information
2179 /// below to update aliases.
2181 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2183 // Compute the final value assignment, assuming that the live ranges can be
2185 SmallVector<int, 16> LHSValNoAssignments;
2186 SmallVector<int, 16> RHSValNoAssignments;
2187 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2188 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2189 SmallVector<VNInfo*, 16> NewVNInfo;
2191 // If a live interval is a physical register, conservatively check if any
2192 // of its sub-registers is overlapping the live interval of the virtual
2193 // register. If so, do not coalesce.
2194 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2195 *tri_->getSubRegisters(LHS.reg)) {
2196 // If it's coalescing a virtual register to a physical register, estimate
2197 // its live interval length. This is the *cost* of scanning an entire live
2198 // interval. If the cost is low, we'll do an exhaustive check instead.
2200 // If this is something like this:
2208 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2209 // less conservative check. It's possible a sub-register is defined before
2210 // v1024 (or live in) and live out of BB1.
2211 if (RHS.containsOneValue() &&
2212 li_->intervalIsInOneMBB(RHS) &&
2213 li_->getApproximateInstructionCount(RHS) <= 10) {
2214 // Perform a more exhaustive check for some common cases.
2215 if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2218 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2219 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2221 dbgs() << "\tInterfere with sub-register ";
2222 li_->getInterval(*SR).print(dbgs(), tri_);
2227 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2228 *tri_->getSubRegisters(RHS.reg)) {
2229 if (LHS.containsOneValue() &&
2230 li_->getApproximateInstructionCount(LHS) <= 10) {
2231 // Perform a more exhaustive check for some common cases.
2232 if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2235 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2236 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2238 dbgs() << "\tInterfere with sub-register ";
2239 li_->getInterval(*SR).print(dbgs(), tri_);
2246 // Compute ultimate value numbers for the LHS and RHS values.
2247 if (RHS.containsOneValue()) {
2248 // Copies from a liveinterval with a single value are simple to handle and
2249 // very common, handle the special case here. This is important, because
2250 // often RHS is small and LHS is large (e.g. a physreg).
2252 // Find out if the RHS is defined as a copy from some value in the LHS.
2253 int RHSVal0DefinedFromLHS = -1;
2255 VNInfo *RHSValNoInfo = NULL;
2256 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2257 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2258 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2259 // If RHS is not defined as a copy from the LHS, we can use simpler and
2260 // faster checks to see if the live ranges are coalescable. This joiner
2261 // can't swap the LHS/RHS intervals though.
2262 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2263 return SimpleJoin(LHS, RHS);
2265 RHSValNoInfo = RHSValNoInfo0;
2268 // It was defined as a copy from the LHS, find out what value # it is.
2270 LHS.getLiveRangeContaining(RHSValNoInfo0->def.getPrevSlot())->valno;
2271 RHSValID = RHSValNoInfo->id;
2272 RHSVal0DefinedFromLHS = RHSValID;
2275 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2276 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2277 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2279 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2280 // should now get updated.
2281 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2284 unsigned VN = VNI->id;
2285 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2286 if (LHSSrcReg != RHS.reg) {
2287 // If this is not a copy from the RHS, its value number will be
2288 // unmodified by the coalescing.
2289 NewVNInfo[VN] = VNI;
2290 LHSValNoAssignments[VN] = VN;
2291 } else if (RHSValID == -1) {
2292 // Otherwise, it is a copy from the RHS, and we don't already have a
2293 // value# for it. Keep the current value number, but remember it.
2294 LHSValNoAssignments[VN] = RHSValID = VN;
2295 NewVNInfo[VN] = RHSValNoInfo;
2296 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2298 // Otherwise, use the specified value #.
2299 LHSValNoAssignments[VN] = RHSValID;
2300 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2301 NewVNInfo[VN] = RHSValNoInfo;
2302 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2306 NewVNInfo[VN] = VNI;
2307 LHSValNoAssignments[VN] = VN;
2311 assert(RHSValID != -1 && "Didn't find value #?");
2312 RHSValNoAssignments[0] = RHSValID;
2313 if (RHSVal0DefinedFromLHS != -1) {
2314 // This path doesn't go through ComputeUltimateVN so just set
2316 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2319 // Loop over the value numbers of the LHS, seeing if any are defined from
2321 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2324 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2327 // DstReg is known to be a register in the LHS interval. If the src is
2328 // from the RHS interval, we can use its value #.
2329 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2332 // Figure out the value # from the RHS.
2333 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2334 assert(lr && "Cannot find live range");
2335 LHSValsDefinedFromRHS[VNI] = lr->valno;
2338 // Loop over the value numbers of the RHS, seeing if any are defined from
2340 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2343 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2346 // DstReg is known to be a register in the RHS interval. If the src is
2347 // from the LHS interval, we can use its value #.
2348 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2351 // Figure out the value # from the LHS.
2352 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2353 assert(lr && "Cannot find live range");
2354 RHSValsDefinedFromLHS[VNI] = lr->valno;
2357 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2358 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2359 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2361 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2364 unsigned VN = VNI->id;
2365 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2367 ComputeUltimateVN(VNI, NewVNInfo,
2368 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2369 LHSValNoAssignments, RHSValNoAssignments);
2371 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2374 unsigned VN = VNI->id;
2375 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2377 // If this value number isn't a copy from the LHS, it's a new number.
2378 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2379 NewVNInfo.push_back(VNI);
2380 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2384 ComputeUltimateVN(VNI, NewVNInfo,
2385 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2386 RHSValNoAssignments, LHSValNoAssignments);
2390 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2391 // interval lists to see if these intervals are coalescable.
2392 LiveInterval::const_iterator I = LHS.begin();
2393 LiveInterval::const_iterator IE = LHS.end();
2394 LiveInterval::const_iterator J = RHS.begin();
2395 LiveInterval::const_iterator JE = RHS.end();
2397 // Skip ahead until the first place of potential sharing.
2398 if (I->start < J->start) {
2399 I = std::upper_bound(I, IE, J->start);
2400 if (I != LHS.begin()) --I;
2401 } else if (J->start < I->start) {
2402 J = std::upper_bound(J, JE, I->start);
2403 if (J != RHS.begin()) --J;
2407 // Determine if these two live ranges overlap.
2409 if (I->start < J->start) {
2410 Overlaps = I->end > J->start;
2412 Overlaps = J->end > I->start;
2415 // If so, check value # info to determine if they are really different.
2417 // If the live range overlap will map to the same value number in the
2418 // result liverange, we can still coalesce them. If not, we can't.
2419 if (LHSValNoAssignments[I->valno->id] !=
2420 RHSValNoAssignments[J->valno->id])
2422 // If it's re-defined by an early clobber somewhere in the live range,
2423 // then conservatively abort coalescing.
2424 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
2428 if (I->end < J->end) {
2437 // Update kill info. Some live ranges are extended due to copy coalescing.
2438 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2439 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2440 VNInfo *VNI = I->first;
2441 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2442 NewVNInfo[LHSValID]->removeKill(VNI->def);
2443 if (VNI->hasPHIKill())
2444 NewVNInfo[LHSValID]->setHasPHIKill(true);
2445 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2448 // Update kill info. Some live ranges are extended due to copy coalescing.
2449 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2450 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2451 VNInfo *VNI = I->first;
2452 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2453 NewVNInfo[RHSValID]->removeKill(VNI->def);
2454 if (VNI->hasPHIKill())
2455 NewVNInfo[RHSValID]->setHasPHIKill(true);
2456 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2459 // If we get here, we know that we can coalesce the live ranges. Ask the
2460 // intervals to coalesce themselves now.
2461 if ((RHS.ranges.size() > LHS.ranges.size() &&
2462 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2463 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2464 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2468 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2476 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2477 // depth of the basic block (the unsigned), and then on the MBB number.
2478 struct DepthMBBCompare {
2479 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2480 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2481 // Deeper loops first
2482 if (LHS.first != RHS.first)
2483 return LHS.first > RHS.first;
2485 // Prefer blocks that are more connected in the CFG. This takes care of
2486 // the most difficult copies first while intervals are short.
2487 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
2488 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
2492 // As a last resort, sort by block number.
2493 return LHS.second->getNumber() < RHS.second->getNumber();
2498 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2499 std::vector<CopyRec> &TryAgain) {
2500 DEBUG(dbgs() << MBB->getName() << ":\n");
2502 std::vector<CopyRec> VirtCopies;
2503 std::vector<CopyRec> PhysCopies;
2504 std::vector<CopyRec> ImpDefCopies;
2505 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2507 MachineInstr *Inst = MII++;
2509 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2510 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2511 bool isInsUndef = false;
2512 if (Inst->isExtractSubreg()) {
2513 DstReg = Inst->getOperand(0).getReg();
2514 SrcReg = Inst->getOperand(1).getReg();
2515 } else if (Inst->isInsertSubreg()) {
2516 DstReg = Inst->getOperand(0).getReg();
2517 SrcReg = Inst->getOperand(2).getReg();
2518 if (Inst->getOperand(1).isUndef())
2520 } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
2521 DstReg = Inst->getOperand(0).getReg();
2522 SrcReg = Inst->getOperand(2).getReg();
2523 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2526 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2527 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2529 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
2530 ImpDefCopies.push_back(CopyRec(Inst, 0));
2531 else if (SrcIsPhys || DstIsPhys)
2532 PhysCopies.push_back(CopyRec(Inst, 0));
2534 VirtCopies.push_back(CopyRec(Inst, 0));
2537 // Try coalescing implicit copies and insert_subreg <undef> first,
2538 // followed by copies to / from physical registers, then finally copies
2539 // from virtual registers to virtual registers.
2540 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2541 CopyRec &TheCopy = ImpDefCopies[i];
2543 if (!JoinCopy(TheCopy, Again))
2545 TryAgain.push_back(TheCopy);
2547 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2548 CopyRec &TheCopy = PhysCopies[i];
2550 if (!JoinCopy(TheCopy, Again))
2552 TryAgain.push_back(TheCopy);
2554 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2555 CopyRec &TheCopy = VirtCopies[i];
2557 if (!JoinCopy(TheCopy, Again))
2559 TryAgain.push_back(TheCopy);
2563 void SimpleRegisterCoalescing::joinIntervals() {
2564 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2566 std::vector<CopyRec> TryAgainList;
2567 if (loopInfo->empty()) {
2568 // If there are no loops in the function, join intervals in function order.
2569 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2571 CopyCoalesceInMBB(I, TryAgainList);
2573 // Otherwise, join intervals in inner loops before other intervals.
2574 // Unfortunately we can't just iterate over loop hierarchy here because
2575 // there may be more MBB's than BB's. Collect MBB's for sorting.
2577 // Join intervals in the function prolog first. We want to join physical
2578 // registers with virtual registers before the intervals got too long.
2579 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2580 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2581 MachineBasicBlock *MBB = I;
2582 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2585 // Sort by loop depth.
2586 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2588 // Finally, join intervals in loop nest order.
2589 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2590 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2593 // Joining intervals can allow other intervals to be joined. Iteratively join
2594 // until we make no progress.
2595 bool ProgressMade = true;
2596 while (ProgressMade) {
2597 ProgressMade = false;
2599 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2600 CopyRec &TheCopy = TryAgainList[i];
2605 bool Success = JoinCopy(TheCopy, Again);
2606 if (Success || !Again) {
2607 TheCopy.MI = 0; // Mark this one as done.
2608 ProgressMade = true;
2614 /// Return true if the two specified registers belong to different register
2615 /// classes. The registers may be either phys or virt regs.
2617 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2618 unsigned RegB) const {
2619 // Get the register classes for the first reg.
2620 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2621 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2622 "Shouldn't consider two physregs!");
2623 return !mri_->getRegClass(RegB)->contains(RegA);
2626 // Compare against the regclass for the second reg.
2627 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2628 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2629 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2630 return RegClassA != RegClassB;
2632 return !RegClassA->contains(RegB);
2635 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
2636 /// between cycles Start and End or NULL if there are no uses.
2638 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
2641 SlotIndex &UseIdx) const{
2642 UseIdx = SlotIndex();
2643 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2644 MachineOperand *LastUse = NULL;
2645 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
2646 E = mri_->use_nodbg_end(); I != E; ++I) {
2647 MachineOperand &Use = I.getOperand();
2648 MachineInstr *UseMI = Use.getParent();
2649 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2650 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2651 SrcReg == DstReg && SrcSubIdx == DstSubIdx)
2652 // Ignore identity copies.
2654 SlotIndex Idx = li_->getInstructionIndex(UseMI);
2655 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
2656 // that compares higher than any other interval.
2657 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2659 UseIdx = Idx.getUseIndex();
2665 SlotIndex s = Start;
2666 SlotIndex e = End.getPrevSlot().getBaseIndex();
2668 // Skip deleted instructions
2669 MachineInstr *MI = li_->getInstructionFromIndex(e);
2670 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
2671 e = e.getPrevIndex();
2672 MI = li_->getInstructionFromIndex(e);
2674 if (e < s || MI == NULL)
2677 // Ignore identity copies.
2678 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2679 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2680 SrcReg == DstReg && SrcSubIdx == DstSubIdx))
2681 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2682 MachineOperand &Use = MI->getOperand(i);
2683 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2684 tri_->regsOverlap(Use.getReg(), Reg)) {
2685 UseIdx = e.getUseIndex();
2690 e = e.getPrevIndex();
2696 void SimpleRegisterCoalescing::releaseMemory() {
2697 JoinedCopies.clear();
2698 ReMatCopies.clear();
2702 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2704 mri_ = &fn.getRegInfo();
2705 tm_ = &fn.getTarget();
2706 tri_ = tm_->getRegisterInfo();
2707 tii_ = tm_->getInstrInfo();
2708 li_ = &getAnalysis<LiveIntervals>();
2709 AA = &getAnalysis<AliasAnalysis>();
2710 loopInfo = &getAnalysis<MachineLoopInfo>();
2712 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2713 << "********** Function: "
2714 << ((Value*)mf_->getFunction())->getName() << '\n');
2716 allocatableRegs_ = tri_->getAllocatableSet(fn);
2717 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2718 E = tri_->regclass_end(); I != E; ++I)
2719 allocatableRCRegs_.insert(std::make_pair(*I,
2720 tri_->getAllocatableSet(fn, *I)));
2722 // Join (coalesce) intervals if requested.
2723 if (EnableJoining) {
2726 dbgs() << "********** INTERVALS POST JOINING **********\n";
2727 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
2729 I->second->print(dbgs(), tri_);
2735 // Perform a final pass over the instructions and compute spill weights
2736 // and remove identity moves.
2737 SmallVector<unsigned, 4> DeadDefs;
2738 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2739 mbbi != mbbe; ++mbbi) {
2740 MachineBasicBlock* mbb = mbbi;
2741 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2743 MachineInstr *MI = mii;
2744 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2745 if (JoinedCopies.count(MI)) {
2746 // Delete all coalesced copies.
2747 bool DoDelete = true;
2748 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2749 assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
2750 MI->isSubregToReg()) && "Unrecognized copy instruction");
2751 DstReg = MI->getOperand(0).getReg();
2752 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2753 // Do not delete extract_subreg, insert_subreg of physical
2754 // registers unless the definition is dead. e.g.
2755 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
2756 // or else the scavenger may complain. LowerSubregs will
2757 // delete them later.
2760 if (MI->allDefsAreDead()) {
2761 LiveInterval &li = li_->getInterval(DstReg);
2762 if (!ShortenDeadCopySrcLiveRange(li, MI))
2763 ShortenDeadCopyLiveRange(li, MI);
2767 mii = llvm::next(mii);
2769 li_->RemoveMachineInstrFromMaps(MI);
2770 mii = mbbi->erase(mii);
2776 // Now check if this is a remat'ed def instruction which is now dead.
2777 if (ReMatDefs.count(MI)) {
2779 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2780 const MachineOperand &MO = MI->getOperand(i);
2783 unsigned Reg = MO.getReg();
2786 if (TargetRegisterInfo::isVirtualRegister(Reg))
2787 DeadDefs.push_back(Reg);
2790 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2791 !mri_->use_nodbg_empty(Reg)) {
2797 while (!DeadDefs.empty()) {
2798 unsigned DeadDef = DeadDefs.back();
2799 DeadDefs.pop_back();
2800 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2802 li_->RemoveMachineInstrFromMaps(mii);
2803 mii = mbbi->erase(mii);
2809 // If the move will be an identity move delete it
2810 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2811 if (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx) {
2812 if (li_->hasInterval(SrcReg)) {
2813 LiveInterval &RegInt = li_->getInterval(SrcReg);
2814 // If def of this move instruction is dead, remove its live range
2815 // from the dstination register's live interval.
2816 if (MI->registerDefIsDead(DstReg)) {
2817 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2818 ShortenDeadCopyLiveRange(RegInt, MI);
2821 li_->RemoveMachineInstrFromMaps(MI);
2822 mii = mbbi->erase(mii);
2829 // Check for now unnecessary kill flags.
2830 if (li_->isNotInMIMap(MI)) continue;
2831 SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex();
2832 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2833 MachineOperand &MO = MI->getOperand(i);
2834 if (!MO.isReg() || !MO.isKill()) continue;
2835 unsigned reg = MO.getReg();
2836 if (!reg || !li_->hasInterval(reg)) continue;
2837 LiveInterval &LI = li_->getInterval(reg);
2838 const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
2840 (!LR->valno->isKill(UseIdx.getDefIndex()) &&
2841 LR->valno->def != UseIdx.getDefIndex()))
2842 MO.setIsKill(false);
2851 /// print - Implement the dump method.
2852 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
2856 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2857 return new SimpleRegisterCoalescing();
2860 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2861 DEFINING_FILE_FOR(SimpleRegisterCoalescing)