1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
46 EnableJoining("join-liveintervals",
47 cl::desc("Coalesce copies (default=true)"),
51 NewHeuristic("new-coalescer-heuristic",
52 cl::desc("Use new coalescer heuristic"),
56 ReMatSpillWeight("tweak-remat-spill-weight",
57 cl::desc("Tweak spill weight of re-materializable intervals"),
60 RegisterPass<SimpleRegisterCoalescing>
61 X("simple-register-coalescing", "Simple Register Coalescing");
63 // Declare that we implement the RegisterCoalescer interface
64 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
67 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
69 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addPreserved<LiveIntervals>();
71 AU.addPreservedID(PHIEliminationID);
72 AU.addPreservedID(TwoAddressInstructionPassID);
73 AU.addRequired<LiveVariables>();
74 AU.addRequired<LiveIntervals>();
75 AU.addRequired<MachineLoopInfo>();
76 MachineFunctionPass::getAnalysisUsage(AU);
79 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
80 /// being the source and IntB being the dest, thus this defines a value number
81 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
82 /// see if we can merge these two pieces of B into a single value number,
83 /// eliminating a copy. For example:
87 /// B1 = A3 <- this copy
89 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
90 /// value number to be replaced with B0 (which simplifies the B liveinterval).
92 /// This returns true if an interval was modified.
94 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
95 MachineInstr *CopyMI) {
96 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
98 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
100 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
101 VNInfo *BValNo = BLR->valno;
103 // Get the location that B is defined at. Two options: either this value has
104 // an unknown definition point or it is defined at CopyIdx. If unknown, we
106 if (!BValNo->reg) return false;
107 assert(BValNo->def == CopyIdx &&
108 "Copy doesn't define the value?");
110 // AValNo is the value number in A that defines the copy, A0 in the example.
111 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
112 VNInfo *AValNo = AValLR->valno;
114 // If AValNo is defined as a copy from IntB, we can potentially process this.
116 // Get the instruction that defines this value number.
117 unsigned SrcReg = AValNo->reg;
118 if (!SrcReg) return false; // Not defined by a copy.
120 // If the value number is not defined by a copy instruction, ignore it.
122 // If the source register comes from an interval other than IntB, we can't
124 if (rep(SrcReg) != IntB.reg) return false;
126 // Get the LiveRange in IntB that this value number starts with.
127 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
129 // Make sure that the end of the live range is inside the same block as
131 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
133 ValLREndInst->getParent() != CopyMI->getParent()) return false;
135 // Okay, we now know that ValLR ends in the same block that the CopyMI
136 // live-range starts. If there are no intervening live ranges between them in
137 // IntB, we can merge them.
138 if (ValLR+1 != BLR) return false;
140 // If a live interval is a physical register, conservatively check if any
141 // of its sub-registers is overlapping the live interval of the virtual
142 // register. If so, do not coalesce.
143 if (MRegisterInfo::isPhysicalRegister(IntB.reg) &&
144 *mri_->getSubRegisters(IntB.reg)) {
145 for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR)
146 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
147 DOUT << "Interfere with sub-register ";
148 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
153 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
155 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
156 // We are about to delete CopyMI, so need to remove it as the 'instruction
157 // that defines this value #'. Update the the valnum with the new defining
159 BValNo->def = FillerStart;
162 // Okay, we can merge them. We need to insert a new liverange:
163 // [ValLR.end, BLR.begin) of either value number, then we merge the
164 // two value numbers.
165 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
167 // If the IntB live range is assigned to a physical register, and if that
168 // physreg has aliases,
169 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
170 // Update the liveintervals of sub-registers.
171 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
172 LiveInterval &AliasLI = li_->getInterval(*AS);
173 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
174 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
178 // Okay, merge "B1" into the same value number as "B0".
179 if (BValNo != ValLR->valno)
180 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
181 DOUT << " result = "; IntB.print(DOUT, mri_);
184 // If the source instruction was killing the source register before the
185 // merge, unset the isKill marker given the live range has been extended.
186 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
188 ValLREndInst->getOperand(UIdx).unsetIsKill();
194 /// AddSubRegIdxPairs - Recursively mark all the registers represented by the
195 /// specified register as sub-registers. The recursion level is expected to be
197 void SimpleRegisterCoalescing::AddSubRegIdxPairs(unsigned Reg, unsigned SubIdx) {
198 std::vector<unsigned> &JoinedRegs = r2rRevMap_[Reg];
199 for (unsigned i = 0, e = JoinedRegs.size(); i != e; ++i) {
200 SubRegIdxes.push_back(std::make_pair(JoinedRegs[i], SubIdx));
201 AddSubRegIdxPairs(JoinedRegs[i], SubIdx);
205 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
207 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
209 MachineBasicBlock *MBB = CopyMI->getParent();
210 const MachineLoop *L = loopInfo->getLoopFor(MBB);
213 if (MBB != L->getLoopLatch())
216 DstReg = rep(DstReg);
217 LiveInterval &LI = li_->getInterval(DstReg);
218 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
219 LiveInterval::const_iterator DstLR =
220 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
221 if (DstLR == LI.end())
223 unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM-1;
224 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0] == KillIdx)
229 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
230 /// which are the src/dst of the copy instruction CopyMI. This returns true
231 /// if the copy was successfully coalesced away. If it is not currently
232 /// possible to coalesce this interval, but it may be possible if other
233 /// things get coalesced, then it returns true by reference in 'Again'.
234 bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
235 MachineInstr *CopyMI = TheCopy.MI;
238 if (JoinedCopies.count(CopyMI))
239 return false; // Already done.
241 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
243 // Get representative registers.
244 unsigned SrcReg = TheCopy.SrcReg;
245 unsigned DstReg = TheCopy.DstReg;
246 unsigned repSrcReg = rep(SrcReg);
247 unsigned repDstReg = rep(DstReg);
249 // If they are already joined we continue.
250 if (repSrcReg == repDstReg) {
251 DOUT << "\tCopy already coalesced.\n";
252 return false; // Not coalescable.
255 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
256 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
258 // If they are both physical registers, we cannot join them.
259 if (SrcIsPhys && DstIsPhys) {
260 DOUT << "\tCan not coalesce physregs.\n";
261 return false; // Not coalescable.
264 // We only join virtual registers with allocatable physical registers.
265 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
266 DOUT << "\tSrc reg is unallocatable physreg.\n";
267 return false; // Not coalescable.
269 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
270 DOUT << "\tDst reg is unallocatable physreg.\n";
271 return false; // Not coalescable.
274 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
275 unsigned RealDstReg = 0;
277 unsigned SubIdx = CopyMI->getOperand(2).getImm();
279 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
280 // coalesced with AX.
281 repSrcReg = mri_->getSubReg(repSrcReg, SubIdx);
282 else if (DstIsPhys) {
283 // If this is a extract_subreg where dst is a physical register, e.g.
284 // cl = EXTRACT_SUBREG reg1024, 1
285 // then create and update the actual physical register allocated to RHS.
286 const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repSrcReg);
287 for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
288 unsigned SR = *SRs; ++SRs) {
289 if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
295 assert(RealDstReg && "Invalid extra_subreg instruction!");
297 // For this type of EXTRACT_SUBREG, conservatively
298 // check if the live interval of the source register interfere with the
299 // actual super physical register we are trying to coalesce with.
300 LiveInterval &RHS = li_->getInterval(repSrcReg);
301 if (li_->hasInterval(RealDstReg) &&
302 RHS.overlaps(li_->getInterval(RealDstReg))) {
303 DOUT << "Interfere with register ";
304 DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_));
305 return false; // Not coalescable
307 for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR)
308 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
309 DOUT << "Interfere with sub-register ";
310 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
311 return false; // Not coalescable
314 unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM;
315 unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM;
316 const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repDstReg);
317 unsigned Threshold = allocatableRCRegs_[RC].count();
318 // Be conservative. If both sides are virtual registers, do not coalesce
319 // if this will cause a high use density interval to target a smaller set
321 if (DstSize > Threshold || SrcSize > Threshold) {
322 LiveVariables::VarInfo &svi = lv_->getVarInfo(repSrcReg);
323 LiveVariables::VarInfo &dvi = lv_->getVarInfo(repDstReg);
324 if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) {
325 Again = true; // May be possible to coalesce later.
330 } else if (differingRegisterClasses(repSrcReg, repDstReg)) {
331 // If they are not of the same register class, we cannot join them.
332 DOUT << "\tSrc/Dest are different register classes.\n";
333 // Allow the coalescer to try again in case either side gets coalesced to
334 // a physical register that's compatible with the other side. e.g.
335 // r1024 = MOV32to32_ r1025
336 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
337 Again = true; // May be possible to coalesce later.
341 LiveInterval &SrcInt = li_->getInterval(repSrcReg);
342 LiveInterval &DstInt = li_->getInterval(repDstReg);
343 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
344 "Register mapping is horribly broken!");
346 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
347 DOUT << " and "; DstInt.print(DOUT, mri_);
350 // Check if it is necessary to propagate "isDead" property before intervals
352 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
353 bool isDead = mopd->isDead();
354 bool isShorten = false;
355 unsigned SrcStart = 0, RemoveStart = 0;
356 unsigned SrcEnd = 0, RemoveEnd = 0;
358 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
359 LiveInterval::iterator SrcLR =
360 SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx));
361 RemoveStart = SrcStart = SrcLR->start;
362 RemoveEnd = SrcEnd = SrcLR->end;
363 // The instruction which defines the src is only truly dead if there are
364 // no intermediate uses and there isn't a use beyond the copy.
365 // FIXME: find the last use, mark is kill and shorten the live range.
366 if (SrcEnd > li_->getDefIndex(CopyIdx)) {
370 MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
372 // Shorten the liveinterval to the end of last use.
376 RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse));
379 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
381 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
383 // A dead def should have a single cycle interval.
390 // We need to be careful about coalescing a source physical register with a
391 // virtual register. Once the coalescing is done, it cannot be broken and
392 // these are not spillable! If the destination interval uses are far away,
393 // think twice about coalescing them!
394 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) {
395 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
396 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
397 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
398 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
399 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
400 if (TheCopy.isBackEdge)
401 Threshold *= 2; // Favors back edge copies.
403 // If the virtual register live interval is long but it has low use desity,
404 // do not join them, instead mark the physical register as its allocation
406 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
407 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
408 if (Length > Threshold &&
409 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
410 JoinVInt.preference = JoinPReg;
412 DOUT << "\tMay tie down a physical register, abort!\n";
413 Again = true; // May be possible to coalesce later.
418 // Okay, attempt to join these two intervals. On failure, this returns false.
419 // Otherwise, if one of the intervals being joined is a physreg, this method
420 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
421 // been modified, so we can use this information below to update aliases.
422 bool Swapped = false;
423 if (JoinIntervals(DstInt, SrcInt, Swapped)) {
425 // Result of the copy is dead. Propagate this property.
427 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
428 "Live-in must be a physical register!");
429 // Live-in to the function but dead. Remove it from entry live-in set.
430 // JoinIntervals may end up swapping the two intervals.
431 mf_->begin()->removeLiveIn(repSrcReg);
433 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
435 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
442 if (isShorten || isDead) {
443 // Shorten the destination live interval.
445 SrcInt.removeRange(RemoveStart, RemoveEnd);
448 // Coalescing failed.
450 // If we can eliminate the copy without merging the live ranges, do so now.
451 if (!isExtSubReg && AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI)) {
452 JoinedCopies.insert(CopyMI);
456 // Otherwise, we are unable to join the intervals.
457 DOUT << "Interference!\n";
458 Again = true; // May be possible to coalesce later.
462 LiveInterval *ResSrcInt = &SrcInt;
463 LiveInterval *ResDstInt = &DstInt;
465 std::swap(repSrcReg, repDstReg);
466 std::swap(ResSrcInt, ResDstInt);
468 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
469 "LiveInterval::join didn't work right!");
471 // If we're about to merge live ranges into a physical register live range,
472 // we have to update any aliased register's live ranges to indicate that they
473 // have clobbered values for this range.
474 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
475 // Unset unnecessary kills.
476 if (!ResDstInt->containsOneValue()) {
477 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
478 E = ResSrcInt->end(); I != E; ++I)
479 unsetRegisterKills(I->start, I->end, repDstReg);
482 // If this is a extract_subreg where dst is a physical register, e.g.
483 // cl = EXTRACT_SUBREG reg1024, 1
484 // then create and update the actual physical register allocated to RHS.
486 LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg);
487 SmallSet<const VNInfo*, 4> CopiedValNos;
488 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
489 E = ResSrcInt->ranges.end(); I != E; ++I) {
490 LiveInterval::const_iterator DstLR =
491 ResDstInt->FindLiveRangeContaining(I->start);
492 assert(DstLR != ResDstInt->end() && "Invalid joined interval!");
493 const VNInfo *DstValNo = DstLR->valno;
494 if (CopiedValNos.insert(DstValNo)) {
495 VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->reg,
496 li_->getVNInfoAllocator());
497 ValNo->hasPHIKill = DstValNo->hasPHIKill;
498 RealDstInt.addKills(ValNo, DstValNo->kills);
499 RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
502 repDstReg = RealDstReg;
505 // Update the liveintervals of sub-registers.
506 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
507 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
508 li_->getVNInfoAllocator());
510 // Merge use info if the destination is a virtual register.
511 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
512 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
513 dVI.NumUses += sVI.NumUses;
516 // Remember these liveintervals have been joined.
517 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
518 if (MRegisterInfo::isVirtualRegister(repDstReg))
519 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
521 if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
523 // Make sure we allocate the larger super-register.
524 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
525 std::swap(repSrcReg, repDstReg);
526 std::swap(ResSrcInt, ResDstInt);
528 unsigned SubIdx = CopyMI->getOperand(2).getImm();
529 SubRegIdxes.push_back(std::make_pair(repSrcReg, SubIdx));
530 AddSubRegIdxPairs(repSrcReg, SubIdx);
534 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
535 e = ResSrcInt->vni_end(); i != e; ++i) {
536 const VNInfo *vni = *i;
537 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
538 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
539 unsigned SrcReg, DstReg;
540 if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) &&
541 JoinedCopies.count(CopyMI) == 0) {
542 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
543 JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth,
544 isBackEdgeCopy(CopyMI, DstReg)));
550 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
553 // repSrcReg is guarateed to be the register whose live interval that is
555 li_->removeInterval(repSrcReg);
556 r2rMap_[repSrcReg] = repDstReg;
557 r2rRevMap_[repDstReg].push_back(repSrcReg);
559 // Finally, delete the copy instruction.
560 JoinedCopies.insert(CopyMI);
566 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
567 /// compute what the resultant value numbers for each value in the input two
568 /// ranges will be. This is complicated by copies between the two which can
569 /// and will commonly cause multiple value numbers to be merged into one.
571 /// VN is the value number that we're trying to resolve. InstDefiningValue
572 /// keeps track of the new InstDefiningValue assignment for the result
573 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
574 /// whether a value in this or other is a copy from the opposite set.
575 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
576 /// already been assigned.
578 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
579 /// contains the value number the copy is from.
581 static unsigned ComputeUltimateVN(VNInfo *VNI,
582 SmallVector<VNInfo*, 16> &NewVNInfo,
583 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
584 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
585 SmallVector<int, 16> &ThisValNoAssignments,
586 SmallVector<int, 16> &OtherValNoAssignments) {
587 unsigned VN = VNI->id;
589 // If the VN has already been computed, just return it.
590 if (ThisValNoAssignments[VN] >= 0)
591 return ThisValNoAssignments[VN];
592 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
594 // If this val is not a copy from the other val, then it must be a new value
595 // number in the destination.
596 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
597 if (I == ThisFromOther.end()) {
598 NewVNInfo.push_back(VNI);
599 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
601 VNInfo *OtherValNo = I->second;
603 // Otherwise, this *is* a copy from the RHS. If the other side has already
604 // been computed, return it.
605 if (OtherValNoAssignments[OtherValNo->id] >= 0)
606 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
608 // Mark this value number as currently being computed, then ask what the
609 // ultimate value # of the other value is.
610 ThisValNoAssignments[VN] = -2;
611 unsigned UltimateVN =
612 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
613 OtherValNoAssignments, ThisValNoAssignments);
614 return ThisValNoAssignments[VN] = UltimateVN;
617 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
618 return std::find(V.begin(), V.end(), Val) != V.end();
621 /// SimpleJoin - Attempt to joint the specified interval into this one. The
622 /// caller of this method must guarantee that the RHS only contains a single
623 /// value number and that the RHS is not defined by a copy from this
624 /// interval. This returns false if the intervals are not joinable, or it
625 /// joins them and returns true.
626 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
627 assert(RHS.containsOneValue());
629 // Some number (potentially more than one) value numbers in the current
630 // interval may be defined as copies from the RHS. Scan the overlapping
631 // portions of the LHS and RHS, keeping track of this and looking for
632 // overlapping live ranges that are NOT defined as copies. If these exist, we
635 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
636 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
638 if (LHSIt->start < RHSIt->start) {
639 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
640 if (LHSIt != LHS.begin()) --LHSIt;
641 } else if (RHSIt->start < LHSIt->start) {
642 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
643 if (RHSIt != RHS.begin()) --RHSIt;
646 SmallVector<VNInfo*, 8> EliminatedLHSVals;
649 // Determine if these live intervals overlap.
650 bool Overlaps = false;
651 if (LHSIt->start <= RHSIt->start)
652 Overlaps = LHSIt->end > RHSIt->start;
654 Overlaps = RHSIt->end > LHSIt->start;
656 // If the live intervals overlap, there are two interesting cases: if the
657 // LHS interval is defined by a copy from the RHS, it's ok and we record
658 // that the LHS value # is the same as the RHS. If it's not, then we cannot
659 // coalesce these live ranges and we bail out.
661 // If we haven't already recorded that this value # is safe, check it.
662 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
663 // Copy from the RHS?
664 unsigned SrcReg = LHSIt->valno->reg;
665 if (rep(SrcReg) != RHS.reg)
666 return false; // Nope, bail out.
668 EliminatedLHSVals.push_back(LHSIt->valno);
671 // We know this entire LHS live range is okay, so skip it now.
672 if (++LHSIt == LHSEnd) break;
676 if (LHSIt->end < RHSIt->end) {
677 if (++LHSIt == LHSEnd) break;
679 // One interesting case to check here. It's possible that we have
680 // something like "X3 = Y" which defines a new value number in the LHS,
681 // and is the last use of this liverange of the RHS. In this case, we
682 // want to notice this copy (so that it gets coalesced away) even though
683 // the live ranges don't actually overlap.
684 if (LHSIt->start == RHSIt->end) {
685 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
686 // We already know that this value number is going to be merged in
687 // if coalescing succeeds. Just skip the liverange.
688 if (++LHSIt == LHSEnd) break;
690 // Otherwise, if this is a copy from the RHS, mark it as being merged
692 if (rep(LHSIt->valno->reg) == RHS.reg) {
693 EliminatedLHSVals.push_back(LHSIt->valno);
695 // We know this entire LHS live range is okay, so skip it now.
696 if (++LHSIt == LHSEnd) break;
701 if (++RHSIt == RHSEnd) break;
705 // If we got here, we know that the coalescing will be successful and that
706 // the value numbers in EliminatedLHSVals will all be merged together. Since
707 // the most common case is that EliminatedLHSVals has a single number, we
708 // optimize for it: if there is more than one value, we merge them all into
709 // the lowest numbered one, then handle the interval as if we were merging
710 // with one value number.
712 if (EliminatedLHSVals.size() > 1) {
713 // Loop through all the equal value numbers merging them into the smallest
715 VNInfo *Smallest = EliminatedLHSVals[0];
716 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
717 if (EliminatedLHSVals[i]->id < Smallest->id) {
718 // Merge the current notion of the smallest into the smaller one.
719 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
720 Smallest = EliminatedLHSVals[i];
722 // Merge into the smallest.
723 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
728 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
729 LHSValNo = EliminatedLHSVals[0];
732 // Okay, now that there is a single LHS value number that we're merging the
733 // RHS into, update the value number info for the LHS to indicate that the
734 // value number is defined where the RHS value number was.
735 const VNInfo *VNI = RHS.getValNumInfo(0);
736 LHSValNo->def = VNI->def;
737 LHSValNo->reg = VNI->reg;
739 // Okay, the final step is to loop over the RHS live intervals, adding them to
741 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
742 LHS.addKills(LHSValNo, VNI->kills);
743 LHS.MergeRangesInAsValue(RHS, LHSValNo);
744 LHS.weight += RHS.weight;
745 if (RHS.preference && !LHS.preference)
746 LHS.preference = RHS.preference;
751 /// JoinIntervals - Attempt to join these two intervals. On failure, this
752 /// returns false. Otherwise, if one of the intervals being joined is a
753 /// physreg, this method always canonicalizes LHS to be it. The output
754 /// "RHS" will not have been modified, so we can use this information
755 /// below to update aliases.
756 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
757 LiveInterval &RHS, bool &Swapped) {
758 // Compute the final value assignment, assuming that the live ranges can be
760 SmallVector<int, 16> LHSValNoAssignments;
761 SmallVector<int, 16> RHSValNoAssignments;
762 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
763 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
764 SmallVector<VNInfo*, 16> NewVNInfo;
766 // If a live interval is a physical register, conservatively check if any
767 // of its sub-registers is overlapping the live interval of the virtual
768 // register. If so, do not coalesce.
769 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
770 *mri_->getSubRegisters(LHS.reg)) {
771 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
772 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
773 DOUT << "Interfere with sub-register ";
774 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
777 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
778 *mri_->getSubRegisters(RHS.reg)) {
779 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
780 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
781 DOUT << "Interfere with sub-register ";
782 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
787 // Compute ultimate value numbers for the LHS and RHS values.
788 if (RHS.containsOneValue()) {
789 // Copies from a liveinterval with a single value are simple to handle and
790 // very common, handle the special case here. This is important, because
791 // often RHS is small and LHS is large (e.g. a physreg).
793 // Find out if the RHS is defined as a copy from some value in the LHS.
794 int RHSVal0DefinedFromLHS = -1;
796 VNInfo *RHSValNoInfo = NULL;
797 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
798 unsigned RHSSrcReg = RHSValNoInfo0->reg;
799 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
800 // If RHS is not defined as a copy from the LHS, we can use simpler and
801 // faster checks to see if the live ranges are coalescable. This joiner
802 // can't swap the LHS/RHS intervals though.
803 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
804 return SimpleJoin(LHS, RHS);
806 RHSValNoInfo = RHSValNoInfo0;
809 // It was defined as a copy from the LHS, find out what value # it is.
810 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
811 RHSValID = RHSValNoInfo->id;
812 RHSVal0DefinedFromLHS = RHSValID;
815 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
816 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
817 NewVNInfo.resize(LHS.getNumValNums(), NULL);
819 // Okay, *all* of the values in LHS that are defined as a copy from RHS
820 // should now get updated.
821 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
824 unsigned VN = VNI->id;
825 if (unsigned LHSSrcReg = VNI->reg) {
826 if (rep(LHSSrcReg) != RHS.reg) {
827 // If this is not a copy from the RHS, its value number will be
828 // unmodified by the coalescing.
830 LHSValNoAssignments[VN] = VN;
831 } else if (RHSValID == -1) {
832 // Otherwise, it is a copy from the RHS, and we don't already have a
833 // value# for it. Keep the current value number, but remember it.
834 LHSValNoAssignments[VN] = RHSValID = VN;
835 NewVNInfo[VN] = RHSValNoInfo;
836 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
838 // Otherwise, use the specified value #.
839 LHSValNoAssignments[VN] = RHSValID;
840 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
841 NewVNInfo[VN] = RHSValNoInfo;
842 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
847 LHSValNoAssignments[VN] = VN;
851 assert(RHSValID != -1 && "Didn't find value #?");
852 RHSValNoAssignments[0] = RHSValID;
853 if (RHSVal0DefinedFromLHS != -1) {
854 // This path doesn't go through ComputeUltimateVN so just set
856 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
859 // Loop over the value numbers of the LHS, seeing if any are defined from
861 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
864 unsigned ValSrcReg = VNI->reg;
865 if (VNI->def == ~1U ||ValSrcReg == 0) // Src not defined by a copy?
868 // DstReg is known to be a register in the LHS interval. If the src is
869 // from the RHS interval, we can use its value #.
870 if (rep(ValSrcReg) != RHS.reg)
873 // Figure out the value # from the RHS.
874 LHSValsDefinedFromRHS[VNI] = RHS.getLiveRangeContaining(VNI->def-1)->valno;
877 // Loop over the value numbers of the RHS, seeing if any are defined from
879 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
882 unsigned ValSrcReg = VNI->reg;
883 if (VNI->def == ~1U || ValSrcReg == 0) // Src not defined by a copy?
886 // DstReg is known to be a register in the RHS interval. If the src is
887 // from the LHS interval, we can use its value #.
888 if (rep(ValSrcReg) != LHS.reg)
891 // Figure out the value # from the LHS.
892 RHSValsDefinedFromLHS[VNI]= LHS.getLiveRangeContaining(VNI->def-1)->valno;
895 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
896 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
897 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
899 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
902 unsigned VN = VNI->id;
903 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
905 ComputeUltimateVN(VNI, NewVNInfo,
906 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
907 LHSValNoAssignments, RHSValNoAssignments);
909 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
912 unsigned VN = VNI->id;
913 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
915 // If this value number isn't a copy from the LHS, it's a new number.
916 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
917 NewVNInfo.push_back(VNI);
918 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
922 ComputeUltimateVN(VNI, NewVNInfo,
923 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
924 RHSValNoAssignments, LHSValNoAssignments);
928 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
929 // interval lists to see if these intervals are coalescable.
930 LiveInterval::const_iterator I = LHS.begin();
931 LiveInterval::const_iterator IE = LHS.end();
932 LiveInterval::const_iterator J = RHS.begin();
933 LiveInterval::const_iterator JE = RHS.end();
935 // Skip ahead until the first place of potential sharing.
936 if (I->start < J->start) {
937 I = std::upper_bound(I, IE, J->start);
938 if (I != LHS.begin()) --I;
939 } else if (J->start < I->start) {
940 J = std::upper_bound(J, JE, I->start);
941 if (J != RHS.begin()) --J;
945 // Determine if these two live ranges overlap.
947 if (I->start < J->start) {
948 Overlaps = I->end > J->start;
950 Overlaps = J->end > I->start;
953 // If so, check value # info to determine if they are really different.
955 // If the live range overlap will map to the same value number in the
956 // result liverange, we can still coalesce them. If not, we can't.
957 if (LHSValNoAssignments[I->valno->id] !=
958 RHSValNoAssignments[J->valno->id])
962 if (I->end < J->end) {
971 // Update kill info. Some live ranges are extended due to copy coalescing.
972 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
973 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
974 VNInfo *VNI = I->first;
975 unsigned LHSValID = LHSValNoAssignments[VNI->id];
976 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
977 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
978 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
981 // Update kill info. Some live ranges are extended due to copy coalescing.
982 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
983 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
984 VNInfo *VNI = I->first;
985 unsigned RHSValID = RHSValNoAssignments[VNI->id];
986 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
987 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
988 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
991 // If we get here, we know that we can coalesce the live ranges. Ask the
992 // intervals to coalesce themselves now.
993 if ((RHS.ranges.size() > LHS.ranges.size() &&
994 MRegisterInfo::isVirtualRegister(LHS.reg)) ||
995 MRegisterInfo::isPhysicalRegister(RHS.reg)) {
996 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
999 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1006 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1007 // depth of the basic block (the unsigned), and then on the MBB number.
1008 struct DepthMBBCompare {
1009 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1010 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1011 if (LHS.first > RHS.first) return true; // Deeper loops first
1012 return LHS.first == RHS.first &&
1013 LHS.second->getNumber() < RHS.second->getNumber();
1018 /// getRepIntervalSize - Returns the size of the interval that represents the
1019 /// specified register.
1021 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1022 return Rc->getRepIntervalSize(Reg);
1025 /// CopyRecSort::operator - Join priority queue sorting function.
1027 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1028 // Inner loops first.
1029 if (left.LoopDepth > right.LoopDepth)
1031 else if (left.LoopDepth == right.LoopDepth) {
1032 if (left.isBackEdge && !right.isBackEdge)
1034 else if (left.isBackEdge == right.isBackEdge) {
1035 // Join virtuals to physical registers first.
1036 bool LDstIsPhys = MRegisterInfo::isPhysicalRegister(left.DstReg);
1037 bool LSrcIsPhys = MRegisterInfo::isPhysicalRegister(left.SrcReg);
1038 bool LIsPhys = LDstIsPhys || LSrcIsPhys;
1039 bool RDstIsPhys = MRegisterInfo::isPhysicalRegister(right.DstReg);
1040 bool RSrcIsPhys = MRegisterInfo::isPhysicalRegister(right.SrcReg);
1041 bool RIsPhys = RDstIsPhys || RSrcIsPhys;
1042 if (LIsPhys && !RIsPhys)
1044 else if (LIsPhys == RIsPhys) {
1045 // Join shorter intervals first.
1049 LSize = LDstIsPhys ? 0 : JPQ->getRepIntervalSize(left.DstReg);
1050 LSize += LSrcIsPhys ? 0 : JPQ->getRepIntervalSize(left.SrcReg);
1051 RSize = RDstIsPhys ? 0 : JPQ->getRepIntervalSize(right.DstReg);
1052 RSize += RSrcIsPhys ? 0 : JPQ->getRepIntervalSize(right.SrcReg);
1054 LSize = std::min(JPQ->getRepIntervalSize(left.DstReg),
1055 JPQ->getRepIntervalSize(left.SrcReg));
1056 RSize = std::min(JPQ->getRepIntervalSize(right.DstReg),
1057 JPQ->getRepIntervalSize(right.SrcReg));
1067 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1068 std::vector<CopyRec> &TryAgain) {
1069 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1071 std::vector<CopyRec> VirtCopies;
1072 std::vector<CopyRec> PhysCopies;
1073 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1074 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1076 MachineInstr *Inst = MII++;
1078 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1079 unsigned SrcReg, DstReg;
1080 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1081 DstReg = Inst->getOperand(0).getReg();
1082 SrcReg = Inst->getOperand(1).getReg();
1083 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1086 unsigned repSrcReg = rep(SrcReg);
1087 unsigned repDstReg = rep(DstReg);
1088 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
1089 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
1091 JoinQueue->push(CopyRec(Inst, SrcReg, DstReg, LoopDepth,
1092 isBackEdgeCopy(Inst, DstReg)));
1094 if (SrcIsPhys || DstIsPhys)
1095 PhysCopies.push_back(CopyRec(Inst, SrcReg, DstReg, 0, false));
1097 VirtCopies.push_back(CopyRec(Inst, SrcReg, DstReg, 0, false));
1104 // Try coalescing physical register + virtual register first.
1105 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1106 CopyRec &TheCopy = PhysCopies[i];
1108 if (!JoinCopy(TheCopy, Again))
1110 TryAgain.push_back(TheCopy);
1112 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1113 CopyRec &TheCopy = VirtCopies[i];
1115 if (!JoinCopy(TheCopy, Again))
1117 TryAgain.push_back(TheCopy);
1121 void SimpleRegisterCoalescing::joinIntervals() {
1122 DOUT << "********** JOINING INTERVALS ***********\n";
1125 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1127 JoinedLIs.resize(li_->getNumIntervals());
1130 std::vector<CopyRec> TryAgainList;
1131 if (loopInfo->begin() == loopInfo->end()) {
1132 // If there are no loops in the function, join intervals in function order.
1133 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1135 CopyCoalesceInMBB(I, TryAgainList);
1137 // Otherwise, join intervals in inner loops before other intervals.
1138 // Unfortunately we can't just iterate over loop hierarchy here because
1139 // there may be more MBB's than BB's. Collect MBB's for sorting.
1141 // Join intervals in the function prolog first. We want to join physical
1142 // registers with virtual registers before the intervals got too long.
1143 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1144 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1145 MachineBasicBlock *MBB = I;
1146 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1149 // Sort by loop depth.
1150 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1152 // Finally, join intervals in loop nest order.
1153 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1154 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1157 // Joining intervals can allow other intervals to be joined. Iteratively join
1158 // until we make no progress.
1160 SmallVector<CopyRec, 16> TryAgain;
1161 bool ProgressMade = true;
1162 while (ProgressMade) {
1163 ProgressMade = false;
1164 while (!JoinQueue->empty()) {
1165 CopyRec R = JoinQueue->pop();
1167 bool Success = JoinCopy(R, Again);
1169 ProgressMade = true;
1171 TryAgain.push_back(R);
1175 while (!TryAgain.empty()) {
1176 JoinQueue->push(TryAgain.back());
1177 TryAgain.pop_back();
1182 bool ProgressMade = true;
1183 while (ProgressMade) {
1184 ProgressMade = false;
1186 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1187 CopyRec &TheCopy = TryAgainList[i];
1190 bool Success = JoinCopy(TheCopy, Again);
1191 if (Success || !Again) {
1192 TheCopy.MI = 0; // Mark this one as done.
1193 ProgressMade = true;
1200 // Some live range has been lengthened due to colaescing, eliminate the
1201 // unnecessary kills.
1202 int RegNum = JoinedLIs.find_first();
1203 while (RegNum != -1) {
1204 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
1205 unsigned repReg = rep(Reg);
1206 LiveInterval &LI = li_->getInterval(repReg);
1207 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
1208 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
1209 MachineInstr *Kill = svi.Kills[i];
1210 // Suppose vr1 = op vr2, x
1211 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
1212 // unless it is a two-address operand.
1213 if (li_->isRemoved(Kill) || hasRegisterDef(Kill, repReg))
1215 if (LI.liveAt(li_->getInstructionIndex(Kill) + InstrSlots::NUM))
1216 unsetRegisterKill(Kill, repReg);
1218 RegNum = JoinedLIs.find_next(RegNum);
1224 DOUT << "*** Register mapping ***\n";
1225 for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i)
1227 DOUT << " reg " << i << " -> ";
1228 DEBUG(printRegName(r2rMap_[i]));
1233 /// Return true if the two specified registers belong to different register
1234 /// classes. The registers may be either phys or virt regs.
1235 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1236 unsigned RegB) const {
1238 // Get the register classes for the first reg.
1239 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1240 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1241 "Shouldn't consider two physregs!");
1242 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1245 // Compare against the regclass for the second reg.
1246 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1247 if (MRegisterInfo::isVirtualRegister(RegB))
1248 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1250 return !RegClass->contains(RegB);
1253 /// lastRegisterUse - Returns the last use of the specific register between
1254 /// cycles Start and End. It also returns the use operand by reference. It
1255 /// returns NULL if there are no uses.
1257 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
1258 MachineOperand *&MOU) {
1259 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1262 // Skip deleted instructions
1263 MachineInstr *MI = li_->getInstructionFromIndex(e);
1264 while ((e - InstrSlots::NUM) >= s && !MI) {
1265 e -= InstrSlots::NUM;
1266 MI = li_->getInstructionFromIndex(e);
1268 if (e < s || MI == NULL)
1271 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1272 MachineOperand &MO = MI->getOperand(i);
1273 if (MO.isRegister() && MO.isUse() && MO.getReg() &&
1274 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1280 e -= InstrSlots::NUM;
1287 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1288 /// register. It returns NULL if the def is not found.
1289 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
1290 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1291 MachineOperand &MO = MI->getOperand(i);
1292 if (MO.isRegister() && MO.isDef() &&
1293 mri_->regsOverlap(rep(MO.getReg()), Reg))
1299 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1300 /// of the specific instruction.
1301 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1302 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1303 MachineOperand &MO = MI->getOperand(i);
1304 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1305 mri_->regsOverlap(rep(MO.getReg()), Reg))
1310 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1311 /// between cycles Start and End.
1312 void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
1314 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1317 // Skip deleted instructions
1318 MachineInstr *MI = li_->getInstructionFromIndex(e);
1319 while ((e - InstrSlots::NUM) >= s && !MI) {
1320 e -= InstrSlots::NUM;
1321 MI = li_->getInstructionFromIndex(e);
1323 if (e < s || MI == NULL)
1326 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1327 MachineOperand &MO = MI->getOperand(i);
1328 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1329 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1334 e -= InstrSlots::NUM;
1338 /// hasRegisterDef - True if the instruction defines the specific register.
1340 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1341 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1342 MachineOperand &MO = MI->getOperand(i);
1343 if (MO.isRegister() && MO.isDef() &&
1344 mri_->regsOverlap(rep(MO.getReg()), Reg))
1350 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1351 if (MRegisterInfo::isPhysicalRegister(reg))
1352 cerr << mri_->getName(reg);
1354 cerr << "%reg" << reg;
1357 void SimpleRegisterCoalescing::releaseMemory() {
1358 for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i)
1359 r2rRevMap_[i].clear();
1363 SubRegIdxes.clear();
1364 JoinedCopies.clear();
1367 static bool isZeroLengthInterval(LiveInterval *li) {
1368 for (LiveInterval::Ranges::const_iterator
1369 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1370 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1375 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1377 tm_ = &fn.getTarget();
1378 mri_ = tm_->getRegisterInfo();
1379 tii_ = tm_->getInstrInfo();
1380 li_ = &getAnalysis<LiveIntervals>();
1381 lv_ = &getAnalysis<LiveVariables>();
1382 loopInfo = &getAnalysis<MachineLoopInfo>();
1384 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1385 << "********** Function: "
1386 << ((Value*)mf_->getFunction())->getName() << '\n';
1388 allocatableRegs_ = mri_->getAllocatableSet(fn);
1389 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
1390 E = mri_->regclass_end(); I != E; ++I)
1391 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
1393 SSARegMap *RegMap = mf_->getSSARegMap();
1394 r2rMap_.grow(RegMap->getLastVirtReg());
1395 r2rRevMap_.grow(RegMap->getLastVirtReg());
1397 // Join (coalesce) intervals if requested.
1398 IndexedMap<unsigned, VirtReg2IndexFunctor> RegSubIdxMap;
1399 if (EnableJoining) {
1401 DOUT << "********** INTERVALS POST JOINING **********\n";
1402 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1403 I->second.print(DOUT, mri_);
1407 // Delete all coalesced copies.
1408 for (SmallPtrSet<MachineInstr*,32>::iterator I = JoinedCopies.begin(),
1409 E = JoinedCopies.end(); I != E; ++I) {
1410 li_->RemoveMachineInstrFromMaps(*I);
1411 (*I)->eraseFromParent();
1414 // Transfer sub-registers info to SSARegMap now that coalescing information
1416 RegSubIdxMap.grow(mf_->getSSARegMap()->getLastVirtReg()+1);
1417 while (!SubRegIdxes.empty()) {
1418 std::pair<unsigned, unsigned> RI = SubRegIdxes.back();
1419 SubRegIdxes.pop_back();
1420 RegSubIdxMap[RI.first] = RI.second;
1424 // perform a final pass over the instructions and compute spill
1425 // weights, coalesce virtual registers and remove identity moves.
1426 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1427 mbbi != mbbe; ++mbbi) {
1428 MachineBasicBlock* mbb = mbbi;
1429 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
1431 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1433 // if the move will be an identity move delete it
1434 unsigned srcReg, dstReg, RegRep;
1435 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
1436 (RegRep = rep(srcReg)) == rep(dstReg)) {
1437 // remove from def list
1438 LiveInterval &RegInt = li_->getOrCreateInterval(RegRep);
1439 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1440 // If def of this move instruction is dead, remove its live range from
1441 // the dstination register's live interval.
1443 unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
1444 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
1445 RegInt.removeRange(MLR->start, MoveIdx+1);
1447 li_->removeInterval(RegRep);
1449 li_->RemoveMachineInstrFromMaps(mii);
1450 mii = mbbi->erase(mii);
1453 SmallSet<unsigned, 4> UniqueUses;
1454 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
1455 const MachineOperand &mop = mii->getOperand(i);
1456 if (mop.isRegister() && mop.getReg() &&
1457 MRegisterInfo::isVirtualRegister(mop.getReg())) {
1458 // replace register with representative register
1459 unsigned OrigReg = mop.getReg();
1460 unsigned reg = rep(OrigReg);
1461 unsigned SubIdx = RegSubIdxMap[OrigReg];
1462 if (SubIdx && MRegisterInfo::isPhysicalRegister(reg))
1463 mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx));
1465 mii->getOperand(i).setReg(reg);
1466 mii->getOperand(i).setSubReg(SubIdx);
1469 // Multiple uses of reg by the same instruction. It should not
1470 // contribute to spill weight again.
1471 if (UniqueUses.count(reg) != 0)
1473 LiveInterval &RegInt = li_->getInterval(reg);
1475 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
1476 UniqueUses.insert(reg);
1484 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1485 LiveInterval &LI = I->second;
1486 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
1487 // If the live interval length is essentially zero, i.e. in every live
1488 // range the use follows def immediately, it doesn't make sense to spill
1489 // it and hope it will be easier to allocate for this li.
1490 if (isZeroLengthInterval(&LI))
1491 LI.weight = HUGE_VALF;
1493 bool isLoad = false;
1494 if (ReMatSpillWeight && li_->isReMaterializable(LI, isLoad)) {
1495 // If all of the definitions of the interval are re-materializable,
1496 // it is a preferred candidate for spilling. If non of the defs are
1497 // loads, then it's potentially very cheap to re-materialize.
1498 // FIXME: this gets much more complicated once we support non-trivial
1499 // re-materialization.
1507 // Slightly prefer live interval that has been assigned a preferred reg.
1511 // Divide the weight of the interval by its size. This encourages
1512 // spilling of intervals that are large and have few uses, and
1513 // discourages spilling of small intervals with many uses.
1514 LI.weight /= LI.getSize();
1522 /// print - Implement the dump method.
1523 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
1527 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1528 return new SimpleRegisterCoalescing();
1531 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1532 DEFINING_FILE_FOR(SimpleRegisterCoalescing)