1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numCrossRCs , "Number of cross class joins performed");
41 STATISTIC(numCommutes , "Number of instruction commuting performed");
42 STATISTIC(numExtends , "Number of copies extended");
43 STATISTIC(NumReMats , "Number of instructions re-materialized");
44 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
45 STATISTIC(numAborts , "Number of times interval joining aborted");
46 STATISTIC(numDeadValNo, "Number of valno def marked dead");
48 char SimpleRegisterCoalescing::ID = 0;
50 EnableJoining("join-liveintervals",
51 cl::desc("Coalesce copies (default=true)"),
55 NewHeuristic("new-coalescer-heuristic",
56 cl::desc("Use new coalescer heuristic"),
57 cl::init(false), cl::Hidden);
60 DisableCrossClassJoin("disable-cross-class-join",
61 cl::desc("Avoid coalescing cross register class copies"),
62 cl::init(false), cl::Hidden);
65 PhysJoinTweak("tweak-phys-join-heuristics",
66 cl::desc("Tweak heuristics for joining phys reg with vr"),
67 cl::init(false), cl::Hidden);
69 static RegisterPass<SimpleRegisterCoalescing>
70 X("simple-register-coalescing", "Simple Register Coalescing");
72 // Declare that we implement the RegisterCoalescer interface
73 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
75 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
77 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
78 AU.addRequired<LiveIntervals>();
79 AU.addPreserved<LiveIntervals>();
80 AU.addRequired<MachineLoopInfo>();
81 AU.addPreserved<MachineLoopInfo>();
82 AU.addPreservedID(MachineDominatorsID);
84 AU.addPreservedID(StrongPHIEliminationID);
86 AU.addPreservedID(PHIEliminationID);
87 AU.addPreservedID(TwoAddressInstructionPassID);
88 MachineFunctionPass::getAnalysisUsage(AU);
91 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
92 /// being the source and IntB being the dest, thus this defines a value number
93 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
94 /// see if we can merge these two pieces of B into a single value number,
95 /// eliminating a copy. For example:
99 /// B1 = A3 <- this copy
101 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
102 /// value number to be replaced with B0 (which simplifies the B liveinterval).
104 /// This returns true if an interval was modified.
106 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
108 MachineInstr *CopyMI) {
109 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
111 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
112 // the example above.
113 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
114 assert(BLR != IntB.end() && "Live range not found!");
115 VNInfo *BValNo = BLR->valno;
117 // Get the location that B is defined at. Two options: either this value has
118 // an unknown definition point or it is defined at CopyIdx. If unknown, we
120 if (!BValNo->copy) return false;
121 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
123 // AValNo is the value number in A that defines the copy, A3 in the example.
124 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
125 assert(ALR != IntA.end() && "Live range not found!");
126 VNInfo *AValNo = ALR->valno;
127 // If it's re-defined by an early clobber somewhere in the live range, then
128 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
130 // 172 %ECX<def> = MOV32rr %reg1039<kill>
131 // 180 INLINEASM <es:subl $5,$1
132 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
133 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
134 // 188 %EAX<def> = MOV32rr %EAX<kill>
135 // 196 %ECX<def> = MOV32rr %ECX<kill>
136 // 204 %ECX<def> = MOV32rr %ECX<kill>
137 // 212 %EAX<def> = MOV32rr %EAX<kill>
138 // 220 %EAX<def> = MOV32rr %EAX
139 // 228 %reg1039<def> = MOV32rr %ECX<kill>
140 // The early clobber operand ties ECX input to the ECX def.
142 // The live interval of ECX is represented as this:
143 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
144 // The coalescer has no idea there was a def in the middle of [174,230].
145 if (AValNo->hasRedefByEC())
148 // If AValNo is defined as a copy from IntB, we can potentially process this.
149 // Get the instruction that defines this value number.
150 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
151 if (!SrcReg) return false; // Not defined by a copy.
153 // If the value number is not defined by a copy instruction, ignore it.
155 // If the source register comes from an interval other than IntB, we can't
157 if (SrcReg != IntB.reg) return false;
159 // Get the LiveRange in IntB that this value number starts with.
160 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
161 assert(ValLR != IntB.end() && "Live range not found!");
163 // Make sure that the end of the live range is inside the same block as
165 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
181 DOUT << "Interfere with sub-register ";
182 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
187 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
189 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
190 // We are about to delete CopyMI, so need to remove it as the 'instruction
191 // that defines this value #'. Update the the valnum with the new defining
193 BValNo->def = FillerStart;
196 // Okay, we can merge them. We need to insert a new liverange:
197 // [ValLR.end, BLR.begin) of either value number, then we merge the
198 // two value numbers.
199 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
201 // If the IntB live range is assigned to a physical register, and if that
202 // physreg has sub-registers, update their live intervals as well.
203 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
204 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
205 LiveInterval &SRLI = li_->getInterval(*SR);
206 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
207 SRLI.getNextValue(FillerStart, 0, true,
208 li_->getVNInfoAllocator())));
212 // Okay, merge "B1" into the same value number as "B0".
213 if (BValNo != ValLR->valno) {
214 IntB.addKills(ValLR->valno, BValNo->kills);
215 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
217 DOUT << " result = "; IntB.print(DOUT, tri_);
220 // If the source instruction was killing the source register before the
221 // merge, unset the isKill marker given the live range has been extended.
222 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
224 ValLREndInst->getOperand(UIdx).setIsKill(false);
225 IntB.removeKill(ValLR->valno, FillerStart);
232 /// HasOtherReachingDefs - Return true if there are definitions of IntB
233 /// other than BValNo val# that can reach uses of AValno val# of IntA.
234 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
238 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
240 if (AI->valno != AValNo) continue;
241 LiveInterval::Ranges::iterator BI =
242 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
243 if (BI != IntB.ranges.begin())
245 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
246 if (BI->valno == BValNo)
248 if (BI->start <= AI->start && BI->end > AI->start)
250 if (BI->start > AI->start && BI->start < AI->end)
257 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
258 /// being the source and IntB being the dest, thus this defines a value number
259 /// in IntB. If the source value number (in IntA) is defined by a commutable
260 /// instruction and its other operand is coalesced to the copy dest register,
261 /// see if we can transform the copy into a noop by commuting the definition. For
264 /// A3 = op A2 B0<kill>
266 /// B1 = A3 <- this copy
268 /// = op A3 <- more uses
272 /// B2 = op B0 A2<kill>
274 /// B1 = B2 <- now an identify copy
276 /// = op B2 <- more uses
278 /// This returns true if an interval was modified.
280 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
282 MachineInstr *CopyMI) {
283 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
285 // FIXME: For now, only eliminate the copy by commuting its def when the
286 // source register is a virtual register. We want to guard against cases
287 // where the copy is a back edge copy and commuting the def lengthen the
288 // live interval of the source register to the entire loop.
289 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
292 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
293 // the example above.
294 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
295 assert(BLR != IntB.end() && "Live range not found!");
296 VNInfo *BValNo = BLR->valno;
298 // Get the location that B is defined at. Two options: either this value has
299 // an unknown definition point or it is defined at CopyIdx. If unknown, we
301 if (!BValNo->copy) return false;
302 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
304 // AValNo is the value number in A that defines the copy, A3 in the example.
305 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
306 assert(ALR != IntA.end() && "Live range not found!");
307 VNInfo *AValNo = ALR->valno;
308 // If other defs can reach uses of this def, then it's not safe to perform
309 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
311 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
312 AValNo->isUnused() || AValNo->hasPHIKill())
314 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
315 const TargetInstrDesc &TID = DefMI->getDesc();
316 if (!TID.isCommutable())
318 // If DefMI is a two-address instruction then commuting it will change the
319 // destination register.
320 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
321 assert(DefIdx != -1);
323 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
325 unsigned Op1, Op2, NewDstIdx;
326 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
330 else if (Op2 == UseOpIdx)
335 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
336 unsigned NewReg = NewDstMO.getReg();
337 if (NewReg != IntB.reg || !NewDstMO.isKill())
340 // Make sure there are no other definitions of IntB that would reach the
341 // uses which the new definition can reach.
342 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
345 // If some of the uses of IntA.reg is already coalesced away, return false.
346 // It's not possible to determine whether it's safe to perform the coalescing.
347 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
348 UE = mri_->use_end(); UI != UE; ++UI) {
349 MachineInstr *UseMI = &*UI;
350 unsigned UseIdx = li_->getInstructionIndex(UseMI);
351 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
352 if (ULR == IntA.end())
354 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
358 // At this point we have decided that it is legal to do this
359 // transformation. Start by commuting the instruction.
360 MachineBasicBlock *MBB = DefMI->getParent();
361 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
364 if (NewMI != DefMI) {
365 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
366 MBB->insert(DefMI, NewMI);
369 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
370 NewMI->getOperand(OpIdx).setIsKill();
372 bool BHasPHIKill = BValNo->hasPHIKill();
373 SmallVector<VNInfo*, 4> BDeadValNos;
374 VNInfo::KillSet BKills;
375 std::map<unsigned, unsigned> BExtend;
377 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
386 // then do not add kills of A to the newly created B interval.
387 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
389 BExtend[ALR->end] = BLR->end;
391 // Update uses of IntA of the specific Val# with IntB.
392 bool BHasSubRegs = false;
393 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
394 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
395 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
396 UE = mri_->use_end(); UI != UE;) {
397 MachineOperand &UseMO = UI.getOperand();
398 MachineInstr *UseMI = &*UI;
400 if (JoinedCopies.count(UseMI))
402 unsigned UseIdx = li_->getInstructionIndex(UseMI);
403 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
404 if (ULR == IntA.end() || ULR->valno != AValNo)
406 UseMO.setReg(NewReg);
409 if (UseMO.isKill()) {
411 UseMO.setIsKill(false);
413 BKills.push_back(VNInfo::KillInfo(false, li_->getUseIndex(UseIdx)+1));
415 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
416 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
418 if (DstReg == IntB.reg) {
419 // This copy will become a noop. If it's defining a new val#,
420 // remove that val# as well. However this live range is being
421 // extended to the end of the existing live range defined by the copy.
422 unsigned DefIdx = li_->getDefIndex(UseIdx);
423 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
424 BHasPHIKill |= DLR->valno->hasPHIKill();
425 assert(DLR->valno->def == DefIdx);
426 BDeadValNos.push_back(DLR->valno);
427 BExtend[DLR->start] = DLR->end;
428 JoinedCopies.insert(UseMI);
429 // If this is a kill but it's going to be removed, the last use
430 // of the same val# is the new kill.
436 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
437 // simply extend BLR if CopyMI doesn't end the range.
438 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
440 // Remove val#'s defined by copies that will be coalesced away.
441 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
442 VNInfo *DeadVNI = BDeadValNos[i];
444 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
445 LiveInterval &SRLI = li_->getInterval(*SR);
446 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
447 SRLI.removeValNo(SRLR->valno);
450 IntB.removeValNo(BDeadValNos[i]);
453 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
454 // is updated. Kills are also updated.
455 VNInfo *ValNo = BValNo;
456 ValNo->def = AValNo->def;
458 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
459 unsigned Kill = ValNo->kills[j].killIdx;
460 if (Kill != BLR->end)
461 BKills.push_back(VNInfo::KillInfo(ValNo->kills[j].isPHIKill, Kill));
463 ValNo->kills.clear();
464 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
466 if (AI->valno != AValNo) continue;
467 unsigned End = AI->end;
468 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
469 if (EI != BExtend.end())
471 IntB.addRange(LiveRange(AI->start, End, ValNo));
473 // If the IntB live range is assigned to a physical register, and if that
474 // physreg has sub-registers, update their live intervals as well.
476 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
477 LiveInterval &SRLI = li_->getInterval(*SR);
478 SRLI.MergeInClobberRange(AI->start, End, li_->getVNInfoAllocator());
482 IntB.addKills(ValNo, BKills);
483 ValNo->setHasPHIKill(BHasPHIKill);
485 DOUT << " result = "; IntB.print(DOUT, tri_);
488 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
489 IntA.removeValNo(AValNo);
490 DOUT << " result = "; IntA.print(DOUT, tri_);
497 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
498 /// fallthoughs to SuccMBB.
499 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
500 MachineBasicBlock *SuccMBB,
501 const TargetInstrInfo *tii_) {
504 MachineBasicBlock *TBB = 0, *FBB = 0;
505 SmallVector<MachineOperand, 4> Cond;
506 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
507 MBB->isSuccessor(SuccMBB);
510 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
511 /// from a physical register live interval as well as from the live intervals
512 /// of its sub-registers.
513 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
514 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
515 li.removeRange(Start, End, true);
516 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
517 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
518 if (!li_->hasInterval(*SR))
520 LiveInterval &sli = li_->getInterval(*SR);
521 unsigned RemoveEnd = Start;
522 while (RemoveEnd != End) {
523 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
526 RemoveEnd = (LR->end < End) ? LR->end : End;
527 sli.removeRange(Start, RemoveEnd, true);
534 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
535 /// as the copy instruction, trim the live interval to the last use and return
538 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
539 MachineBasicBlock *CopyMBB,
541 const LiveRange *LR) {
542 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
544 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
547 MachineInstr *LastUseMI = LastUse->getParent();
548 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
555 // r1025<dead> = r1024<kill>
556 if (MBBStart < LR->end)
557 removeRange(li, MBBStart, LR->end, li_, tri_);
561 // There are uses before the copy, just shorten the live range to the end
563 LastUse->setIsKill();
564 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
565 li.addKill(LR->valno, LastUseIdx+1, false);
566 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
567 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
569 // Last use is itself an identity code.
570 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
571 LastUseMI->getOperand(DeadIdx).setIsDead();
577 if (LR->start <= MBBStart && LR->end > MBBStart) {
578 if (LR->start == 0) {
579 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
580 // Live-in to the function but dead. Remove it from entry live-in set.
581 mf_->begin()->removeLiveIn(li.reg);
583 // FIXME: Shorten intervals in BBs that reaches this BB.
589 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
590 /// computation, replace the copy by rematerialize the definition.
591 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
594 MachineInstr *CopyMI) {
595 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
596 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
597 assert(SrcLR != SrcInt.end() && "Live range not found!");
598 VNInfo *ValNo = SrcLR->valno;
599 // If other defs can reach uses of this def, then it's not safe to perform
600 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
602 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
603 ValNo->isUnused() || ValNo->hasPHIKill())
605 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
606 const TargetInstrDesc &TID = DefMI->getDesc();
607 if (!TID.isAsCheapAsAMove())
609 if (!DefMI->getDesc().isRematerializable() ||
610 !tii_->isTriviallyReMaterializable(DefMI))
612 bool SawStore = false;
613 if (!DefMI->isSafeToMove(tii_, SawStore))
615 if (TID.getNumDefs() != 1)
617 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
618 // Make sure the copy destination register class fits the instruction
619 // definition register class. The mismatch can happen as a result of earlier
620 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
621 const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
622 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
623 if (mri_->getRegClass(DstReg) != RC)
625 } else if (!RC->contains(DstReg))
629 unsigned DefIdx = li_->getDefIndex(CopyIdx);
630 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
631 DLR->valno->copy = NULL;
632 // Don't forget to update sub-register intervals.
633 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
634 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
635 if (!li_->hasInterval(*SR))
637 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
638 if (DLR && DLR->valno->copy == CopyMI)
639 DLR->valno->copy = NULL;
643 // If copy kills the source register, find the last use and propagate
645 bool checkForDeadDef = false;
646 MachineBasicBlock *MBB = CopyMI->getParent();
647 if (CopyMI->killsRegister(SrcInt.reg))
648 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
649 checkForDeadDef = true;
652 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
653 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI);
654 MachineInstr *NewMI = prior(MII);
656 if (checkForDeadDef) {
657 // PR4090 fix: Trim interval failed because there was no use of the
658 // source interval in this MBB. If the def is in this MBB too then we
659 // should mark it dead:
660 if (DefMI->getParent() == MBB) {
661 DefMI->addRegisterDead(SrcInt.reg, tri_);
662 SrcLR->end = SrcLR->start + 1;
666 // CopyMI may have implicit operands, transfer them over to the newly
667 // rematerialized instruction. And update implicit def interval valnos.
668 for (unsigned i = CopyMI->getDesc().getNumOperands(),
669 e = CopyMI->getNumOperands(); i != e; ++i) {
670 MachineOperand &MO = CopyMI->getOperand(i);
671 if (MO.isReg() && MO.isImplicit())
672 NewMI->addOperand(MO);
673 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
674 unsigned Reg = MO.getReg();
675 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
676 if (DLR && DLR->valno->copy == CopyMI)
677 DLR->valno->copy = NULL;
681 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
682 CopyMI->eraseFromParent();
683 ReMatCopies.insert(CopyMI);
684 ReMatDefs.insert(DefMI);
689 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
691 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
692 unsigned DstReg) const {
693 MachineBasicBlock *MBB = CopyMI->getParent();
694 const MachineLoop *L = loopInfo->getLoopFor(MBB);
697 if (MBB != L->getLoopLatch())
700 LiveInterval &LI = li_->getInterval(DstReg);
701 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
702 LiveInterval::const_iterator DstLR =
703 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
704 if (DstLR == LI.end())
706 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIKill)
711 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
712 /// update the subregister number if it is not zero. If DstReg is a
713 /// physical register and the existing subregister number of the def / use
714 /// being updated is not zero, make sure to set it to the correct physical
717 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
719 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
720 if (DstIsPhys && SubIdx) {
721 // Figure out the real physical register we are updating with.
722 DstReg = tri_->getSubReg(DstReg, SubIdx);
726 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
727 E = mri_->reg_end(); I != E; ) {
728 MachineOperand &O = I.getOperand();
729 MachineInstr *UseMI = &*I;
731 unsigned OldSubIdx = O.getSubReg();
733 unsigned UseDstReg = DstReg;
735 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
737 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
738 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
739 CopySrcSubIdx, CopyDstSubIdx) &&
740 CopySrcReg != CopyDstReg &&
741 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
742 // If the use is a copy and it won't be coalesced away, and its source
743 // is defined by a trivial computation, try to rematerialize it instead.
744 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
745 CopyDstSubIdx, UseMI))
754 // Sub-register indexes goes from small to large. e.g.
755 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
756 // EAX: 1 -> AL, 2 -> AX
757 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
758 // sub-register 2 is also AX.
759 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
760 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
763 // Remove would-be duplicated kill marker.
764 if (O.isKill() && UseMI->killsRegister(DstReg))
768 // After updating the operand, check if the machine instruction has
769 // become a copy. If so, update its val# information.
770 if (JoinedCopies.count(UseMI))
773 const TargetInstrDesc &TID = UseMI->getDesc();
774 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
775 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
776 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
777 CopySrcSubIdx, CopyDstSubIdx) &&
778 CopySrcReg != CopyDstReg &&
779 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
780 allocatableRegs_[CopyDstReg])) {
781 LiveInterval &LI = li_->getInterval(CopyDstReg);
782 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
783 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
784 if (DLR->valno->def == DefIdx)
785 DLR->valno->copy = UseMI;
791 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
792 /// due to live range lengthening as the result of coalescing.
793 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
795 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
796 UE = mri_->use_end(); UI != UE; ++UI) {
797 MachineOperand &UseMO = UI.getOperand();
798 if (UseMO.isKill()) {
799 MachineInstr *UseMI = UseMO.getParent();
800 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
801 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
802 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
803 UseMO.setIsKill(false);
808 /// removeIntervalIfEmpty - Check if the live interval of a physical register
809 /// is empty, if so remove it and also remove the empty intervals of its
810 /// sub-registers. Return true if live interval is removed.
811 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
812 const TargetRegisterInfo *tri_) {
814 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
815 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
816 if (!li_->hasInterval(*SR))
818 LiveInterval &sli = li_->getInterval(*SR);
820 li_->removeInterval(*SR);
822 li_->removeInterval(li.reg);
828 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
829 /// Return true if live interval is removed.
830 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
831 MachineInstr *CopyMI) {
832 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
833 LiveInterval::iterator MLR =
834 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
836 return false; // Already removed by ShortenDeadCopySrcLiveRange.
837 unsigned RemoveStart = MLR->start;
838 unsigned RemoveEnd = MLR->end;
839 unsigned DefIdx = li_->getDefIndex(CopyIdx);
840 // Remove the liverange that's defined by this.
841 if (RemoveStart == DefIdx && RemoveEnd == DefIdx+1) {
842 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
843 return removeIntervalIfEmpty(li, li_, tri_);
848 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
849 /// the val# it defines. If the live interval becomes empty, remove it as well.
850 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
851 MachineInstr *DefMI) {
852 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
853 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
854 if (DefIdx != MLR->valno->def)
856 li.removeValNo(MLR->valno);
857 return removeIntervalIfEmpty(li, li_, tri_);
860 /// PropagateDeadness - Propagate the dead marker to the instruction which
861 /// defines the val#.
862 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
863 unsigned &LRStart, LiveIntervals *li_,
864 const TargetRegisterInfo* tri_) {
865 MachineInstr *DefMI =
866 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
867 if (DefMI && DefMI != CopyMI) {
868 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
870 DefMI->getOperand(DeadIdx).setIsDead();
871 // A dead def should have a single cycle interval.
877 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
878 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
879 /// ends the live range there. If there isn't another use, then this live range
880 /// is dead. Return true if live interval is removed.
882 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
883 MachineInstr *CopyMI) {
884 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
886 // FIXME: special case: function live in. It can be a general case if the
887 // first instruction index starts at > 0 value.
888 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
889 // Live-in to the function but dead. Remove it from entry live-in set.
890 if (mf_->begin()->isLiveIn(li.reg))
891 mf_->begin()->removeLiveIn(li.reg);
892 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
893 removeRange(li, LR->start, LR->end, li_, tri_);
894 return removeIntervalIfEmpty(li, li_, tri_);
897 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
899 // Livein but defined by a phi.
902 unsigned RemoveStart = LR->start;
903 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
904 if (LR->end > RemoveEnd)
905 // More uses past this copy? Nothing to do.
908 // If there is a last use in the same bb, we can't remove the live range.
909 // Shorten the live interval and return.
910 MachineBasicBlock *CopyMBB = CopyMI->getParent();
911 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
914 // There are other kills of the val#. Nothing to do.
915 if (!li.isOnlyLROfValNo(LR))
918 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
919 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
920 // If the live range starts in another mbb and the copy mbb is not a fall
921 // through mbb, then we can only cut the range from the beginning of the
923 RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
925 if (LR->valno->def == RemoveStart) {
926 // If the def MI defines the val# and this copy is the only kill of the
927 // val#, then propagate the dead marker.
928 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
931 if (li.isKill(LR->valno, RemoveEnd))
932 li.removeKill(LR->valno, RemoveEnd);
935 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
936 return removeIntervalIfEmpty(li, li_, tri_);
939 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
940 /// from an implicit def to another register can be coalesced away.
941 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
943 LiveInterval &ImpLi) const{
944 if (!CopyMI->killsRegister(ImpLi.reg))
946 // Make sure this is the only use.
947 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
948 UE = mri_->use_end(); UI != UE;) {
949 MachineInstr *UseMI = &*UI;
951 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
959 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
960 /// a virtual destination register with physical source register.
962 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
963 MachineBasicBlock *CopyMBB,
964 LiveInterval &DstInt,
965 LiveInterval &SrcInt) {
966 // If the virtual register live interval is long but it has low use desity,
967 // do not join them, instead mark the physical register as its allocation
969 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
970 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
971 unsigned Length = li_->getApproximateInstructionCount(DstInt);
972 if (Length > Threshold &&
973 (((float)std::distance(mri_->use_begin(DstInt.reg),
974 mri_->use_end()) / Length) < (1.0 / Threshold)))
977 // If the virtual register live interval extends into a loop, turn down
979 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
980 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
982 // Let's see if the virtual register live interval extends into the loop.
983 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
984 assert(DLR != DstInt.end() && "Live range not found!");
985 DLR = DstInt.FindLiveRangeContaining(DLR->end+1);
986 if (DLR != DstInt.end()) {
987 CopyMBB = li_->getMBBFromIndex(DLR->start);
988 L = loopInfo->getLoopFor(CopyMBB);
992 if (!L || Length <= Threshold)
995 unsigned UseIdx = li_->getUseIndex(CopyIdx);
996 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
997 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
998 if (loopInfo->getLoopFor(SMBB) != L) {
999 if (!loopInfo->isLoopHeader(CopyMBB))
1001 // If vr's live interval extends pass the loop header, do not join.
1002 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1003 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1004 MachineBasicBlock *SuccMBB = *SI;
1005 if (SuccMBB == CopyMBB)
1007 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1008 li_->getMBBEndIdx(SuccMBB)+1))
1015 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1016 /// copy from a virtual source register to a physical destination register.
1018 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1019 MachineBasicBlock *CopyMBB,
1020 LiveInterval &DstInt,
1021 LiveInterval &SrcInt) {
1022 // If the virtual register live interval is long but it has low use desity,
1023 // do not join them, instead mark the physical register as its allocation
1025 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1026 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1027 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1028 if (Length > Threshold &&
1029 (((float)std::distance(mri_->use_begin(SrcInt.reg),
1030 mri_->use_end()) / Length) < (1.0 / Threshold)))
1034 // Must be implicit_def.
1037 // If the virtual register live interval is defined or cross a loop, turn
1038 // down aggressiveness.
1039 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1040 unsigned UseIdx = li_->getUseIndex(CopyIdx);
1041 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1042 assert(SLR != SrcInt.end() && "Live range not found!");
1043 SLR = SrcInt.FindLiveRangeContaining(SLR->start-1);
1044 if (SLR == SrcInt.end())
1046 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1047 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1049 if (!L || Length <= Threshold)
1052 if (loopInfo->getLoopFor(CopyMBB) != L) {
1053 if (SMBB != L->getLoopLatch())
1055 // If vr's live interval is extended from before the loop latch, do not
1057 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1058 PE = SMBB->pred_end(); PI != PE; ++PI) {
1059 MachineBasicBlock *PredMBB = *PI;
1060 if (PredMBB == SMBB)
1062 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1063 li_->getMBBEndIdx(PredMBB)+1))
1070 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1071 /// two virtual registers from different register classes.
1073 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned LargeReg,
1075 unsigned Threshold) {
1076 // Then make sure the intervals are *short*.
1077 LiveInterval &LargeInt = li_->getInterval(LargeReg);
1078 LiveInterval &SmallInt = li_->getInterval(SmallReg);
1079 unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
1080 unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
1081 if (SmallSize > Threshold || LargeSize > Threshold)
1082 if ((float)std::distance(mri_->use_begin(SmallReg),
1083 mri_->use_end()) / SmallSize <
1084 (float)std::distance(mri_->use_begin(LargeReg),
1085 mri_->use_end()) / LargeSize)
1090 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1091 /// register with a physical register, check if any of the virtual register
1092 /// operand is a sub-register use or def. If so, make sure it won't result
1093 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1094 /// vr1024 = extract_subreg vr1025, 1
1096 /// vr1024 = mov8rr AH
1097 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1098 /// AH does not have a super-reg whose sub-register 1 is AH.
1100 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1103 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1104 E = mri_->reg_end(); I != E; ++I) {
1105 MachineOperand &O = I.getOperand();
1106 MachineInstr *MI = &*I;
1107 if (MI == CopyMI || JoinedCopies.count(MI))
1109 unsigned SubIdx = O.getSubReg();
1110 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1112 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1113 SubIdx = MI->getOperand(2).getImm();
1114 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1117 unsigned SrcReg = MI->getOperand(1).getReg();
1118 const TargetRegisterClass *RC =
1119 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1120 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1121 : mri_->getRegClass(SrcReg);
1122 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1126 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
1127 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
1128 SubIdx = MI->getOperand(3).getImm();
1129 if (VirtReg == MI->getOperand(0).getReg()) {
1130 if (!tri_->getSubReg(PhysReg, SubIdx))
1133 unsigned DstReg = MI->getOperand(0).getReg();
1134 const TargetRegisterClass *RC =
1135 TargetRegisterInfo::isPhysicalRegister(DstReg)
1136 ? tri_->getPhysicalRegisterRegClass(DstReg)
1137 : mri_->getRegClass(DstReg);
1138 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1147 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1148 /// an extract_subreg where dst is a physical register, e.g.
1149 /// cl = EXTRACT_SUBREG reg1024, 1
1151 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1152 unsigned SrcReg, unsigned SubIdx,
1153 unsigned &RealDstReg) {
1154 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1155 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1156 assert(RealDstReg && "Invalid extract_subreg instruction!");
1158 // For this type of EXTRACT_SUBREG, conservatively
1159 // check if the live interval of the source register interfere with the
1160 // actual super physical register we are trying to coalesce with.
1161 LiveInterval &RHS = li_->getInterval(SrcReg);
1162 if (li_->hasInterval(RealDstReg) &&
1163 RHS.overlaps(li_->getInterval(RealDstReg))) {
1164 DOUT << "Interfere with register ";
1165 DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
1166 return false; // Not coalescable
1168 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1169 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1170 DOUT << "Interfere with sub-register ";
1171 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1172 return false; // Not coalescable
1177 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1178 /// an insert_subreg where src is a physical register, e.g.
1179 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1181 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1182 unsigned SrcReg, unsigned SubIdx,
1183 unsigned &RealSrcReg) {
1184 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1185 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1186 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1188 LiveInterval &RHS = li_->getInterval(DstReg);
1189 if (li_->hasInterval(RealSrcReg) &&
1190 RHS.overlaps(li_->getInterval(RealSrcReg))) {
1191 DOUT << "Interfere with register ";
1192 DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
1193 return false; // Not coalescable
1195 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1196 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1197 DOUT << "Interfere with sub-register ";
1198 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1199 return false; // Not coalescable
1204 /// getRegAllocPreference - Return register allocation preference register.
1206 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1207 MachineRegisterInfo *MRI,
1208 const TargetRegisterInfo *TRI) {
1209 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1211 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1212 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1215 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1216 /// which are the src/dst of the copy instruction CopyMI. This returns true
1217 /// if the copy was successfully coalesced away. If it is not currently
1218 /// possible to coalesce this interval, but it may be possible if other
1219 /// things get coalesced, then it returns true by reference in 'Again'.
1220 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1221 MachineInstr *CopyMI = TheCopy.MI;
1224 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1225 return false; // Already done.
1227 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1229 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1230 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1231 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1232 bool isSubRegToReg = CopyMI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG;
1233 unsigned SubIdx = 0;
1235 DstReg = CopyMI->getOperand(0).getReg();
1236 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1237 SrcReg = CopyMI->getOperand(1).getReg();
1238 SrcSubIdx = CopyMI->getOperand(2).getImm();
1239 } else if (isInsSubReg || isSubRegToReg) {
1240 DstReg = CopyMI->getOperand(0).getReg();
1241 DstSubIdx = CopyMI->getOperand(3).getImm();
1242 SrcReg = CopyMI->getOperand(2).getReg();
1243 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1244 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1245 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1246 // coalesced to a larger register so the subreg indices cancel out.
1247 DOUT << "\tSource of insert_subreg is already coalesced "
1248 << "to another register.\n";
1249 return false; // Not coalescable.
1251 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
1252 llvm_unreachable("Unrecognized copy instruction!");
1255 // If they are already joined we continue.
1256 if (SrcReg == DstReg) {
1257 DOUT << "\tCopy already coalesced.\n";
1258 return false; // Not coalescable.
1261 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1262 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1264 // If they are both physical registers, we cannot join them.
1265 if (SrcIsPhys && DstIsPhys) {
1266 DOUT << "\tCan not coalesce physregs.\n";
1267 return false; // Not coalescable.
1270 // We only join virtual registers with allocatable physical registers.
1271 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1272 DOUT << "\tSrc reg is unallocatable physreg.\n";
1273 return false; // Not coalescable.
1275 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1276 DOUT << "\tDst reg is unallocatable physreg.\n";
1277 return false; // Not coalescable.
1280 // Check that a physical source register is compatible with dst regclass
1282 unsigned SrcSubReg = SrcSubIdx ?
1283 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1284 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1285 const TargetRegisterClass *DstSubRC = DstRC;
1287 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1288 assert(DstSubRC && "Illegal subregister index");
1289 if (!DstSubRC->contains(SrcSubReg)) {
1290 DOUT << "\tIncompatible destination regclass: "
1291 << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
1293 return false; // Not coalescable.
1297 // Check that a physical dst register is compatible with source regclass
1299 unsigned DstSubReg = DstSubIdx ?
1300 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1301 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1302 const TargetRegisterClass *SrcSubRC = SrcRC;
1304 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1305 assert(SrcSubRC && "Illegal subregister index");
1306 if (!SrcSubRC->contains(DstReg)) {
1307 DOUT << "\tIncompatible source regclass: "
1308 << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
1310 return false; // Not coalescable.
1314 // Should be non-null only when coalescing to a sub-register class.
1315 bool CrossRC = false;
1316 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1317 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1318 const TargetRegisterClass *NewRC = NULL;
1319 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1320 unsigned RealDstReg = 0;
1321 unsigned RealSrcReg = 0;
1322 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1323 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1324 if (SrcIsPhys && isExtSubReg) {
1325 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1326 // coalesced with AX.
1327 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1329 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1330 // coalesced to a larger register so the subreg indices cancel out.
1331 if (DstSubIdx != SubIdx) {
1332 DOUT << "\t Sub-register indices mismatch.\n";
1333 return false; // Not coalescable.
1336 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1338 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1339 // EAX = INSERT_SUBREG EAX, r1024, 0
1340 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1342 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1343 // coalesced to a larger register so the subreg indices cancel out.
1344 if (SrcSubIdx != SubIdx) {
1345 DOUT << "\t Sub-register indices mismatch.\n";
1346 return false; // Not coalescable.
1349 DstReg = tri_->getSubReg(DstReg, SubIdx);
1351 } else if ((DstIsPhys && isExtSubReg) ||
1352 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1353 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1354 DOUT << "\tSrc of extract_subreg already coalesced with reg"
1355 << " of a super-class.\n";
1356 return false; // Not coalescable.
1360 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1361 return false; // Not coalescable
1363 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1364 return false; // Not coalescable
1368 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1369 : CopyMI->getOperand(2).getSubReg();
1371 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1372 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1373 // coalesced to a larger register so the subreg indices cancel out.
1374 // Also check if the other larger register is of the same register
1375 // class as the would be resulting register.
1378 DOUT << "\t Sub-register indices mismatch.\n";
1379 return false; // Not coalescable.
1383 if (!DstIsPhys && !SrcIsPhys) {
1384 if (isInsSubReg || isSubRegToReg) {
1385 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1386 } else // extract_subreg {
1387 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1390 DOUT << "\t Conflicting sub-register indices.\n";
1391 return false; // Not coalescable
1394 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1395 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1396 unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
1397 if (!isWinToJoinCrossClass(LargeReg, SmallReg, Limit)) {
1398 Again = true; // May be possible to coalesce later.
1403 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1404 if (DisableCrossClassJoin)
1408 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1409 // with another? If it's the resulting destination register, then
1410 // the subidx must be propagated to uses (but only those defined
1411 // by the EXTRACT_SUBREG). If it's being coalesced into another
1412 // register, it should be safe because register is assumed to have
1413 // the register class of the super-register.
1415 // Process moves where one of the registers have a sub-register index.
1416 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1417 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1418 SubIdx = DstMO->getSubReg();
1420 if (SrcMO->getSubReg())
1421 // FIXME: can we handle this?
1423 // This is not an insert_subreg but it looks like one.
1424 // e.g. %reg1024:4 = MOV32rr %EAX
1427 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1428 return false; // Not coalescable
1432 SubIdx = SrcMO->getSubReg();
1434 // This is not a extract_subreg but it looks like one.
1435 // e.g. %cl = MOV16rr %reg1024:1
1438 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1439 return false; // Not coalescable
1445 unsigned LargeReg = SrcReg;
1446 unsigned SmallReg = DstReg;
1448 // Now determine the register class of the joined register.
1450 if (SubIdx && DstRC && DstRC->isASubClass()) {
1451 // This is a move to a sub-register class. However, the source is a
1452 // sub-register of a larger register class. We don't know what should
1453 // the register class be. FIXME.
1457 if (!DstIsPhys && !SrcIsPhys)
1459 } else if (!SrcIsPhys && !DstIsPhys) {
1460 NewRC = getCommonSubClass(SrcRC, DstRC);
1462 DOUT << "\tDisjoint regclasses: "
1463 << SrcRC->getName() << ", "
1464 << DstRC->getName() << ".\n";
1465 return false; // Not coalescable.
1467 if (DstRC->getSize() > SrcRC->getSize())
1468 std::swap(LargeReg, SmallReg);
1471 // If we are joining two virtual registers and the resulting register
1472 // class is more restrictive (fewer register, smaller size). Check if it's
1473 // worth doing the merge.
1474 if (!SrcIsPhys && !DstIsPhys &&
1475 (isExtSubReg || DstRC->isASubClass()) &&
1476 !isWinToJoinCrossClass(LargeReg, SmallReg,
1477 allocatableRCRegs_[NewRC].count())) {
1478 DOUT << "\tSrc/Dest are different register classes.\n";
1479 // Allow the coalescer to try again in case either side gets coalesced to
1480 // a physical register that's compatible with the other side. e.g.
1481 // r1024 = MOV32to32_ r1025
1482 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1483 Again = true; // May be possible to coalesce later.
1488 // Will it create illegal extract_subreg / insert_subreg?
1489 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1491 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1494 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1495 LiveInterval &DstInt = li_->getInterval(DstReg);
1496 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1497 "Register mapping is horribly broken!");
1499 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1500 DOUT << " and "; DstInt.print(DOUT, tri_);
1503 // Save a copy of the virtual register live interval. We'll manually
1504 // merge this into the "real" physical register live interval this is
1506 LiveInterval *SavedLI = 0;
1508 SavedLI = li_->dupInterval(&SrcInt);
1509 else if (RealSrcReg)
1510 SavedLI = li_->dupInterval(&DstInt);
1512 // Check if it is necessary to propagate "isDead" property.
1513 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1514 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1515 bool isDead = mopd->isDead();
1517 // We need to be careful about coalescing a source physical register with a
1518 // virtual register. Once the coalescing is done, it cannot be broken and
1519 // these are not spillable! If the destination interval uses are far away,
1520 // think twice about coalescing them!
1521 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1522 // If the copy is in a loop, take care not to coalesce aggressively if the
1523 // src is coming in from outside the loop (or the dst is out of the loop).
1524 // If it's not in a loop, then determine whether to join them base purely
1525 // by the length of the interval.
1526 if (PhysJoinTweak) {
1528 if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1529 mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
1531 DOUT << "\tMay tie down a physical register, abort!\n";
1532 Again = true; // May be possible to coalesce later.
1536 if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
1537 mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
1539 DOUT << "\tMay tie down a physical register, abort!\n";
1540 Again = true; // May be possible to coalesce later.
1545 // If the virtual register live interval is long but it has low use desity,
1546 // do not join them, instead mark the physical register as its allocation
1548 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1549 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1550 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1551 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1552 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1553 if (TheCopy.isBackEdge)
1554 Threshold *= 2; // Favors back edge copies.
1556 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1557 float Ratio = 1.0 / Threshold;
1558 if (Length > Threshold &&
1559 (((float)std::distance(mri_->use_begin(JoinVReg),
1560 mri_->use_end()) / Length) < Ratio)) {
1561 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1563 DOUT << "\tMay tie down a physical register, abort!\n";
1564 Again = true; // May be possible to coalesce later.
1571 // Okay, attempt to join these two intervals. On failure, this returns false.
1572 // Otherwise, if one of the intervals being joined is a physreg, this method
1573 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1574 // been modified, so we can use this information below to update aliases.
1575 bool Swapped = false;
1576 // If SrcInt is implicitly defined, it's safe to coalesce.
1577 bool isEmpty = SrcInt.empty();
1578 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1579 // Only coalesce an empty interval (defined by implicit_def) with
1580 // another interval which has a valno defined by the CopyMI and the CopyMI
1581 // is a kill of the implicit def.
1582 DOUT << "Not profitable!\n";
1586 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1587 // Coalescing failed.
1589 // If definition of source is defined by trivial computation, try
1590 // rematerializing it.
1591 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1592 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1595 // If we can eliminate the copy without merging the live ranges, do so now.
1596 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1597 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1598 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1599 JoinedCopies.insert(CopyMI);
1603 // Otherwise, we are unable to join the intervals.
1604 DOUT << "Interference!\n";
1605 Again = true; // May be possible to coalesce later.
1609 LiveInterval *ResSrcInt = &SrcInt;
1610 LiveInterval *ResDstInt = &DstInt;
1612 std::swap(SrcReg, DstReg);
1613 std::swap(ResSrcInt, ResDstInt);
1615 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1616 "LiveInterval::join didn't work right!");
1618 // If we're about to merge live ranges into a physical register live interval,
1619 // we have to update any aliased register's live ranges to indicate that they
1620 // have clobbered values for this range.
1621 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1622 // If this is a extract_subreg where dst is a physical register, e.g.
1623 // cl = EXTRACT_SUBREG reg1024, 1
1624 // then create and update the actual physical register allocated to RHS.
1625 if (RealDstReg || RealSrcReg) {
1626 LiveInterval &RealInt =
1627 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1628 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1629 E = SavedLI->vni_end(); I != E; ++I) {
1630 const VNInfo *ValNo = *I;
1631 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy,
1632 false, // updated at *
1633 li_->getVNInfoAllocator());
1634 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1635 RealInt.addKills(NewValNo, ValNo->kills);
1636 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1638 RealInt.weight += SavedLI->weight;
1639 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1642 // Update the liveintervals of sub-registers.
1643 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1644 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1645 li_->getVNInfoAllocator());
1648 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1649 // larger super-register.
1650 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1651 !SrcIsPhys && !DstIsPhys) {
1652 if ((isExtSubReg && !Swapped) ||
1653 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1654 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1655 std::swap(SrcReg, DstReg);
1656 std::swap(ResSrcInt, ResDstInt);
1660 // Coalescing to a virtual register that is of a sub-register class of the
1661 // other. Make sure the resulting register is set to the right register class.
1665 // This may happen even if it's cross-rc coalescing. e.g.
1666 // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
1667 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1668 // be allocate a register from GR64_ABCD.
1670 mri_->setRegClass(DstReg, NewRC);
1673 // Add all copies that define val# in the source interval into the queue.
1674 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1675 e = ResSrcInt->vni_end(); i != e; ++i) {
1676 const VNInfo *vni = *i;
1677 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1678 if (!vni->def || vni->isUnused() || vni->isPHIDef() || !vni->isDefAccurate())
1680 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1681 unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
1683 JoinedCopies.count(CopyMI) == 0 &&
1684 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
1685 NewSrcSubIdx, NewDstSubIdx)) {
1686 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1687 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1688 isBackEdgeCopy(CopyMI, DstReg)));
1693 // Remember to delete the copy instruction.
1694 JoinedCopies.insert(CopyMI);
1696 // Some live range has been lengthened due to colaescing, eliminate the
1697 // unnecessary kills.
1698 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1699 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1700 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1702 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1704 // SrcReg is guarateed to be the register whose live interval that is
1706 li_->removeInterval(SrcReg);
1708 // Update regalloc hint.
1709 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1711 // Manually deleted the live interval copy.
1717 // If resulting interval has a preference that no longer fits because of subreg
1718 // coalescing, just clear the preference.
1719 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1720 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1721 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1722 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1723 if (!RC->contains(Preference))
1724 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1727 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1734 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1735 /// compute what the resultant value numbers for each value in the input two
1736 /// ranges will be. This is complicated by copies between the two which can
1737 /// and will commonly cause multiple value numbers to be merged into one.
1739 /// VN is the value number that we're trying to resolve. InstDefiningValue
1740 /// keeps track of the new InstDefiningValue assignment for the result
1741 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1742 /// whether a value in this or other is a copy from the opposite set.
1743 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1744 /// already been assigned.
1746 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1747 /// contains the value number the copy is from.
1749 static unsigned ComputeUltimateVN(VNInfo *VNI,
1750 SmallVector<VNInfo*, 16> &NewVNInfo,
1751 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1752 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1753 SmallVector<int, 16> &ThisValNoAssignments,
1754 SmallVector<int, 16> &OtherValNoAssignments) {
1755 unsigned VN = VNI->id;
1757 // If the VN has already been computed, just return it.
1758 if (ThisValNoAssignments[VN] >= 0)
1759 return ThisValNoAssignments[VN];
1760 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1762 // If this val is not a copy from the other val, then it must be a new value
1763 // number in the destination.
1764 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1765 if (I == ThisFromOther.end()) {
1766 NewVNInfo.push_back(VNI);
1767 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1769 VNInfo *OtherValNo = I->second;
1771 // Otherwise, this *is* a copy from the RHS. If the other side has already
1772 // been computed, return it.
1773 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1774 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1776 // Mark this value number as currently being computed, then ask what the
1777 // ultimate value # of the other value is.
1778 ThisValNoAssignments[VN] = -2;
1779 unsigned UltimateVN =
1780 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1781 OtherValNoAssignments, ThisValNoAssignments);
1782 return ThisValNoAssignments[VN] = UltimateVN;
1785 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1786 return std::find(V.begin(), V.end(), Val) != V.end();
1789 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1790 /// the specified live interval is defined by a copy from the specified
1792 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1795 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1798 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1799 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1800 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1801 *tri_->getSuperRegisters(li.reg)) {
1802 // It's a sub-register live interval, we may not have precise information.
1804 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1805 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1807 tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
1808 DstReg == li.reg && SrcReg == Reg) {
1809 // Cache computed info.
1810 LR->valno->def = LR->start;
1811 LR->valno->copy = DefMI;
1818 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1819 /// caller of this method must guarantee that the RHS only contains a single
1820 /// value number and that the RHS is not defined by a copy from this
1821 /// interval. This returns false if the intervals are not joinable, or it
1822 /// joins them and returns true.
1823 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1824 assert(RHS.containsOneValue());
1826 // Some number (potentially more than one) value numbers in the current
1827 // interval may be defined as copies from the RHS. Scan the overlapping
1828 // portions of the LHS and RHS, keeping track of this and looking for
1829 // overlapping live ranges that are NOT defined as copies. If these exist, we
1832 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1833 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1835 if (LHSIt->start < RHSIt->start) {
1836 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1837 if (LHSIt != LHS.begin()) --LHSIt;
1838 } else if (RHSIt->start < LHSIt->start) {
1839 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1840 if (RHSIt != RHS.begin()) --RHSIt;
1843 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1846 // Determine if these live intervals overlap.
1847 bool Overlaps = false;
1848 if (LHSIt->start <= RHSIt->start)
1849 Overlaps = LHSIt->end > RHSIt->start;
1851 Overlaps = RHSIt->end > LHSIt->start;
1853 // If the live intervals overlap, there are two interesting cases: if the
1854 // LHS interval is defined by a copy from the RHS, it's ok and we record
1855 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1856 // coalesce these live ranges and we bail out.
1858 // If we haven't already recorded that this value # is safe, check it.
1859 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1860 // Copy from the RHS?
1861 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1862 return false; // Nope, bail out.
1864 if (LHSIt->contains(RHSIt->valno->def))
1865 // Here is an interesting situation:
1867 // vr1025 = copy vr1024
1872 // Even though vr1025 is copied from vr1024, it's not safe to
1873 // coalesce them since the live range of vr1025 intersects the
1874 // def of vr1024. This happens because vr1025 is assigned the
1875 // value of the previous iteration of vr1024.
1877 EliminatedLHSVals.push_back(LHSIt->valno);
1880 // We know this entire LHS live range is okay, so skip it now.
1881 if (++LHSIt == LHSEnd) break;
1885 if (LHSIt->end < RHSIt->end) {
1886 if (++LHSIt == LHSEnd) break;
1888 // One interesting case to check here. It's possible that we have
1889 // something like "X3 = Y" which defines a new value number in the LHS,
1890 // and is the last use of this liverange of the RHS. In this case, we
1891 // want to notice this copy (so that it gets coalesced away) even though
1892 // the live ranges don't actually overlap.
1893 if (LHSIt->start == RHSIt->end) {
1894 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1895 // We already know that this value number is going to be merged in
1896 // if coalescing succeeds. Just skip the liverange.
1897 if (++LHSIt == LHSEnd) break;
1899 // Otherwise, if this is a copy from the RHS, mark it as being merged
1901 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1902 if (LHSIt->contains(RHSIt->valno->def))
1903 // Here is an interesting situation:
1905 // vr1025 = copy vr1024
1910 // Even though vr1025 is copied from vr1024, it's not safe to
1911 // coalesced them since live range of vr1025 intersects the
1912 // def of vr1024. This happens because vr1025 is assigned the
1913 // value of the previous iteration of vr1024.
1915 EliminatedLHSVals.push_back(LHSIt->valno);
1917 // We know this entire LHS live range is okay, so skip it now.
1918 if (++LHSIt == LHSEnd) break;
1923 if (++RHSIt == RHSEnd) break;
1927 // If we got here, we know that the coalescing will be successful and that
1928 // the value numbers in EliminatedLHSVals will all be merged together. Since
1929 // the most common case is that EliminatedLHSVals has a single number, we
1930 // optimize for it: if there is more than one value, we merge them all into
1931 // the lowest numbered one, then handle the interval as if we were merging
1932 // with one value number.
1933 VNInfo *LHSValNo = NULL;
1934 if (EliminatedLHSVals.size() > 1) {
1935 // Loop through all the equal value numbers merging them into the smallest
1937 VNInfo *Smallest = EliminatedLHSVals[0];
1938 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1939 if (EliminatedLHSVals[i]->id < Smallest->id) {
1940 // Merge the current notion of the smallest into the smaller one.
1941 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1942 Smallest = EliminatedLHSVals[i];
1944 // Merge into the smallest.
1945 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1948 LHSValNo = Smallest;
1949 } else if (EliminatedLHSVals.empty()) {
1950 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1951 *tri_->getSuperRegisters(LHS.reg))
1952 // Imprecise sub-register information. Can't handle it.
1954 llvm_unreachable("No copies from the RHS?");
1956 LHSValNo = EliminatedLHSVals[0];
1959 // Okay, now that there is a single LHS value number that we're merging the
1960 // RHS into, update the value number info for the LHS to indicate that the
1961 // value number is defined where the RHS value number was.
1962 const VNInfo *VNI = RHS.getValNumInfo(0);
1963 LHSValNo->def = VNI->def;
1964 LHSValNo->copy = VNI->copy;
1966 // Okay, the final step is to loop over the RHS live intervals, adding them to
1968 if (VNI->hasPHIKill())
1969 LHSValNo->setHasPHIKill(true);
1970 LHS.addKills(LHSValNo, VNI->kills);
1971 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1973 // If either of these intervals was spilled, the weight is the
1974 // weight of the non-spilled interval. This can only happen
1975 // with iterative coalescers.
1976 if (LHS.weight == HUGE_VALF && !TargetRegisterInfo::isPhysicalRegister(LHS.reg)) {
1977 // Remove this assert if you have an iterative coalescer
1978 assert(0 && "Joining to spilled interval");
1979 LHS.weight = RHS.weight;
1981 else if (RHS.weight != HUGE_VALF) {
1982 LHS.weight += RHS.weight;
1985 // Remove this assert if you have an iterative coalescer
1986 assert(0 && "Joining from spilled interval");
1989 // Otherwise the LHS weight stays the same
1991 // Update regalloc hint if both are virtual registers.
1992 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
1993 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
1994 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
1995 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
1996 if (RHSPref != LHSPref)
1997 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2000 // Update the liveintervals of sub-registers.
2001 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2002 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2003 li_->getOrCreateInterval(*AS).MergeInClobberRanges(LHS,
2004 li_->getVNInfoAllocator());
2009 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2010 /// returns false. Otherwise, if one of the intervals being joined is a
2011 /// physreg, this method always canonicalizes LHS to be it. The output
2012 /// "RHS" will not have been modified, so we can use this information
2013 /// below to update aliases.
2015 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2017 // Compute the final value assignment, assuming that the live ranges can be
2019 SmallVector<int, 16> LHSValNoAssignments;
2020 SmallVector<int, 16> RHSValNoAssignments;
2021 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2022 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2023 SmallVector<VNInfo*, 16> NewVNInfo;
2025 // If a live interval is a physical register, conservatively check if any
2026 // of its sub-registers is overlapping the live interval of the virtual
2027 // register. If so, do not coalesce.
2028 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2029 *tri_->getSubRegisters(LHS.reg)) {
2030 // If it's coalescing a virtual register to a physical register, estimate
2031 // its live interval length. This is the *cost* of scanning an entire live
2032 // interval. If the cost is low, we'll do an exhaustive check instead.
2034 // If this is something like this:
2042 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2043 // less conservative check. It's possible a sub-register is defined before
2044 // v1024 (or live in) and live out of BB1.
2045 if (RHS.containsOneValue() &&
2046 li_->intervalIsInOneMBB(RHS) &&
2047 li_->getApproximateInstructionCount(RHS) <= 10) {
2048 // Perform a more exhaustive check for some common cases.
2049 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2052 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2053 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2054 DOUT << "Interfere with sub-register ";
2055 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2059 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2060 *tri_->getSubRegisters(RHS.reg)) {
2061 if (LHS.containsOneValue() &&
2062 li_->getApproximateInstructionCount(LHS) <= 10) {
2063 // Perform a more exhaustive check for some common cases.
2064 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2067 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2068 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2069 DOUT << "Interfere with sub-register ";
2070 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
2076 // Compute ultimate value numbers for the LHS and RHS values.
2077 if (RHS.containsOneValue()) {
2078 // Copies from a liveinterval with a single value are simple to handle and
2079 // very common, handle the special case here. This is important, because
2080 // often RHS is small and LHS is large (e.g. a physreg).
2082 // Find out if the RHS is defined as a copy from some value in the LHS.
2083 int RHSVal0DefinedFromLHS = -1;
2085 VNInfo *RHSValNoInfo = NULL;
2086 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2087 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2088 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2089 // If RHS is not defined as a copy from the LHS, we can use simpler and
2090 // faster checks to see if the live ranges are coalescable. This joiner
2091 // can't swap the LHS/RHS intervals though.
2092 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2093 return SimpleJoin(LHS, RHS);
2095 RHSValNoInfo = RHSValNoInfo0;
2098 // It was defined as a copy from the LHS, find out what value # it is.
2099 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
2100 RHSValID = RHSValNoInfo->id;
2101 RHSVal0DefinedFromLHS = RHSValID;
2104 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2105 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2106 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2108 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2109 // should now get updated.
2110 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2113 unsigned VN = VNI->id;
2114 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2115 if (LHSSrcReg != RHS.reg) {
2116 // If this is not a copy from the RHS, its value number will be
2117 // unmodified by the coalescing.
2118 NewVNInfo[VN] = VNI;
2119 LHSValNoAssignments[VN] = VN;
2120 } else if (RHSValID == -1) {
2121 // Otherwise, it is a copy from the RHS, and we don't already have a
2122 // value# for it. Keep the current value number, but remember it.
2123 LHSValNoAssignments[VN] = RHSValID = VN;
2124 NewVNInfo[VN] = RHSValNoInfo;
2125 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2127 // Otherwise, use the specified value #.
2128 LHSValNoAssignments[VN] = RHSValID;
2129 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2130 NewVNInfo[VN] = RHSValNoInfo;
2131 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2135 NewVNInfo[VN] = VNI;
2136 LHSValNoAssignments[VN] = VN;
2140 assert(RHSValID != -1 && "Didn't find value #?");
2141 RHSValNoAssignments[0] = RHSValID;
2142 if (RHSVal0DefinedFromLHS != -1) {
2143 // This path doesn't go through ComputeUltimateVN so just set
2145 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2148 // Loop over the value numbers of the LHS, seeing if any are defined from
2150 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2153 if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
2156 // DstReg is known to be a register in the LHS interval. If the src is
2157 // from the RHS interval, we can use its value #.
2158 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2161 // Figure out the value # from the RHS.
2162 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
2165 // Loop over the value numbers of the RHS, seeing if any are defined from
2167 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2170 if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
2173 // DstReg is known to be a register in the RHS interval. If the src is
2174 // from the LHS interval, we can use its value #.
2175 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2178 // Figure out the value # from the LHS.
2179 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
2182 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2183 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2184 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2186 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2189 unsigned VN = VNI->id;
2190 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2192 ComputeUltimateVN(VNI, NewVNInfo,
2193 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2194 LHSValNoAssignments, RHSValNoAssignments);
2196 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2199 unsigned VN = VNI->id;
2200 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2202 // If this value number isn't a copy from the LHS, it's a new number.
2203 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2204 NewVNInfo.push_back(VNI);
2205 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2209 ComputeUltimateVN(VNI, NewVNInfo,
2210 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2211 RHSValNoAssignments, LHSValNoAssignments);
2215 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2216 // interval lists to see if these intervals are coalescable.
2217 LiveInterval::const_iterator I = LHS.begin();
2218 LiveInterval::const_iterator IE = LHS.end();
2219 LiveInterval::const_iterator J = RHS.begin();
2220 LiveInterval::const_iterator JE = RHS.end();
2222 // Skip ahead until the first place of potential sharing.
2223 if (I->start < J->start) {
2224 I = std::upper_bound(I, IE, J->start);
2225 if (I != LHS.begin()) --I;
2226 } else if (J->start < I->start) {
2227 J = std::upper_bound(J, JE, I->start);
2228 if (J != RHS.begin()) --J;
2232 // Determine if these two live ranges overlap.
2234 if (I->start < J->start) {
2235 Overlaps = I->end > J->start;
2237 Overlaps = J->end > I->start;
2240 // If so, check value # info to determine if they are really different.
2242 // If the live range overlap will map to the same value number in the
2243 // result liverange, we can still coalesce them. If not, we can't.
2244 if (LHSValNoAssignments[I->valno->id] !=
2245 RHSValNoAssignments[J->valno->id])
2249 if (I->end < J->end) {
2258 // Update kill info. Some live ranges are extended due to copy coalescing.
2259 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2260 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2261 VNInfo *VNI = I->first;
2262 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2263 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
2264 if (VNI->hasPHIKill())
2265 NewVNInfo[LHSValID]->setHasPHIKill(true);
2266 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2269 // Update kill info. Some live ranges are extended due to copy coalescing.
2270 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2271 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2272 VNInfo *VNI = I->first;
2273 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2274 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
2275 if (VNI->hasPHIKill())
2276 NewVNInfo[RHSValID]->setHasPHIKill(true);
2277 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2280 // If we get here, we know that we can coalesce the live ranges. Ask the
2281 // intervals to coalesce themselves now.
2282 if ((RHS.ranges.size() > LHS.ranges.size() &&
2283 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2284 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2285 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2289 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2297 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2298 // depth of the basic block (the unsigned), and then on the MBB number.
2299 struct DepthMBBCompare {
2300 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2301 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2302 if (LHS.first > RHS.first) return true; // Deeper loops first
2303 return LHS.first == RHS.first &&
2304 LHS.second->getNumber() < RHS.second->getNumber();
2309 /// getRepIntervalSize - Returns the size of the interval that represents the
2310 /// specified register.
2312 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2313 return Rc->getRepIntervalSize(Reg);
2316 /// CopyRecSort::operator - Join priority queue sorting function.
2318 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2319 // Inner loops first.
2320 if (left.LoopDepth > right.LoopDepth)
2322 else if (left.LoopDepth == right.LoopDepth)
2323 if (left.isBackEdge && !right.isBackEdge)
2328 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2329 std::vector<CopyRec> &TryAgain) {
2330 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2332 std::vector<CopyRec> VirtCopies;
2333 std::vector<CopyRec> PhysCopies;
2334 std::vector<CopyRec> ImpDefCopies;
2335 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2336 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2338 MachineInstr *Inst = MII++;
2340 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2341 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2342 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2343 DstReg = Inst->getOperand(0).getReg();
2344 SrcReg = Inst->getOperand(1).getReg();
2345 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2346 Inst->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
2347 DstReg = Inst->getOperand(0).getReg();
2348 SrcReg = Inst->getOperand(2).getReg();
2349 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2352 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2353 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2355 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2357 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2358 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2359 else if (SrcIsPhys || DstIsPhys)
2360 PhysCopies.push_back(CopyRec(Inst, 0, false));
2362 VirtCopies.push_back(CopyRec(Inst, 0, false));
2369 // Try coalescing implicit copies first, followed by copies to / from
2370 // physical registers, then finally copies from virtual registers to
2371 // virtual registers.
2372 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2373 CopyRec &TheCopy = ImpDefCopies[i];
2375 if (!JoinCopy(TheCopy, Again))
2377 TryAgain.push_back(TheCopy);
2379 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2380 CopyRec &TheCopy = PhysCopies[i];
2382 if (!JoinCopy(TheCopy, Again))
2384 TryAgain.push_back(TheCopy);
2386 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2387 CopyRec &TheCopy = VirtCopies[i];
2389 if (!JoinCopy(TheCopy, Again))
2391 TryAgain.push_back(TheCopy);
2395 void SimpleRegisterCoalescing::joinIntervals() {
2396 DOUT << "********** JOINING INTERVALS ***********\n";
2399 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2401 std::vector<CopyRec> TryAgainList;
2402 if (loopInfo->empty()) {
2403 // If there are no loops in the function, join intervals in function order.
2404 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2406 CopyCoalesceInMBB(I, TryAgainList);
2408 // Otherwise, join intervals in inner loops before other intervals.
2409 // Unfortunately we can't just iterate over loop hierarchy here because
2410 // there may be more MBB's than BB's. Collect MBB's for sorting.
2412 // Join intervals in the function prolog first. We want to join physical
2413 // registers with virtual registers before the intervals got too long.
2414 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2415 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2416 MachineBasicBlock *MBB = I;
2417 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2420 // Sort by loop depth.
2421 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2423 // Finally, join intervals in loop nest order.
2424 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2425 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2428 // Joining intervals can allow other intervals to be joined. Iteratively join
2429 // until we make no progress.
2431 SmallVector<CopyRec, 16> TryAgain;
2432 bool ProgressMade = true;
2433 while (ProgressMade) {
2434 ProgressMade = false;
2435 while (!JoinQueue->empty()) {
2436 CopyRec R = JoinQueue->pop();
2438 bool Success = JoinCopy(R, Again);
2440 ProgressMade = true;
2442 TryAgain.push_back(R);
2446 while (!TryAgain.empty()) {
2447 JoinQueue->push(TryAgain.back());
2448 TryAgain.pop_back();
2453 bool ProgressMade = true;
2454 while (ProgressMade) {
2455 ProgressMade = false;
2457 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2458 CopyRec &TheCopy = TryAgainList[i];
2461 bool Success = JoinCopy(TheCopy, Again);
2462 if (Success || !Again) {
2463 TheCopy.MI = 0; // Mark this one as done.
2464 ProgressMade = true;
2475 /// Return true if the two specified registers belong to different register
2476 /// classes. The registers may be either phys or virt regs.
2478 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2479 unsigned RegB) const {
2480 // Get the register classes for the first reg.
2481 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2482 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2483 "Shouldn't consider two physregs!");
2484 return !mri_->getRegClass(RegB)->contains(RegA);
2487 // Compare against the regclass for the second reg.
2488 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2489 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2490 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2491 return RegClassA != RegClassB;
2493 return !RegClassA->contains(RegB);
2496 /// lastRegisterUse - Returns the last use of the specific register between
2497 /// cycles Start and End or NULL if there are no uses.
2499 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2500 unsigned Reg, unsigned &UseIdx) const{
2502 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2503 MachineOperand *LastUse = NULL;
2504 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2505 E = mri_->use_end(); I != E; ++I) {
2506 MachineOperand &Use = I.getOperand();
2507 MachineInstr *UseMI = Use.getParent();
2508 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2509 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2511 // Ignore identity copies.
2513 unsigned Idx = li_->getInstructionIndex(UseMI);
2514 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2516 UseIdx = li_->getUseIndex(Idx);
2522 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2525 // Skip deleted instructions
2526 MachineInstr *MI = li_->getInstructionFromIndex(e);
2527 while ((e - InstrSlots::NUM) >= s && !MI) {
2528 e -= InstrSlots::NUM;
2529 MI = li_->getInstructionFromIndex(e);
2531 if (e < s || MI == NULL)
2534 // Ignore identity copies.
2535 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2536 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2538 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2539 MachineOperand &Use = MI->getOperand(i);
2540 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2541 tri_->regsOverlap(Use.getReg(), Reg)) {
2542 UseIdx = li_->getUseIndex(e);
2547 e -= InstrSlots::NUM;
2554 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2555 if (TargetRegisterInfo::isPhysicalRegister(reg))
2556 cerr << tri_->getName(reg);
2558 cerr << "%reg" << reg;
2561 void SimpleRegisterCoalescing::releaseMemory() {
2562 JoinedCopies.clear();
2563 ReMatCopies.clear();
2567 static bool isZeroLengthInterval(LiveInterval *li) {
2568 for (LiveInterval::Ranges::const_iterator
2569 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2570 if (i->end - i->start > LiveInterval::InstrSlots::NUM)
2576 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2578 mri_ = &fn.getRegInfo();
2579 tm_ = &fn.getTarget();
2580 tri_ = tm_->getRegisterInfo();
2581 tii_ = tm_->getInstrInfo();
2582 li_ = &getAnalysis<LiveIntervals>();
2583 loopInfo = &getAnalysis<MachineLoopInfo>();
2585 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2586 << "********** Function: "
2587 << ((Value*)mf_->getFunction())->getName() << '\n';
2589 allocatableRegs_ = tri_->getAllocatableSet(fn);
2590 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2591 E = tri_->regclass_end(); I != E; ++I)
2592 allocatableRCRegs_.insert(std::make_pair(*I,
2593 tri_->getAllocatableSet(fn, *I)));
2595 // Join (coalesce) intervals if requested.
2596 if (EnableJoining) {
2599 DOUT << "********** INTERVALS POST JOINING **********\n";
2600 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2601 I->second->print(DOUT, tri_);
2607 // Perform a final pass over the instructions and compute spill weights
2608 // and remove identity moves.
2609 SmallVector<unsigned, 4> DeadDefs;
2610 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2611 mbbi != mbbe; ++mbbi) {
2612 MachineBasicBlock* mbb = mbbi;
2613 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2615 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2617 MachineInstr *MI = mii;
2618 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2619 if (JoinedCopies.count(MI)) {
2620 // Delete all coalesced copies.
2621 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2622 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2623 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
2624 MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
2625 "Unrecognized copy instruction");
2626 DstReg = MI->getOperand(0).getReg();
2628 if (MI->registerDefIsDead(DstReg)) {
2629 LiveInterval &li = li_->getInterval(DstReg);
2630 if (!ShortenDeadCopySrcLiveRange(li, MI))
2631 ShortenDeadCopyLiveRange(li, MI);
2633 li_->RemoveMachineInstrFromMaps(MI);
2634 mii = mbbi->erase(mii);
2639 // Now check if this is a remat'ed def instruction which is now dead.
2640 if (ReMatDefs.count(MI)) {
2642 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2643 const MachineOperand &MO = MI->getOperand(i);
2646 unsigned Reg = MO.getReg();
2649 if (TargetRegisterInfo::isVirtualRegister(Reg))
2650 DeadDefs.push_back(Reg);
2653 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2654 !mri_->use_empty(Reg)) {
2660 while (!DeadDefs.empty()) {
2661 unsigned DeadDef = DeadDefs.back();
2662 DeadDefs.pop_back();
2663 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2665 li_->RemoveMachineInstrFromMaps(mii);
2666 mii = mbbi->erase(mii);
2672 // If the move will be an identity move delete it
2673 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2674 if (isMove && SrcReg == DstReg) {
2675 if (li_->hasInterval(SrcReg)) {
2676 LiveInterval &RegInt = li_->getInterval(SrcReg);
2677 // If def of this move instruction is dead, remove its live range
2678 // from the dstination register's live interval.
2679 if (MI->registerDefIsDead(DstReg)) {
2680 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2681 ShortenDeadCopyLiveRange(RegInt, MI);
2684 li_->RemoveMachineInstrFromMaps(MI);
2685 mii = mbbi->erase(mii);
2688 SmallSet<unsigned, 4> UniqueUses;
2689 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2690 const MachineOperand &mop = MI->getOperand(i);
2691 if (mop.isReg() && mop.getReg() &&
2692 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2693 unsigned reg = mop.getReg();
2694 // Multiple uses of reg by the same instruction. It should not
2695 // contribute to spill weight again.
2696 if (UniqueUses.count(reg) != 0)
2698 LiveInterval &RegInt = li_->getInterval(reg);
2700 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2701 UniqueUses.insert(reg);
2709 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2710 LiveInterval &LI = *I->second;
2711 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2712 // If the live interval length is essentially zero, i.e. in every live
2713 // range the use follows def immediately, it doesn't make sense to spill
2714 // it and hope it will be easier to allocate for this li.
2715 if (isZeroLengthInterval(&LI))
2716 LI.weight = HUGE_VALF;
2718 bool isLoad = false;
2719 SmallVector<LiveInterval*, 4> SpillIs;
2720 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2721 // If all of the definitions of the interval are re-materializable,
2722 // it is a preferred candidate for spilling. If non of the defs are
2723 // loads, then it's potentially very cheap to re-materialize.
2724 // FIXME: this gets much more complicated once we support non-trivial
2725 // re-materialization.
2733 // Slightly prefer live interval that has been assigned a preferred reg.
2734 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
2735 if (Hint.first || Hint.second)
2738 // Divide the weight of the interval by its size. This encourages
2739 // spilling of intervals that are large and have few uses, and
2740 // discourages spilling of small intervals with many uses.
2741 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2749 /// print - Implement the dump method.
2750 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2754 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2755 return new SimpleRegisterCoalescing();
2758 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2759 DEFINING_FILE_FOR(SimpleRegisterCoalescing)