1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numSubJoins , "Number of subclass joins performed");
40 STATISTIC(numCommutes , "Number of instruction commuting performed");
41 STATISTIC(numExtends , "Number of copies extended");
42 STATISTIC(NumReMats , "Number of instructions re-materialized");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numAborts , "Number of times interval joining aborted");
46 char SimpleRegisterCoalescing::ID = 0;
48 EnableJoining("join-liveintervals",
49 cl::desc("Coalesce copies (default=true)"),
53 NewHeuristic("new-coalescer-heuristic",
54 cl::desc("Use new coalescer heuristic"),
55 cl::init(false), cl::Hidden);
58 CrossClassJoin("join-subclass-copies",
59 cl::desc("Coalesce copies to sub- register class"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<LiveIntervals>();
72 AU.addPreserved<LiveIntervals>();
73 AU.addRequired<MachineLoopInfo>();
74 AU.addPreserved<MachineLoopInfo>();
75 AU.addPreservedID(MachineDominatorsID);
77 AU.addPreservedID(StrongPHIEliminationID);
79 AU.addPreservedID(PHIEliminationID);
80 AU.addPreservedID(TwoAddressInstructionPassID);
81 MachineFunctionPass::getAnalysisUsage(AU);
84 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
85 /// being the source and IntB being the dest, thus this defines a value number
86 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
87 /// see if we can merge these two pieces of B into a single value number,
88 /// eliminating a copy. For example:
92 /// B1 = A3 <- this copy
94 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
95 /// value number to be replaced with B0 (which simplifies the B liveinterval).
97 /// This returns true if an interval was modified.
99 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
101 MachineInstr *CopyMI) {
102 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
104 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
105 // the example above.
106 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
107 if (BLR == IntB.end()) // Should never happen!
109 VNInfo *BValNo = BLR->valno;
111 // Get the location that B is defined at. Two options: either this value has
112 // an unknown definition point or it is defined at CopyIdx. If unknown, we
114 if (!BValNo->copy) return false;
115 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
117 // AValNo is the value number in A that defines the copy, A3 in the example.
118 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
119 if (ALR == IntA.end()) // Should never happen!
121 VNInfo *AValNo = ALR->valno;
123 // If AValNo is defined as a copy from IntB, we can potentially process this.
124 // Get the instruction that defines this value number.
125 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
126 if (!SrcReg) return false; // Not defined by a copy.
128 // If the value number is not defined by a copy instruction, ignore it.
130 // If the source register comes from an interval other than IntB, we can't
132 if (SrcReg != IntB.reg) return false;
134 // Get the LiveRange in IntB that this value number starts with.
135 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
136 if (ValLR == IntB.end()) // Should never happen!
139 // Make sure that the end of the live range is inside the same block as
141 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
143 ValLREndInst->getParent() != CopyMI->getParent()) return false;
145 // Okay, we now know that ValLR ends in the same block that the CopyMI
146 // live-range starts. If there are no intervening live ranges between them in
147 // IntB, we can merge them.
148 if (ValLR+1 != BLR) return false;
150 // If a live interval is a physical register, conservatively check if any
151 // of its sub-registers is overlapping the live interval of the virtual
152 // register. If so, do not coalesce.
153 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
154 *tri_->getSubRegisters(IntB.reg)) {
155 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
156 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
157 DOUT << "Interfere with sub-register ";
158 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
163 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
165 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
166 // We are about to delete CopyMI, so need to remove it as the 'instruction
167 // that defines this value #'. Update the the valnum with the new defining
169 BValNo->def = FillerStart;
172 // Okay, we can merge them. We need to insert a new liverange:
173 // [ValLR.end, BLR.begin) of either value number, then we merge the
174 // two value numbers.
175 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
177 // If the IntB live range is assigned to a physical register, and if that
178 // physreg has aliases,
179 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
180 // Update the liveintervals of sub-registers.
181 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
182 LiveInterval &AliasLI = li_->getInterval(*AS);
183 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
184 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
188 // Okay, merge "B1" into the same value number as "B0".
189 if (BValNo != ValLR->valno) {
190 IntB.addKills(ValLR->valno, BValNo->kills);
191 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
193 DOUT << " result = "; IntB.print(DOUT, tri_);
196 // If the source instruction was killing the source register before the
197 // merge, unset the isKill marker given the live range has been extended.
198 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
200 ValLREndInst->getOperand(UIdx).setIsKill(false);
201 IntB.removeKill(ValLR->valno, FillerStart);
208 /// HasOtherReachingDefs - Return true if there are definitions of IntB
209 /// other than BValNo val# that can reach uses of AValno val# of IntA.
210 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
214 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
216 if (AI->valno != AValNo) continue;
217 LiveInterval::Ranges::iterator BI =
218 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
219 if (BI != IntB.ranges.begin())
221 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
222 if (BI->valno == BValNo)
224 if (BI->start <= AI->start && BI->end > AI->start)
226 if (BI->start > AI->start && BI->start < AI->end)
233 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
234 /// being the source and IntB being the dest, thus this defines a value number
235 /// in IntB. If the source value number (in IntA) is defined by a commutable
236 /// instruction and its other operand is coalesced to the copy dest register,
237 /// see if we can transform the copy into a noop by commuting the definition. For
240 /// A3 = op A2 B0<kill>
242 /// B1 = A3 <- this copy
244 /// = op A3 <- more uses
248 /// B2 = op B0 A2<kill>
250 /// B1 = B2 <- now an identify copy
252 /// = op B2 <- more uses
254 /// This returns true if an interval was modified.
256 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
258 MachineInstr *CopyMI) {
259 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
261 // FIXME: For now, only eliminate the copy by commuting its def when the
262 // source register is a virtual register. We want to guard against cases
263 // where the copy is a back edge copy and commuting the def lengthen the
264 // live interval of the source register to the entire loop.
265 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
268 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
269 // the example above.
270 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
271 if (BLR == IntB.end()) // Should never happen!
273 VNInfo *BValNo = BLR->valno;
275 // Get the location that B is defined at. Two options: either this value has
276 // an unknown definition point or it is defined at CopyIdx. If unknown, we
278 if (!BValNo->copy) return false;
279 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
281 // AValNo is the value number in A that defines the copy, A3 in the example.
282 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
283 if (ALR == IntA.end()) // Should never happen!
285 VNInfo *AValNo = ALR->valno;
286 // If other defs can reach uses of this def, then it's not safe to perform
288 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
290 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
291 const TargetInstrDesc &TID = DefMI->getDesc();
293 if (!TID.isCommutable() ||
294 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
297 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
298 unsigned NewReg = NewDstMO.getReg();
299 if (NewReg != IntB.reg || !NewDstMO.isKill())
302 // Make sure there are no other definitions of IntB that would reach the
303 // uses which the new definition can reach.
304 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
307 // If some of the uses of IntA.reg is already coalesced away, return false.
308 // It's not possible to determine whether it's safe to perform the coalescing.
309 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
310 UE = mri_->use_end(); UI != UE; ++UI) {
311 MachineInstr *UseMI = &*UI;
312 unsigned UseIdx = li_->getInstructionIndex(UseMI);
313 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
314 if (ULR == IntA.end())
316 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
320 // At this point we have decided that it is legal to do this
321 // transformation. Start by commuting the instruction.
322 MachineBasicBlock *MBB = DefMI->getParent();
323 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
326 if (NewMI != DefMI) {
327 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
328 MBB->insert(DefMI, NewMI);
331 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
332 NewMI->getOperand(OpIdx).setIsKill();
334 bool BHasPHIKill = BValNo->hasPHIKill;
335 SmallVector<VNInfo*, 4> BDeadValNos;
336 SmallVector<unsigned, 4> BKills;
337 std::map<unsigned, unsigned> BExtend;
339 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
348 // then do not add kills of A to the newly created B interval.
349 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
351 BExtend[ALR->end] = BLR->end;
353 // Update uses of IntA of the specific Val# with IntB.
354 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
355 UE = mri_->use_end(); UI != UE;) {
356 MachineOperand &UseMO = UI.getOperand();
357 MachineInstr *UseMI = &*UI;
359 if (JoinedCopies.count(UseMI))
361 unsigned UseIdx = li_->getInstructionIndex(UseMI);
362 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
363 if (ULR == IntA.end() || ULR->valno != AValNo)
365 UseMO.setReg(NewReg);
368 if (UseMO.isKill()) {
370 UseMO.setIsKill(false);
372 BKills.push_back(li_->getUseIndex(UseIdx)+1);
374 unsigned SrcReg, DstReg;
375 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
377 if (DstReg == IntB.reg) {
378 // This copy will become a noop. If it's defining a new val#,
379 // remove that val# as well. However this live range is being
380 // extended to the end of the existing live range defined by the copy.
381 unsigned DefIdx = li_->getDefIndex(UseIdx);
382 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
383 BHasPHIKill |= DLR->valno->hasPHIKill;
384 assert(DLR->valno->def == DefIdx);
385 BDeadValNos.push_back(DLR->valno);
386 BExtend[DLR->start] = DLR->end;
387 JoinedCopies.insert(UseMI);
388 // If this is a kill but it's going to be removed, the last use
389 // of the same val# is the new kill.
395 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
396 // simply extend BLR if CopyMI doesn't end the range.
397 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
399 // Remove val#'s defined by copies that will be coalesced away.
400 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
401 IntB.removeValNo(BDeadValNos[i]);
403 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
404 // is updated. Kills are also updated.
405 VNInfo *ValNo = BValNo;
406 ValNo->def = AValNo->def;
408 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
409 unsigned Kill = ValNo->kills[j];
410 if (Kill != BLR->end)
411 BKills.push_back(Kill);
413 ValNo->kills.clear();
414 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
416 if (AI->valno != AValNo) continue;
417 unsigned End = AI->end;
418 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
419 if (EI != BExtend.end())
421 IntB.addRange(LiveRange(AI->start, End, ValNo));
423 IntB.addKills(ValNo, BKills);
424 ValNo->hasPHIKill = BHasPHIKill;
426 DOUT << " result = "; IntB.print(DOUT, tri_);
429 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
430 IntA.removeValNo(AValNo);
431 DOUT << " result = "; IntA.print(DOUT, tri_);
438 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
439 /// computation, replace the copy by rematerialize the definition.
440 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
442 MachineInstr *CopyMI) {
443 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
444 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
445 if (SrcLR == SrcInt.end()) // Should never happen!
447 VNInfo *ValNo = SrcLR->valno;
448 // If other defs can reach uses of this def, then it's not safe to perform
450 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
452 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
453 const TargetInstrDesc &TID = DefMI->getDesc();
454 if (!TID.isAsCheapAsAMove())
456 bool SawStore = false;
457 if (!DefMI->isSafeToMove(tii_, SawStore))
460 unsigned DefIdx = li_->getDefIndex(CopyIdx);
461 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
462 DLR->valno->copy = NULL;
464 MachineBasicBlock::iterator MII = CopyMI;
465 MachineBasicBlock *MBB = CopyMI->getParent();
466 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
467 MachineInstr *NewMI = prior(MII);
468 // CopyMI may have implicit instructions, transfer them over to the newly
469 // rematerialized instruction. And update implicit def interval valnos.
470 for (unsigned i = CopyMI->getDesc().getNumOperands(),
471 e = CopyMI->getNumOperands(); i != e; ++i) {
472 MachineOperand &MO = CopyMI->getOperand(i);
473 if (MO.isReg() && MO.isImplicit())
474 NewMI->addOperand(MO);
475 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
476 unsigned Reg = MO.getReg();
477 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
478 if (DLR && DLR->valno->copy == CopyMI)
479 DLR->valno->copy = NULL;
483 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
484 CopyMI->eraseFromParent();
485 ReMatCopies.insert(CopyMI);
486 ReMatDefs.insert(DefMI);
491 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
493 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
494 unsigned DstReg) const {
495 MachineBasicBlock *MBB = CopyMI->getParent();
496 const MachineLoop *L = loopInfo->getLoopFor(MBB);
499 if (MBB != L->getLoopLatch())
502 LiveInterval &LI = li_->getInterval(DstReg);
503 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
504 LiveInterval::const_iterator DstLR =
505 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
506 if (DstLR == LI.end())
508 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
509 if (DstLR->valno->kills.size() == 1 &&
510 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
515 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
516 /// update the subregister number if it is not zero. If DstReg is a
517 /// physical register and the existing subregister number of the def / use
518 /// being updated is not zero, make sure to set it to the correct physical
521 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
523 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
524 if (DstIsPhys && SubIdx) {
525 // Figure out the real physical register we are updating with.
526 DstReg = tri_->getSubReg(DstReg, SubIdx);
530 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
531 E = mri_->reg_end(); I != E; ) {
532 MachineOperand &O = I.getOperand();
533 MachineInstr *UseMI = &*I;
535 unsigned OldSubIdx = O.getSubReg();
537 unsigned UseDstReg = DstReg;
539 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
541 unsigned CopySrcReg, CopyDstReg;
542 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
543 CopySrcReg != CopyDstReg &&
544 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
545 // If the use is a copy and it won't be coalesced away, and its source
546 // is defined by a trivial computation, try to rematerialize it instead.
547 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
556 // Sub-register indexes goes from small to large. e.g.
557 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
558 // EAX: 1 -> AL, 2 -> AX
559 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
560 // sub-register 2 is also AX.
561 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
562 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
565 // Remove would-be duplicated kill marker.
566 if (O.isKill() && UseMI->killsRegister(DstReg))
570 // After updating the operand, check if the machine instruction has
571 // become a copy. If so, update its val# information.
572 const TargetInstrDesc &TID = UseMI->getDesc();
573 unsigned CopySrcReg, CopyDstReg;
574 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
575 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
576 CopySrcReg != CopyDstReg &&
577 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
578 allocatableRegs_[CopyDstReg])) {
579 LiveInterval &LI = li_->getInterval(CopyDstReg);
580 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
581 const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
582 if (DLR->valno->def == DefIdx)
583 DLR->valno->copy = UseMI;
588 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
589 /// registers due to insert_subreg coalescing. e.g.
591 /// r1025 = implicit_def
592 /// r1025 = insert_subreg r1025, r1024
596 /// r1025 = implicit_def
597 /// r1025 = insert_subreg r1025, r1025
600 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
601 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
602 E = mri_->reg_end(); I != E; ) {
603 MachineOperand &O = I.getOperand();
604 MachineInstr *DefMI = &*I;
608 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
610 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
612 li_->RemoveMachineInstrFromMaps(DefMI);
613 DefMI->eraseFromParent();
617 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
618 /// due to live range lengthening as the result of coalescing.
619 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
621 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
622 UE = mri_->use_end(); UI != UE; ++UI) {
623 MachineOperand &UseMO = UI.getOperand();
624 if (UseMO.isKill()) {
625 MachineInstr *UseMI = UseMO.getParent();
626 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
627 if (JoinedCopies.count(UseMI))
629 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
630 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
631 UseMO.setIsKill(false);
636 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
637 /// from a physical register live interval as well as from the live intervals
638 /// of its sub-registers.
639 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
640 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
641 li.removeRange(Start, End, true);
642 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
643 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
644 if (!li_->hasInterval(*SR))
646 LiveInterval &sli = li_->getInterval(*SR);
647 unsigned RemoveEnd = Start;
648 while (RemoveEnd != End) {
649 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
652 RemoveEnd = (LR->end < End) ? LR->end : End;
653 sli.removeRange(Start, RemoveEnd, true);
660 /// removeIntervalIfEmpty - Check if the live interval of a physical register
661 /// is empty, if so remove it and also remove the empty intervals of its
662 /// sub-registers. Return true if live interval is removed.
663 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
664 const TargetRegisterInfo *tri_) {
666 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
667 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
668 if (!li_->hasInterval(*SR))
670 LiveInterval &sli = li_->getInterval(*SR);
672 li_->removeInterval(*SR);
674 li_->removeInterval(li.reg);
680 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
681 /// Return true if live interval is removed.
682 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
683 MachineInstr *CopyMI) {
684 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
685 LiveInterval::iterator MLR =
686 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
688 return false; // Already removed by ShortenDeadCopySrcLiveRange.
689 unsigned RemoveStart = MLR->start;
690 unsigned RemoveEnd = MLR->end;
691 // Remove the liverange that's defined by this.
692 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
693 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
694 return removeIntervalIfEmpty(li, li_, tri_);
699 /// PropagateDeadness - Propagate the dead marker to the instruction which
700 /// defines the val#.
701 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
702 unsigned &LRStart, LiveIntervals *li_,
703 const TargetRegisterInfo* tri_) {
704 MachineInstr *DefMI =
705 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
706 if (DefMI && DefMI != CopyMI) {
707 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
709 DefMI->getOperand(DeadIdx).setIsDead();
710 // A dead def should have a single cycle interval.
716 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
717 /// fallthoughs to SuccMBB.
718 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
719 MachineBasicBlock *SuccMBB,
720 const TargetInstrInfo *tii_) {
723 MachineBasicBlock *TBB = 0, *FBB = 0;
724 SmallVector<MachineOperand, 4> Cond;
725 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
726 MBB->isSuccessor(SuccMBB);
729 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
730 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
731 /// ends the live range there. If there isn't another use, then this live range
732 /// is dead. Return true if live interval is removed.
734 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
735 MachineInstr *CopyMI) {
736 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
738 // FIXME: special case: function live in. It can be a general case if the
739 // first instruction index starts at > 0 value.
740 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
741 // Live-in to the function but dead. Remove it from entry live-in set.
742 if (mf_->begin()->isLiveIn(li.reg))
743 mf_->begin()->removeLiveIn(li.reg);
744 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
745 removeRange(li, LR->start, LR->end, li_, tri_);
746 return removeIntervalIfEmpty(li, li_, tri_);
749 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
751 // Livein but defined by a phi.
754 unsigned RemoveStart = LR->start;
755 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
756 if (LR->end > RemoveEnd)
757 // More uses past this copy? Nothing to do.
760 MachineBasicBlock *CopyMBB = CopyMI->getParent();
761 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
763 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
766 MachineInstr *LastUseMI = LastUse->getParent();
767 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
774 // r1025<dead> = r1024<kill>
775 if (MBBStart < LR->end)
776 removeRange(li, MBBStart, LR->end, li_, tri_);
780 // There are uses before the copy, just shorten the live range to the end
782 LastUse->setIsKill();
783 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
784 unsigned SrcReg, DstReg;
785 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
787 // Last use is itself an identity code.
788 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
789 LastUseMI->getOperand(DeadIdx).setIsDead();
795 if (LR->start <= MBBStart && LR->end > MBBStart) {
796 if (LR->start == 0) {
797 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
798 // Live-in to the function but dead. Remove it from entry live-in set.
799 mf_->begin()->removeLiveIn(li.reg);
801 // FIXME: Shorten intervals in BBs that reaches this BB.
804 if (LR->valno->def == RemoveStart)
805 // If the def MI defines the val#, propagate the dead marker.
806 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
808 removeRange(li, RemoveStart, LR->end, li_, tri_);
809 return removeIntervalIfEmpty(li, li_, tri_);
812 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
813 /// from an implicit def to another register can be coalesced away.
814 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
816 LiveInterval &ImpLi) const{
817 if (!CopyMI->killsRegister(ImpLi.reg))
819 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
820 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
823 if (LR->valno->hasPHIKill)
825 if (LR->valno->def != CopyIdx)
827 // Make sure all of val# uses are copies.
828 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
829 UE = mri_->use_end(); UI != UE;) {
830 MachineInstr *UseMI = &*UI;
832 if (JoinedCopies.count(UseMI))
834 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
835 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
836 if (ULR == li.end() || ULR->valno != LR->valno)
838 // If the use is not a use, then it's not safe to coalesce the move.
839 unsigned SrcReg, DstReg;
840 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
841 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
842 UseMI->getOperand(1).getReg() == li.reg)
851 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
852 /// def and it is being removed. Turn all copies from this value# into
853 /// identity copies so they will be removed.
854 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
856 SmallVector<MachineInstr*, 4> ImpDefs;
857 MachineOperand *LastUse = NULL;
858 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
859 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
860 RE = mri_->reg_end(); RI != RE;) {
861 MachineOperand *MO = &RI.getOperand();
862 MachineInstr *MI = &*RI;
865 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
866 ImpDefs.push_back(MI);
870 if (JoinedCopies.count(MI))
872 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
873 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
874 if (ULR == li.end() || ULR->valno != VNI)
876 // If the use is a copy, turn it into an identity copy.
877 unsigned SrcReg, DstReg;
878 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
879 // Each use MI may have multiple uses of this register. Change them all.
880 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
881 MachineOperand &MO = MI->getOperand(i);
882 if (MO.isReg() && MO.getReg() == li.reg)
885 JoinedCopies.insert(MI);
886 } else if (UseIdx > LastUseIdx) {
892 LastUse->setIsKill();
894 // Remove dead implicit_def's.
895 while (!ImpDefs.empty()) {
896 MachineInstr *ImpDef = ImpDefs.back();
898 li_->RemoveMachineInstrFromMaps(ImpDef);
899 ImpDef->eraseFromParent();
904 /// getMatchingSuperReg - Return a super-register of the specified register
905 /// Reg so its sub-register of index SubIdx is Reg.
906 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
907 const TargetRegisterClass *RC,
908 const TargetRegisterInfo* TRI) {
909 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
910 unsigned SR = *SRs; ++SRs)
911 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
916 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
917 /// a subset of the register class of SrcReg, return true if it's profitable
918 /// to coalesce the two registers.
920 SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg,
922 MachineBasicBlock *MBB){
926 // First let's make sure all uses are in the same MBB.
927 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
928 RE = mri_->reg_end(); RI != RE; ++RI) {
929 MachineInstr &MI = *RI;
930 if (MI.getParent() != MBB)
933 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(DstReg),
934 RE = mri_->reg_end(); RI != RE; ++RI) {
935 MachineInstr &MI = *RI;
936 if (MI.getParent() != MBB)
940 // Then make sure the intervals are *short*.
941 LiveInterval &SrcInt = li_->getInterval(SrcReg);
942 LiveInterval &DstInt = li_->getInterval(DstReg);
943 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
944 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
945 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
946 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
947 return (SrcSize + DstSize) <= Threshold;
950 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
951 /// register with a physical register, check if any of the virtual register
952 /// operand is a sub-register use or def. If so, make sure it won't result
953 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
954 /// vr1024 = extract_subreg vr1025, 1
956 /// vr1024 = mov8rr AH
957 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
958 /// AH does not have a super-reg whose sub-register 1 is AH.
960 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
963 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
964 E = mri_->reg_end(); I != E; ++I) {
965 MachineOperand &O = I.getOperand();
966 MachineInstr *MI = &*I;
967 if (MI == CopyMI || JoinedCopies.count(MI))
969 unsigned SubIdx = O.getSubReg();
970 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
972 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
973 SubIdx = MI->getOperand(2).getImm();
974 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
977 unsigned SrcReg = MI->getOperand(1).getReg();
978 const TargetRegisterClass *RC =
979 TargetRegisterInfo::isPhysicalRegister(SrcReg)
980 ? tri_->getPhysicalRegisterRegClass(SrcReg)
981 : mri_->getRegClass(SrcReg);
982 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
986 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
987 SubIdx = MI->getOperand(3).getImm();
988 if (VirtReg == MI->getOperand(0).getReg()) {
989 if (!tri_->getSubReg(PhysReg, SubIdx))
992 unsigned DstReg = MI->getOperand(0).getReg();
993 const TargetRegisterClass *RC =
994 TargetRegisterInfo::isPhysicalRegister(DstReg)
995 ? tri_->getPhysicalRegisterRegClass(DstReg)
996 : mri_->getRegClass(DstReg);
997 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1006 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1007 /// which are the src/dst of the copy instruction CopyMI. This returns true
1008 /// if the copy was successfully coalesced away. If it is not currently
1009 /// possible to coalesce this interval, but it may be possible if other
1010 /// things get coalesced, then it returns true by reference in 'Again'.
1011 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1012 MachineInstr *CopyMI = TheCopy.MI;
1015 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1016 return false; // Already done.
1018 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1022 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1023 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1024 unsigned SubIdx = 0;
1026 DstReg = CopyMI->getOperand(0).getReg();
1027 SrcReg = CopyMI->getOperand(1).getReg();
1028 } else if (isInsSubReg) {
1029 if (CopyMI->getOperand(2).getSubReg()) {
1030 DOUT << "\tSource of insert_subreg is already coalesced "
1031 << "to another register.\n";
1032 return false; // Not coalescable.
1034 DstReg = CopyMI->getOperand(0).getReg();
1035 SrcReg = CopyMI->getOperand(2).getReg();
1036 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
1037 assert(0 && "Unrecognized copy instruction!");
1041 // If they are already joined we continue.
1042 if (SrcReg == DstReg) {
1043 DOUT << "\tCopy already coalesced.\n";
1044 return false; // Not coalescable.
1047 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1048 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1050 // If they are both physical registers, we cannot join them.
1051 if (SrcIsPhys && DstIsPhys) {
1052 DOUT << "\tCan not coalesce physregs.\n";
1053 return false; // Not coalescable.
1056 // We only join virtual registers with allocatable physical registers.
1057 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1058 DOUT << "\tSrc reg is unallocatable physreg.\n";
1059 return false; // Not coalescable.
1061 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1062 DOUT << "\tDst reg is unallocatable physreg.\n";
1063 return false; // Not coalescable.
1066 // Should be non-null only when coalescing to a sub-register class.
1067 const TargetRegisterClass *SubRC = NULL;
1068 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1069 unsigned RealDstReg = 0;
1070 unsigned RealSrcReg = 0;
1071 if (isExtSubReg || isInsSubReg) {
1072 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1073 if (SrcIsPhys && isExtSubReg) {
1074 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1075 // coalesced with AX.
1076 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1078 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1079 // coalesced to a larger register so the subreg indices cancel out.
1080 if (DstSubIdx != SubIdx) {
1081 DOUT << "\t Sub-register indices mismatch.\n";
1082 return false; // Not coalescable.
1085 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1087 } else if (DstIsPhys && isInsSubReg) {
1088 // EAX = INSERT_SUBREG EAX, r1024, 0
1089 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1091 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1092 // coalesced to a larger register so the subreg indices cancel out.
1093 if (SrcSubIdx != SubIdx) {
1094 DOUT << "\t Sub-register indices mismatch.\n";
1095 return false; // Not coalescable.
1098 DstReg = tri_->getSubReg(DstReg, SubIdx);
1100 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
1101 // If this is a extract_subreg where dst is a physical register, e.g.
1102 // cl = EXTRACT_SUBREG reg1024, 1
1103 // then create and update the actual physical register allocated to RHS.
1105 // reg1024 = INSERT_SUBREG r1024, cl, 1
1106 if (CopyMI->getOperand(1).getSubReg()) {
1107 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
1108 << " of a super-class.\n";
1109 return false; // Not coalescable.
1111 const TargetRegisterClass *RC =
1112 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
1114 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
1115 assert(RealDstReg && "Invalid extract_subreg instruction!");
1117 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
1118 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1121 // For this type of EXTRACT_SUBREG, conservatively
1122 // check if the live interval of the source register interfere with the
1123 // actual super physical register we are trying to coalesce with.
1124 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
1125 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
1126 if (li_->hasInterval(PhysReg) &&
1127 RHS.overlaps(li_->getInterval(PhysReg))) {
1128 DOUT << "Interfere with register ";
1129 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
1130 return false; // Not coalescable
1132 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
1133 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1134 DOUT << "Interfere with sub-register ";
1135 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1136 return false; // Not coalescable
1140 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1141 : CopyMI->getOperand(2).getSubReg();
1143 if (OldSubIdx == SubIdx &&
1144 !differingRegisterClasses(SrcReg, DstReg, SubRC))
1145 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1146 // coalesced to a larger register so the subreg indices cancel out.
1147 // Also check if the other larger register is of the same register
1148 // class as the would be resulting register.
1151 DOUT << "\t Sub-register indices mismatch.\n";
1152 return false; // Not coalescable.
1156 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1157 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1158 unsigned LargeRegSize =
1159 li_->getApproximateInstructionCount(li_->getInterval(LargeReg));
1160 unsigned SmallRegSize =
1161 li_->getApproximateInstructionCount(li_->getInterval(SmallReg));
1162 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
1163 unsigned Threshold = allocatableRCRegs_[RC].count();
1164 // Be conservative. If both sides are virtual registers, do not coalesce
1165 // if this will cause a high use density interval to target a smaller
1166 // set of registers.
1167 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
1168 if ((float)std::distance(mri_->use_begin(SmallReg),
1169 mri_->use_end()) / SmallRegSize <
1170 (float)std::distance(mri_->use_begin(LargeReg),
1171 mri_->use_end()) / LargeRegSize) {
1172 Again = true; // May be possible to coalesce later.
1178 } else if (differingRegisterClasses(SrcReg, DstReg, SubRC)) {
1179 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
1180 // with another? If it's the resulting destination register, then
1181 // the subidx must be propagated to uses (but only those defined
1182 // by the EXTRACT_SUBREG). If it's being coalesced into another
1183 // register, it should be safe because register is assumed to have
1184 // the register class of the super-register.
1186 if (!SubRC || !isProfitableToCoalesceToSubRC(SrcReg, DstReg, CopyMBB)) {
1187 // If they are not of the same register class, we cannot join them.
1188 DOUT << "\tSrc/Dest are different register classes.\n";
1189 // Allow the coalescer to try again in case either side gets coalesced to
1190 // a physical register that's compatible with the other side. e.g.
1191 // r1024 = MOV32to32_ r1025
1192 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1193 Again = true; // May be possible to coalesce later.
1198 // Will it create illegal extract_subreg / insert_subreg?
1199 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1201 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1204 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1205 LiveInterval &DstInt = li_->getInterval(DstReg);
1206 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1207 "Register mapping is horribly broken!");
1209 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1210 DOUT << " and "; DstInt.print(DOUT, tri_);
1213 // Check if it is necessary to propagate "isDead" property.
1214 if (!isExtSubReg && !isInsSubReg) {
1215 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1216 bool isDead = mopd->isDead();
1218 // We need to be careful about coalescing a source physical register with a
1219 // virtual register. Once the coalescing is done, it cannot be broken and
1220 // these are not spillable! If the destination interval uses are far away,
1221 // think twice about coalescing them!
1222 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1223 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1224 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1225 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1226 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1227 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1228 if (TheCopy.isBackEdge)
1229 Threshold *= 2; // Favors back edge copies.
1231 // If the virtual register live interval is long but it has low use desity,
1232 // do not join them, instead mark the physical register as its allocation
1234 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1235 if (Length > Threshold &&
1236 (((float)std::distance(mri_->use_begin(JoinVReg),
1237 mri_->use_end()) / Length) < (1.0 / Threshold))) {
1238 JoinVInt.preference = JoinPReg;
1240 DOUT << "\tMay tie down a physical register, abort!\n";
1241 Again = true; // May be possible to coalesce later.
1247 // Okay, attempt to join these two intervals. On failure, this returns false.
1248 // Otherwise, if one of the intervals being joined is a physreg, this method
1249 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1250 // been modified, so we can use this information below to update aliases.
1251 bool Swapped = false;
1252 // If SrcInt is implicitly defined, it's safe to coalesce.
1253 bool isEmpty = SrcInt.empty();
1254 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1255 // Only coalesce an empty interval (defined by implicit_def) with
1256 // another interval which has a valno defined by the CopyMI and the CopyMI
1257 // is a kill of the implicit def.
1258 DOUT << "Not profitable!\n";
1262 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1263 // Coalescing failed.
1265 // If definition of source is defined by trivial computation, try
1266 // rematerializing it.
1267 if (!isExtSubReg && !isInsSubReg &&
1268 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1271 // If we can eliminate the copy without merging the live ranges, do so now.
1272 if (!isExtSubReg && !isInsSubReg &&
1273 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1274 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1275 JoinedCopies.insert(CopyMI);
1279 // Otherwise, we are unable to join the intervals.
1280 DOUT << "Interference!\n";
1281 Again = true; // May be possible to coalesce later.
1285 LiveInterval *ResSrcInt = &SrcInt;
1286 LiveInterval *ResDstInt = &DstInt;
1288 std::swap(SrcReg, DstReg);
1289 std::swap(ResSrcInt, ResDstInt);
1291 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1292 "LiveInterval::join didn't work right!");
1294 // If we're about to merge live ranges into a physical register live range,
1295 // we have to update any aliased register's live ranges to indicate that they
1296 // have clobbered values for this range.
1297 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1298 // If this is a extract_subreg where dst is a physical register, e.g.
1299 // cl = EXTRACT_SUBREG reg1024, 1
1300 // then create and update the actual physical register allocated to RHS.
1301 if (RealDstReg || RealSrcReg) {
1302 LiveInterval &RealInt =
1303 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1304 SmallSet<const VNInfo*, 4> CopiedValNos;
1305 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1306 E = ResSrcInt->ranges.end(); I != E; ++I) {
1307 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1308 assert(DstLR && "Invalid joined interval!");
1309 const VNInfo *DstValNo = DstLR->valno;
1310 if (CopiedValNos.insert(DstValNo)) {
1311 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1312 li_->getVNInfoAllocator());
1313 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1314 RealInt.addKills(ValNo, DstValNo->kills);
1315 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1319 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1322 // Update the liveintervals of sub-registers.
1323 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1324 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1325 li_->getVNInfoAllocator());
1328 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1329 // larger super-register.
1330 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1331 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1332 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1333 std::swap(SrcReg, DstReg);
1334 std::swap(ResSrcInt, ResDstInt);
1338 // Coalescing to a virtual register that is of a sub-register class of the
1339 // other. Make sure the resulting register is set to the right register class.
1341 mri_->setRegClass(DstReg, SubRC);
1346 // Add all copies that define val# in the source interval into the queue.
1347 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1348 e = ResSrcInt->vni_end(); i != e; ++i) {
1349 const VNInfo *vni = *i;
1350 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1352 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1353 unsigned NewSrcReg, NewDstReg;
1355 JoinedCopies.count(CopyMI) == 0 &&
1356 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1357 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1358 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1359 isBackEdgeCopy(CopyMI, DstReg)));
1364 // Remember to delete the copy instruction.
1365 JoinedCopies.insert(CopyMI);
1367 // Some live range has been lengthened due to colaescing, eliminate the
1368 // unnecessary kills.
1369 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1370 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1371 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1376 // r1024 = implicit_def
1379 RemoveDeadImpDef(DstReg, *ResDstInt);
1380 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1382 // SrcReg is guarateed to be the register whose live interval that is
1384 li_->removeInterval(SrcReg);
1387 // Now the copy is being coalesced away, the val# previously defined
1388 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1389 // length interval. Remove the val#.
1390 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1391 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1392 VNInfo *ImpVal = LR->valno;
1393 assert(ImpVal->def == CopyIdx);
1394 unsigned NextDef = LR->end;
1395 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1396 ResDstInt->removeValNo(ImpVal);
1397 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1398 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1399 // Special case: vr1024 = implicit_def
1400 // vr1024 = insert_subreg vr1024, vr1025, c
1401 // The insert_subreg becomes a "copy" that defines a val# which can itself
1402 // be coalesced away.
1403 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1404 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1405 LR->valno->copy = DefMI;
1409 // If resulting interval has a preference that no longer fits because of subreg
1410 // coalescing, just clear the preference.
1411 if (ResDstInt->preference && (isExtSubReg || isInsSubReg) &&
1412 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1413 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1414 if (!RC->contains(ResDstInt->preference))
1415 ResDstInt->preference = 0;
1418 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1425 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1426 /// compute what the resultant value numbers for each value in the input two
1427 /// ranges will be. This is complicated by copies between the two which can
1428 /// and will commonly cause multiple value numbers to be merged into one.
1430 /// VN is the value number that we're trying to resolve. InstDefiningValue
1431 /// keeps track of the new InstDefiningValue assignment for the result
1432 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1433 /// whether a value in this or other is a copy from the opposite set.
1434 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1435 /// already been assigned.
1437 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1438 /// contains the value number the copy is from.
1440 static unsigned ComputeUltimateVN(VNInfo *VNI,
1441 SmallVector<VNInfo*, 16> &NewVNInfo,
1442 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1443 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1444 SmallVector<int, 16> &ThisValNoAssignments,
1445 SmallVector<int, 16> &OtherValNoAssignments) {
1446 unsigned VN = VNI->id;
1448 // If the VN has already been computed, just return it.
1449 if (ThisValNoAssignments[VN] >= 0)
1450 return ThisValNoAssignments[VN];
1451 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1453 // If this val is not a copy from the other val, then it must be a new value
1454 // number in the destination.
1455 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1456 if (I == ThisFromOther.end()) {
1457 NewVNInfo.push_back(VNI);
1458 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1460 VNInfo *OtherValNo = I->second;
1462 // Otherwise, this *is* a copy from the RHS. If the other side has already
1463 // been computed, return it.
1464 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1465 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1467 // Mark this value number as currently being computed, then ask what the
1468 // ultimate value # of the other value is.
1469 ThisValNoAssignments[VN] = -2;
1470 unsigned UltimateVN =
1471 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1472 OtherValNoAssignments, ThisValNoAssignments);
1473 return ThisValNoAssignments[VN] = UltimateVN;
1476 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1477 return std::find(V.begin(), V.end(), Val) != V.end();
1480 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1481 /// the specified live interval is defined by a copy from the specified
1483 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1486 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1489 if (LR->valno->def == ~0U &&
1490 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1491 *tri_->getSuperRegisters(li.reg)) {
1492 // It's a sub-register live interval, we may not have precise information.
1494 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1495 unsigned SrcReg, DstReg;
1496 if (DefMI && tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1497 DstReg == li.reg && SrcReg == Reg) {
1498 // Cache computed info.
1499 LR->valno->def = LR->start;
1500 LR->valno->copy = DefMI;
1507 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1508 /// caller of this method must guarantee that the RHS only contains a single
1509 /// value number and that the RHS is not defined by a copy from this
1510 /// interval. This returns false if the intervals are not joinable, or it
1511 /// joins them and returns true.
1512 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1513 assert(RHS.containsOneValue());
1515 // Some number (potentially more than one) value numbers in the current
1516 // interval may be defined as copies from the RHS. Scan the overlapping
1517 // portions of the LHS and RHS, keeping track of this and looking for
1518 // overlapping live ranges that are NOT defined as copies. If these exist, we
1521 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1522 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1524 if (LHSIt->start < RHSIt->start) {
1525 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1526 if (LHSIt != LHS.begin()) --LHSIt;
1527 } else if (RHSIt->start < LHSIt->start) {
1528 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1529 if (RHSIt != RHS.begin()) --RHSIt;
1532 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1535 // Determine if these live intervals overlap.
1536 bool Overlaps = false;
1537 if (LHSIt->start <= RHSIt->start)
1538 Overlaps = LHSIt->end > RHSIt->start;
1540 Overlaps = RHSIt->end > LHSIt->start;
1542 // If the live intervals overlap, there are two interesting cases: if the
1543 // LHS interval is defined by a copy from the RHS, it's ok and we record
1544 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1545 // coalesce these live ranges and we bail out.
1547 // If we haven't already recorded that this value # is safe, check it.
1548 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1549 // Copy from the RHS?
1550 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1551 return false; // Nope, bail out.
1553 if (LHSIt->contains(RHSIt->valno->def))
1554 // Here is an interesting situation:
1556 // vr1025 = copy vr1024
1561 // Even though vr1025 is copied from vr1024, it's not safe to
1562 // coalesced them since live range of vr1025 intersects the
1563 // def of vr1024. This happens because vr1025 is assigned the
1564 // value of the previous iteration of vr1024.
1566 EliminatedLHSVals.push_back(LHSIt->valno);
1569 // We know this entire LHS live range is okay, so skip it now.
1570 if (++LHSIt == LHSEnd) break;
1574 if (LHSIt->end < RHSIt->end) {
1575 if (++LHSIt == LHSEnd) break;
1577 // One interesting case to check here. It's possible that we have
1578 // something like "X3 = Y" which defines a new value number in the LHS,
1579 // and is the last use of this liverange of the RHS. In this case, we
1580 // want to notice this copy (so that it gets coalesced away) even though
1581 // the live ranges don't actually overlap.
1582 if (LHSIt->start == RHSIt->end) {
1583 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1584 // We already know that this value number is going to be merged in
1585 // if coalescing succeeds. Just skip the liverange.
1586 if (++LHSIt == LHSEnd) break;
1588 // Otherwise, if this is a copy from the RHS, mark it as being merged
1590 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1591 if (LHSIt->contains(RHSIt->valno->def))
1592 // Here is an interesting situation:
1594 // vr1025 = copy vr1024
1599 // Even though vr1025 is copied from vr1024, it's not safe to
1600 // coalesced them since live range of vr1025 intersects the
1601 // def of vr1024. This happens because vr1025 is assigned the
1602 // value of the previous iteration of vr1024.
1604 EliminatedLHSVals.push_back(LHSIt->valno);
1606 // We know this entire LHS live range is okay, so skip it now.
1607 if (++LHSIt == LHSEnd) break;
1612 if (++RHSIt == RHSEnd) break;
1616 // If we got here, we know that the coalescing will be successful and that
1617 // the value numbers in EliminatedLHSVals will all be merged together. Since
1618 // the most common case is that EliminatedLHSVals has a single number, we
1619 // optimize for it: if there is more than one value, we merge them all into
1620 // the lowest numbered one, then handle the interval as if we were merging
1621 // with one value number.
1623 if (EliminatedLHSVals.size() > 1) {
1624 // Loop through all the equal value numbers merging them into the smallest
1626 VNInfo *Smallest = EliminatedLHSVals[0];
1627 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1628 if (EliminatedLHSVals[i]->id < Smallest->id) {
1629 // Merge the current notion of the smallest into the smaller one.
1630 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1631 Smallest = EliminatedLHSVals[i];
1633 // Merge into the smallest.
1634 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1637 LHSValNo = Smallest;
1638 } else if (EliminatedLHSVals.empty()) {
1639 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1640 *tri_->getSuperRegisters(LHS.reg))
1641 // Imprecise sub-register information. Can't handle it.
1643 assert(0 && "No copies from the RHS?");
1645 LHSValNo = EliminatedLHSVals[0];
1648 // Okay, now that there is a single LHS value number that we're merging the
1649 // RHS into, update the value number info for the LHS to indicate that the
1650 // value number is defined where the RHS value number was.
1651 const VNInfo *VNI = RHS.getValNumInfo(0);
1652 LHSValNo->def = VNI->def;
1653 LHSValNo->copy = VNI->copy;
1655 // Okay, the final step is to loop over the RHS live intervals, adding them to
1657 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1658 LHS.addKills(LHSValNo, VNI->kills);
1659 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1660 LHS.weight += RHS.weight;
1661 if (RHS.preference && !LHS.preference)
1662 LHS.preference = RHS.preference;
1667 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1668 /// returns false. Otherwise, if one of the intervals being joined is a
1669 /// physreg, this method always canonicalizes LHS to be it. The output
1670 /// "RHS" will not have been modified, so we can use this information
1671 /// below to update aliases.
1672 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
1673 LiveInterval &RHS, bool &Swapped) {
1674 // Compute the final value assignment, assuming that the live ranges can be
1676 SmallVector<int, 16> LHSValNoAssignments;
1677 SmallVector<int, 16> RHSValNoAssignments;
1678 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1679 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1680 SmallVector<VNInfo*, 16> NewVNInfo;
1682 // If a live interval is a physical register, conservatively check if any
1683 // of its sub-registers is overlapping the live interval of the virtual
1684 // register. If so, do not coalesce.
1685 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1686 *tri_->getSubRegisters(LHS.reg)) {
1687 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1688 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1689 DOUT << "Interfere with sub-register ";
1690 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1693 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1694 *tri_->getSubRegisters(RHS.reg)) {
1695 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1696 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1697 DOUT << "Interfere with sub-register ";
1698 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1703 // Compute ultimate value numbers for the LHS and RHS values.
1704 if (RHS.containsOneValue()) {
1705 // Copies from a liveinterval with a single value are simple to handle and
1706 // very common, handle the special case here. This is important, because
1707 // often RHS is small and LHS is large (e.g. a physreg).
1709 // Find out if the RHS is defined as a copy from some value in the LHS.
1710 int RHSVal0DefinedFromLHS = -1;
1712 VNInfo *RHSValNoInfo = NULL;
1713 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1714 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1715 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1716 // If RHS is not defined as a copy from the LHS, we can use simpler and
1717 // faster checks to see if the live ranges are coalescable. This joiner
1718 // can't swap the LHS/RHS intervals though.
1719 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1720 return SimpleJoin(LHS, RHS);
1722 RHSValNoInfo = RHSValNoInfo0;
1725 // It was defined as a copy from the LHS, find out what value # it is.
1726 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1727 RHSValID = RHSValNoInfo->id;
1728 RHSVal0DefinedFromLHS = RHSValID;
1731 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1732 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1733 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1735 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1736 // should now get updated.
1737 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1740 unsigned VN = VNI->id;
1741 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1742 if (LHSSrcReg != RHS.reg) {
1743 // If this is not a copy from the RHS, its value number will be
1744 // unmodified by the coalescing.
1745 NewVNInfo[VN] = VNI;
1746 LHSValNoAssignments[VN] = VN;
1747 } else if (RHSValID == -1) {
1748 // Otherwise, it is a copy from the RHS, and we don't already have a
1749 // value# for it. Keep the current value number, but remember it.
1750 LHSValNoAssignments[VN] = RHSValID = VN;
1751 NewVNInfo[VN] = RHSValNoInfo;
1752 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1754 // Otherwise, use the specified value #.
1755 LHSValNoAssignments[VN] = RHSValID;
1756 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1757 NewVNInfo[VN] = RHSValNoInfo;
1758 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1762 NewVNInfo[VN] = VNI;
1763 LHSValNoAssignments[VN] = VN;
1767 assert(RHSValID != -1 && "Didn't find value #?");
1768 RHSValNoAssignments[0] = RHSValID;
1769 if (RHSVal0DefinedFromLHS != -1) {
1770 // This path doesn't go through ComputeUltimateVN so just set
1772 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1775 // Loop over the value numbers of the LHS, seeing if any are defined from
1777 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1780 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1783 // DstReg is known to be a register in the LHS interval. If the src is
1784 // from the RHS interval, we can use its value #.
1785 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1788 // Figure out the value # from the RHS.
1789 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1792 // Loop over the value numbers of the RHS, seeing if any are defined from
1794 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1797 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1800 // DstReg is known to be a register in the RHS interval. If the src is
1801 // from the LHS interval, we can use its value #.
1802 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1805 // Figure out the value # from the LHS.
1806 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1809 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1810 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1811 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1813 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1816 unsigned VN = VNI->id;
1817 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1819 ComputeUltimateVN(VNI, NewVNInfo,
1820 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1821 LHSValNoAssignments, RHSValNoAssignments);
1823 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1826 unsigned VN = VNI->id;
1827 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1829 // If this value number isn't a copy from the LHS, it's a new number.
1830 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1831 NewVNInfo.push_back(VNI);
1832 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1836 ComputeUltimateVN(VNI, NewVNInfo,
1837 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1838 RHSValNoAssignments, LHSValNoAssignments);
1842 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1843 // interval lists to see if these intervals are coalescable.
1844 LiveInterval::const_iterator I = LHS.begin();
1845 LiveInterval::const_iterator IE = LHS.end();
1846 LiveInterval::const_iterator J = RHS.begin();
1847 LiveInterval::const_iterator JE = RHS.end();
1849 // Skip ahead until the first place of potential sharing.
1850 if (I->start < J->start) {
1851 I = std::upper_bound(I, IE, J->start);
1852 if (I != LHS.begin()) --I;
1853 } else if (J->start < I->start) {
1854 J = std::upper_bound(J, JE, I->start);
1855 if (J != RHS.begin()) --J;
1859 // Determine if these two live ranges overlap.
1861 if (I->start < J->start) {
1862 Overlaps = I->end > J->start;
1864 Overlaps = J->end > I->start;
1867 // If so, check value # info to determine if they are really different.
1869 // If the live range overlap will map to the same value number in the
1870 // result liverange, we can still coalesce them. If not, we can't.
1871 if (LHSValNoAssignments[I->valno->id] !=
1872 RHSValNoAssignments[J->valno->id])
1876 if (I->end < J->end) {
1885 // Update kill info. Some live ranges are extended due to copy coalescing.
1886 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1887 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1888 VNInfo *VNI = I->first;
1889 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1890 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1891 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1892 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1895 // Update kill info. Some live ranges are extended due to copy coalescing.
1896 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1897 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1898 VNInfo *VNI = I->first;
1899 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1900 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1901 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1902 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1905 // If we get here, we know that we can coalesce the live ranges. Ask the
1906 // intervals to coalesce themselves now.
1907 if ((RHS.ranges.size() > LHS.ranges.size() &&
1908 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1909 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1910 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1913 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1920 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1921 // depth of the basic block (the unsigned), and then on the MBB number.
1922 struct DepthMBBCompare {
1923 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1924 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1925 if (LHS.first > RHS.first) return true; // Deeper loops first
1926 return LHS.first == RHS.first &&
1927 LHS.second->getNumber() < RHS.second->getNumber();
1932 /// getRepIntervalSize - Returns the size of the interval that represents the
1933 /// specified register.
1935 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1936 return Rc->getRepIntervalSize(Reg);
1939 /// CopyRecSort::operator - Join priority queue sorting function.
1941 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1942 // Inner loops first.
1943 if (left.LoopDepth > right.LoopDepth)
1945 else if (left.LoopDepth == right.LoopDepth)
1946 if (left.isBackEdge && !right.isBackEdge)
1951 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1952 std::vector<CopyRec> &TryAgain) {
1953 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1955 std::vector<CopyRec> VirtCopies;
1956 std::vector<CopyRec> PhysCopies;
1957 std::vector<CopyRec> ImpDefCopies;
1958 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1959 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1961 MachineInstr *Inst = MII++;
1963 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1964 unsigned SrcReg, DstReg;
1965 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1966 DstReg = Inst->getOperand(0).getReg();
1967 SrcReg = Inst->getOperand(1).getReg();
1968 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1969 DstReg = Inst->getOperand(0).getReg();
1970 SrcReg = Inst->getOperand(2).getReg();
1971 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1974 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1975 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1977 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
1979 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1980 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
1981 else if (SrcIsPhys || DstIsPhys)
1982 PhysCopies.push_back(CopyRec(Inst, 0, false));
1984 VirtCopies.push_back(CopyRec(Inst, 0, false));
1991 // Try coalescing implicit copies first, followed by copies to / from
1992 // physical registers, then finally copies from virtual registers to
1993 // virtual registers.
1994 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1995 CopyRec &TheCopy = ImpDefCopies[i];
1997 if (!JoinCopy(TheCopy, Again))
1999 TryAgain.push_back(TheCopy);
2001 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2002 CopyRec &TheCopy = PhysCopies[i];
2004 if (!JoinCopy(TheCopy, Again))
2006 TryAgain.push_back(TheCopy);
2008 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2009 CopyRec &TheCopy = VirtCopies[i];
2011 if (!JoinCopy(TheCopy, Again))
2013 TryAgain.push_back(TheCopy);
2017 void SimpleRegisterCoalescing::joinIntervals() {
2018 DOUT << "********** JOINING INTERVALS ***********\n";
2021 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2023 std::vector<CopyRec> TryAgainList;
2024 if (loopInfo->empty()) {
2025 // If there are no loops in the function, join intervals in function order.
2026 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2028 CopyCoalesceInMBB(I, TryAgainList);
2030 // Otherwise, join intervals in inner loops before other intervals.
2031 // Unfortunately we can't just iterate over loop hierarchy here because
2032 // there may be more MBB's than BB's. Collect MBB's for sorting.
2034 // Join intervals in the function prolog first. We want to join physical
2035 // registers with virtual registers before the intervals got too long.
2036 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2037 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2038 MachineBasicBlock *MBB = I;
2039 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2042 // Sort by loop depth.
2043 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2045 // Finally, join intervals in loop nest order.
2046 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2047 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2050 // Joining intervals can allow other intervals to be joined. Iteratively join
2051 // until we make no progress.
2053 SmallVector<CopyRec, 16> TryAgain;
2054 bool ProgressMade = true;
2055 while (ProgressMade) {
2056 ProgressMade = false;
2057 while (!JoinQueue->empty()) {
2058 CopyRec R = JoinQueue->pop();
2060 bool Success = JoinCopy(R, Again);
2062 ProgressMade = true;
2064 TryAgain.push_back(R);
2068 while (!TryAgain.empty()) {
2069 JoinQueue->push(TryAgain.back());
2070 TryAgain.pop_back();
2075 bool ProgressMade = true;
2076 while (ProgressMade) {
2077 ProgressMade = false;
2079 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2080 CopyRec &TheCopy = TryAgainList[i];
2083 bool Success = JoinCopy(TheCopy, Again);
2084 if (Success || !Again) {
2085 TheCopy.MI = 0; // Mark this one as done.
2086 ProgressMade = true;
2097 /// Return true if the two specified registers belong to different register
2098 /// classes. The registers may be either phys or virt regs. In the
2099 /// case where both registers are virtual registers, it would also returns
2100 /// true by reference the RegB register class in SubRC if it is a subset of
2101 /// RegA's register class.
2103 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB,
2104 const TargetRegisterClass *&SubRC) const {
2106 // Get the register classes for the first reg.
2107 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2108 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2109 "Shouldn't consider two physregs!");
2110 return !mri_->getRegClass(RegB)->contains(RegA);
2113 // Compare against the regclass for the second reg.
2114 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2115 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2116 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2117 if (RegClassA == RegClassB)
2119 SubRC = (RegClassA->hasSubClass(RegClassB)) ? RegClassB : NULL;
2122 return !RegClassA->contains(RegB);
2125 /// lastRegisterUse - Returns the last use of the specific register between
2126 /// cycles Start and End or NULL if there are no uses.
2128 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2129 unsigned Reg, unsigned &UseIdx) const{
2131 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2132 MachineOperand *LastUse = NULL;
2133 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2134 E = mri_->use_end(); I != E; ++I) {
2135 MachineOperand &Use = I.getOperand();
2136 MachineInstr *UseMI = Use.getParent();
2137 unsigned SrcReg, DstReg;
2138 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
2139 // Ignore identity copies.
2141 unsigned Idx = li_->getInstructionIndex(UseMI);
2142 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2150 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2153 // Skip deleted instructions
2154 MachineInstr *MI = li_->getInstructionFromIndex(e);
2155 while ((e - InstrSlots::NUM) >= s && !MI) {
2156 e -= InstrSlots::NUM;
2157 MI = li_->getInstructionFromIndex(e);
2159 if (e < s || MI == NULL)
2162 // Ignore identity copies.
2163 unsigned SrcReg, DstReg;
2164 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
2165 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2166 MachineOperand &Use = MI->getOperand(i);
2167 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2168 tri_->regsOverlap(Use.getReg(), Reg)) {
2174 e -= InstrSlots::NUM;
2181 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2182 if (TargetRegisterInfo::isPhysicalRegister(reg))
2183 cerr << tri_->getName(reg);
2185 cerr << "%reg" << reg;
2188 void SimpleRegisterCoalescing::releaseMemory() {
2189 JoinedCopies.clear();
2190 ReMatCopies.clear();
2194 static bool isZeroLengthInterval(LiveInterval *li) {
2195 for (LiveInterval::Ranges::const_iterator
2196 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2197 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
2202 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2203 /// turn the copy into an implicit def.
2205 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2206 MachineBasicBlock *MBB,
2207 unsigned DstReg, unsigned SrcReg) {
2208 MachineInstr *CopyMI = &*I;
2209 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2210 if (!li_->hasInterval(SrcReg))
2212 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2213 if (!SrcInt.empty())
2215 if (!li_->hasInterval(DstReg))
2217 LiveInterval &DstInt = li_->getInterval(DstReg);
2218 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2219 DstInt.removeValNo(DstLR->valno);
2220 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2221 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2222 CopyMI->RemoveOperand(i);
2223 bool NoUse = mri_->use_empty(SrcReg);
2225 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2226 E = mri_->reg_end(); I != E; ) {
2227 assert(I.getOperand().isDef());
2228 MachineInstr *DefMI = &*I;
2230 // The implicit_def source has no other uses, delete it.
2231 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2232 li_->RemoveMachineInstrFromMaps(DefMI);
2233 DefMI->eraseFromParent();
2241 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2243 mri_ = &fn.getRegInfo();
2244 tm_ = &fn.getTarget();
2245 tri_ = tm_->getRegisterInfo();
2246 tii_ = tm_->getInstrInfo();
2247 li_ = &getAnalysis<LiveIntervals>();
2248 loopInfo = &getAnalysis<MachineLoopInfo>();
2250 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2251 << "********** Function: "
2252 << ((Value*)mf_->getFunction())->getName() << '\n';
2254 allocatableRegs_ = tri_->getAllocatableSet(fn);
2255 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2256 E = tri_->regclass_end(); I != E; ++I)
2257 allocatableRCRegs_.insert(std::make_pair(*I,
2258 tri_->getAllocatableSet(fn, *I)));
2260 // Join (coalesce) intervals if requested.
2261 if (EnableJoining) {
2263 DOUT << "********** INTERVALS POST JOINING **********\n";
2264 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2265 I->second->print(DOUT, tri_);
2270 // Perform a final pass over the instructions and compute spill weights
2271 // and remove identity moves.
2272 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2273 mbbi != mbbe; ++mbbi) {
2274 MachineBasicBlock* mbb = mbbi;
2275 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2277 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2279 MachineInstr *MI = mii;
2280 unsigned SrcReg, DstReg;
2281 if (JoinedCopies.count(MI)) {
2282 // Delete all coalesced copies.
2283 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) {
2284 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2285 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2286 "Unrecognized copy instruction");
2287 DstReg = MI->getOperand(0).getReg();
2289 if (MI->registerDefIsDead(DstReg)) {
2290 LiveInterval &li = li_->getInterval(DstReg);
2291 if (!ShortenDeadCopySrcLiveRange(li, MI))
2292 ShortenDeadCopyLiveRange(li, MI);
2294 li_->RemoveMachineInstrFromMaps(MI);
2295 mii = mbbi->erase(mii);
2300 // Now check if this is a remat'ed def instruction which is now dead.
2301 if (ReMatDefs.count(MI)) {
2303 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2304 const MachineOperand &MO = MI->getOperand(i);
2305 if (!MO.isReg() || MO.isDead())
2307 unsigned Reg = MO.getReg();
2308 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2309 !mri_->use_empty(Reg)) {
2315 li_->RemoveMachineInstrFromMaps(mii);
2316 mii = mbbi->erase(mii);
2321 // If the move will be an identity move delete it
2322 bool isMove = tii_->isMoveInstr(*MI, SrcReg, DstReg);
2323 if (isMove && SrcReg == DstReg) {
2324 if (li_->hasInterval(SrcReg)) {
2325 LiveInterval &RegInt = li_->getInterval(SrcReg);
2326 // If def of this move instruction is dead, remove its live range
2327 // from the dstination register's live interval.
2328 if (MI->registerDefIsDead(DstReg)) {
2329 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2330 ShortenDeadCopyLiveRange(RegInt, MI);
2333 li_->RemoveMachineInstrFromMaps(MI);
2334 mii = mbbi->erase(mii);
2336 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2337 SmallSet<unsigned, 4> UniqueUses;
2338 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2339 const MachineOperand &mop = MI->getOperand(i);
2340 if (mop.isReg() && mop.getReg() &&
2341 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2342 unsigned reg = mop.getReg();
2343 // Multiple uses of reg by the same instruction. It should not
2344 // contribute to spill weight again.
2345 if (UniqueUses.count(reg) != 0)
2347 LiveInterval &RegInt = li_->getInterval(reg);
2349 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2350 UniqueUses.insert(reg);
2358 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2359 LiveInterval &LI = *I->second;
2360 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2361 // If the live interval length is essentially zero, i.e. in every live
2362 // range the use follows def immediately, it doesn't make sense to spill
2363 // it and hope it will be easier to allocate for this li.
2364 if (isZeroLengthInterval(&LI))
2365 LI.weight = HUGE_VALF;
2367 bool isLoad = false;
2368 SmallVector<LiveInterval*, 4> SpillIs;
2369 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2370 // If all of the definitions of the interval are re-materializable,
2371 // it is a preferred candidate for spilling. If non of the defs are
2372 // loads, then it's potentially very cheap to re-materialize.
2373 // FIXME: this gets much more complicated once we support non-trivial
2374 // re-materialization.
2382 // Slightly prefer live interval that has been assigned a preferred reg.
2386 // Divide the weight of the interval by its size. This encourages
2387 // spilling of intervals that are large and have few uses, and
2388 // discourages spilling of small intervals with many uses.
2389 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2397 /// print - Implement the dump method.
2398 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2402 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2403 return new SimpleRegisterCoalescing();
2406 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2407 DEFINING_FILE_FOR(SimpleRegisterCoalescing)