1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
23 class SimpleRegisterCoalescing;
25 class TargetRegisterInfo;
26 class TargetInstrInfo;
28 class MachineLoopInfo;
30 /// CopyRec - Representation for copy instructions in coalescer queue.
35 CopyRec(MachineInstr *mi, unsigned depth)
36 : MI(mi), LoopDepth(depth) {};
39 class SimpleRegisterCoalescing : public MachineFunctionPass,
40 public RegisterCoalescer {
42 MachineRegisterInfo* mri_;
43 const TargetMachine* tm_;
44 const TargetRegisterInfo* tri_;
45 const TargetInstrInfo* tii_;
47 const MachineLoopInfo* loopInfo;
50 BitVector allocatableRegs_;
51 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
53 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
55 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
57 /// ReMatCopies - Keep track of copies eliminated due to remat.
59 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
61 /// ReMatDefs - Keep track of definition instructions which have
63 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
66 static char ID; // Pass identifcation, replacement for typeid
67 SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
79 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
80 virtual void releaseMemory();
82 /// runOnMachineFunction - pass entry point
83 virtual bool runOnMachineFunction(MachineFunction&);
85 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
86 // This runs as an independent pass, so don't do anything.
90 /// print - Implement the dump method.
91 virtual void print(raw_ostream &O, const Module* = 0) const;
94 /// joinIntervals - join compatible live intervals
97 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
98 /// copies that cannot yet be coalesced into the "TryAgain" list.
99 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
100 std::vector<CopyRec> &TryAgain);
102 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
103 /// which are the src/dst of the copy instruction CopyMI. This returns true
104 /// if the copy was successfully coalesced away. If it is not currently
105 /// possible to coalesce this interval, but it may be possible if other
106 /// things get coalesced, then it returns true by reference in 'Again'.
107 bool JoinCopy(CopyRec &TheCopy, bool &Again);
109 /// JoinIntervals - Attempt to join these two intervals. On failure, this
110 /// returns false. Otherwise, if one of the intervals being joined is a
111 /// physreg, this method always canonicalizes DestInt to be it. The output
112 /// "SrcInt" will not have been modified, so we can use this information
113 /// below to update aliases.
114 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
116 /// SimpleJoin - Attempt to join the specified interval into this one. The
117 /// caller of this method must guarantee that the RHS only contains a single
118 /// value number and that the RHS is not defined by a copy from this
119 /// interval. This returns false if the intervals are not joinable, or it
120 /// joins them and returns true.
121 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
123 /// Return true if the two specified registers belong to different register
124 /// classes. The registers may be either phys or virt regs.
125 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
127 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
128 /// the source value number is defined by a copy from the destination reg
129 /// see if we can merge these two destination reg valno# into a single
130 /// value number, eliminating a copy.
131 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
132 MachineInstr *CopyMI);
134 /// HasOtherReachingDefs - Return true if there are definitions of IntB
135 /// other than BValNo val# that can reach uses of AValno val# of IntA.
136 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
137 VNInfo *AValNo, VNInfo *BValNo);
139 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
140 /// If the source value number is defined by a commutable instruction and
141 /// its other operand is coalesced to the copy dest register, see if we
142 /// can transform the copy into a noop by commuting the definition.
143 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
144 MachineInstr *CopyMI);
146 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic
147 /// block as the copy instruction, trim the ive interval to the last use
149 bool TrimLiveIntervalToLastUse(LiveIndex CopyIdx,
150 MachineBasicBlock *CopyMBB,
151 LiveInterval &li, const LiveRange *LR);
153 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
154 /// computation, replace the copy by rematerialize the definition.
155 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
156 unsigned DstSubIdx, MachineInstr *CopyMI);
158 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
159 /// from an implicit def to another register can be coalesced away.
160 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
161 LiveInterval &li, LiveInterval &ImpLi) const;
163 /// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
164 /// implicit_def and it is being removed. Turn all copies from this value#
165 /// into implicit_defs.
166 void TurnCopiesFromValNoToImpDefs(LiveInterval &li, VNInfo *VNI);
168 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
169 /// a virtual destination register with physical source register.
170 bool isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
171 MachineBasicBlock *CopyMBB,
172 LiveInterval &DstInt, LiveInterval &SrcInt);
174 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
175 /// copy from a virtual source register to a physical destination register.
176 bool isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
177 MachineBasicBlock *CopyMBB,
178 LiveInterval &DstInt, LiveInterval &SrcInt);
180 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
181 /// two virtual registers from different register classes.
182 bool isWinToJoinCrossClass(unsigned LargeReg, unsigned SmallReg,
185 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
186 /// register with a physical register, check if any of the virtual register
187 /// operand is a sub-register use or def. If so, make sure it won't result
188 /// in an illegal extract_subreg or insert_subreg instruction.
189 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
190 unsigned VirtReg, unsigned PhysReg);
192 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
193 /// an extract_subreg where dst is a physical register, e.g.
194 /// cl = EXTRACT_SUBREG reg1024, 1
195 bool CanJoinExtractSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
196 unsigned SubIdx, unsigned &RealDstReg);
198 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
199 /// an insert_subreg where src is a physical register, e.g.
200 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
201 bool CanJoinInsertSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
202 unsigned SubIdx, unsigned &RealDstReg);
204 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
205 /// the specified live interval is defined by a copy from the specified
207 bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
210 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
211 /// update the subregister number if it is not zero. If DstReg is a
212 /// physical register and the existing subregister number of the def / use
213 /// being updated is not zero, make sure to set it to the correct physical
215 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
217 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
218 /// due to live range lengthening as the result of coalescing.
219 void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
221 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
222 /// Return true if live interval is removed.
223 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
225 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
226 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
227 /// as ends the live range there. If there isn't another use, then this
228 /// live range is dead. Return true if live interval is removed.
229 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
231 /// RemoveDeadDef - If a def of a live interval is now determined dead,
232 /// remove the val# it defines. If the live interval becomes empty, remove
234 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
236 /// lastRegisterUse - Returns the last use of the specific register between
237 /// cycles Start and End or NULL if there are no uses.
238 MachineOperand *lastRegisterUse(LiveIndex Start,
239 LiveIndex End, unsigned Reg,
240 LiveIndex &LastUseIdx) const;
242 /// CalculateSpillWeights - Compute spill weights for all virtual register
244 void CalculateSpillWeights();
246 void printRegName(unsigned reg) const;
249 } // End llvm namespace