1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/RegisterCoalescer.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/IndexedMap.h"
26 class SimpleRegisterCoalescing;
28 class TargetRegisterInfo;
29 class TargetInstrInfo;
31 class MachineLoopInfo;
33 /// CopyRec - Representation for copy instructions in coalescer queue.
39 CopyRec(MachineInstr *mi, unsigned depth, bool be)
40 : MI(mi), LoopDepth(depth), isBackEdge(be) {};
43 template<class SF> class JoinPriorityQueue;
45 /// CopyRecSort - Sorting function for coalescer queue.
47 struct CopyRecSort : public std::binary_function<CopyRec,CopyRec,bool> {
48 JoinPriorityQueue<CopyRecSort> *JPQ;
49 explicit CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
50 CopyRecSort(const CopyRecSort &RHS) : JPQ(RHS.JPQ) {}
51 bool operator()(CopyRec left, CopyRec right) const;
54 /// JoinQueue - A priority queue of copy instructions the coalescer is
57 class JoinPriorityQueue {
58 SimpleRegisterCoalescing *Rc;
59 std::priority_queue<CopyRec, std::vector<CopyRec>, SF> Queue;
62 explicit JoinPriorityQueue(SimpleRegisterCoalescing *rc)
63 : Rc(rc), Queue(SF(this)) {}
65 bool empty() const { return Queue.empty(); }
66 void push(CopyRec R) { Queue.push(R); }
68 if (empty()) return CopyRec(0, 0, false);
69 CopyRec R = Queue.top();
74 // Callbacks to SimpleRegisterCoalescing.
75 unsigned getRepIntervalSize(unsigned Reg);
78 class SimpleRegisterCoalescing : public MachineFunctionPass,
79 public RegisterCoalescer {
81 MachineRegisterInfo* mri_;
82 const TargetMachine* tm_;
83 const TargetRegisterInfo* tri_;
84 const TargetInstrInfo* tii_;
86 const MachineLoopInfo* loopInfo;
88 BitVector allocatableRegs_;
89 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
91 /// JoinQueue - A priority queue of copy instructions the coalescer is
93 JoinPriorityQueue<CopyRecSort> *JoinQueue;
95 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
97 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
99 /// ReMatCopies - Keep track of copies eliminated due to remat.
101 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
103 /// ReMatDefs - Keep track of definition instructions which have
105 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
108 static char ID; // Pass identifcation, replacement for typeid
109 SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
121 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
122 virtual void releaseMemory();
124 /// runOnMachineFunction - pass entry point
125 virtual bool runOnMachineFunction(MachineFunction&);
127 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
128 // This runs as an independent pass, so don't do anything.
132 /// getRepIntervalSize - Called from join priority queue sorting function.
133 /// It returns the size of the interval that represent the given register.
134 unsigned getRepIntervalSize(unsigned Reg) {
135 if (!li_->hasInterval(Reg))
137 return li_->getApproximateInstructionCount(li_->getInterval(Reg)) *
138 LiveIntervals::InstrSlots::NUM;
141 /// print - Implement the dump method.
142 virtual void print(std::ostream &O, const Module* = 0) const;
143 void print(std::ostream *O, const Module* M = 0) const {
148 /// joinIntervals - join compatible live intervals
149 void joinIntervals();
151 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
152 /// copies that cannot yet be coalesced into the "TryAgain" list.
153 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
154 std::vector<CopyRec> &TryAgain);
156 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
157 /// which are the src/dst of the copy instruction CopyMI. This returns true
158 /// if the copy was successfully coalesced away. If it is not currently
159 /// possible to coalesce this interval, but it may be possible if other
160 /// things get coalesced, then it returns true by reference in 'Again'.
161 bool JoinCopy(CopyRec &TheCopy, bool &Again);
163 /// JoinIntervals - Attempt to join these two intervals. On failure, this
164 /// returns false. Otherwise, if one of the intervals being joined is a
165 /// physreg, this method always canonicalizes DestInt to be it. The output
166 /// "SrcInt" will not have been modified, so we can use this information
167 /// below to update aliases.
168 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
170 /// SimpleJoin - Attempt to join the specified interval into this one. The
171 /// caller of this method must guarantee that the RHS only contains a single
172 /// value number and that the RHS is not defined by a copy from this
173 /// interval. This returns false if the intervals are not joinable, or it
174 /// joins them and returns true.
175 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
177 /// Return true if the two specified registers belong to different register
178 /// classes. The registers may be either phys or virt regs. In the
179 /// case where both registers are virtual registers, it would also returns
180 /// true by reference the RegB register class in SubRC if it is a subset of
181 /// RegA's register class.
182 bool differingRegisterClasses(unsigned RegA, unsigned RegB,
183 const TargetRegisterClass *&SubRC) const;
186 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
187 /// the source value number is defined by a copy from the destination reg
188 /// see if we can merge these two destination reg valno# into a single
189 /// value number, eliminating a copy.
190 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
191 MachineInstr *CopyMI);
193 /// HasOtherReachingDefs - Return true if there are definitions of IntB
194 /// other than BValNo val# that can reach uses of AValno val# of IntA.
195 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
196 VNInfo *AValNo, VNInfo *BValNo);
198 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
199 /// If the source value number is defined by a commutable instruction and
200 /// its other operand is coalesced to the copy dest register, see if we
201 /// can transform the copy into a noop by commuting the definition.
202 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
203 MachineInstr *CopyMI);
205 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
206 MachineInstr *CopyMI);
208 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
209 /// turn the copy into an implicit def.
210 bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
211 MachineBasicBlock *MBB,
212 unsigned DstReg, unsigned SrcReg);
214 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
215 /// from an implicit def to another register can be coalesced away.
216 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
217 LiveInterval &li, LiveInterval &ImpLi) const;
219 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
220 /// def and it is being removed. Turn all copies from this value# into
221 /// identity copies so they will be removed.
222 void RemoveCopiesFromValNo(LiveInterval &li, VNInfo *VNI);
224 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
225 /// a subset of the register class of SrcReg, return true if it's profitable
226 /// to coalesce the two registers.
227 bool isProfitableToCoalesceToSubRC(unsigned SrcReg, unsigned DstReg,
228 MachineBasicBlock *MBB);
230 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
231 /// register with a physical register, check if any of the virtual register
232 /// operand is a sub-register use or def. If so, make sure it won't result
233 /// in an illegal extract_subreg or insert_subreg instruction.
234 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
235 unsigned VirtReg, unsigned PhysReg);
237 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
238 /// the specified live interval is defined by a copy from the specified
240 bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
243 /// isBackEdgeCopy - Return true if CopyMI is a back edge copy.
245 bool isBackEdgeCopy(MachineInstr *CopyMI, unsigned DstReg) const;
247 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
248 /// update the subregister number if it is not zero. If DstReg is a
249 /// physical register and the existing subregister number of the def / use
250 /// being updated is not zero, make sure to set it to the correct physical
252 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
254 /// RemoveDeadImpDef - Remove implicit_def instructions which are
255 /// "re-defining" registers due to insert_subreg coalescing. e.g.
256 void RemoveDeadImpDef(unsigned Reg, LiveInterval &LI);
258 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
259 /// due to live range lengthening as the result of coalescing.
260 void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
262 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
263 /// Return true if live interval is removed.
264 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
266 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
267 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
268 /// as ends the live range there. If there isn't another use, then this
269 /// live range is dead. Return true if live interval is removed.
270 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
272 /// RemoveDeadDef - If a def of a live interval is now determined dead,
273 /// remove the val# it defines. If the live interval becomes empty, remove
275 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
277 /// lastRegisterUse - Returns the last use of the specific register between
278 /// cycles Start and End or NULL if there are no uses.
279 MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
280 unsigned &LastUseIdx) const;
282 void printRegName(unsigned reg) const;
285 } // End llvm namespace