1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/RegisterCoalescer.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/IndexedMap.h"
26 class SimpleRegisterCoalescing;
28 class TargetRegisterInfo;
29 class TargetInstrInfo;
31 class MachineLoopInfo;
33 /// CopyRec - Representation for copy instructions in coalescer queue.
39 CopyRec(MachineInstr *mi, unsigned depth, bool be)
40 : MI(mi), LoopDepth(depth), isBackEdge(be) {};
43 template<class SF> class JoinPriorityQueue;
45 /// CopyRecSort - Sorting function for coalescer queue.
47 struct CopyRecSort : public std::binary_function<CopyRec,CopyRec,bool> {
48 JoinPriorityQueue<CopyRecSort> *JPQ;
49 explicit CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
50 CopyRecSort(const CopyRecSort &RHS) : JPQ(RHS.JPQ) {}
51 bool operator()(CopyRec left, CopyRec right) const;
54 /// JoinQueue - A priority queue of copy instructions the coalescer is
57 class JoinPriorityQueue {
58 SimpleRegisterCoalescing *Rc;
59 std::priority_queue<CopyRec, std::vector<CopyRec>, SF> Queue;
62 explicit JoinPriorityQueue(SimpleRegisterCoalescing *rc)
63 : Rc(rc), Queue(SF(this)) {}
65 bool empty() const { return Queue.empty(); }
66 void push(CopyRec R) { Queue.push(R); }
68 if (empty()) return CopyRec(0, 0, false);
69 CopyRec R = Queue.top();
74 // Callbacks to SimpleRegisterCoalescing.
75 unsigned getRepIntervalSize(unsigned Reg);
78 class SimpleRegisterCoalescing : public MachineFunctionPass,
79 public RegisterCoalescer {
81 MachineRegisterInfo* mri_;
82 const TargetMachine* tm_;
83 const TargetRegisterInfo* tri_;
84 const TargetInstrInfo* tii_;
86 const MachineLoopInfo* loopInfo;
88 BitVector allocatableRegs_;
89 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
91 /// JoinQueue - A priority queue of copy instructions the coalescer is
93 JoinPriorityQueue<CopyRecSort> *JoinQueue;
95 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
97 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
100 static char ID; // Pass identifcation, replacement for typeid
101 SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}
113 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
114 virtual void releaseMemory();
116 /// runOnMachineFunction - pass entry point
117 virtual bool runOnMachineFunction(MachineFunction&);
119 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
120 // This runs as an independent pass, so don't do anything.
124 /// getRepIntervalSize - Called from join priority queue sorting function.
125 /// It returns the size of the interval that represent the given register.
126 unsigned getRepIntervalSize(unsigned Reg) {
127 if (!li_->hasInterval(Reg))
129 return li_->getApproximateInstructionCount(li_->getInterval(Reg)) *
130 LiveIntervals::InstrSlots::NUM;
133 /// print - Implement the dump method.
134 virtual void print(std::ostream &O, const Module* = 0) const;
135 void print(std::ostream *O, const Module* M = 0) const {
140 /// joinIntervals - join compatible live intervals
141 void joinIntervals();
143 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
144 /// copies that cannot yet be coalesced into the "TryAgain" list.
145 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
146 std::vector<CopyRec> &TryAgain);
148 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
149 /// which are the src/dst of the copy instruction CopyMI. This returns true
150 /// if the copy was successfully coalesced away. If it is not currently
151 /// possible to coalesce this interval, but it may be possible if other
152 /// things get coalesced, then it returns true by reference in 'Again'.
153 bool JoinCopy(CopyRec &TheCopy, bool &Again);
155 /// JoinIntervals - Attempt to join these two intervals. On failure, this
156 /// returns false. Otherwise, if one of the intervals being joined is a
157 /// physreg, this method always canonicalizes DestInt to be it. The output
158 /// "SrcInt" will not have been modified, so we can use this information
159 /// below to update aliases.
160 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
162 /// SimpleJoin - Attempt to join the specified interval into this one. The
163 /// caller of this method must guarantee that the RHS only contains a single
164 /// value number and that the RHS is not defined by a copy from this
165 /// interval. This returns false if the intervals are not joinable, or it
166 /// joins them and returns true.
167 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
169 /// Return true if the two specified registers belong to different register
170 /// classes. The registers may be either phys or virt regs. In the
171 /// case where both registers are virtual registers, it would also returns
172 /// true by reference the RegB register class in SubRC if it is a subset of
173 /// RegA's register class.
174 bool differingRegisterClasses(unsigned RegA, unsigned RegB,
175 const TargetRegisterClass *&SubRC) const;
178 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
179 /// the source value number is defined by a copy from the destination reg
180 /// see if we can merge these two destination reg valno# into a single
181 /// value number, eliminating a copy.
182 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
183 MachineInstr *CopyMI);
185 /// HasOtherReachingDefs - Return true if there are definitions of IntB
186 /// other than BValNo val# that can reach uses of AValno val# of IntA.
187 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
188 VNInfo *AValNo, VNInfo *BValNo);
190 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
191 /// If the source value number is defined by a commutable instruction and
192 /// its other operand is coalesced to the copy dest register, see if we
193 /// can transform the copy into a noop by commuting the definition.
194 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
195 MachineInstr *CopyMI);
197 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
198 /// turn the copy into an implicit def.
199 bool TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
200 MachineBasicBlock *MBB,
201 unsigned DstReg, unsigned SrcReg);
203 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
204 /// from an implicit def to another register can be coalesced away.
205 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
206 LiveInterval &li, LiveInterval &ImpLi) const;
208 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
209 /// def and it is being removed. Turn all copies from this value# into
210 /// identity copies so they will be removed.
211 void RemoveCopiesFromValNo(LiveInterval &li, VNInfo *VNI);
213 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
214 /// a subset of the register class of SrcReg, return true if it's profitable
215 /// to coalesce the two registers.
216 bool isProfitableToCoalesceToSubRC(unsigned SrcReg, unsigned DstReg,
217 MachineBasicBlock *MBB);
219 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
220 /// the specified live interval is defined by a copy from the specified
222 bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
225 /// isBackEdgeCopy - Return true if CopyMI is a back edge copy.
227 bool isBackEdgeCopy(MachineInstr *CopyMI, unsigned DstReg) const;
229 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
230 /// update the subregister number if it is not zero. If DstReg is a
231 /// physical register and the existing subregister number of the def / use
232 /// being updated is not zero, make sure to set it to the correct physical
234 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
236 /// RemoveDeadImpDef - Remove implicit_def instructions which are
237 /// "re-defining" registers due to insert_subreg coalescing. e.g.
238 void RemoveDeadImpDef(unsigned Reg, LiveInterval &LI);
240 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
241 /// due to live range lengthening as the result of coalescing.
242 void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
244 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
245 /// Return true if live interval is removed.
246 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
248 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
249 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
250 /// as ends the live range there. If there isn't another use, then this
251 /// live range is dead. Return true if live interval is removed.
252 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
254 /// lastRegisterUse - Returns the last use of the specific register between
255 /// cycles Start and End or NULL if there are no uses.
256 MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
257 unsigned &LastUseIdx) const;
259 void printRegName(unsigned reg) const;
262 } // End llvm namespace