1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
12 #include "llvm/CodeGen/LiveRangeEdit.h"
13 #include "llvm/CodeGen/LiveStackAnalysis.h"
14 #include "llvm/CodeGen/MachineFrameInfo.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineLoopInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "spiller"
32 enum SpillerName { trivial, inline_ };
35 static cl::opt<SpillerName>
37 cl::desc("Spiller to use: (default: standard)"),
39 cl::values(clEnumVal(trivial, "trivial spiller"),
40 clEnumValN(inline_, "inline", "inline spiller"),
44 // Spiller virtual destructor implementation.
45 Spiller::~Spiller() {}
49 /// Utility class for spillers.
50 class SpillerBase : public Spiller {
52 MachineFunctionPass *pass;
56 MachineFrameInfo *mfi;
57 MachineRegisterInfo *mri;
58 const TargetInstrInfo *tii;
59 const TargetRegisterInfo *tri;
61 /// Construct a spiller base.
62 SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
63 : pass(&pass), mf(&mf), vrm(&vrm)
65 lis = &pass.getAnalysis<LiveIntervals>();
66 mfi = mf.getFrameInfo();
67 mri = &mf.getRegInfo();
68 tii = mf.getTarget().getInstrInfo();
69 tri = mf.getTarget().getRegisterInfo();
72 /// Add spill ranges for every use/def of the live interval, inserting loads
73 /// immediately before each use, and stores after each def. No folding or
74 /// remat is attempted.
75 void trivialSpillEverywhere(LiveRangeEdit& LRE) {
76 LiveInterval* li = &LRE.getParent();
78 DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
80 assert(li->weight != llvm::huge_valf &&
81 "Attempting to spill already spilled value.");
83 assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
84 "Trying to spill a stack slot.");
86 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
89 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
91 // Iterate over reg uses/defs.
92 for (MachineRegisterInfo::reg_instr_iterator
93 regItr = mri->reg_instr_begin(li->reg);
94 regItr != mri->reg_instr_end();) {
96 // Grab the use/def instr.
97 MachineInstr *mi = &*regItr;
99 DEBUG(dbgs() << " Processing " << *mi);
101 // Step regItr to the next use/def instr.
104 // Collect uses & defs for this instr.
105 SmallVector<unsigned, 2> indices;
108 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
109 MachineOperand &op = mi->getOperand(i);
110 if (!op.isReg() || op.getReg() != li->reg)
112 hasUse |= mi->getOperand(i).isUse();
113 hasDef |= mi->getOperand(i).isDef();
114 indices.push_back(i);
117 // Create a new virtual register for the load and/or store.
118 unsigned NewVReg = LRE.create();
120 // Update the reg operands & kill flags.
121 for (unsigned i = 0; i < indices.size(); ++i) {
122 unsigned mopIdx = indices[i];
123 MachineOperand &mop = mi->getOperand(mopIdx);
125 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
129 assert(hasUse || hasDef);
131 // Insert reload if necessary.
132 MachineBasicBlock::iterator miItr(mi);
134 MachineInstrSpan MIS(miItr);
136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc,
138 lis->InsertMachineInstrRangeInMaps(MIS.begin(), miItr);
141 // Insert store if necessary.
143 MachineInstrSpan MIS(miItr);
145 tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg,
147 lis->InsertMachineInstrRangeInMaps(std::next(miItr), MIS.end());
153 } // end anonymous namespace
157 /// Spills any live range using the spill-everywhere method with no attempt at
159 class TrivialSpiller : public SpillerBase {
162 TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
164 : SpillerBase(pass, mf, vrm) {}
166 void spill(LiveRangeEdit &LRE) override {
167 // Ignore spillIs - we don't use it.
168 trivialSpillEverywhere(LRE);
172 } // end anonymous namespace
174 void Spiller::anchor() { }
176 llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
179 switch (spillerOpt) {
180 case trivial: return new TrivialSpiller(pass, mf, vrm);
181 case inline_: return createInlineSpiller(pass, mf, vrm);
183 llvm_unreachable("Invalid spiller optimization");