1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "spiller"
13 #include "VirtRegMap.h"
14 #include "LiveRangeEdit.h"
15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
16 #include "llvm/CodeGen/LiveStackAnalysis.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
32 enum SpillerName { trivial, inline_ };
35 static cl::opt<SpillerName>
37 cl::desc("Spiller to use: (default: standard)"),
39 cl::values(clEnumVal(trivial, "trivial spiller"),
40 clEnumValN(inline_, "inline", "inline spiller"),
44 // Spiller virtual destructor implementation.
45 Spiller::~Spiller() {}
49 /// Utility class for spillers.
50 class SpillerBase : public Spiller {
52 MachineFunctionPass *pass;
56 MachineFrameInfo *mfi;
57 MachineRegisterInfo *mri;
58 const TargetInstrInfo *tii;
59 const TargetRegisterInfo *tri;
61 /// Construct a spiller base.
62 SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
63 : pass(&pass), mf(&mf), vrm(&vrm)
65 lis = &pass.getAnalysis<LiveIntervals>();
66 mfi = mf.getFrameInfo();
67 mri = &mf.getRegInfo();
68 tii = mf.getTarget().getInstrInfo();
69 tri = mf.getTarget().getRegisterInfo();
72 /// Add spill ranges for every use/def of the live interval, inserting loads
73 /// immediately before each use, and stores after each def. No folding or
74 /// remat is attempted.
75 void trivialSpillEverywhere(LiveInterval *li,
76 SmallVectorImpl<LiveInterval*> &newIntervals) {
77 DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
79 assert(li->weight != HUGE_VALF &&
80 "Attempting to spill already spilled value.");
82 assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
83 "Trying to spill a stack slot.");
85 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
87 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
88 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
90 // Iterate over reg uses/defs.
91 for (MachineRegisterInfo::reg_iterator
92 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
94 // Grab the use/def instr.
95 MachineInstr *mi = &*regItr;
97 DEBUG(dbgs() << " Processing " << *mi);
99 // Step regItr to the next use/def instr.
102 } while (regItr != mri->reg_end() && (&*regItr == mi));
104 // Collect uses & defs for this instr.
105 SmallVector<unsigned, 2> indices;
108 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
109 MachineOperand &op = mi->getOperand(i);
110 if (!op.isReg() || op.getReg() != li->reg)
112 hasUse |= mi->getOperand(i).isUse();
113 hasDef |= mi->getOperand(i).isDef();
114 indices.push_back(i);
117 // Create a new vreg & interval for this instr.
118 unsigned newVReg = mri->createVirtualRegister(trc);
120 vrm->assignVirt2StackSlot(newVReg, ss);
121 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
122 newLI->weight = HUGE_VALF;
124 // Update the reg operands & kill flags.
125 for (unsigned i = 0; i < indices.size(); ++i) {
126 unsigned mopIdx = indices[i];
127 MachineOperand &mop = mi->getOperand(mopIdx);
129 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
133 assert(hasUse || hasDef);
135 // Insert reload if necessary.
136 MachineBasicBlock::iterator miItr(mi);
138 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
140 MachineInstr *loadInstr(prior(miItr));
141 SlotIndex loadIndex =
142 lis->InsertMachineInstrInMaps(loadInstr).getRegSlot();
143 SlotIndex endIndex = loadIndex.getNextIndex();
145 newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
146 newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
149 // Insert store if necessary.
151 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
153 MachineInstr *storeInstr(llvm::next(miItr));
154 SlotIndex storeIndex =
155 lis->InsertMachineInstrInMaps(storeInstr).getRegSlot();
156 SlotIndex beginIndex = storeIndex.getPrevIndex();
158 newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());
159 newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
162 newIntervals.push_back(newLI);
167 } // end anonymous namespace
171 /// Spills any live range using the spill-everywhere method with no attempt at
173 class TrivialSpiller : public SpillerBase {
176 TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
178 : SpillerBase(pass, mf, vrm) {}
180 void spill(LiveRangeEdit &LRE) {
181 // Ignore spillIs - we don't use it.
182 trivialSpillEverywhere(&LRE.getParent(), *LRE.getNewVRegs());
186 } // end anonymous namespace
188 llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
191 switch (spillerOpt) {
192 default: assert(0 && "unknown spiller");
193 case trivial: return new TrivialSpiller(pass, mf, vrm);
194 case inline_: return createInlineSpiller(pass, mf, vrm);