1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "spiller"
13 #include "VirtRegMap.h"
14 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
28 enum SpillerName { trivial, standard, splitting };
31 static cl::opt<SpillerName>
33 cl::desc("Spiller to use: (default: standard)"),
35 cl::values(clEnumVal(trivial, "trivial spiller"),
36 clEnumVal(standard, "default spiller"),
37 clEnumVal(splitting, "splitting spiller"),
41 // Spiller virtual destructor implementation.
42 Spiller::~Spiller() {}
46 /// Utility class for spillers.
47 class SpillerBase : public Spiller {
51 MachineFrameInfo *mfi;
52 MachineRegisterInfo *mri;
53 const TargetInstrInfo *tii;
54 const TargetRegisterInfo *tri;
57 /// Construct a spiller base.
58 SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
59 : mf(mf), lis(lis), vrm(vrm)
61 mfi = mf->getFrameInfo();
62 mri = &mf->getRegInfo();
63 tii = mf->getTarget().getInstrInfo();
64 tri = mf->getTarget().getRegisterInfo();
67 /// Add spill ranges for every use/def of the live interval, inserting loads
68 /// immediately before each use, and stores after each def. No folding or
69 /// remat is attempted.
70 std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
71 DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
73 assert(li->weight != HUGE_VALF &&
74 "Attempting to spill already spilled value.");
76 assert(!li->isStackSlot() &&
77 "Trying to spill a stack slot.");
79 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
81 std::vector<LiveInterval*> added;
83 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
84 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
86 // Iterate over reg uses/defs.
87 for (MachineRegisterInfo::reg_iterator
88 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
90 // Grab the use/def instr.
91 MachineInstr *mi = &*regItr;
93 DEBUG(dbgs() << " Processing " << *mi);
95 // Step regItr to the next use/def instr.
98 } while (regItr != mri->reg_end() && (&*regItr == mi));
100 // Collect uses & defs for this instr.
101 SmallVector<unsigned, 2> indices;
104 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
105 MachineOperand &op = mi->getOperand(i);
106 if (!op.isReg() || op.getReg() != li->reg)
108 hasUse |= mi->getOperand(i).isUse();
109 hasDef |= mi->getOperand(i).isDef();
110 indices.push_back(i);
113 // Create a new vreg & interval for this instr.
114 unsigned newVReg = mri->createVirtualRegister(trc);
116 vrm->assignVirt2StackSlot(newVReg, ss);
117 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
118 newLI->weight = HUGE_VALF;
120 // Update the reg operands & kill flags.
121 for (unsigned i = 0; i < indices.size(); ++i) {
122 unsigned mopIdx = indices[i];
123 MachineOperand &mop = mi->getOperand(mopIdx);
125 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
129 assert(hasUse || hasDef);
131 // Insert reload if necessary.
132 MachineBasicBlock::iterator miItr(mi);
134 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
136 MachineInstr *loadInstr(prior(miItr));
137 SlotIndex loadIndex =
138 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
139 SlotIndex endIndex = loadIndex.getNextIndex();
141 newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
142 loadVNI->addKill(endIndex);
143 newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
146 // Insert store if necessary.
148 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
150 MachineInstr *storeInstr(llvm::next(miItr));
151 SlotIndex storeIndex =
152 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
153 SlotIndex beginIndex = storeIndex.getPrevIndex();
155 newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
156 storeVNI->addKill(storeIndex);
157 newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
160 added.push_back(newLI);
167 } // end anonymous namespace
171 /// Spills any live range using the spill-everywhere method with no attempt at
173 class TrivialSpiller : public SpillerBase {
176 TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
177 : SpillerBase(mf, lis, vrm) {}
179 std::vector<LiveInterval*> spill(LiveInterval *li,
180 SmallVectorImpl<LiveInterval*> &spillIs,
182 // Ignore spillIs - we don't use it.
183 return trivialSpillEverywhere(li);
187 } // end anonymous namespace
191 /// Falls back on LiveIntervals::addIntervalsForSpills.
192 class StandardSpiller : public Spiller {
195 const MachineLoopInfo *loopInfo;
198 StandardSpiller(LiveIntervals *lis, const MachineLoopInfo *loopInfo,
200 : lis(lis), loopInfo(loopInfo), vrm(vrm) {}
202 /// Falls back on LiveIntervals::addIntervalsForSpills.
203 std::vector<LiveInterval*> spill(LiveInterval *li,
204 SmallVectorImpl<LiveInterval*> &spillIs,
206 return lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
210 } // end anonymous namespace
214 /// When a call to spill is placed this spiller will first try to break the
215 /// interval up into its component values (one new interval per value).
216 /// If this fails, or if a call is placed to spill a previously split interval
217 /// then the spiller falls back on the standard spilling mechanism.
218 class SplittingSpiller : public StandardSpiller {
220 SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
221 const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
222 : StandardSpiller(lis, loopInfo, vrm) {
224 mri = &mf->getRegInfo();
225 tii = mf->getTarget().getInstrInfo();
226 tri = mf->getTarget().getRegisterInfo();
229 std::vector<LiveInterval*> spill(LiveInterval *li,
230 SmallVectorImpl<LiveInterval*> &spillIs,
231 SlotIndex *earliestStart) {
233 if (worthTryingToSplit(li)) {
234 return tryVNISplit(li, earliestStart);
237 return StandardSpiller::spill(li, spillIs, earliestStart);
242 MachineRegisterInfo *mri;
243 const TargetInstrInfo *tii;
244 const TargetRegisterInfo *tri;
245 DenseSet<LiveInterval*> alreadySplit;
247 bool worthTryingToSplit(LiveInterval *li) const {
248 return (!alreadySplit.count(li) && li->getNumValNums() > 1);
251 /// Try to break a LiveInterval into its component values.
252 std::vector<LiveInterval*> tryVNISplit(LiveInterval *li,
253 SlotIndex *earliestStart) {
255 DEBUG(dbgs() << "Trying VNI split of %reg" << *li << "\n");
257 std::vector<LiveInterval*> added;
258 SmallVector<VNInfo*, 4> vnis;
260 std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis));
262 for (SmallVectorImpl<VNInfo*>::iterator vniItr = vnis.begin(),
263 vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) {
264 VNInfo *vni = *vniItr;
266 // Skip unused VNIs, or VNIs with no kills.
267 if (vni->isUnused() || vni->kills.empty())
270 DEBUG(dbgs() << " Extracted Val #" << vni->id << " as ");
271 LiveInterval *splitInterval = extractVNI(li, vni);
273 if (splitInterval != 0) {
274 DEBUG(dbgs() << *splitInterval << "\n");
275 added.push_back(splitInterval);
276 alreadySplit.insert(splitInterval);
277 if (earliestStart != 0) {
278 if (splitInterval->beginIndex() < *earliestStart)
279 *earliestStart = splitInterval->beginIndex();
282 DEBUG(dbgs() << "0\n");
286 DEBUG(dbgs() << "Original LI: " << *li << "\n");
288 // If there original interval still contains some live ranges
289 // add it to added and alreadySplit.
292 alreadySplit.insert(li);
293 if (earliestStart != 0) {
294 if (li->beginIndex() < *earliestStart)
295 *earliestStart = li->beginIndex();
302 /// Extract the given value number from the interval.
303 LiveInterval* extractVNI(LiveInterval *li, VNInfo *vni) const {
304 assert(vni->isDefAccurate() || vni->isPHIDef());
305 assert(!vni->kills.empty());
307 // Create a new vreg and live interval, copy VNI kills & ranges over.
308 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
309 unsigned newVReg = mri->createVirtualRegister(trc);
311 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
312 VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator());
314 // Start by copying all live ranges in the VN to the new interval.
315 for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end();
316 rItr != rEnd; ++rItr) {
317 if (rItr->valno == vni) {
318 newLI->addRange(LiveRange(rItr->start, rItr->end, newVNI));
322 // Erase the old VNI & ranges.
323 li->removeValNo(vni);
325 // Collect all current uses of the register belonging to the given VNI.
326 // We'll use this to rename the register after we've dealt with the def.
327 std::set<MachineInstr*> uses;
328 for (MachineRegisterInfo::use_iterator
329 useItr = mri->use_begin(li->reg), useEnd = mri->use_end();
330 useItr != useEnd; ++useItr) {
331 uses.insert(&*useItr);
334 // Process the def instruction for this VNI.
335 if (newVNI->isPHIDef()) {
336 // Insert a copy at the start of the MBB. The range proceeding the
337 // copy will be attached to the original LiveInterval.
338 MachineBasicBlock *defMBB = lis->getMBBFromIndex(newVNI->def);
339 tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc,
341 MachineInstr *copyMI = defMBB->begin();
342 copyMI->addRegisterKilled(li->reg, tri);
343 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
344 VNInfo *phiDefVNI = li->getNextValue(lis->getMBBStartIdx(defMBB),
345 0, false, lis->getVNInfoAllocator());
346 phiDefVNI->setIsPHIDef(true);
347 phiDefVNI->addKill(copyIdx.getDefIndex());
348 li->addRange(LiveRange(phiDefVNI->def, copyIdx.getDefIndex(), phiDefVNI));
349 LiveRange *oldPHIDefRange =
350 newLI->getLiveRangeContaining(lis->getMBBStartIdx(defMBB));
352 // If the old phi def starts in the middle of the range chop it up.
353 if (oldPHIDefRange->start < lis->getMBBStartIdx(defMBB)) {
354 LiveRange oldPHIDefRange2(copyIdx.getDefIndex(), oldPHIDefRange->end,
355 oldPHIDefRange->valno);
356 oldPHIDefRange->end = lis->getMBBStartIdx(defMBB);
357 newLI->addRange(oldPHIDefRange2);
358 } else if (oldPHIDefRange->start == lis->getMBBStartIdx(defMBB)) {
359 // Otherwise if it's at the start of the range just trim it.
360 oldPHIDefRange->start = copyIdx.getDefIndex();
362 assert(false && "PHI def range doesn't cover PHI def?");
365 newVNI->def = copyIdx.getDefIndex();
366 newVNI->setCopy(copyMI);
367 newVNI->setIsPHIDef(false); // not a PHI def anymore.
368 newVNI->setIsDefAccurate(true);
370 // non-PHI def. Rename the def. If it's two-addr that means renaming the use
371 // and inserting a new copy too.
372 MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def);
373 // We'll rename this now, so we can remove it from uses.
375 unsigned defOpIdx = defInst->findRegisterDefOperandIdx(li->reg);
376 bool isTwoAddr = defInst->isRegTiedToUseOperand(defOpIdx),
377 twoAddrUseIsUndef = false;
379 for (unsigned i = 0; i < defInst->getNumOperands(); ++i) {
380 MachineOperand &mo = defInst->getOperand(i);
381 if (mo.isReg() && (mo.isDef() || isTwoAddr) && (mo.getReg()==li->reg)) {
383 if (isTwoAddr && mo.isUse() && mo.isUndef())
384 twoAddrUseIsUndef = true;
388 SlotIndex defIdx = lis->getInstructionIndex(defInst);
389 newVNI->def = defIdx.getDefIndex();
391 if (isTwoAddr && !twoAddrUseIsUndef) {
392 MachineBasicBlock *defMBB = defInst->getParent();
393 tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc,
395 MachineInstr *copyMI = prior(MachineBasicBlock::iterator(defInst));
396 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
397 copyMI->addRegisterKilled(li->reg, tri);
398 LiveRange *origUseRange =
399 li->getLiveRangeContaining(newVNI->def.getUseIndex());
400 VNInfo *origUseVNI = origUseRange->valno;
401 origUseRange->end = copyIdx.getDefIndex();
402 bool updatedKills = false;
403 for (unsigned k = 0; k < origUseVNI->kills.size(); ++k) {
404 if (origUseVNI->kills[k] == defIdx.getDefIndex()) {
405 origUseVNI->kills[k] = copyIdx.getDefIndex();
410 assert(updatedKills && "Failed to update VNI kill list.");
411 VNInfo *copyVNI = newLI->getNextValue(copyIdx.getDefIndex(), copyMI,
412 true, lis->getVNInfoAllocator());
413 copyVNI->addKill(defIdx.getDefIndex());
414 LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
415 newLI->addRange(copyRange);
419 for (std::set<MachineInstr*>::iterator
420 usesItr = uses.begin(), usesEnd = uses.end();
421 usesItr != usesEnd; ++usesItr) {
422 MachineInstr *useInst = *usesItr;
423 SlotIndex useIdx = lis->getInstructionIndex(useInst);
424 LiveRange *useRange =
425 newLI->getLiveRangeContaining(useIdx.getUseIndex());
427 // If this use doesn't belong to the new interval skip it.
431 // This use doesn't belong to the VNI, skip it.
432 if (useRange->valno != newVNI)
435 // Check if this instr is two address.
436 unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg);
437 bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx);
439 // Rename uses (and defs for two-address instrs).
440 for (unsigned i = 0; i < useInst->getNumOperands(); ++i) {
441 MachineOperand &mo = useInst->getOperand(i);
442 if (mo.isReg() && (mo.isUse() || isTwoAddress) &&
443 (mo.getReg() == li->reg)) {
448 // If this is a two address instruction we've got some extra work to do.
450 // We modified the def operand, so we need to copy back to the original
452 MachineBasicBlock *useMBB = useInst->getParent();
453 MachineBasicBlock::iterator useItr(useInst);
454 tii->copyRegToReg(*useMBB, llvm::next(useItr), li->reg, newVReg, trc, trc,
456 MachineInstr *copyMI = llvm::next(useItr);
457 copyMI->addRegisterKilled(newVReg, tri);
458 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
460 // Change the old two-address defined range & vni to start at
461 // (and be defined by) the copy.
462 LiveRange *origDefRange =
463 li->getLiveRangeContaining(useIdx.getDefIndex());
464 origDefRange->start = copyIdx.getDefIndex();
465 origDefRange->valno->def = copyIdx.getDefIndex();
466 origDefRange->valno->setCopy(copyMI);
468 // Insert a new range & vni for the two-address-to-copy value. This
469 // will be attached to the new live interval.
471 newLI->getNextValue(useIdx.getDefIndex(), 0, true,
472 lis->getVNInfoAllocator());
473 copyVNI->addKill(copyIdx.getDefIndex());
474 LiveRange copyRange(useIdx.getDefIndex(),copyIdx.getDefIndex(),copyVNI);
475 newLI->addRange(copyRange);
479 // Iterate over any PHI kills - we'll need to insert new copies for them.
480 for (VNInfo::KillSet::iterator
481 killItr = newVNI->kills.begin(), killEnd = newVNI->kills.end();
482 killItr != killEnd; ++killItr) {
483 SlotIndex killIdx(*killItr);
484 if (killItr->isPHI()) {
485 MachineBasicBlock *killMBB = lis->getMBBFromIndex(killIdx);
486 LiveRange *oldKillRange =
487 newLI->getLiveRangeContaining(killIdx);
489 assert(oldKillRange != 0 && "No kill range?");
491 tii->copyRegToReg(*killMBB, killMBB->getFirstTerminator(),
492 li->reg, newVReg, trc, trc,
494 MachineInstr *copyMI = prior(killMBB->getFirstTerminator());
495 copyMI->addRegisterKilled(newVReg, tri);
496 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
498 // Save the current end. We may need it to add a new range if the
499 // current range runs of the end of the MBB.
500 SlotIndex newKillRangeEnd = oldKillRange->end;
501 oldKillRange->end = copyIdx.getDefIndex();
503 if (newKillRangeEnd != lis->getMBBEndIdx(killMBB)) {
504 assert(newKillRangeEnd > lis->getMBBEndIdx(killMBB) &&
505 "PHI kill range doesn't reach kill-block end. Not sane.");
506 newLI->addRange(LiveRange(lis->getMBBEndIdx(killMBB),
507 newKillRangeEnd, newVNI));
510 *killItr = oldKillRange->end;
511 VNInfo *newKillVNI = li->getNextValue(copyIdx.getDefIndex(),
513 lis->getVNInfoAllocator());
514 newKillVNI->addKill(lis->getMBBTerminatorGap(killMBB));
515 newKillVNI->setHasPHIKill(true);
516 li->addRange(LiveRange(copyIdx.getDefIndex(),
517 lis->getMBBEndIdx(killMBB),
523 newVNI->setHasPHIKill(false);
530 } // end anonymous namespace
533 llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
534 const MachineLoopInfo *loopInfo,
536 switch (spillerOpt) {
537 default: assert(0 && "unknown spiller");
538 case trivial: return new TrivialSpiller(mf, lis, vrm);
539 case standard: return new StandardSpiller(lis, loopInfo, vrm);
540 case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm);