1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "spiller"
13 #include "VirtRegMap.h"
14 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
29 enum SpillerName { trivial, standard, splitting, inline_ };
32 static cl::opt<SpillerName>
34 cl::desc("Spiller to use: (default: standard)"),
36 cl::values(clEnumVal(trivial, "trivial spiller"),
37 clEnumVal(standard, "default spiller"),
38 clEnumVal(splitting, "splitting spiller"),
39 "inline", inline_, "inline spiller",
43 // Spiller virtual destructor implementation.
44 Spiller::~Spiller() {}
48 /// Utility class for spillers.
49 class SpillerBase : public Spiller {
53 MachineFrameInfo *mfi;
54 MachineRegisterInfo *mri;
55 const TargetInstrInfo *tii;
56 const TargetRegisterInfo *tri;
59 /// Construct a spiller base.
60 SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
61 : mf(mf), lis(lis), vrm(vrm)
63 mfi = mf->getFrameInfo();
64 mri = &mf->getRegInfo();
65 tii = mf->getTarget().getInstrInfo();
66 tri = mf->getTarget().getRegisterInfo();
69 /// Add spill ranges for every use/def of the live interval, inserting loads
70 /// immediately before each use, and stores after each def. No folding or
71 /// remat is attempted.
72 void trivialSpillEverywhere(LiveInterval *li,
73 std::vector<LiveInterval*> &newIntervals) {
74 DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
76 assert(li->weight != HUGE_VALF &&
77 "Attempting to spill already spilled value.");
79 assert(!li->isStackSlot() &&
80 "Trying to spill a stack slot.");
82 DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
84 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
85 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
87 // Iterate over reg uses/defs.
88 for (MachineRegisterInfo::reg_iterator
89 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
91 // Grab the use/def instr.
92 MachineInstr *mi = &*regItr;
94 DEBUG(dbgs() << " Processing " << *mi);
96 // Step regItr to the next use/def instr.
99 } while (regItr != mri->reg_end() && (&*regItr == mi));
101 // Collect uses & defs for this instr.
102 SmallVector<unsigned, 2> indices;
105 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
106 MachineOperand &op = mi->getOperand(i);
107 if (!op.isReg() || op.getReg() != li->reg)
109 hasUse |= mi->getOperand(i).isUse();
110 hasDef |= mi->getOperand(i).isDef();
111 indices.push_back(i);
114 // Create a new vreg & interval for this instr.
115 unsigned newVReg = mri->createVirtualRegister(trc);
117 vrm->assignVirt2StackSlot(newVReg, ss);
118 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
119 newLI->weight = HUGE_VALF;
121 // Update the reg operands & kill flags.
122 for (unsigned i = 0; i < indices.size(); ++i) {
123 unsigned mopIdx = indices[i];
124 MachineOperand &mop = mi->getOperand(mopIdx);
126 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
130 assert(hasUse || hasDef);
132 // Insert reload if necessary.
133 MachineBasicBlock::iterator miItr(mi);
135 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
137 MachineInstr *loadInstr(prior(miItr));
138 SlotIndex loadIndex =
139 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
140 SlotIndex endIndex = loadIndex.getNextIndex();
142 newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
143 newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
146 // Insert store if necessary.
148 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
150 MachineInstr *storeInstr(llvm::next(miItr));
151 SlotIndex storeIndex =
152 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
153 SlotIndex beginIndex = storeIndex.getPrevIndex();
155 newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
156 newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
159 newIntervals.push_back(newLI);
164 } // end anonymous namespace
168 /// Spills any live range using the spill-everywhere method with no attempt at
170 class TrivialSpiller : public SpillerBase {
173 TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
174 : SpillerBase(mf, lis, vrm) {}
176 void spill(LiveInterval *li,
177 std::vector<LiveInterval*> &newIntervals,
178 SmallVectorImpl<LiveInterval*> &,
180 // Ignore spillIs - we don't use it.
181 trivialSpillEverywhere(li, newIntervals);
185 } // end anonymous namespace
189 /// Falls back on LiveIntervals::addIntervalsForSpills.
190 class StandardSpiller : public Spiller {
193 const MachineLoopInfo *loopInfo;
196 StandardSpiller(LiveIntervals *lis, const MachineLoopInfo *loopInfo,
198 : lis(lis), loopInfo(loopInfo), vrm(vrm) {}
200 /// Falls back on LiveIntervals::addIntervalsForSpills.
201 void spill(LiveInterval *li,
202 std::vector<LiveInterval*> &newIntervals,
203 SmallVectorImpl<LiveInterval*> &spillIs,
205 std::vector<LiveInterval*> added =
206 lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
207 newIntervals.insert(newIntervals.end(), added.begin(), added.end());
211 } // end anonymous namespace
215 /// When a call to spill is placed this spiller will first try to break the
216 /// interval up into its component values (one new interval per value).
217 /// If this fails, or if a call is placed to spill a previously split interval
218 /// then the spiller falls back on the standard spilling mechanism.
219 class SplittingSpiller : public StandardSpiller {
221 SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
222 const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
223 : StandardSpiller(lis, loopInfo, vrm) {
225 mri = &mf->getRegInfo();
226 tii = mf->getTarget().getInstrInfo();
227 tri = mf->getTarget().getRegisterInfo();
230 void spill(LiveInterval *li,
231 std::vector<LiveInterval*> &newIntervals,
232 SmallVectorImpl<LiveInterval*> &spillIs,
233 SlotIndex *earliestStart) {
234 if (worthTryingToSplit(li))
235 tryVNISplit(li, earliestStart);
237 StandardSpiller::spill(li, newIntervals, spillIs, earliestStart);
242 MachineRegisterInfo *mri;
243 const TargetInstrInfo *tii;
244 const TargetRegisterInfo *tri;
245 DenseSet<LiveInterval*> alreadySplit;
247 bool worthTryingToSplit(LiveInterval *li) const {
248 return (!alreadySplit.count(li) && li->getNumValNums() > 1);
251 /// Try to break a LiveInterval into its component values.
252 std::vector<LiveInterval*> tryVNISplit(LiveInterval *li,
253 SlotIndex *earliestStart) {
255 DEBUG(dbgs() << "Trying VNI split of %reg" << *li << "\n");
257 std::vector<LiveInterval*> added;
258 SmallVector<VNInfo*, 4> vnis;
260 std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis));
262 for (SmallVectorImpl<VNInfo*>::iterator vniItr = vnis.begin(),
263 vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) {
264 VNInfo *vni = *vniItr;
270 DEBUG(dbgs() << " Extracted Val #" << vni->id << " as ");
271 LiveInterval *splitInterval = extractVNI(li, vni);
273 if (splitInterval != 0) {
274 DEBUG(dbgs() << *splitInterval << "\n");
275 added.push_back(splitInterval);
276 alreadySplit.insert(splitInterval);
277 if (earliestStart != 0) {
278 if (splitInterval->beginIndex() < *earliestStart)
279 *earliestStart = splitInterval->beginIndex();
282 DEBUG(dbgs() << "0\n");
286 DEBUG(dbgs() << "Original LI: " << *li << "\n");
288 // If there original interval still contains some live ranges
289 // add it to added and alreadySplit.
292 alreadySplit.insert(li);
293 if (earliestStart != 0) {
294 if (li->beginIndex() < *earliestStart)
295 *earliestStart = li->beginIndex();
302 /// Extract the given value number from the interval.
303 LiveInterval* extractVNI(LiveInterval *li, VNInfo *vni) const {
304 assert(vni->isDefAccurate() || vni->isPHIDef());
306 // Create a new vreg and live interval, copy VNI ranges over.
307 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
308 unsigned newVReg = mri->createVirtualRegister(trc);
310 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
311 VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator());
313 // Start by copying all live ranges in the VN to the new interval.
314 for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end();
315 rItr != rEnd; ++rItr) {
316 if (rItr->valno == vni) {
317 newLI->addRange(LiveRange(rItr->start, rItr->end, newVNI));
321 // Erase the old VNI & ranges.
322 li->removeValNo(vni);
324 // Collect all current uses of the register belonging to the given VNI.
325 // We'll use this to rename the register after we've dealt with the def.
326 std::set<MachineInstr*> uses;
327 for (MachineRegisterInfo::use_iterator
328 useItr = mri->use_begin(li->reg), useEnd = mri->use_end();
329 useItr != useEnd; ++useItr) {
330 uses.insert(&*useItr);
333 // Process the def instruction for this VNI.
334 if (newVNI->isPHIDef()) {
335 // Insert a copy at the start of the MBB. The range proceeding the
336 // copy will be attached to the original LiveInterval.
337 MachineBasicBlock *defMBB = lis->getMBBFromIndex(newVNI->def);
338 tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc,
340 MachineInstr *copyMI = defMBB->begin();
341 copyMI->addRegisterKilled(li->reg, tri);
342 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
343 VNInfo *phiDefVNI = li->getNextValue(lis->getMBBStartIdx(defMBB),
344 0, false, lis->getVNInfoAllocator());
345 phiDefVNI->setIsPHIDef(true);
346 li->addRange(LiveRange(phiDefVNI->def, copyIdx.getDefIndex(), phiDefVNI));
347 LiveRange *oldPHIDefRange =
348 newLI->getLiveRangeContaining(lis->getMBBStartIdx(defMBB));
350 // If the old phi def starts in the middle of the range chop it up.
351 if (oldPHIDefRange->start < lis->getMBBStartIdx(defMBB)) {
352 LiveRange oldPHIDefRange2(copyIdx.getDefIndex(), oldPHIDefRange->end,
353 oldPHIDefRange->valno);
354 oldPHIDefRange->end = lis->getMBBStartIdx(defMBB);
355 newLI->addRange(oldPHIDefRange2);
356 } else if (oldPHIDefRange->start == lis->getMBBStartIdx(defMBB)) {
357 // Otherwise if it's at the start of the range just trim it.
358 oldPHIDefRange->start = copyIdx.getDefIndex();
360 assert(false && "PHI def range doesn't cover PHI def?");
363 newVNI->def = copyIdx.getDefIndex();
364 newVNI->setCopy(copyMI);
365 newVNI->setIsPHIDef(false); // not a PHI def anymore.
366 newVNI->setIsDefAccurate(true);
368 // non-PHI def. Rename the def. If it's two-addr that means renaming the use
369 // and inserting a new copy too.
370 MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def);
371 // We'll rename this now, so we can remove it from uses.
373 unsigned defOpIdx = defInst->findRegisterDefOperandIdx(li->reg);
374 bool isTwoAddr = defInst->isRegTiedToUseOperand(defOpIdx),
375 twoAddrUseIsUndef = false;
377 for (unsigned i = 0; i < defInst->getNumOperands(); ++i) {
378 MachineOperand &mo = defInst->getOperand(i);
379 if (mo.isReg() && (mo.isDef() || isTwoAddr) && (mo.getReg()==li->reg)) {
381 if (isTwoAddr && mo.isUse() && mo.isUndef())
382 twoAddrUseIsUndef = true;
386 SlotIndex defIdx = lis->getInstructionIndex(defInst);
387 newVNI->def = defIdx.getDefIndex();
389 if (isTwoAddr && !twoAddrUseIsUndef) {
390 MachineBasicBlock *defMBB = defInst->getParent();
391 tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc,
393 MachineInstr *copyMI = prior(MachineBasicBlock::iterator(defInst));
394 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
395 copyMI->addRegisterKilled(li->reg, tri);
396 LiveRange *origUseRange =
397 li->getLiveRangeContaining(newVNI->def.getUseIndex());
398 origUseRange->end = copyIdx.getDefIndex();
399 VNInfo *copyVNI = newLI->getNextValue(copyIdx.getDefIndex(), copyMI,
400 true, lis->getVNInfoAllocator());
401 LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
402 newLI->addRange(copyRange);
406 for (std::set<MachineInstr*>::iterator
407 usesItr = uses.begin(), usesEnd = uses.end();
408 usesItr != usesEnd; ++usesItr) {
409 MachineInstr *useInst = *usesItr;
410 SlotIndex useIdx = lis->getInstructionIndex(useInst);
411 LiveRange *useRange =
412 newLI->getLiveRangeContaining(useIdx.getUseIndex());
414 // If this use doesn't belong to the new interval skip it.
418 // This use doesn't belong to the VNI, skip it.
419 if (useRange->valno != newVNI)
422 // Check if this instr is two address.
423 unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg);
424 bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx);
426 // Rename uses (and defs for two-address instrs).
427 for (unsigned i = 0; i < useInst->getNumOperands(); ++i) {
428 MachineOperand &mo = useInst->getOperand(i);
429 if (mo.isReg() && (mo.isUse() || isTwoAddress) &&
430 (mo.getReg() == li->reg)) {
435 // If this is a two address instruction we've got some extra work to do.
437 // We modified the def operand, so we need to copy back to the original
439 MachineBasicBlock *useMBB = useInst->getParent();
440 MachineBasicBlock::iterator useItr(useInst);
441 tii->copyRegToReg(*useMBB, llvm::next(useItr), li->reg, newVReg, trc, trc,
443 MachineInstr *copyMI = llvm::next(useItr);
444 copyMI->addRegisterKilled(newVReg, tri);
445 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
447 // Change the old two-address defined range & vni to start at
448 // (and be defined by) the copy.
449 LiveRange *origDefRange =
450 li->getLiveRangeContaining(useIdx.getDefIndex());
451 origDefRange->start = copyIdx.getDefIndex();
452 origDefRange->valno->def = copyIdx.getDefIndex();
453 origDefRange->valno->setCopy(copyMI);
455 // Insert a new range & vni for the two-address-to-copy value. This
456 // will be attached to the new live interval.
458 newLI->getNextValue(useIdx.getDefIndex(), 0, true,
459 lis->getVNInfoAllocator());
460 LiveRange copyRange(useIdx.getDefIndex(),copyIdx.getDefIndex(),copyVNI);
461 newLI->addRange(copyRange);
465 // Iterate over any PHI kills - we'll need to insert new copies for them.
466 for (LiveInterval::iterator LRI = newLI->begin(), LRE = newLI->end();
468 if (LRI->valno != newVNI || LRI->end.isPHI())
470 SlotIndex killIdx = LRI->end;
471 MachineBasicBlock *killMBB = lis->getMBBFromIndex(killIdx);
473 tii->copyRegToReg(*killMBB, killMBB->getFirstTerminator(),
474 li->reg, newVReg, trc, trc,
476 MachineInstr *copyMI = prior(killMBB->getFirstTerminator());
477 copyMI->addRegisterKilled(newVReg, tri);
478 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
480 // Save the current end. We may need it to add a new range if the
481 // current range runs of the end of the MBB.
482 SlotIndex newKillRangeEnd = LRI->end;
483 LRI->end = copyIdx.getDefIndex();
485 if (newKillRangeEnd != lis->getMBBEndIdx(killMBB)) {
486 assert(newKillRangeEnd > lis->getMBBEndIdx(killMBB) &&
487 "PHI kill range doesn't reach kill-block end. Not sane.");
488 newLI->addRange(LiveRange(lis->getMBBEndIdx(killMBB),
489 newKillRangeEnd, newVNI));
492 VNInfo *newKillVNI = li->getNextValue(copyIdx.getDefIndex(),
494 lis->getVNInfoAllocator());
495 newKillVNI->setHasPHIKill(true);
496 li->addRange(LiveRange(copyIdx.getDefIndex(),
497 lis->getMBBEndIdx(killMBB),
500 newVNI->setHasPHIKill(false);
507 } // end anonymous namespace
511 Spiller *createInlineSpiller(MachineFunction*,
513 const MachineLoopInfo*,
517 llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
518 const MachineLoopInfo *loopInfo,
520 switch (spillerOpt) {
521 default: assert(0 && "unknown spiller");
522 case trivial: return new TrivialSpiller(mf, lis, vrm);
523 case standard: return new StandardSpiller(lis, loopInfo, vrm);
524 case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm);
525 case inline_: return createInlineSpiller(mf, lis, loopInfo, vrm);