1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "spiller"
13 #include "VirtRegMap.h"
14 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
27 enum SpillerName { trivial, standard };
30 static cl::opt<SpillerName>
32 cl::desc("Spiller to use: (default: standard)"),
34 cl::values(clEnumVal(trivial, "trivial spiller"),
35 clEnumVal(standard, "default spiller"),
39 Spiller::~Spiller() {}
43 /// Utility class for spillers.
44 class SpillerBase : public Spiller {
49 MachineFrameInfo *mfi;
50 MachineRegisterInfo *mri;
51 const TargetInstrInfo *tii;
54 /// Construct a spiller base.
55 SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
56 : mf(mf), lis(lis), vrm(vrm)
58 mfi = mf->getFrameInfo();
59 mri = &mf->getRegInfo();
60 tii = mf->getTarget().getInstrInfo();
63 /// Add spill ranges for every use/def of the live interval, inserting loads
64 /// immediately before each use, and stores after each def. No folding or
65 /// remat is attempted.
66 std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
67 DEBUG(errs() << "Spilling everywhere " << *li << "\n");
69 assert(li->weight != HUGE_VALF &&
70 "Attempting to spill already spilled value.");
72 assert(!li->isStackSlot() &&
73 "Trying to spill a stack slot.");
75 DEBUG(errs() << "Trivial spill everywhere of reg" << li->reg << "\n");
77 std::vector<LiveInterval*> added;
79 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
80 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
82 // Iterate over reg uses/defs.
83 for (MachineRegisterInfo::reg_iterator
84 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
86 // Grab the use/def instr.
87 MachineInstr *mi = &*regItr;
89 DEBUG(errs() << " Processing " << *mi);
91 // Step regItr to the next use/def instr.
94 } while (regItr != mri->reg_end() && (&*regItr == mi));
96 // Collect uses & defs for this instr.
97 SmallVector<unsigned, 2> indices;
100 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
101 MachineOperand &op = mi->getOperand(i);
102 if (!op.isReg() || op.getReg() != li->reg)
104 hasUse |= mi->getOperand(i).isUse();
105 hasDef |= mi->getOperand(i).isDef();
106 indices.push_back(i);
109 // Create a new vreg & interval for this instr.
110 unsigned newVReg = mri->createVirtualRegister(trc);
112 vrm->assignVirt2StackSlot(newVReg, ss);
113 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
114 newLI->weight = HUGE_VALF;
116 // Update the reg operands & kill flags.
117 for (unsigned i = 0; i < indices.size(); ++i) {
118 unsigned mopIdx = indices[i];
119 MachineOperand &mop = mi->getOperand(mopIdx);
121 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
125 assert(hasUse || hasDef);
127 // Insert reload if necessary.
128 MachineBasicBlock::iterator miItr(mi);
130 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc);
131 MachineInstr *loadInstr(prior(miItr));
132 SlotIndex loadIndex =
133 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
134 SlotIndex endIndex = loadIndex.getNextIndex();
136 newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
137 loadVNI->addKill(endIndex);
138 newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
141 // Insert store if necessary.
143 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg, true,
145 MachineInstr *storeInstr(llvm::next(miItr));
146 SlotIndex storeIndex =
147 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
148 SlotIndex beginIndex = storeIndex.getPrevIndex();
150 newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
151 storeVNI->addKill(storeIndex);
152 newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
155 added.push_back(newLI);
164 /// Spills any live range using the spill-everywhere method with no attempt at
166 class TrivialSpiller : public SpillerBase {
169 TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
170 : SpillerBase(mf, lis, vrm) {}
172 std::vector<LiveInterval*> spill(LiveInterval *li,
173 SmallVectorImpl<LiveInterval*> &spillIs) {
174 // Ignore spillIs - we don't use it.
175 return trivialSpillEverywhere(li);
180 /// Falls back on LiveIntervals::addIntervalsForSpills.
181 class StandardSpiller : public Spiller {
184 const MachineLoopInfo *loopInfo;
187 StandardSpiller(MachineFunction *mf, LiveIntervals *lis,
188 const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
189 : lis(lis), loopInfo(loopInfo), vrm(vrm) {}
191 /// Falls back on LiveIntervals::addIntervalsForSpills.
192 std::vector<LiveInterval*> spill(LiveInterval *li,
193 SmallVectorImpl<LiveInterval*> &spillIs) {
194 return lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
201 llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
202 const MachineLoopInfo *loopInfo,
204 switch (spillerOpt) {
205 case trivial: return new TrivialSpiller(mf, lis, vrm); break;
206 case standard: return new StandardSpiller(mf, lis, loopInfo, vrm); break;
207 default: llvm_unreachable("Unreachable!"); break;