1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "spiller"
13 #include "VirtRegMap.h"
14 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
15 #include "llvm/CodeGen/LiveStackAnalysis.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
28 enum SpillerName { trivial, standard };
31 static cl::opt<SpillerName>
33 cl::desc("Spiller to use: (default: standard)"),
35 cl::values(clEnumVal(trivial, "trivial spiller"),
36 clEnumVal(standard, "default spiller"),
40 Spiller::~Spiller() {}
44 /// Utility class for spillers.
45 class SpillerBase : public Spiller {
51 MachineFrameInfo *mfi;
52 MachineRegisterInfo *mri;
53 const TargetInstrInfo *tii;
56 /// Construct a spiller base.
57 SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
59 mf(mf), lis(lis), ls(ls), vrm(vrm)
61 mfi = mf->getFrameInfo();
62 mri = &mf->getRegInfo();
63 tii = mf->getTarget().getInstrInfo();
66 /// Add spill ranges for every use/def of the live interval, inserting loads
67 /// immediately before each use, and stores after each def. No folding or
68 /// remat is attempted.
69 std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
70 DEBUG(errs() << "Spilling everywhere " << *li << "\n");
72 assert(li->weight != HUGE_VALF &&
73 "Attempting to spill already spilled value.");
75 assert(!li->isStackSlot() &&
76 "Trying to spill a stack slot.");
78 DEBUG(errs() << "Trivial spill everywhere of reg" << li->reg << "\n");
80 std::vector<LiveInterval*> added;
82 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
83 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
85 // Iterate over reg uses/defs.
86 for (MachineRegisterInfo::reg_iterator
87 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
89 // Grab the use/def instr.
90 MachineInstr *mi = &*regItr;
92 DEBUG(errs() << " Processing " << *mi);
94 // Step regItr to the next use/def instr.
97 } while (regItr != mri->reg_end() && (&*regItr == mi));
99 // Collect uses & defs for this instr.
100 SmallVector<unsigned, 2> indices;
103 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
104 MachineOperand &op = mi->getOperand(i);
105 if (!op.isReg() || op.getReg() != li->reg)
107 hasUse |= mi->getOperand(i).isUse();
108 hasDef |= mi->getOperand(i).isDef();
109 indices.push_back(i);
112 // Create a new vreg & interval for this instr.
113 unsigned newVReg = mri->createVirtualRegister(trc);
115 vrm->assignVirt2StackSlot(newVReg, ss);
116 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
117 newLI->weight = HUGE_VALF;
119 // Update the reg operands & kill flags.
120 for (unsigned i = 0; i < indices.size(); ++i) {
121 unsigned mopIdx = indices[i];
122 MachineOperand &mop = mi->getOperand(mopIdx);
124 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
128 assert(hasUse || hasDef);
130 // Insert reload if necessary.
131 MachineBasicBlock::iterator miItr(mi);
133 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc);
134 MachineInstr *loadInstr(prior(miItr));
135 SlotIndex loadIndex =
136 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
137 SlotIndex endIndex = loadIndex.getNextIndex();
139 newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
140 loadVNI->addKill(endIndex);
141 newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
144 // Insert store if necessary.
146 tii->storeRegToStackSlot(*mi->getParent(), next(miItr), newVReg, true,
148 MachineInstr *storeInstr(next(miItr));
149 SlotIndex storeIndex =
150 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
151 SlotIndex beginIndex = storeIndex.getPrevIndex();
153 newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());
154 storeVNI->addKill(storeIndex);
155 newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
158 added.push_back(newLI);
167 /// Spills any live range using the spill-everywhere method with no attempt at
169 class TrivialSpiller : public SpillerBase {
172 TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
174 : SpillerBase(mf, lis, ls, vrm) {}
176 std::vector<LiveInterval*> spill(LiveInterval *li,
177 SmallVectorImpl<LiveInterval*> &spillIs) {
178 // Ignore spillIs - we don't use it.
179 return trivialSpillEverywhere(li);
184 /// Falls back on LiveIntervals::addIntervalsForSpills.
185 class StandardSpiller : public Spiller {
188 const MachineLoopInfo *loopInfo;
191 StandardSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
192 const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
193 : lis(lis), loopInfo(loopInfo), vrm(vrm) {}
195 /// Falls back on LiveIntervals::addIntervalsForSpills.
196 std::vector<LiveInterval*> spill(LiveInterval *li,
197 SmallVectorImpl<LiveInterval*> &spillIs) {
198 return lis->addIntervalsForSpills(*li, spillIs, loopInfo, *vrm);
205 llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
207 const MachineLoopInfo *loopInfo,
209 switch (spillerOpt) {
210 case trivial: return new TrivialSpiller(mf, lis, ls, vrm); break;
211 case standard: return new StandardSpiller(mf, lis, ls, loopInfo, vrm); break;
212 default: llvm_unreachable("Unreachable!"); break;