1 //===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "spiller"
13 #include "VirtRegMap.h"
14 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Support/Debug.h"
27 Spiller::~Spiller() {}
31 class TrivialSpiller : public Spiller {
33 TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) :
34 mf(mf), lis(lis), vrm(vrm)
36 mfi = mf->getFrameInfo();
37 mri = &mf->getRegInfo();
38 tii = mf->getTarget().getInstrInfo();
41 std::vector<LiveInterval*> spill(LiveInterval *li) {
43 DOUT << "Trivial spiller spilling " << *li << "\n";
45 assert(li->weight != HUGE_VALF &&
46 "Attempting to spill already spilled value.");
48 assert(!li->isStackSlot() &&
49 "Trying to spill a stack slot.");
51 std::vector<LiveInterval*> added;
53 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
54 /*unsigned ss = mfi->CreateStackObject(trc->getSize(),
55 trc->getAlignment());*/
56 unsigned ss = vrm->assignVirt2StackSlot(li->reg);
58 MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(li->reg);
60 while (regItr != mri->reg_end()) {
62 MachineInstr *mi = &*regItr;
64 SmallVector<unsigned, 2> indices;
68 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
69 MachineOperand &op = mi->getOperand(i);
71 if (!op.isReg() || op.getReg() != li->reg)
74 hasUse |= mi->getOperand(i).isUse();
75 hasDef |= mi->getOperand(i).isDef();
80 unsigned newVReg = mri->createVirtualRegister(trc);
81 LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
82 newLI->weight = HUGE_VALF;
85 vrm->assignVirt2StackSlot(newVReg, ss);
87 for (unsigned i = 0; i < indices.size(); ++i) {
88 mi->getOperand(indices[i]).setReg(newVReg);
90 if (mi->getOperand(indices[i]).isUse()) {
91 mi->getOperand(indices[i]).setIsKill(true);
96 unsigned loadInstIdx = insertLoadFor(mi, ss, newVReg, trc);
97 unsigned start = lis->getDefIndex(loadInstIdx),
98 end = lis->getUseIndex(lis->getInstructionIndex(mi));
101 newLI->getNextValue(loadInstIdx, 0, lis->getVNInfoAllocator());
102 vni->kills.push_back(lis->getInstructionIndex(mi));
103 LiveRange lr(start, end, vni);
106 added.push_back(newLI);
110 unsigned storeInstIdx = insertStoreFor(mi, ss, newVReg, trc);
111 unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
112 end = lis->getUseIndex(storeInstIdx);
115 newLI->getNextValue(storeInstIdx, 0, lis->getVNInfoAllocator());
116 vni->kills.push_back(storeInstIdx);
117 LiveRange lr(start, end, vni);
120 added.push_back(newLI);
123 regItr = mri->reg_begin(li->reg);
135 MachineFrameInfo *mfi;
136 MachineRegisterInfo *mri;
137 const TargetInstrInfo *tii;
142 void makeRoomForInsertBefore(MachineInstr *mi) {
143 if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
144 lis->computeNumbering();
147 assert(lis->hasGapBeforeInstr(lis->getInstructionIndex(mi)));
150 unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
152 const TargetRegisterClass *trc) {
153 MachineBasicBlock::iterator nextInstItr(mi);
156 makeRoomForInsertBefore(&*nextInstItr);
158 unsigned miIdx = lis->getInstructionIndex(mi);
160 tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg,
162 MachineBasicBlock::iterator storeInstItr(mi);
164 MachineInstr *storeInst = &*storeInstItr;
165 unsigned storeInstIdx = miIdx + LiveIntervals::InstrSlots::NUM;
167 assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
168 "Store inst index already in use.");
170 lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
175 unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
177 const TargetRegisterClass *trc) {
178 MachineBasicBlock::iterator useInstItr(mi);
180 makeRoomForInsertBefore(mi);
182 unsigned miIdx = lis->getInstructionIndex(mi);
184 tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc);
185 MachineBasicBlock::iterator loadInstItr(mi);
187 MachineInstr *loadInst = &*loadInstItr;
188 unsigned loadInstIdx = miIdx - LiveIntervals::InstrSlots::NUM;
190 assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
191 "Load inst index already in use.");
193 lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
203 llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
205 return new TrivialSpiller(mf, lis, vrm);