1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 STATISTIC(NumFinished, "Number of splits finished");
32 STATISTIC(NumSimple, "Number of splits that were simple");
33 STATISTIC(NumCopies, "Number of copies inserted for splitting");
34 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
35 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42 const LiveIntervals &lis,
43 const MachineLoopInfo &mli)
44 : MF(vrm.getMachineFunction()),
48 TII(*MF.getTarget().getInstrInfo()),
50 LastSplitPoint(MF.getNumBlockIDs()) {}
52 void SplitAnalysis::clear() {
55 ThroughBlocks.clear();
57 DidRepairRange = false;
60 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 // Compute split points on the first call. The pair is independent of the
66 // current live interval.
67 if (!LSP.first.isValid()) {
68 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getMBBEndIdx(MBB);
72 LSP.first = LIS.getInstructionIndex(FirstTerm);
74 // If there is a landing pad successor, also find the call instruction.
77 // There may not be a call instruction (?) in which case we ignore LPad.
78 LSP.second = LSP.first;
79 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
82 if (I->getDesc().isCall()) {
83 LSP.second = LIS.getInstructionIndex(I);
89 // If CurLI is live into a landing pad successor, move the last split point
90 // back to the call that may throw.
91 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
97 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98 void SplitAnalysis::analyzeUses() {
99 assert(UseSlots.empty() && "Call clear first");
101 // First get all the defs from the interval values. This provides the correct
102 // slots for early clobbers.
103 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104 E = CurLI->vni_end(); I != E; ++I)
105 if (!(*I)->isPHIDef() && !(*I)->isUnused())
106 UseSlots.push_back((*I)->def);
108 // Get use slots form the use-def chain.
109 const MachineRegisterInfo &MRI = MF.getRegInfo();
110 for (MachineRegisterInfo::use_nodbg_iterator
111 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
113 if (!I.getOperand().isUndef())
114 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
116 array_pod_sort(UseSlots.begin(), UseSlots.end());
118 // Remove duplicates, keeping the smaller slot for each instruction.
119 // That is what we want for early clobbers.
120 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121 SlotIndex::isSameInstr),
124 // Compute per-live block info.
125 if (!calcLiveBlockInfo()) {
126 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127 // I am looking at you, RegisterCoalescer!
128 DidRepairRange = true;
130 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131 const_cast<LiveIntervals&>(LIS)
132 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
134 ThroughBlocks.clear();
135 bool fixed = calcLiveBlockInfo();
137 assert(fixed && "Couldn't fix broken live interval");
140 DEBUG(dbgs() << "Analyze counted "
141 << UseSlots.size() << " instrs in "
142 << UseBlocks.size() << " blocks, through "
143 << NumThroughBlocks << " blocks.\n");
146 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147 /// where CurLI is live.
148 bool SplitAnalysis::calcLiveBlockInfo() {
149 ThroughBlocks.resize(MF.getNumBlockIDs());
150 NumThroughBlocks = NumGapBlocks = 0;
154 LiveInterval::const_iterator LVI = CurLI->begin();
155 LiveInterval::const_iterator LVE = CurLI->end();
157 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158 UseI = UseSlots.begin();
159 UseE = UseSlots.end();
161 // Loop over basic blocks where CurLI is live.
162 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
166 SlotIndex Start, Stop;
167 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
169 // If the block contains no uses, the range must be live through. At one
170 // point, RegisterCoalescer could create dangling ranges that ended
172 if (UseI == UseE || *UseI >= Stop) {
174 ThroughBlocks.set(BI.MBB->getNumber());
175 // The range shouldn't end mid-block if there are no uses. This shouldn't
180 // This block has uses. Find the first and last uses in the block.
182 assert(BI.FirstUse >= Start);
184 while (UseI != UseE && *UseI < Stop);
185 BI.LastUse = UseI[-1];
186 assert(BI.LastUse < Stop);
188 // LVI is the first live segment overlapping MBB.
189 BI.LiveIn = LVI->start <= Start;
191 // Look for gaps in the live range.
193 while (LVI->end < Stop) {
194 SlotIndex LastStop = LVI->end;
195 if (++LVI == LVE || LVI->start >= Stop) {
197 BI.LastUse = LastStop;
200 if (LastStop < LVI->start) {
201 // There is a gap in the live range. Create duplicate entries for the
202 // live-in snippet and the live-out snippet.
205 // Push the Live-in part.
207 UseBlocks.push_back(BI);
208 UseBlocks.back().LastUse = LastStop;
210 // Set up BI for the live-out part.
213 BI.FirstUse = LVI->start;
217 UseBlocks.push_back(BI);
219 // LVI is now at LVE or LVI->end >= Stop.
224 // Live segment ends exactly at Stop. Move to the next segment.
225 if (LVI->end == Stop && ++LVI == LVE)
228 // Pick the next basic block.
229 if (LVI->start < Stop)
232 MFI = LIS.getMBBFromIndex(LVI->start);
235 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
239 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
242 LiveInterval *li = const_cast<LiveInterval*>(cli);
243 LiveInterval::iterator LVI = li->begin();
244 LiveInterval::iterator LVE = li->end();
247 // Loop over basic blocks where li is live.
248 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
249 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
252 LVI = li->advanceTo(LVI, Stop);
257 Stop = LIS.getMBBEndIdx(MFI);
258 } while (Stop <= LVI->start);
262 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
263 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
264 const LiveInterval &Orig = LIS.getInterval(OrigReg);
265 assert(!Orig.empty() && "Splitting empty interval?");
266 LiveInterval::const_iterator I = Orig.find(Idx);
268 // Range containing Idx should begin at Idx.
269 if (I != Orig.end() && I->start <= Idx)
270 return I->start == Idx;
272 // Range does not contain Idx, previous must end at Idx.
273 return I != Orig.begin() && (--I)->end == Idx;
276 void SplitAnalysis::analyze(const LiveInterval *li) {
283 //===----------------------------------------------------------------------===//
285 //===----------------------------------------------------------------------===//
287 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
288 SplitEditor::SplitEditor(SplitAnalysis &sa,
291 MachineDominatorTree &mdt)
292 : SA(sa), LIS(lis), VRM(vrm),
293 MRI(vrm.getMachineFunction().getRegInfo()),
295 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
296 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
302 void SplitEditor::reset(LiveRangeEdit &lre) {
308 // We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
311 // We don't need an AliasAnalysis since we will only be performing
312 // cheap-as-a-copy remats anyway.
313 Edit->anyRematerializable(LIS, TII, 0);
316 void SplitEditor::dump() const {
317 if (RegAssign.empty()) {
318 dbgs() << " empty\n";
322 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
323 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
327 VNInfo *SplitEditor::defValue(unsigned RegIdx,
328 const VNInfo *ParentVNI,
330 assert(ParentVNI && "Mapping NULL value");
331 assert(Idx.isValid() && "Invalid SlotIndex");
332 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
333 LiveInterval *LI = Edit->get(RegIdx);
335 // Create a new value.
336 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
338 // Use insert for lookup, so we can add missing values with a second lookup.
339 std::pair<ValueMap::iterator, bool> InsP =
340 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
342 // This was the first time (RegIdx, ParentVNI) was mapped.
343 // Keep it as a simple def without any liveness.
347 // If the previous value was a simple mapping, add liveness for it now.
348 if (VNInfo *OldVNI = InsP.first->second) {
349 SlotIndex Def = OldVNI->def;
350 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
351 // No longer a simple mapping.
352 InsP.first->second = 0;
355 // This is a complex mapping, add liveness for VNI
356 SlotIndex Def = VNI->def;
357 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
362 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
363 assert(ParentVNI && "Mapping NULL value");
364 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
366 // ParentVNI was either unmapped or already complex mapped. Either way.
370 // This was previously a single mapping. Make sure the old def is represented
371 // by a trivial live range.
372 SlotIndex Def = VNI->def;
373 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
377 // extendRange - Extend the live range to reach Idx.
378 // Potentially create phi-def values.
379 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
380 assert(Idx.isValid() && "Invalid SlotIndex");
381 MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
382 assert(IdxMBB && "No MBB at Idx");
383 LiveInterval *LI = Edit->get(RegIdx);
385 // Is there a def in the same MBB we can extend?
386 if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
389 // Now for the fun part. We know that ParentVNI potentially has multiple defs,
390 // and we may need to create even more phi-defs to preserve VNInfo SSA form.
391 // Perform a search for all predecessor blocks where we know the dominating
393 VNInfo *VNI = findReachingDefs(LI, IdxMBB, Idx.getNextSlot());
395 // When there were multiple different values, we may need new PHIs.
399 // Poor man's SSA update for the single-value case.
400 LiveOutPair LOP(VNI, MDT[LIS.getMBBFromIndex(VNI->def)]);
401 for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
402 E = LiveInBlocks.end(); I != E; ++I) {
403 MachineBasicBlock *MBB = I->DomNode->getBlock();
404 SlotIndex Start = LIS.getMBBStartIdx(MBB);
405 if (I->Kill.isValid())
406 LI->addRange(LiveRange(Start, I->Kill, VNI));
408 LiveOutCache[MBB] = LOP;
409 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
414 /// findReachingDefs - Search the CFG for known live-out values.
415 /// Add required live-in blocks to LiveInBlocks.
416 VNInfo *SplitEditor::findReachingDefs(LiveInterval *LI,
417 MachineBasicBlock *KillMBB,
419 // Initialize the live-out cache the first time it is needed.
420 if (LiveOutSeen.empty()) {
421 unsigned N = VRM.getMachineFunction().getNumBlockIDs();
422 LiveOutSeen.resize(N);
423 LiveOutCache.resize(N);
426 // Blocks where LI should be live-in.
427 SmallVector<MachineBasicBlock*, 16> WorkList(1, KillMBB);
429 // Remember if we have seen more than one value.
430 bool UniqueVNI = true;
433 // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
434 for (unsigned i = 0; i != WorkList.size(); ++i) {
435 MachineBasicBlock *MBB = WorkList[i];
436 assert(!MBB->pred_empty() && "Value live-in to entry block?");
437 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
438 PE = MBB->pred_end(); PI != PE; ++PI) {
439 MachineBasicBlock *Pred = *PI;
440 LiveOutPair &LOP = LiveOutCache[Pred];
442 // Is this a known live-out block?
443 if (LiveOutSeen.test(Pred->getNumber())) {
444 if (VNInfo *VNI = LOP.first) {
445 if (TheVNI && TheVNI != VNI)
452 // First time. LOP is garbage and must be cleared below.
453 LiveOutSeen.set(Pred->getNumber());
455 // Does Pred provide a live-out value?
456 SlotIndex Start, Last;
457 tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
458 Last = Last.getPrevSlot();
459 VNInfo *VNI = LI->extendInBlock(Start, Last);
462 LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
463 if (TheVNI && TheVNI != VNI)
470 // No, we need a live-in value for Pred as well
472 WorkList.push_back(Pred);
474 // Loopback to KillMBB, so value is really live through.
479 // Transfer WorkList to LiveInBlocks in reverse order.
480 // This ordering works best with updateSSA().
481 LiveInBlocks.clear();
482 LiveInBlocks.reserve(WorkList.size());
483 while(!WorkList.empty())
484 LiveInBlocks.push_back(MDT[WorkList.pop_back_val()]);
486 // The kill block may not be live-through.
487 assert(LiveInBlocks.back().DomNode->getBlock() == KillMBB);
488 LiveInBlocks.back().Kill = Kill;
490 return UniqueVNI ? TheVNI : 0;
493 void SplitEditor::updateSSA() {
494 // This is essentially the same iterative algorithm that SSAUpdater uses,
495 // except we already have a dominator tree, so we don't have to recompute it.
499 // Propagate live-out values down the dominator tree, inserting phi-defs
501 for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
502 E = LiveInBlocks.end(); I != E; ++I) {
503 MachineDomTreeNode *Node = I->DomNode;
504 // Skip block if the live-in value has already been determined.
507 MachineBasicBlock *MBB = Node->getBlock();
508 MachineDomTreeNode *IDom = Node->getIDom();
509 LiveOutPair IDomValue;
511 // We need a live-in value to a block with no immediate dominator?
512 // This is probably an unreachable block that has survived somehow.
513 bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
515 // IDom dominates all of our predecessors, but it may not be their
516 // immediate dominator. Check if any of them have live-out values that are
517 // properly dominated by IDom. If so, we need a phi-def here.
519 IDomValue = LiveOutCache[IDom->getBlock()];
520 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
521 PE = MBB->pred_end(); PI != PE; ++PI) {
522 LiveOutPair Value = LiveOutCache[*PI];
523 if (!Value.first || Value.first == IDomValue.first)
525 // This predecessor is carrying something other than IDomValue.
526 // It could be because IDomValue hasn't propagated yet, or it could be
527 // because MBB is in the dominance frontier of that value.
528 if (MDT.dominates(IDom, Value.second)) {
535 // The value may be live-through even if Kill is set, as can happen when
536 // we are called from extendRange. In that case LiveOutSeen is true, and
537 // LiveOutCache indicates a foreign or missing value.
538 LiveOutPair &LOP = LiveOutCache[MBB];
540 // Create a phi-def if required.
543 SlotIndex Start = LIS.getMBBStartIdx(MBB);
544 unsigned RegIdx = RegAssign.lookup(Start);
545 LiveInterval *LI = Edit->get(RegIdx);
546 VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
547 VNI->setIsPHIDef(true);
549 // This block is done, we know the final value.
551 if (I->Kill.isValid())
552 LI->addRange(LiveRange(Start, I->Kill, VNI));
554 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
555 LOP = LiveOutPair(VNI, Node);
557 } else if (IDomValue.first) {
558 // No phi-def here. Remember incoming value.
559 I->Value = IDomValue.first;
560 if (I->Kill.isValid())
562 // Propagate IDomValue if needed:
563 // MBB is live-out and doesn't define its own value.
564 if (LOP.second != Node && LOP.first != IDomValue.first) {
572 // The values in LiveInBlocks are now accurate. No more phi-defs are needed
573 // for these blocks, so we can color the live ranges.
574 for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
575 E = LiveInBlocks.end(); I != E; ++I) {
578 assert(I->Value && "No live-in value found");
579 MachineBasicBlock *MBB = I->DomNode->getBlock();
580 SlotIndex Start = LIS.getMBBStartIdx(MBB);
581 unsigned RegIdx = RegAssign.lookup(Start);
582 LiveInterval *LI = Edit->get(RegIdx);
583 LI->addRange(LiveRange(Start, I->Kill.isValid() ?
584 I->Kill : LIS.getMBBEndIdx(MBB), I->Value));
588 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
591 MachineBasicBlock &MBB,
592 MachineBasicBlock::iterator I) {
593 MachineInstr *CopyMI = 0;
595 LiveInterval *LI = Edit->get(RegIdx);
597 // We may be trying to avoid interference that ends at a deleted instruction,
598 // so always begin RegIdx 0 early and all others late.
599 bool Late = RegIdx != 0;
601 // Attempt cheap-as-a-copy rematerialization.
602 LiveRangeEdit::Remat RM(ParentVNI);
603 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
604 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
607 // Can't remat, just insert a copy from parent.
608 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
609 .addReg(Edit->getReg());
610 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
615 // Define the value in Reg.
616 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
617 VNI->setCopy(CopyMI);
621 /// Create a new virtual register and live interval.
622 unsigned SplitEditor::openIntv() {
623 // Create the complement as index 0.
625 Edit->create(LIS, VRM);
627 // Create the open interval.
628 OpenIdx = Edit->size();
629 Edit->create(LIS, VRM);
633 void SplitEditor::selectIntv(unsigned Idx) {
634 assert(Idx != 0 && "Cannot select the complement interval");
635 assert(Idx < Edit->size() && "Can only select previously opened interval");
636 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
640 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
641 assert(OpenIdx && "openIntv not called before enterIntvBefore");
642 DEBUG(dbgs() << " enterIntvBefore " << Idx);
643 Idx = Idx.getBaseIndex();
644 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
646 DEBUG(dbgs() << ": not live\n");
649 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
650 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
651 assert(MI && "enterIntvBefore called with invalid index");
653 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
657 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
658 assert(OpenIdx && "openIntv not called before enterIntvAfter");
659 DEBUG(dbgs() << " enterIntvAfter " << Idx);
660 Idx = Idx.getBoundaryIndex();
661 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
663 DEBUG(dbgs() << ": not live\n");
666 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
667 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
668 assert(MI && "enterIntvAfter called with invalid index");
670 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
671 llvm::next(MachineBasicBlock::iterator(MI)));
675 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
676 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
677 SlotIndex End = LIS.getMBBEndIdx(&MBB);
678 SlotIndex Last = End.getPrevSlot();
679 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
680 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
682 DEBUG(dbgs() << ": not live\n");
685 DEBUG(dbgs() << ": valno " << ParentVNI->id);
686 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
687 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
688 RegAssign.insert(VNI->def, End, OpenIdx);
693 /// useIntv - indicate that all instructions in MBB should use OpenLI.
694 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
695 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
698 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
699 assert(OpenIdx && "openIntv not called before useIntv");
700 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
701 RegAssign.insert(Start, End, OpenIdx);
705 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
706 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
707 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
709 // The interval must be live beyond the instruction at Idx.
710 Idx = Idx.getBoundaryIndex();
711 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
713 DEBUG(dbgs() << ": not live\n");
714 return Idx.getNextSlot();
716 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
718 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
719 assert(MI && "No instruction at index");
720 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
721 llvm::next(MachineBasicBlock::iterator(MI)));
725 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
726 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
727 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
729 // The interval must be live into the instruction at Idx.
730 Idx = Idx.getBaseIndex();
731 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
733 DEBUG(dbgs() << ": not live\n");
734 return Idx.getNextSlot();
736 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
738 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
739 assert(MI && "No instruction at index");
740 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
744 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
745 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
746 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
747 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
749 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
751 DEBUG(dbgs() << ": not live\n");
755 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
756 MBB.SkipPHIsAndLabels(MBB.begin()));
757 RegAssign.insert(Start, VNI->def, OpenIdx);
762 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
763 assert(OpenIdx && "openIntv not called before overlapIntv");
764 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
765 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
766 "Parent changes value in extended range");
767 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
768 "Range cannot span basic blocks");
770 // The complement interval will be extended as needed by extendRange().
772 markComplexMapped(0, ParentVNI);
773 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
774 RegAssign.insert(Start, End, OpenIdx);
778 /// transferValues - Transfer all possible values to the new live ranges.
779 /// Values that were rematerialized are left alone, they need extendRange().
780 bool SplitEditor::transferValues() {
781 bool Skipped = false;
782 LiveInBlocks.clear();
783 RegAssignMap::const_iterator AssignI = RegAssign.begin();
784 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
785 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
786 DEBUG(dbgs() << " blit " << *ParentI << ':');
787 VNInfo *ParentVNI = ParentI->valno;
788 // RegAssign has holes where RegIdx 0 should be used.
789 SlotIndex Start = ParentI->start;
790 AssignI.advanceTo(Start);
793 SlotIndex End = ParentI->end;
794 if (!AssignI.valid()) {
796 } else if (AssignI.start() <= Start) {
797 RegIdx = AssignI.value();
798 if (AssignI.stop() < End) {
799 End = AssignI.stop();
804 End = std::min(End, AssignI.start());
807 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
808 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
809 LiveInterval *LI = Edit->get(RegIdx);
811 // Check for a simply defined value that can be blitted directly.
812 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
813 DEBUG(dbgs() << ':' << VNI->id);
814 LI->addRange(LiveRange(Start, End, VNI));
819 // Skip rematerialized values, we need to use extendRange() and
820 // extendPHIKillRanges() to completely recompute the live ranges.
821 if (Edit->didRematerialize(ParentVNI)) {
822 DEBUG(dbgs() << "(remat)");
828 // Initialize the live-out cache the first time it is needed.
829 if (LiveOutSeen.empty()) {
830 unsigned N = VRM.getMachineFunction().getNumBlockIDs();
831 LiveOutSeen.resize(N);
832 LiveOutCache.resize(N);
835 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
836 // so the live range is accurate. Add live-in blocks in [Start;End) to the
838 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
839 SlotIndex BlockStart, BlockEnd;
840 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
842 // The first block may be live-in, or it may have its own def.
843 if (Start != BlockStart) {
844 VNInfo *VNI = LI->extendInBlock(BlockStart,
845 std::min(BlockEnd, End).getPrevSlot());
846 assert(VNI && "Missing def for complex mapped value");
847 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
848 // MBB has its own def. Is it also live-out?
849 if (BlockEnd <= End) {
850 LiveOutSeen.set(MBB->getNumber());
851 LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
853 // Skip to the next block for live-in.
855 BlockStart = BlockEnd;
858 // Handle the live-in blocks covered by [Start;End).
859 assert(Start <= BlockStart && "Expected live-in block");
860 while (BlockStart < End) {
861 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
862 BlockEnd = LIS.getMBBEndIdx(MBB);
863 if (BlockStart == ParentVNI->def) {
864 // This block has the def of a parent PHI, so it isn't live-in.
865 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
866 VNInfo *VNI = LI->extendInBlock(BlockStart,
867 std::min(BlockEnd, End).getPrevSlot());
868 assert(VNI && "Missing def for complex mapped parent PHI");
869 if (End >= BlockEnd) {
871 LiveOutSeen.set(MBB->getNumber());
872 LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
875 // This block needs a live-in value.
876 LiveInBlocks.push_back(MDT[MBB]);
877 // The last block covered may not be live-out.
879 LiveInBlocks.back().Kill = End;
881 // Live-out, but we need updateSSA to tell us the value.
882 LiveOutSeen.set(MBB->getNumber());
883 LiveOutCache[MBB] = LiveOutPair((VNInfo*)0,
884 (MachineDomTreeNode*)0);
887 BlockStart = BlockEnd;
891 } while (Start != ParentI->end);
892 DEBUG(dbgs() << '\n');
895 if (!LiveInBlocks.empty())
901 void SplitEditor::extendPHIKillRanges() {
902 // Extend live ranges to be live-out for successor PHI values.
903 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
904 E = Edit->getParent().vni_end(); I != E; ++I) {
905 const VNInfo *PHIVNI = *I;
906 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
908 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
909 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
910 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
911 PE = MBB->pred_end(); PI != PE; ++PI) {
912 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
913 // The predecessor may not have a live-out value. That is OK, like an
914 // undef PHI operand.
915 if (Edit->getParent().liveAt(End)) {
916 assert(RegAssign.lookup(End) == RegIdx &&
917 "Different register assignment in phi predecessor");
918 extendRange(RegIdx, End);
924 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
925 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
926 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
927 RE = MRI.reg_end(); RI != RE;) {
928 MachineOperand &MO = RI.getOperand();
929 MachineInstr *MI = MO.getParent();
931 // LiveDebugVariables should have handled all DBG_VALUE instructions.
932 if (MI->isDebugValue()) {
933 DEBUG(dbgs() << "Zapping " << *MI);
938 // <undef> operands don't really read the register, so it doesn't matter
939 // which register we choose. When the use operand is tied to a def, we must
940 // use the same register as the def, so just do that always.
941 SlotIndex Idx = LIS.getInstructionIndex(MI);
942 if (MO.isDef() || MO.isUndef())
943 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
945 // Rewrite to the mapped register at Idx.
946 unsigned RegIdx = RegAssign.lookup(Idx);
947 MO.setReg(Edit->get(RegIdx)->reg);
948 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
949 << Idx << ':' << RegIdx << '\t' << *MI);
951 // Extend liveness to Idx if the instruction reads reg.
952 if (!ExtendRanges || MO.isUndef())
955 // Skip instructions that don't read Reg.
957 if (!MO.getSubReg() && !MO.isEarlyClobber())
959 // We may wan't to extend a live range for a partial redef, or for a use
960 // tied to an early clobber.
961 Idx = Idx.getPrevSlot();
962 if (!Edit->getParent().liveAt(Idx))
965 Idx = Idx.getUseIndex();
967 extendRange(RegIdx, Idx);
971 void SplitEditor::deleteRematVictims() {
972 SmallVector<MachineInstr*, 8> Dead;
973 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
974 LiveInterval *LI = *I;
975 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
977 // Dead defs end at the store slot.
978 if (LII->end != LII->valno->def.getNextSlot())
980 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
981 assert(MI && "Missing instruction for dead def");
982 MI->addRegisterDead(LI->reg, &TRI);
984 if (!MI->allDefsAreDead())
987 DEBUG(dbgs() << "All defs dead: " << *MI);
995 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
998 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1001 // At this point, the live intervals in Edit contain VNInfos corresponding to
1002 // the inserted copies.
1004 // Add the original defs from the parent interval.
1005 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
1006 E = Edit->getParent().vni_end(); I != E; ++I) {
1007 const VNInfo *ParentVNI = *I;
1008 if (ParentVNI->isUnused())
1010 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1011 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
1012 VNI->setIsPHIDef(ParentVNI->isPHIDef());
1013 VNI->setCopy(ParentVNI->getCopy());
1015 // Mark rematted values as complex everywhere to force liveness computation.
1016 // The new live ranges may be truncated.
1017 if (Edit->didRematerialize(ParentVNI))
1018 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1019 markComplexMapped(i, ParentVNI);
1022 // Transfer the simply mapped values, check if any are skipped.
1023 bool Skipped = transferValues();
1025 extendPHIKillRanges();
1029 // Rewrite virtual registers, possibly extending ranges.
1030 rewriteAssigned(Skipped);
1032 // Delete defs that were rematted everywhere.
1034 deleteRematVictims();
1036 // Get rid of unused values and set phi-kill flags.
1037 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
1038 (*I)->RenumberValues(LIS);
1040 // Provide a reverse mapping from original indices to Edit ranges.
1043 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1044 LRMap->push_back(i);
1047 // Now check if any registers were separated into multiple components.
1048 ConnectedVNInfoEqClasses ConEQ(LIS);
1049 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1050 // Don't use iterators, they are invalidated by create() below.
1051 LiveInterval *li = Edit->get(i);
1052 unsigned NumComp = ConEQ.Classify(li);
1055 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
1056 SmallVector<LiveInterval*, 8> dups;
1058 for (unsigned j = 1; j != NumComp; ++j)
1059 dups.push_back(&Edit->create(LIS, VRM));
1060 ConEQ.Distribute(&dups[0], MRI);
1061 // The new intervals all map back to i.
1063 LRMap->resize(Edit->size(), i);
1066 // Calculate spill weight and allocation hints for new intervals.
1067 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
1069 assert(!LRMap || LRMap->size() == Edit->size());
1073 //===----------------------------------------------------------------------===//
1074 // Single Block Splitting
1075 //===----------------------------------------------------------------------===//
1077 /// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
1078 /// may be an advantage to split CurLI for the duration of the block.
1079 bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
1080 // If CurLI is local to one block, there is no point to splitting it.
1081 if (UseBlocks.size() <= 1)
1083 // Add blocks with multiple uses.
1084 for (unsigned i = 0, e = UseBlocks.size(); i != e; ++i) {
1085 const BlockInfo &BI = UseBlocks[i];
1086 if (BI.FirstUse == BI.LastUse)
1088 Blocks.insert(BI.MBB);
1090 return !Blocks.empty();
1093 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1095 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1096 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstUse,
1098 if (!BI.LiveOut || BI.LastUse < LastSplitPoint) {
1099 useIntv(SegStart, leaveIntvAfter(BI.LastUse));
1101 // The last use is after the last valid split point.
1102 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1103 useIntv(SegStart, SegStop);
1104 overlapIntv(SegStop, BI.LastUse);
1108 /// splitSingleBlocks - Split CurLI into a separate live interval inside each
1109 /// basic block in Blocks.
1110 void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
1111 DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
1112 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA.getUseBlocks();
1113 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1114 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1115 if (Blocks.count(BI.MBB))
1116 splitSingleBlock(BI);
1122 //===----------------------------------------------------------------------===//
1123 // Global Live Range Splitting Support
1124 //===----------------------------------------------------------------------===//
1126 // These methods support a method of global live range splitting that uses a
1127 // global algorithm to decide intervals for CFG edges. They will insert split
1128 // points and color intervals in basic blocks while avoiding interference.
1130 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1131 // are on the stack.
1133 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1134 unsigned IntvIn, SlotIndex LeaveBefore,
1135 unsigned IntvOut, SlotIndex EnterAfter){
1136 SlotIndex Start, Stop;
1137 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1139 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1140 << ") intf " << LeaveBefore << '-' << EnterAfter
1141 << ", live-through " << IntvIn << " -> " << IntvOut);
1143 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1145 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1146 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1147 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1149 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1152 DEBUG(dbgs() << ", spill on entry.\n");
1154 // <<<<<<<<< Possible LeaveBefore interference.
1155 // |-----------| Live through.
1156 // -____________ Spill on entry.
1159 SlotIndex Idx = leaveIntvAtTop(*MBB);
1160 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1166 DEBUG(dbgs() << ", reload on exit.\n");
1168 // >>>>>>> Possible EnterAfter interference.
1169 // |-----------| Live through.
1170 // ___________-- Reload on exit.
1172 selectIntv(IntvOut);
1173 SlotIndex Idx = enterIntvAtEnd(*MBB);
1174 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1179 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1180 DEBUG(dbgs() << ", straight through.\n");
1182 // |-----------| Live through.
1183 // ------------- Straight through, same intv, no interference.
1185 selectIntv(IntvOut);
1186 useIntv(Start, Stop);
1190 // We cannot legally insert splits after LSP.
1191 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1192 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1194 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1195 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1196 DEBUG(dbgs() << ", switch avoiding interference.\n");
1198 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1199 // |-----------| Live through.
1200 // ------======= Switch intervals between interference.
1202 selectIntv(IntvOut);
1204 if (LeaveBefore && LeaveBefore < LSP) {
1205 Idx = enterIntvBefore(LeaveBefore);
1208 Idx = enterIntvAtEnd(*MBB);
1211 useIntv(Start, Idx);
1212 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1213 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1217 DEBUG(dbgs() << ", create local intv for interference.\n");
1219 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1220 // |-----------| Live through.
1221 // ==---------== Switch intervals before/after interference.
1223 assert(LeaveBefore <= EnterAfter && "Missed case");
1225 selectIntv(IntvOut);
1226 SlotIndex Idx = enterIntvAfter(EnterAfter);
1228 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1231 Idx = leaveIntvBefore(LeaveBefore);
1232 useIntv(Start, Idx);
1233 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1237 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1238 unsigned IntvIn, SlotIndex LeaveBefore) {
1239 SlotIndex Start, Stop;
1240 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1242 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1243 << "), uses " << BI.FirstUse << '-' << BI.LastUse
1244 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1245 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1247 assert(IntvIn && "Must have register in");
1248 assert(BI.LiveIn && "Must be live-in");
1249 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1251 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastUse)) {
1252 DEBUG(dbgs() << " before interference.\n");
1254 // <<< Interference after kill.
1255 // |---o---x | Killed in block.
1256 // ========= Use IntvIn everywhere.
1259 useIntv(Start, BI.LastUse);
1263 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1265 if (!LeaveBefore || LeaveBefore > BI.LastUse.getBoundaryIndex()) {
1267 // <<< Possible interference after last use.
1268 // |---o---o---| Live-out on stack.
1269 // =========____ Leave IntvIn after last use.
1271 // < Interference after last use.
1272 // |---o---o--o| Live-out on stack, late last use.
1273 // ============ Copy to stack after LSP, overlap IntvIn.
1274 // \_____ Stack interval is live-out.
1276 if (BI.LastUse < LSP) {
1277 DEBUG(dbgs() << ", spill after last use before interference.\n");
1279 SlotIndex Idx = leaveIntvAfter(BI.LastUse);
1280 useIntv(Start, Idx);
1281 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1283 DEBUG(dbgs() << ", spill before last split point.\n");
1285 SlotIndex Idx = leaveIntvBefore(LSP);
1286 overlapIntv(Idx, BI.LastUse);
1287 useIntv(Start, Idx);
1288 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1293 // The interference is overlapping somewhere we wanted to use IntvIn. That
1294 // means we need to create a local interval that can be allocated a
1295 // different register.
1296 unsigned LocalIntv = openIntv();
1298 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1300 if (!BI.LiveOut || BI.LastUse < LSP) {
1302 // <<<<<<< Interference overlapping uses.
1303 // |---o---o---| Live-out on stack.
1304 // =====----____ Leave IntvIn before interference, then spill.
1306 SlotIndex To = leaveIntvAfter(BI.LastUse);
1307 SlotIndex From = enterIntvBefore(LeaveBefore);
1310 useIntv(Start, From);
1311 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1315 // <<<<<<< Interference overlapping uses.
1316 // |---o---o--o| Live-out on stack, late last use.
1317 // =====------- Copy to stack before LSP, overlap LocalIntv.
1318 // \_____ Stack interval is live-out.
1320 SlotIndex To = leaveIntvBefore(LSP);
1321 overlapIntv(To, BI.LastUse);
1322 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1325 useIntv(Start, From);
1326 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1329 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1330 unsigned IntvOut, SlotIndex EnterAfter) {
1331 SlotIndex Start, Stop;
1332 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1334 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1335 << "), uses " << BI.FirstUse << '-' << BI.LastUse
1336 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1337 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1339 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1341 assert(IntvOut && "Must have register out");
1342 assert(BI.LiveOut && "Must be live-out");
1343 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1345 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstUse)) {
1346 DEBUG(dbgs() << " after interference.\n");
1348 // >>>> Interference before def.
1349 // | o---o---| Defined in block.
1350 // ========= Use IntvOut everywhere.
1352 selectIntv(IntvOut);
1353 useIntv(BI.FirstUse, Stop);
1357 if (!EnterAfter || EnterAfter < BI.FirstUse.getBaseIndex()) {
1358 DEBUG(dbgs() << ", reload after interference.\n");
1360 // >>>> Interference before def.
1361 // |---o---o---| Live-through, stack-in.
1362 // ____========= Enter IntvOut before first use.
1364 selectIntv(IntvOut);
1365 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstUse));
1367 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1371 // The interference is overlapping somewhere we wanted to use IntvOut. That
1372 // means we need to create a local interval that can be allocated a
1373 // different register.
1374 DEBUG(dbgs() << ", interference overlaps uses.\n");
1376 // >>>>>>> Interference overlapping uses.
1377 // |---o---o---| Live-through, stack-in.
1378 // ____---====== Create local interval for interference range.
1380 selectIntv(IntvOut);
1381 SlotIndex Idx = enterIntvAfter(EnterAfter);
1383 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1386 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstUse));