1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/CalcSpillWeights.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
34 AllowSplit("spiller-splits-edges",
35 cl::desc("Allow critical edge splitting during spilling"));
37 STATISTIC(NumFinished, "Number of splits finished");
38 STATISTIC(NumSimple, "Number of splits that were simple");
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
45 const LiveIntervals &lis,
46 const MachineLoopInfo &mli)
47 : MF(vrm.getMachineFunction()),
51 TII(*MF.getTarget().getInstrInfo()),
54 void SplitAnalysis::clear() {
62 bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
63 MachineBasicBlock *T, *F;
64 SmallVector<MachineOperand, 4> Cond;
65 return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
68 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
69 void SplitAnalysis::analyzeUses() {
70 const MachineRegisterInfo &MRI = MF.getRegInfo();
71 for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
72 E = MRI.reg_end(); I != E; ++I) {
73 MachineOperand &MO = I.getOperand();
74 if (MO.isUse() && MO.isUndef())
76 MachineInstr *MI = MO.getParent();
77 if (MI->isDebugValue() || !UsingInstrs.insert(MI))
79 UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
80 MachineBasicBlock *MBB = MI->getParent();
83 array_pod_sort(UseSlots.begin(), UseSlots.end());
85 DEBUG(dbgs() << " counted "
86 << UsingInstrs.size() << " instrs, "
87 << UsingBlocks.size() << " blocks.\n");
90 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
91 /// where CurLI is live.
92 void SplitAnalysis::calcLiveBlockInfo() {
96 LiveInterval::const_iterator LVI = CurLI->begin();
97 LiveInterval::const_iterator LVE = CurLI->end();
99 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
100 UseI = UseSlots.begin();
101 UseE = UseSlots.end();
103 // Loop over basic blocks where CurLI is live.
104 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
108 tie(BI.Start, BI.Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
110 // The last split point is the latest possible insertion point that dominates
111 // all successor blocks. If interference reaches LastSplitPoint, it is not
112 // possible to insert a split or reload that makes CurLI live in the
114 MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
115 if (LSP == BI.MBB->end())
116 BI.LastSplitPoint = BI.Stop;
118 BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
120 // LVI is the first live segment overlapping MBB.
121 BI.LiveIn = LVI->start <= BI.Start;
125 // Find the first and last uses in the block.
126 BI.Uses = hasUses(MFI);
127 if (BI.Uses && UseI != UseE) {
129 assert(BI.FirstUse >= BI.Start);
131 while (UseI != UseE && *UseI < BI.Stop);
132 BI.LastUse = UseI[-1];
133 assert(BI.LastUse < BI.Stop);
136 // Look for gaps in the live range.
139 while (LVI->end < BI.Stop) {
140 SlotIndex LastStop = LVI->end;
141 if (++LVI == LVE || LVI->start >= BI.Stop) {
146 if (LastStop < LVI->start) {
153 // Don't set LiveThrough when the block has a gap.
154 BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
155 LiveBlocks.push_back(BI);
157 // LVI is now at LVE or LVI->end >= Stop.
161 // Live segment ends exactly at Stop. Move to the next segment.
162 if (LVI->end == BI.Stop && ++LVI == LVE)
165 // Pick the next basic block.
166 if (LVI->start < BI.Stop)
169 MFI = LIS.getMBBFromIndex(LVI->start);
173 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
174 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
175 const LiveInterval &Orig = LIS.getInterval(OrigReg);
176 assert(!Orig.empty() && "Splitting empty interval?");
177 LiveInterval::const_iterator I = Orig.find(Idx);
179 // Range containing Idx should begin at Idx.
180 if (I != Orig.end() && I->start <= Idx)
181 return I->start == Idx;
183 // Range does not contain Idx, previous must end at Idx.
184 return I != Orig.begin() && (--I)->end == Idx;
187 void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
188 for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
189 unsigned count = UsingBlocks.lookup(*I);
190 OS << " BB#" << (*I)->getNumber();
192 OS << '(' << count << ')';
196 void SplitAnalysis::analyze(const LiveInterval *li) {
203 //===----------------------------------------------------------------------===//
205 //===----------------------------------------------------------------------===//
207 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
208 SplitEditor::SplitEditor(SplitAnalysis &sa,
211 MachineDominatorTree &mdt)
212 : SA(sa), LIS(lis), VRM(vrm),
213 MRI(vrm.getMachineFunction().getRegInfo()),
215 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
216 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
222 void SplitEditor::reset(LiveRangeEdit &lre) {
227 LiveOutCache.clear();
229 // We don't need an AliasAnalysis since we will only be performing
230 // cheap-as-a-copy remats anyway.
231 Edit->anyRematerializable(LIS, TII, 0);
234 void SplitEditor::dump() const {
235 if (RegAssign.empty()) {
236 dbgs() << " empty\n";
240 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
241 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
245 VNInfo *SplitEditor::defValue(unsigned RegIdx,
246 const VNInfo *ParentVNI,
248 assert(ParentVNI && "Mapping NULL value");
249 assert(Idx.isValid() && "Invalid SlotIndex");
250 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
251 LiveInterval *LI = Edit->get(RegIdx);
253 // Create a new value.
254 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
256 // Preserve the PHIDef bit.
257 if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
258 VNI->setIsPHIDef(true);
260 // Use insert for lookup, so we can add missing values with a second lookup.
261 std::pair<ValueMap::iterator, bool> InsP =
262 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
264 // This was the first time (RegIdx, ParentVNI) was mapped.
265 // Keep it as a simple def without any liveness.
269 // If the previous value was a simple mapping, add liveness for it now.
270 if (VNInfo *OldVNI = InsP.first->second) {
271 SlotIndex Def = OldVNI->def;
272 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
273 // No longer a simple mapping.
274 InsP.first->second = 0;
277 // This is a complex mapping, add liveness for VNI
278 SlotIndex Def = VNI->def;
279 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
284 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
285 assert(ParentVNI && "Mapping NULL value");
286 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
288 // ParentVNI was either unmapped or already complex mapped. Either way.
292 // This was previously a single mapping. Make sure the old def is represented
293 // by a trivial live range.
294 SlotIndex Def = VNI->def;
295 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
299 // extendRange - Extend the live range to reach Idx.
300 // Potentially create phi-def values.
301 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
302 assert(Idx.isValid() && "Invalid SlotIndex");
303 MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
304 assert(IdxMBB && "No MBB at Idx");
305 LiveInterval *LI = Edit->get(RegIdx);
307 // Is there a def in the same MBB we can extend?
308 if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
311 // Now for the fun part. We know that ParentVNI potentially has multiple defs,
312 // and we may need to create even more phi-defs to preserve VNInfo SSA form.
313 // Perform a search for all predecessor blocks where we know the dominating
314 // VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
315 DEBUG(dbgs() << "\n Reaching defs for BB#" << IdxMBB->getNumber()
316 << " at " << Idx << " in " << *LI << '\n');
318 // Blocks where LI should be live-in.
319 SmallVector<MachineDomTreeNode*, 16> LiveIn;
320 LiveIn.push_back(MDT[IdxMBB]);
322 // Remember if we have seen more than one value.
323 bool UniqueVNI = true;
326 // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
327 for (unsigned i = 0; i != LiveIn.size(); ++i) {
328 MachineBasicBlock *MBB = LiveIn[i]->getBlock();
329 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
330 PE = MBB->pred_end(); PI != PE; ++PI) {
331 MachineBasicBlock *Pred = *PI;
332 // Is this a known live-out block?
333 std::pair<LiveOutMap::iterator,bool> LOIP =
334 LiveOutCache.insert(std::make_pair(Pred, LiveOutPair()));
335 // Yes, we have been here before.
337 if (VNInfo *VNI = LOIP.first->second.first) {
338 if (IdxVNI && IdxVNI != VNI)
344 // Does Pred provide a live-out value?
345 SlotIndex Start, Last;
346 tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
347 Last = Last.getPrevSlot();
348 if (VNInfo *VNI = LI->extendInBlock(Start, Last)) {
349 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(VNI->def);
350 LiveOutPair &LOP = LOIP.first->second;
352 LOP.second = MDT[DefMBB];
353 if (IdxVNI && IdxVNI != VNI)
358 // No, we need a live-in value for Pred as well
360 LiveIn.push_back(MDT[Pred]);
362 UniqueVNI = false; // Loopback to IdxMBB, ask updateSSA() for help.
366 // We may need to add phi-def values to preserve the SSA form.
368 LiveOutPair LOP(IdxVNI, MDT[LIS.getMBBFromIndex(IdxVNI->def)]);
369 // Update LiveOutCache, but skip IdxMBB at LiveIn[0].
370 for (unsigned i = 1, e = LiveIn.size(); i != e; ++i)
371 LiveOutCache[LiveIn[i]->getBlock()] = LOP;
373 IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
376 // Check the LiveOutCache invariants.
377 for (LiveOutMap::iterator I = LiveOutCache.begin(), E = LiveOutCache.end();
379 assert(I->first && "Null MBB entry in cache");
380 assert(I->second.first && "Null VNInfo in cache");
381 assert(I->second.second && "Null DomTreeNode in cache");
382 if (I->second.second->getBlock() == I->first)
384 for (MachineBasicBlock::pred_iterator PI = I->first->pred_begin(),
385 PE = I->first->pred_end(); PI != PE; ++PI)
386 assert(LiveOutCache.lookup(*PI) == I->second && "Bad invariant");
390 // Since we went through the trouble of a full BFS visiting all reaching defs,
391 // the values in LiveIn are now accurate. No more phi-defs are needed
392 // for these blocks, so we can color the live ranges.
393 for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
394 MachineBasicBlock *MBB = LiveIn[i]->getBlock();
395 SlotIndex Start = LIS.getMBBStartIdx(MBB);
396 VNInfo *VNI = LiveOutCache.lookup(MBB).first;
398 // Anything in LiveIn other than IdxMBB is live-through.
399 // In IdxMBB, we should stop at Idx unless the same value is live-out.
400 if (MBB == IdxMBB && IdxVNI != VNI)
401 LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
403 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
407 VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
408 SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
410 const MachineBasicBlock *IdxMBB) {
411 // This is essentially the same iterative algorithm that SSAUpdater uses,
412 // except we already have a dominator tree, so we don't have to recompute it.
413 LiveInterval *LI = Edit->get(RegIdx);
418 DEBUG(dbgs() << " Iterating over " << LiveIn.size() << " blocks.\n");
419 // Propagate live-out values down the dominator tree, inserting phi-defs
420 // when necessary. Since LiveIn was created by a BFS, going backwards makes
421 // it more likely for us to visit immediate dominators before their
423 for (unsigned i = LiveIn.size(); i; --i) {
424 MachineDomTreeNode *Node = LiveIn[i-1];
425 MachineBasicBlock *MBB = Node->getBlock();
426 MachineDomTreeNode *IDom = Node->getIDom();
427 LiveOutPair IDomValue;
428 // We need a live-in value to a block with no immediate dominator?
429 // This is probably an unreachable block that has survived somehow.
430 bool needPHI = !IDom;
432 // Get the IDom live-out value.
434 LiveOutMap::iterator I = LiveOutCache.find(IDom->getBlock());
435 if (I != LiveOutCache.end())
436 IDomValue = I->second;
438 // If IDom is outside our set of live-out blocks, there must be new
439 // defs, and we need a phi-def here.
443 // IDom dominates all of our predecessors, but it may not be the immediate
444 // dominator. Check if any of them have live-out values that are properly
445 // dominated by IDom. If so, we need a phi-def here.
447 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
448 PE = MBB->pred_end(); PI != PE; ++PI) {
449 LiveOutPair Value = LiveOutCache[*PI];
450 if (!Value.first || Value.first == IDomValue.first)
452 // This predecessor is carrying something other than IDomValue.
453 // It could be because IDomValue hasn't propagated yet, or it could be
454 // because MBB is in the dominance frontier of that value.
455 if (MDT.dominates(IDom, Value.second)) {
462 // Create a phi-def if required.
465 SlotIndex Start = LIS.getMBBStartIdx(MBB);
466 VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
467 VNI->setIsPHIDef(true);
468 DEBUG(dbgs() << " - BB#" << MBB->getNumber()
469 << " phi-def #" << VNI->id << " at " << Start << '\n');
470 // We no longer need LI to be live-in.
471 LiveIn.erase(LiveIn.begin()+(i-1));
472 // Blocks in LiveIn are either IdxMBB, or have a value live-through.
475 // Check if we need to update live-out info.
476 LiveOutMap::iterator I = LiveOutCache.find(MBB);
477 if (I == LiveOutCache.end() || I->second.second == Node) {
478 // We already have a live-out defined in MBB, so this must be IdxMBB.
479 assert(MBB == IdxMBB && "Adding phi-def to known live-out");
480 LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
482 // This phi-def is also live-out, so color the whole block.
483 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
484 I->second = LiveOutPair(VNI, Node);
486 } else if (IDomValue.first) {
487 // No phi-def here. Remember incoming value for IdxMBB.
489 IdxVNI = IDomValue.first;
490 // Propagate IDomValue if needed:
491 // MBB is live-out and doesn't define its own value.
492 LiveOutMap::iterator I = LiveOutCache.find(MBB);
493 if (I != LiveOutCache.end() && I->second.second != Node &&
494 I->second.first != IDomValue.first) {
496 I->second = IDomValue;
497 DEBUG(dbgs() << " - BB#" << MBB->getNumber()
498 << " idom valno #" << IDomValue.first->id
499 << " from BB#" << IDom->getBlock()->getNumber() << '\n');
503 DEBUG(dbgs() << " - made " << Changes << " changes.\n");
506 assert(IdxVNI && "Didn't find value for Idx");
510 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
513 MachineBasicBlock &MBB,
514 MachineBasicBlock::iterator I) {
515 MachineInstr *CopyMI = 0;
517 LiveInterval *LI = Edit->get(RegIdx);
519 // Attempt cheap-as-a-copy rematerialization.
520 LiveRangeEdit::Remat RM(ParentVNI);
521 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
522 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
524 // Can't remat, just insert a copy from parent.
525 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
526 .addReg(Edit->getReg());
527 Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
530 // Define the value in Reg.
531 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
532 VNI->setCopy(CopyMI);
536 /// Create a new virtual register and live interval.
537 void SplitEditor::openIntv() {
538 assert(!OpenIdx && "Previous LI not closed before openIntv");
540 // Create the complement as index 0.
542 Edit->create(MRI, LIS, VRM);
544 // Create the open interval.
545 OpenIdx = Edit->size();
546 Edit->create(MRI, LIS, VRM);
549 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
550 assert(OpenIdx && "openIntv not called before enterIntvBefore");
551 DEBUG(dbgs() << " enterIntvBefore " << Idx);
552 Idx = Idx.getBaseIndex();
553 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
555 DEBUG(dbgs() << ": not live\n");
558 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
559 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
560 assert(MI && "enterIntvBefore called with invalid index");
562 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
566 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
567 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
568 SlotIndex End = LIS.getMBBEndIdx(&MBB);
569 SlotIndex Last = End.getPrevSlot();
570 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
571 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
573 DEBUG(dbgs() << ": not live\n");
576 DEBUG(dbgs() << ": valno " << ParentVNI->id);
577 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
578 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
579 RegAssign.insert(VNI->def, End, OpenIdx);
584 /// useIntv - indicate that all instructions in MBB should use OpenLI.
585 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
586 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
589 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
590 assert(OpenIdx && "openIntv not called before useIntv");
591 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
592 RegAssign.insert(Start, End, OpenIdx);
596 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
597 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
598 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
600 // The interval must be live beyond the instruction at Idx.
601 Idx = Idx.getBoundaryIndex();
602 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
604 DEBUG(dbgs() << ": not live\n");
605 return Idx.getNextSlot();
607 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
609 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
610 assert(MI && "No instruction at index");
611 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
612 llvm::next(MachineBasicBlock::iterator(MI)));
616 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
617 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
618 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
620 // The interval must be live into the instruction at Idx.
621 Idx = Idx.getBoundaryIndex();
622 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
624 DEBUG(dbgs() << ": not live\n");
625 return Idx.getNextSlot();
627 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
629 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
630 assert(MI && "No instruction at index");
631 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
635 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
636 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
637 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
638 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
640 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
642 DEBUG(dbgs() << ": not live\n");
646 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
647 MBB.SkipPHIsAndLabels(MBB.begin()));
648 RegAssign.insert(Start, VNI->def, OpenIdx);
653 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
654 assert(OpenIdx && "openIntv not called before overlapIntv");
655 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
656 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
657 "Parent changes value in extended range");
658 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
659 "Range cannot span basic blocks");
661 // The complement interval will be extended as needed by extendRange().
662 markComplexMapped(0, ParentVNI);
663 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
664 RegAssign.insert(Start, End, OpenIdx);
668 /// closeIntv - Indicate that we are done editing the currently open
669 /// LiveInterval, and ranges can be trimmed.
670 void SplitEditor::closeIntv() {
671 assert(OpenIdx && "openIntv not called before closeIntv");
675 /// transferSimpleValues - Transfer all simply defined values to the new live
677 /// Values that were rematerialized or that have multiple defs are left alone.
678 bool SplitEditor::transferSimpleValues() {
679 bool Skipped = false;
680 RegAssignMap::const_iterator AssignI = RegAssign.begin();
681 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
682 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
683 DEBUG(dbgs() << " blit " << *ParentI << ':');
684 VNInfo *ParentVNI = ParentI->valno;
685 // RegAssign has holes where RegIdx 0 should be used.
686 SlotIndex Start = ParentI->start;
687 AssignI.advanceTo(Start);
690 SlotIndex End = ParentI->end;
691 if (!AssignI.valid()) {
693 } else if (AssignI.start() <= Start) {
694 RegIdx = AssignI.value();
695 if (AssignI.stop() < End) {
696 End = AssignI.stop();
701 End = std::min(End, AssignI.start());
703 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
704 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
705 DEBUG(dbgs() << ':' << VNI->id);
706 Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
710 } while (Start != ParentI->end);
711 DEBUG(dbgs() << '\n');
716 void SplitEditor::extendPHIKillRanges() {
717 // Extend live ranges to be live-out for successor PHI values.
718 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
719 E = Edit->getParent().vni_end(); I != E; ++I) {
720 const VNInfo *PHIVNI = *I;
721 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
723 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
724 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
725 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
726 PE = MBB->pred_end(); PI != PE; ++PI) {
727 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
728 // The predecessor may not have a live-out value. That is OK, like an
729 // undef PHI operand.
730 if (Edit->getParent().liveAt(End)) {
731 assert(RegAssign.lookup(End) == RegIdx &&
732 "Different register assignment in phi predecessor");
733 extendRange(RegIdx, End);
739 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
740 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
741 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
742 RE = MRI.reg_end(); RI != RE;) {
743 MachineOperand &MO = RI.getOperand();
744 MachineInstr *MI = MO.getParent();
746 // LiveDebugVariables should have handled all DBG_VALUE instructions.
747 if (MI->isDebugValue()) {
748 DEBUG(dbgs() << "Zapping " << *MI);
753 // <undef> operands don't really read the register, so just assign them to
755 if (MO.isUse() && MO.isUndef()) {
756 MO.setReg(Edit->get(0)->reg);
760 SlotIndex Idx = LIS.getInstructionIndex(MI);
761 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
763 // Rewrite to the mapped register at Idx.
764 unsigned RegIdx = RegAssign.lookup(Idx);
765 MO.setReg(Edit->get(RegIdx)->reg);
766 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
767 << Idx << ':' << RegIdx << '\t' << *MI);
769 // Extend liveness to Idx.
771 extendRange(RegIdx, Idx);
775 /// rewriteSplit - Rewrite uses of Intvs[0] according to the ConEQ mapping.
776 void SplitEditor::rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
777 const ConnectedVNInfoEqClasses &ConEq) {
778 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Intvs[0]->reg),
779 RE = MRI.reg_end(); RI != RE;) {
780 MachineOperand &MO = RI.getOperand();
781 MachineInstr *MI = MO.getParent();
783 if (MO.isUse() && MO.isUndef())
785 // DBG_VALUE instructions should have been eliminated earlier.
786 SlotIndex Idx = LIS.getInstructionIndex(MI);
787 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
788 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
790 const VNInfo *VNI = Intvs[0]->getVNInfoAt(Idx);
791 assert(VNI && "Interval not live at use.");
792 MO.setReg(Intvs[ConEq.getEqClass(VNI)]->reg);
793 DEBUG(dbgs() << VNI->id << '\t' << *MI);
797 void SplitEditor::finish() {
798 assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
801 // At this point, the live intervals in Edit contain VNInfos corresponding to
802 // the inserted copies.
804 // Add the original defs from the parent interval.
805 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
806 E = Edit->getParent().vni_end(); I != E; ++I) {
807 const VNInfo *ParentVNI = *I;
808 if (ParentVNI->isUnused())
810 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
811 defValue(RegIdx, ParentVNI, ParentVNI->def);
812 // Mark rematted values as complex everywhere to force liveness computation.
813 // The new live ranges may be truncated.
814 if (Edit->didRematerialize(ParentVNI))
815 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
816 markComplexMapped(i, ParentVNI);
820 // Every new interval must have a def by now, otherwise the split is bogus.
821 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
822 assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
825 // Transfer the simply mapped values, check if any are complex.
826 bool Complex = transferSimpleValues();
828 extendPHIKillRanges();
832 // Rewrite virtual registers, possibly extending ranges.
833 rewriteAssigned(Complex);
835 // FIXME: Delete defs that were rematted everywhere.
837 // Get rid of unused values and set phi-kill flags.
838 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
839 (*I)->RenumberValues(LIS);
841 // Now check if any registers were separated into multiple components.
842 ConnectedVNInfoEqClasses ConEQ(LIS);
843 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
844 // Don't use iterators, they are invalidated by create() below.
845 LiveInterval *li = Edit->get(i);
846 unsigned NumComp = ConEQ.Classify(li);
849 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
850 SmallVector<LiveInterval*, 8> dups;
852 for (unsigned i = 1; i != NumComp; ++i)
853 dups.push_back(&Edit->create(MRI, LIS, VRM));
854 rewriteComponents(dups, ConEQ);
855 ConEQ.Distribute(&dups[0]);
858 // Calculate spill weight and allocation hints for new intervals.
859 VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
860 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
861 LiveInterval &li = **I;
862 vrai.CalculateRegClass(li.reg);
863 vrai.CalculateWeightAndHint(li);
864 DEBUG(dbgs() << " new interval " << MRI.getRegClass(li.reg)->getName()
865 << ":" << li << '\n');
870 //===----------------------------------------------------------------------===//
871 // Single Block Splitting
872 //===----------------------------------------------------------------------===//
874 /// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
875 /// may be an advantage to split CurLI for the duration of the block.
876 bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
877 // If CurLI is local to one block, there is no point to splitting it.
878 if (LiveBlocks.size() <= 1)
880 // Add blocks with multiple uses.
881 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
882 const BlockInfo &BI = LiveBlocks[i];
885 unsigned Instrs = UsingBlocks.lookup(BI.MBB);
888 if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
890 Blocks.insert(BI.MBB);
892 return !Blocks.empty();
895 /// splitSingleBlocks - Split CurLI into a separate live interval inside each
896 /// basic block in Blocks.
897 void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
898 DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
900 for (unsigned i = 0, e = SA.LiveBlocks.size(); i != e; ++i) {
901 const SplitAnalysis::BlockInfo &BI = SA.LiveBlocks[i];
902 if (!BI.Uses || !Blocks.count(BI.MBB))
906 SlotIndex SegStart = enterIntvBefore(BI.FirstUse);
907 if (!BI.LiveOut || BI.LastUse < BI.LastSplitPoint) {
908 useIntv(SegStart, leaveIntvAfter(BI.LastUse));
910 // The last use is after the last valid split point.
911 SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
912 useIntv(SegStart, SegStop);
913 overlapIntv(SegStop, BI.LastUse);