1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveRangeEdit.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineLoopInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/VirtRegMap.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 #define DEBUG_TYPE "regalloc"
33 STATISTIC(NumFinished, "Number of splits finished");
34 STATISTIC(NumSimple, "Number of splits that were simple");
35 STATISTIC(NumCopies, "Number of copies inserted for splitting");
36 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
37 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
44 const MachineLoopInfo &mli)
45 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
46 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
47 LastSplitPoint(MF.getNumBlockIDs()) {}
49 void SplitAnalysis::clear() {
52 ThroughBlocks.clear();
54 DidRepairRange = false;
57 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
58 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
59 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
60 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
61 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
63 // Compute split points on the first call. The pair is independent of the
64 // current live interval.
65 if (!LSP.first.isValid()) {
66 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
67 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getInstructionIndex(FirstTerm);
72 // If there is a landing pad successor, also find the call instruction.
75 // There may not be a call instruction (?) in which case we ignore LPad.
76 LSP.second = LSP.first;
77 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
81 LSP.second = LIS.getInstructionIndex(I);
87 // If CurLI is live into a landing pad successor, move the last split point
88 // back to the call that may throw.
89 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
92 // Find the value leaving MBB.
93 const VNInfo *VNI = CurLI->getVNInfoBefore(MBBEnd);
97 // If the value leaving MBB was defined after the call in MBB, it can't
98 // really be live-in to the landing pad. This can happen if the landing pad
99 // has a PHI, and this register is undef on the exceptional edge.
100 // <rdar://problem/10664933>
101 if (!SlotIndex::isEarlierInstr(VNI->def, LSP.second) && VNI->def < MBBEnd)
104 // Value is properly live-in to the landing pad.
105 // Only allow splits before the call.
109 MachineBasicBlock::iterator
110 SplitAnalysis::getLastSplitPointIter(MachineBasicBlock *MBB) {
111 SlotIndex LSP = getLastSplitPoint(MBB->getNumber());
112 if (LSP == LIS.getMBBEndIdx(MBB))
114 return LIS.getInstructionFromIndex(LSP);
117 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
118 void SplitAnalysis::analyzeUses() {
119 assert(UseSlots.empty() && "Call clear first");
121 // First get all the defs from the interval values. This provides the correct
122 // slots for early clobbers.
123 for (const VNInfo *VNI : CurLI->valnos)
124 if (!VNI->isPHIDef() && !VNI->isUnused())
125 UseSlots.push_back(VNI->def);
127 // Get use slots form the use-def chain.
128 const MachineRegisterInfo &MRI = MF.getRegInfo();
129 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
131 UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot());
133 array_pod_sort(UseSlots.begin(), UseSlots.end());
135 // Remove duplicates, keeping the smaller slot for each instruction.
136 // That is what we want for early clobbers.
137 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
138 SlotIndex::isSameInstr),
141 // Compute per-live block info.
142 if (!calcLiveBlockInfo()) {
143 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
144 // I am looking at you, RegisterCoalescer!
145 DidRepairRange = true;
147 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
148 const_cast<LiveIntervals&>(LIS)
149 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
151 ThroughBlocks.clear();
152 bool fixed = calcLiveBlockInfo();
154 assert(fixed && "Couldn't fix broken live interval");
157 DEBUG(dbgs() << "Analyze counted "
158 << UseSlots.size() << " instrs in "
159 << UseBlocks.size() << " blocks, through "
160 << NumThroughBlocks << " blocks.\n");
163 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
164 /// where CurLI is live.
165 bool SplitAnalysis::calcLiveBlockInfo() {
166 ThroughBlocks.resize(MF.getNumBlockIDs());
167 NumThroughBlocks = NumGapBlocks = 0;
171 LiveInterval::const_iterator LVI = CurLI->begin();
172 LiveInterval::const_iterator LVE = CurLI->end();
174 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
175 UseI = UseSlots.begin();
176 UseE = UseSlots.end();
178 // Loop over basic blocks where CurLI is live.
179 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
183 SlotIndex Start, Stop;
184 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
186 // If the block contains no uses, the range must be live through. At one
187 // point, RegisterCoalescer could create dangling ranges that ended
189 if (UseI == UseE || *UseI >= Stop) {
191 ThroughBlocks.set(BI.MBB->getNumber());
192 // The range shouldn't end mid-block if there are no uses. This shouldn't
197 // This block has uses. Find the first and last uses in the block.
198 BI.FirstInstr = *UseI;
199 assert(BI.FirstInstr >= Start);
201 while (UseI != UseE && *UseI < Stop);
202 BI.LastInstr = UseI[-1];
203 assert(BI.LastInstr < Stop);
205 // LVI is the first live segment overlapping MBB.
206 BI.LiveIn = LVI->start <= Start;
208 // When not live in, the first use should be a def.
210 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
211 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
212 BI.FirstDef = BI.FirstInstr;
215 // Look for gaps in the live range.
217 while (LVI->end < Stop) {
218 SlotIndex LastStop = LVI->end;
219 if (++LVI == LVE || LVI->start >= Stop) {
221 BI.LastInstr = LastStop;
225 if (LastStop < LVI->start) {
226 // There is a gap in the live range. Create duplicate entries for the
227 // live-in snippet and the live-out snippet.
230 // Push the Live-in part.
232 UseBlocks.push_back(BI);
233 UseBlocks.back().LastInstr = LastStop;
235 // Set up BI for the live-out part.
238 BI.FirstInstr = BI.FirstDef = LVI->start;
241 // A Segment that starts in the middle of the block must be a def.
242 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
244 BI.FirstDef = LVI->start;
247 UseBlocks.push_back(BI);
249 // LVI is now at LVE or LVI->end >= Stop.
254 // Live segment ends exactly at Stop. Move to the next segment.
255 if (LVI->end == Stop && ++LVI == LVE)
258 // Pick the next basic block.
259 if (LVI->start < Stop)
262 MFI = LIS.getMBBFromIndex(LVI->start);
265 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
269 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
272 LiveInterval *li = const_cast<LiveInterval*>(cli);
273 LiveInterval::iterator LVI = li->begin();
274 LiveInterval::iterator LVE = li->end();
277 // Loop over basic blocks where li is live.
278 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
279 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
282 LVI = li->advanceTo(LVI, Stop);
287 Stop = LIS.getMBBEndIdx(MFI);
288 } while (Stop <= LVI->start);
292 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
293 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
294 const LiveInterval &Orig = LIS.getInterval(OrigReg);
295 assert(!Orig.empty() && "Splitting empty interval?");
296 LiveInterval::const_iterator I = Orig.find(Idx);
298 // Range containing Idx should begin at Idx.
299 if (I != Orig.end() && I->start <= Idx)
300 return I->start == Idx;
302 // Range does not contain Idx, previous must end at Idx.
303 return I != Orig.begin() && (--I)->end == Idx;
306 void SplitAnalysis::analyze(const LiveInterval *li) {
313 //===----------------------------------------------------------------------===//
315 //===----------------------------------------------------------------------===//
317 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
318 SplitEditor::SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm,
319 MachineDominatorTree &mdt,
320 MachineBlockFrequencyInfo &mbfi)
321 : SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()),
322 MDT(mdt), TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
323 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
324 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
325 RegAssign(Allocator) {}
327 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
334 // Reset the LiveRangeCalc instances needed for this spill mode.
335 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
336 &LIS.getVNInfoAllocator());
338 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
339 &LIS.getVNInfoAllocator());
341 // We don't need an AliasAnalysis since we will only be performing
342 // cheap-as-a-copy remats anyway.
343 Edit->anyRematerializable(nullptr);
346 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
347 void SplitEditor::dump() const {
348 if (RegAssign.empty()) {
349 dbgs() << " empty\n";
353 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
354 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
359 VNInfo *SplitEditor::defValue(unsigned RegIdx,
360 const VNInfo *ParentVNI,
362 assert(ParentVNI && "Mapping NULL value");
363 assert(Idx.isValid() && "Invalid SlotIndex");
364 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
365 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
367 // Create a new value.
368 VNInfo *VNI = LI->getNextValue(Idx, LIS.getVNInfoAllocator());
370 // Use insert for lookup, so we can add missing values with a second lookup.
371 std::pair<ValueMap::iterator, bool> InsP =
372 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
373 ValueForcePair(VNI, false)));
375 // This was the first time (RegIdx, ParentVNI) was mapped.
376 // Keep it as a simple def without any liveness.
380 // If the previous value was a simple mapping, add liveness for it now.
381 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
382 SlotIndex Def = OldVNI->def;
383 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), OldVNI));
384 // No longer a simple mapping. Switch to a complex, non-forced mapping.
385 InsP.first->second = ValueForcePair();
388 // This is a complex mapping, add liveness for VNI
389 SlotIndex Def = VNI->def;
390 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI));
395 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
396 assert(ParentVNI && "Mapping NULL value");
397 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
398 VNInfo *VNI = VFP.getPointer();
400 // ParentVNI was either unmapped or already complex mapped. Either way, just
401 // set the force bit.
407 // This was previously a single mapping. Make sure the old def is represented
408 // by a trivial live range.
409 SlotIndex Def = VNI->def;
410 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
411 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI));
412 // Mark as complex mapped, forced.
413 VFP = ValueForcePair(nullptr, true);
416 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
419 MachineBasicBlock &MBB,
420 MachineBasicBlock::iterator I) {
421 MachineInstr *CopyMI = nullptr;
423 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
425 // We may be trying to avoid interference that ends at a deleted instruction,
426 // so always begin RegIdx 0 early and all others late.
427 bool Late = RegIdx != 0;
429 // Attempt cheap-as-a-copy rematerialization.
430 LiveRangeEdit::Remat RM(ParentVNI);
431 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
432 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late);
435 // Can't remat, just insert a copy from parent.
436 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
437 .addReg(Edit->getReg());
438 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
443 // Define the value in Reg.
444 return defValue(RegIdx, ParentVNI, Def);
447 /// Create a new virtual register and live interval.
448 unsigned SplitEditor::openIntv() {
449 // Create the complement as index 0.
451 Edit->createEmptyInterval();
453 // Create the open interval.
454 OpenIdx = Edit->size();
455 Edit->createEmptyInterval();
459 void SplitEditor::selectIntv(unsigned Idx) {
460 assert(Idx != 0 && "Cannot select the complement interval");
461 assert(Idx < Edit->size() && "Can only select previously opened interval");
462 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
466 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
467 assert(OpenIdx && "openIntv not called before enterIntvBefore");
468 DEBUG(dbgs() << " enterIntvBefore " << Idx);
469 Idx = Idx.getBaseIndex();
470 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
472 DEBUG(dbgs() << ": not live\n");
475 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
476 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
477 assert(MI && "enterIntvBefore called with invalid index");
479 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
483 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
484 assert(OpenIdx && "openIntv not called before enterIntvAfter");
485 DEBUG(dbgs() << " enterIntvAfter " << Idx);
486 Idx = Idx.getBoundaryIndex();
487 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
489 DEBUG(dbgs() << ": not live\n");
492 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
493 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
494 assert(MI && "enterIntvAfter called with invalid index");
496 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
497 std::next(MachineBasicBlock::iterator(MI)));
501 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
502 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
503 SlotIndex End = LIS.getMBBEndIdx(&MBB);
504 SlotIndex Last = End.getPrevSlot();
505 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
506 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
508 DEBUG(dbgs() << ": not live\n");
511 DEBUG(dbgs() << ": valno " << ParentVNI->id);
512 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
513 SA.getLastSplitPointIter(&MBB));
514 RegAssign.insert(VNI->def, End, OpenIdx);
519 /// useIntv - indicate that all instructions in MBB should use OpenLI.
520 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
521 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
524 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
525 assert(OpenIdx && "openIntv not called before useIntv");
526 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
527 RegAssign.insert(Start, End, OpenIdx);
531 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
532 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
533 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
535 // The interval must be live beyond the instruction at Idx.
536 SlotIndex Boundary = Idx.getBoundaryIndex();
537 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary);
539 DEBUG(dbgs() << ": not live\n");
540 return Boundary.getNextSlot();
542 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
543 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
544 assert(MI && "No instruction at index");
546 // In spill mode, make live ranges as short as possible by inserting the copy
547 // before MI. This is only possible if that instruction doesn't redefine the
548 // value. The inserted COPY is not a kill, and we don't need to recompute
549 // the source live range. The spiller also won't try to hoist this copy.
550 if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
551 MI->readsVirtualRegister(Edit->getReg())) {
552 forceRecompute(0, ParentVNI);
553 defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
557 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
558 std::next(MachineBasicBlock::iterator(MI)));
562 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
563 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
564 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
566 // The interval must be live into the instruction at Idx.
567 Idx = Idx.getBaseIndex();
568 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
570 DEBUG(dbgs() << ": not live\n");
571 return Idx.getNextSlot();
573 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
575 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
576 assert(MI && "No instruction at index");
577 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
581 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
582 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
583 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
584 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
586 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
588 DEBUG(dbgs() << ": not live\n");
592 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
593 MBB.SkipPHIsAndLabels(MBB.begin()));
594 RegAssign.insert(Start, VNI->def, OpenIdx);
599 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
600 assert(OpenIdx && "openIntv not called before overlapIntv");
601 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
602 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
603 "Parent changes value in extended range");
604 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
605 "Range cannot span basic blocks");
607 // The complement interval will be extended as needed by LRCalc.extend().
609 forceRecompute(0, ParentVNI);
610 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
611 RegAssign.insert(Start, End, OpenIdx);
615 //===----------------------------------------------------------------------===//
617 //===----------------------------------------------------------------------===//
619 void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
620 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
621 DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
622 RegAssignMap::iterator AssignI;
623 AssignI.setMap(RegAssign);
625 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
626 VNInfo *VNI = Copies[i];
627 SlotIndex Def = VNI->def;
628 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
629 assert(MI && "No instruction for back-copy");
631 MachineBasicBlock *MBB = MI->getParent();
632 MachineBasicBlock::iterator MBBI(MI);
634 do AtBegin = MBBI == MBB->begin();
635 while (!AtBegin && (--MBBI)->isDebugValue());
637 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
638 LI->removeValNo(VNI);
639 LIS.RemoveMachineInstrFromMaps(MI);
640 MI->eraseFromParent();
642 // Adjust RegAssign if a register assignment is killed at VNI->def. We
643 // want to avoid calculating the live range of the source register if
645 AssignI.find(Def.getPrevSlot());
646 if (!AssignI.valid() || AssignI.start() >= Def)
648 // If MI doesn't kill the assigned register, just leave it.
649 if (AssignI.stop() != Def)
651 unsigned RegIdx = AssignI.value();
652 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
653 DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
654 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
656 SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
657 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
658 AssignI.setStop(Kill);
664 SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
665 MachineBasicBlock *DefMBB) {
668 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
670 const MachineLoopInfo &Loops = SA.Loops;
671 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
672 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
674 // Best candidate so far.
675 MachineBasicBlock *BestMBB = MBB;
676 unsigned BestDepth = UINT_MAX;
679 const MachineLoop *Loop = Loops.getLoopFor(MBB);
681 // MBB isn't in a loop, it doesn't get any better. All dominators have a
682 // higher frequency by definition.
684 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
685 << MBB->getNumber() << " at depth 0\n");
689 // We'll never be able to exit the DefLoop.
690 if (Loop == DefLoop) {
691 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
692 << MBB->getNumber() << " in the same loop\n");
696 // Least busy dominator seen so far.
697 unsigned Depth = Loop->getLoopDepth();
698 if (Depth < BestDepth) {
701 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
702 << MBB->getNumber() << " at depth " << Depth << '\n');
705 // Leave loop by going to the immediate dominator of the loop header.
706 // This is a bigger stride than simply walking up the dominator tree.
707 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
709 // Too far up the dominator tree?
710 if (!IDom || !MDT.dominates(DefDomNode, IDom))
713 MBB = IDom->getBlock();
717 void SplitEditor::hoistCopiesForSize() {
718 // Get the complement interval, always RegIdx 0.
719 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
720 LiveInterval *Parent = &Edit->getParent();
722 // Track the nearest common dominator for all back-copies for each ParentVNI,
723 // indexed by ParentVNI->id.
724 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
725 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
727 // Find the nearest common dominator for parent values with multiple
728 // back-copies. If a single back-copy dominates, put it in DomPair.second.
729 for (VNInfo *VNI : LI->valnos) {
732 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
733 assert(ParentVNI && "Parent not live at complement def");
735 // Don't hoist remats. The complement is probably going to disappear
736 // completely anyway.
737 if (Edit->didRematerialize(ParentVNI))
740 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
741 DomPair &Dom = NearestDom[ParentVNI->id];
743 // Keep directly defined parent values. This is either a PHI or an
744 // instruction in the complement range. All other copies of ParentVNI
745 // should be eliminated.
746 if (VNI->def == ParentVNI->def) {
747 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
748 Dom = DomPair(ValMBB, VNI->def);
751 // Skip the singly mapped values. There is nothing to gain from hoisting a
753 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
754 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
759 // First time we see ParentVNI. VNI dominates itself.
760 Dom = DomPair(ValMBB, VNI->def);
761 } else if (Dom.first == ValMBB) {
762 // Two defs in the same block. Pick the earlier def.
763 if (!Dom.second.isValid() || VNI->def < Dom.second)
764 Dom.second = VNI->def;
766 // Different basic blocks. Check if one dominates.
767 MachineBasicBlock *Near =
768 MDT.findNearestCommonDominator(Dom.first, ValMBB);
770 // Def ValMBB dominates.
771 Dom = DomPair(ValMBB, VNI->def);
772 else if (Near != Dom.first)
773 // None dominate. Hoist to common dominator, need new def.
774 Dom = DomPair(Near, SlotIndex());
777 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
778 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
779 << " hoist to BB#" << Dom.first->getNumber() << ' '
780 << Dom.second << '\n');
783 // Insert the hoisted copies.
784 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
785 DomPair &Dom = NearestDom[i];
786 if (!Dom.first || Dom.second.isValid())
788 // This value needs a hoisted copy inserted at the end of Dom.first.
789 VNInfo *ParentVNI = Parent->getValNumInfo(i);
790 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
791 // Get a less loopy dominator than Dom.first.
792 Dom.first = findShallowDominator(Dom.first, DefMBB);
793 SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
795 defFromParent(0, ParentVNI, Last, *Dom.first,
796 SA.getLastSplitPointIter(Dom.first))->def;
799 // Remove redundant back-copies that are now known to be dominated by another
800 // def with the same value.
801 SmallVector<VNInfo*, 8> BackCopies;
802 for (VNInfo *VNI : LI->valnos) {
805 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
806 const DomPair &Dom = NearestDom[ParentVNI->id];
807 if (!Dom.first || Dom.second == VNI->def)
809 BackCopies.push_back(VNI);
810 forceRecompute(0, ParentVNI);
812 removeBackCopies(BackCopies);
816 /// transferValues - Transfer all possible values to the new live ranges.
817 /// Values that were rematerialized are left alone, they need LRCalc.extend().
818 bool SplitEditor::transferValues() {
819 bool Skipped = false;
820 RegAssignMap::const_iterator AssignI = RegAssign.begin();
821 for (const LiveRange::Segment &S : Edit->getParent()) {
822 DEBUG(dbgs() << " blit " << S << ':');
823 VNInfo *ParentVNI = S.valno;
824 // RegAssign has holes where RegIdx 0 should be used.
825 SlotIndex Start = S.start;
826 AssignI.advanceTo(Start);
829 SlotIndex End = S.end;
830 if (!AssignI.valid()) {
832 } else if (AssignI.start() <= Start) {
833 RegIdx = AssignI.value();
834 if (AssignI.stop() < End) {
835 End = AssignI.stop();
840 End = std::min(End, AssignI.start());
843 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
844 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
845 LiveRange &LR = LIS.getInterval(Edit->get(RegIdx));
847 // Check for a simply defined value that can be blitted directly.
848 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
849 if (VNInfo *VNI = VFP.getPointer()) {
850 DEBUG(dbgs() << ':' << VNI->id);
851 LR.addSegment(LiveInterval::Segment(Start, End, VNI));
856 // Skip values with forced recomputation.
858 DEBUG(dbgs() << "(recalc)");
864 LiveRangeCalc &LRC = getLRCalc(RegIdx);
866 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
867 // so the live range is accurate. Add live-in blocks in [Start;End) to the
869 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
870 SlotIndex BlockStart, BlockEnd;
871 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
873 // The first block may be live-in, or it may have its own def.
874 if (Start != BlockStart) {
875 VNInfo *VNI = LR.extendInBlock(BlockStart, std::min(BlockEnd, End));
876 assert(VNI && "Missing def for complex mapped value");
877 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
878 // MBB has its own def. Is it also live-out?
880 LRC.setLiveOutValue(MBB, VNI);
882 // Skip to the next block for live-in.
884 BlockStart = BlockEnd;
887 // Handle the live-in blocks covered by [Start;End).
888 assert(Start <= BlockStart && "Expected live-in block");
889 while (BlockStart < End) {
890 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
891 BlockEnd = LIS.getMBBEndIdx(MBB);
892 if (BlockStart == ParentVNI->def) {
893 // This block has the def of a parent PHI, so it isn't live-in.
894 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
895 VNInfo *VNI = LR.extendInBlock(BlockStart, std::min(BlockEnd, End));
896 assert(VNI && "Missing def for complex mapped parent PHI");
898 LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
900 // This block needs a live-in value. The last block covered may not
903 LRC.addLiveInBlock(LR, MDT[MBB], End);
905 // Live-through, and we don't know the value.
906 LRC.addLiveInBlock(LR, MDT[MBB]);
907 LRC.setLiveOutValue(MBB, nullptr);
910 BlockStart = BlockEnd;
914 } while (Start != S.end);
915 DEBUG(dbgs() << '\n');
918 LRCalc[0].calculateValues();
920 LRCalc[1].calculateValues();
925 void SplitEditor::extendPHIKillRanges() {
926 // Extend live ranges to be live-out for successor PHI values.
927 for (const VNInfo *PHIVNI : Edit->getParent().valnos) {
928 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
930 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
931 LiveRange &LR = LIS.getInterval(Edit->get(RegIdx));
932 LiveRangeCalc &LRC = getLRCalc(RegIdx);
933 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
934 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
935 PE = MBB->pred_end(); PI != PE; ++PI) {
936 SlotIndex End = LIS.getMBBEndIdx(*PI);
937 SlotIndex LastUse = End.getPrevSlot();
938 // The predecessor may not have a live-out value. That is OK, like an
939 // undef PHI operand.
940 if (Edit->getParent().liveAt(LastUse)) {
941 assert(RegAssign.lookup(LastUse) == RegIdx &&
942 "Different register assignment in phi predecessor");
949 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
950 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
951 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
952 RE = MRI.reg_end(); RI != RE;) {
953 MachineOperand &MO = *RI;
954 MachineInstr *MI = MO.getParent();
956 // LiveDebugVariables should have handled all DBG_VALUE instructions.
957 if (MI->isDebugValue()) {
958 DEBUG(dbgs() << "Zapping " << *MI);
963 // <undef> operands don't really read the register, so it doesn't matter
964 // which register we choose. When the use operand is tied to a def, we must
965 // use the same register as the def, so just do that always.
966 SlotIndex Idx = LIS.getInstructionIndex(MI);
967 if (MO.isDef() || MO.isUndef())
968 Idx = Idx.getRegSlot(MO.isEarlyClobber());
970 // Rewrite to the mapped register at Idx.
971 unsigned RegIdx = RegAssign.lookup(Idx);
972 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
974 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
975 << Idx << ':' << RegIdx << '\t' << *MI);
977 // Extend liveness to Idx if the instruction reads reg.
978 if (!ExtendRanges || MO.isUndef())
981 // Skip instructions that don't read Reg.
983 if (!MO.getSubReg() && !MO.isEarlyClobber())
985 // We may wan't to extend a live range for a partial redef, or for a use
986 // tied to an early clobber.
987 Idx = Idx.getPrevSlot();
988 if (!Edit->getParent().liveAt(Idx))
991 Idx = Idx.getRegSlot(true);
993 getLRCalc(RegIdx).extend(*LI, Idx.getNextSlot());
997 void SplitEditor::deleteRematVictims() {
998 SmallVector<MachineInstr*, 8> Dead;
999 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
1000 LiveInterval *LI = &LIS.getInterval(*I);
1001 for (const LiveRange::Segment &S : LI->segments) {
1002 // Dead defs end at the dead slot.
1003 if (S.end != S.valno->def.getDeadSlot())
1005 MachineInstr *MI = LIS.getInstructionFromIndex(S.valno->def);
1006 assert(MI && "Missing instruction for dead def");
1007 MI->addRegisterDead(LI->reg, &TRI);
1009 if (!MI->allDefsAreDead())
1012 DEBUG(dbgs() << "All defs dead: " << *MI);
1020 Edit->eliminateDeadDefs(Dead);
1023 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1026 // At this point, the live intervals in Edit contain VNInfos corresponding to
1027 // the inserted copies.
1029 // Add the original defs from the parent interval.
1030 for (const VNInfo *ParentVNI : Edit->getParent().valnos) {
1031 if (ParentVNI->isUnused())
1033 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1034 defValue(RegIdx, ParentVNI, ParentVNI->def);
1036 // Force rematted values to be recomputed everywhere.
1037 // The new live ranges may be truncated.
1038 if (Edit->didRematerialize(ParentVNI))
1039 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1040 forceRecompute(i, ParentVNI);
1043 // Hoist back-copies to the complement interval when in spill mode.
1044 switch (SpillMode) {
1046 // Leave all back-copies as is.
1049 hoistCopiesForSize();
1052 llvm_unreachable("Spill mode 'speed' not implemented yet");
1055 // Transfer the simply mapped values, check if any are skipped.
1056 bool Skipped = transferValues();
1058 extendPHIKillRanges();
1062 // Rewrite virtual registers, possibly extending ranges.
1063 rewriteAssigned(Skipped);
1065 // Delete defs that were rematted everywhere.
1067 deleteRematVictims();
1069 // Get rid of unused values and set phi-kill flags.
1070 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) {
1071 LiveInterval &LI = LIS.getInterval(*I);
1072 LI.RenumberValues();
1075 // Provide a reverse mapping from original indices to Edit ranges.
1078 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1079 LRMap->push_back(i);
1082 // Now check if any registers were separated into multiple components.
1083 ConnectedVNInfoEqClasses ConEQ(LIS);
1084 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1085 // Don't use iterators, they are invalidated by create() below.
1086 LiveInterval *li = &LIS.getInterval(Edit->get(i));
1087 unsigned NumComp = ConEQ.Classify(li);
1090 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
1091 SmallVector<LiveInterval*, 8> dups;
1093 for (unsigned j = 1; j != NumComp; ++j)
1094 dups.push_back(&Edit->createEmptyInterval());
1095 ConEQ.Distribute(&dups[0], MRI);
1096 // The new intervals all map back to i.
1098 LRMap->resize(Edit->size(), i);
1101 // Calculate spill weight and allocation hints for new intervals.
1102 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops, MBFI);
1104 assert(!LRMap || LRMap->size() == Edit->size());
1108 //===----------------------------------------------------------------------===//
1109 // Single Block Splitting
1110 //===----------------------------------------------------------------------===//
1112 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1113 bool SingleInstrs) const {
1114 // Always split for multiple instructions.
1115 if (!BI.isOneInstr())
1117 // Don't split for single instructions unless explicitly requested.
1120 // Splitting a live-through range always makes progress.
1121 if (BI.LiveIn && BI.LiveOut)
1123 // No point in isolating a copy. It has no register class constraints.
1124 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1126 // Finally, don't isolate an end point that was created by earlier splits.
1127 return isOriginalEndpoint(BI.FirstInstr);
1130 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1132 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1133 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1135 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1136 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1138 // The last use is after the last valid split point.
1139 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1140 useIntv(SegStart, SegStop);
1141 overlapIntv(SegStop, BI.LastInstr);
1146 //===----------------------------------------------------------------------===//
1147 // Global Live Range Splitting Support
1148 //===----------------------------------------------------------------------===//
1150 // These methods support a method of global live range splitting that uses a
1151 // global algorithm to decide intervals for CFG edges. They will insert split
1152 // points and color intervals in basic blocks while avoiding interference.
1154 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1155 // are on the stack.
1157 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1158 unsigned IntvIn, SlotIndex LeaveBefore,
1159 unsigned IntvOut, SlotIndex EnterAfter){
1160 SlotIndex Start, Stop;
1161 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1163 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1164 << ") intf " << LeaveBefore << '-' << EnterAfter
1165 << ", live-through " << IntvIn << " -> " << IntvOut);
1167 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1169 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1170 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1171 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1173 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1176 DEBUG(dbgs() << ", spill on entry.\n");
1178 // <<<<<<<<< Possible LeaveBefore interference.
1179 // |-----------| Live through.
1180 // -____________ Spill on entry.
1183 SlotIndex Idx = leaveIntvAtTop(*MBB);
1184 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1190 DEBUG(dbgs() << ", reload on exit.\n");
1192 // >>>>>>> Possible EnterAfter interference.
1193 // |-----------| Live through.
1194 // ___________-- Reload on exit.
1196 selectIntv(IntvOut);
1197 SlotIndex Idx = enterIntvAtEnd(*MBB);
1198 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1203 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1204 DEBUG(dbgs() << ", straight through.\n");
1206 // |-----------| Live through.
1207 // ------------- Straight through, same intv, no interference.
1209 selectIntv(IntvOut);
1210 useIntv(Start, Stop);
1214 // We cannot legally insert splits after LSP.
1215 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1216 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1218 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1219 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1220 DEBUG(dbgs() << ", switch avoiding interference.\n");
1222 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1223 // |-----------| Live through.
1224 // ------======= Switch intervals between interference.
1226 selectIntv(IntvOut);
1228 if (LeaveBefore && LeaveBefore < LSP) {
1229 Idx = enterIntvBefore(LeaveBefore);
1232 Idx = enterIntvAtEnd(*MBB);
1235 useIntv(Start, Idx);
1236 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1237 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1241 DEBUG(dbgs() << ", create local intv for interference.\n");
1243 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1244 // |-----------| Live through.
1245 // ==---------== Switch intervals before/after interference.
1247 assert(LeaveBefore <= EnterAfter && "Missed case");
1249 selectIntv(IntvOut);
1250 SlotIndex Idx = enterIntvAfter(EnterAfter);
1252 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1255 Idx = leaveIntvBefore(LeaveBefore);
1256 useIntv(Start, Idx);
1257 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1261 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1262 unsigned IntvIn, SlotIndex LeaveBefore) {
1263 SlotIndex Start, Stop;
1264 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1266 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1267 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1268 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1269 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1271 assert(IntvIn && "Must have register in");
1272 assert(BI.LiveIn && "Must be live-in");
1273 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1275 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1276 DEBUG(dbgs() << " before interference.\n");
1278 // <<< Interference after kill.
1279 // |---o---x | Killed in block.
1280 // ========= Use IntvIn everywhere.
1283 useIntv(Start, BI.LastInstr);
1287 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1289 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1291 // <<< Possible interference after last use.
1292 // |---o---o---| Live-out on stack.
1293 // =========____ Leave IntvIn after last use.
1295 // < Interference after last use.
1296 // |---o---o--o| Live-out on stack, late last use.
1297 // ============ Copy to stack after LSP, overlap IntvIn.
1298 // \_____ Stack interval is live-out.
1300 if (BI.LastInstr < LSP) {
1301 DEBUG(dbgs() << ", spill after last use before interference.\n");
1303 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1304 useIntv(Start, Idx);
1305 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1307 DEBUG(dbgs() << ", spill before last split point.\n");
1309 SlotIndex Idx = leaveIntvBefore(LSP);
1310 overlapIntv(Idx, BI.LastInstr);
1311 useIntv(Start, Idx);
1312 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1317 // The interference is overlapping somewhere we wanted to use IntvIn. That
1318 // means we need to create a local interval that can be allocated a
1319 // different register.
1320 unsigned LocalIntv = openIntv();
1322 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1324 if (!BI.LiveOut || BI.LastInstr < LSP) {
1326 // <<<<<<< Interference overlapping uses.
1327 // |---o---o---| Live-out on stack.
1328 // =====----____ Leave IntvIn before interference, then spill.
1330 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1331 SlotIndex From = enterIntvBefore(LeaveBefore);
1334 useIntv(Start, From);
1335 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1339 // <<<<<<< Interference overlapping uses.
1340 // |---o---o--o| Live-out on stack, late last use.
1341 // =====------- Copy to stack before LSP, overlap LocalIntv.
1342 // \_____ Stack interval is live-out.
1344 SlotIndex To = leaveIntvBefore(LSP);
1345 overlapIntv(To, BI.LastInstr);
1346 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1349 useIntv(Start, From);
1350 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1353 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1354 unsigned IntvOut, SlotIndex EnterAfter) {
1355 SlotIndex Start, Stop;
1356 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1358 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1359 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1360 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1361 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1363 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1365 assert(IntvOut && "Must have register out");
1366 assert(BI.LiveOut && "Must be live-out");
1367 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1369 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1370 DEBUG(dbgs() << " after interference.\n");
1372 // >>>> Interference before def.
1373 // | o---o---| Defined in block.
1374 // ========= Use IntvOut everywhere.
1376 selectIntv(IntvOut);
1377 useIntv(BI.FirstInstr, Stop);
1381 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1382 DEBUG(dbgs() << ", reload after interference.\n");
1384 // >>>> Interference before def.
1385 // |---o---o---| Live-through, stack-in.
1386 // ____========= Enter IntvOut before first use.
1388 selectIntv(IntvOut);
1389 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1391 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1395 // The interference is overlapping somewhere we wanted to use IntvOut. That
1396 // means we need to create a local interval that can be allocated a
1397 // different register.
1398 DEBUG(dbgs() << ", interference overlaps uses.\n");
1400 // >>>>>>> Interference overlapping uses.
1401 // |---o---o---| Live-through, stack-in.
1402 // ____---====== Create local interval for interference range.
1404 selectIntv(IntvOut);
1405 SlotIndex Idx = enterIntvAfter(EnterAfter);
1407 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1410 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));