1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveRangeEdit.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineLoopInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/VirtRegMap.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 #define DEBUG_TYPE "regalloc"
33 STATISTIC(NumFinished, "Number of splits finished");
34 STATISTIC(NumSimple, "Number of splits that were simple");
35 STATISTIC(NumCopies, "Number of copies inserted for splitting");
36 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
37 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
44 const MachineLoopInfo &mli)
45 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
46 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
47 LastSplitPoint(MF.getNumBlockIDs()) {}
49 void SplitAnalysis::clear() {
52 ThroughBlocks.clear();
54 DidRepairRange = false;
57 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
58 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
59 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
60 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
61 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
63 // Compute split points on the first call. The pair is independent of the
64 // current live interval.
65 if (!LSP.first.isValid()) {
66 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
67 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getInstructionIndex(FirstTerm);
72 // If there is a landing pad successor, also find the call instruction.
75 // There may not be a call instruction (?) in which case we ignore LPad.
76 LSP.second = LSP.first;
77 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
81 LSP.second = LIS.getInstructionIndex(I);
87 // If CurLI is live into a landing pad successor, move the last split point
88 // back to the call that may throw.
89 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
92 // Find the value leaving MBB.
93 const VNInfo *VNI = CurLI->getVNInfoBefore(MBBEnd);
97 // If the value leaving MBB was defined after the call in MBB, it can't
98 // really be live-in to the landing pad. This can happen if the landing pad
99 // has a PHI, and this register is undef on the exceptional edge.
100 // <rdar://problem/10664933>
101 if (!SlotIndex::isEarlierInstr(VNI->def, LSP.second) && VNI->def < MBBEnd)
104 // Value is properly live-in to the landing pad.
105 // Only allow splits before the call.
109 MachineBasicBlock::iterator
110 SplitAnalysis::getLastSplitPointIter(MachineBasicBlock *MBB) {
111 SlotIndex LSP = getLastSplitPoint(MBB->getNumber());
112 if (LSP == LIS.getMBBEndIdx(MBB))
114 return LIS.getInstructionFromIndex(LSP);
117 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
118 void SplitAnalysis::analyzeUses() {
119 assert(UseSlots.empty() && "Call clear first");
121 // First get all the defs from the interval values. This provides the correct
122 // slots for early clobbers.
123 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
124 E = CurLI->vni_end(); I != E; ++I)
125 if (!(*I)->isPHIDef() && !(*I)->isUnused())
126 UseSlots.push_back((*I)->def);
128 // Get use slots form the use-def chain.
129 const MachineRegisterInfo &MRI = MF.getRegInfo();
130 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
132 UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot());
134 array_pod_sort(UseSlots.begin(), UseSlots.end());
136 // Remove duplicates, keeping the smaller slot for each instruction.
137 // That is what we want for early clobbers.
138 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
139 SlotIndex::isSameInstr),
142 // Compute per-live block info.
143 if (!calcLiveBlockInfo()) {
144 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
145 // I am looking at you, RegisterCoalescer!
146 DidRepairRange = true;
148 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
149 const_cast<LiveIntervals&>(LIS)
150 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
152 ThroughBlocks.clear();
153 bool fixed = calcLiveBlockInfo();
155 assert(fixed && "Couldn't fix broken live interval");
158 DEBUG(dbgs() << "Analyze counted "
159 << UseSlots.size() << " instrs in "
160 << UseBlocks.size() << " blocks, through "
161 << NumThroughBlocks << " blocks.\n");
164 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
165 /// where CurLI is live.
166 bool SplitAnalysis::calcLiveBlockInfo() {
167 ThroughBlocks.resize(MF.getNumBlockIDs());
168 NumThroughBlocks = NumGapBlocks = 0;
172 LiveInterval::const_iterator LVI = CurLI->begin();
173 LiveInterval::const_iterator LVE = CurLI->end();
175 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
176 UseI = UseSlots.begin();
177 UseE = UseSlots.end();
179 // Loop over basic blocks where CurLI is live.
180 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
184 SlotIndex Start, Stop;
185 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
187 // If the block contains no uses, the range must be live through. At one
188 // point, RegisterCoalescer could create dangling ranges that ended
190 if (UseI == UseE || *UseI >= Stop) {
192 ThroughBlocks.set(BI.MBB->getNumber());
193 // The range shouldn't end mid-block if there are no uses. This shouldn't
198 // This block has uses. Find the first and last uses in the block.
199 BI.FirstInstr = *UseI;
200 assert(BI.FirstInstr >= Start);
202 while (UseI != UseE && *UseI < Stop);
203 BI.LastInstr = UseI[-1];
204 assert(BI.LastInstr < Stop);
206 // LVI is the first live segment overlapping MBB.
207 BI.LiveIn = LVI->start <= Start;
209 // When not live in, the first use should be a def.
211 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
212 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
213 BI.FirstDef = BI.FirstInstr;
216 // Look for gaps in the live range.
218 while (LVI->end < Stop) {
219 SlotIndex LastStop = LVI->end;
220 if (++LVI == LVE || LVI->start >= Stop) {
222 BI.LastInstr = LastStop;
226 if (LastStop < LVI->start) {
227 // There is a gap in the live range. Create duplicate entries for the
228 // live-in snippet and the live-out snippet.
231 // Push the Live-in part.
233 UseBlocks.push_back(BI);
234 UseBlocks.back().LastInstr = LastStop;
236 // Set up BI for the live-out part.
239 BI.FirstInstr = BI.FirstDef = LVI->start;
242 // A Segment that starts in the middle of the block must be a def.
243 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
245 BI.FirstDef = LVI->start;
248 UseBlocks.push_back(BI);
250 // LVI is now at LVE or LVI->end >= Stop.
255 // Live segment ends exactly at Stop. Move to the next segment.
256 if (LVI->end == Stop && ++LVI == LVE)
259 // Pick the next basic block.
260 if (LVI->start < Stop)
263 MFI = LIS.getMBBFromIndex(LVI->start);
266 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
270 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
273 LiveInterval *li = const_cast<LiveInterval*>(cli);
274 LiveInterval::iterator LVI = li->begin();
275 LiveInterval::iterator LVE = li->end();
278 // Loop over basic blocks where li is live.
279 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
280 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
283 LVI = li->advanceTo(LVI, Stop);
288 Stop = LIS.getMBBEndIdx(MFI);
289 } while (Stop <= LVI->start);
293 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
294 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
295 const LiveInterval &Orig = LIS.getInterval(OrigReg);
296 assert(!Orig.empty() && "Splitting empty interval?");
297 LiveInterval::const_iterator I = Orig.find(Idx);
299 // Range containing Idx should begin at Idx.
300 if (I != Orig.end() && I->start <= Idx)
301 return I->start == Idx;
303 // Range does not contain Idx, previous must end at Idx.
304 return I != Orig.begin() && (--I)->end == Idx;
307 void SplitAnalysis::analyze(const LiveInterval *li) {
314 //===----------------------------------------------------------------------===//
316 //===----------------------------------------------------------------------===//
318 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
319 SplitEditor::SplitEditor(SplitAnalysis &sa, LiveIntervals &lis, VirtRegMap &vrm,
320 MachineDominatorTree &mdt,
321 MachineBlockFrequencyInfo &mbfi)
322 : SA(sa), LIS(lis), VRM(vrm), MRI(vrm.getMachineFunction().getRegInfo()),
323 MDT(mdt), TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
324 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
325 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
326 RegAssign(Allocator) {}
328 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
335 // Reset the LiveRangeCalc instances needed for this spill mode.
336 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
337 &LIS.getVNInfoAllocator());
339 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
340 &LIS.getVNInfoAllocator());
342 // We don't need an AliasAnalysis since we will only be performing
343 // cheap-as-a-copy remats anyway.
344 Edit->anyRematerializable(nullptr);
347 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
348 void SplitEditor::dump() const {
349 if (RegAssign.empty()) {
350 dbgs() << " empty\n";
354 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
355 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
360 VNInfo *SplitEditor::defValue(unsigned RegIdx,
361 const VNInfo *ParentVNI,
363 assert(ParentVNI && "Mapping NULL value");
364 assert(Idx.isValid() && "Invalid SlotIndex");
365 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
366 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
368 // Create a new value.
369 VNInfo *VNI = LI->getNextValue(Idx, LIS.getVNInfoAllocator());
371 // Use insert for lookup, so we can add missing values with a second lookup.
372 std::pair<ValueMap::iterator, bool> InsP =
373 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
374 ValueForcePair(VNI, false)));
376 // This was the first time (RegIdx, ParentVNI) was mapped.
377 // Keep it as a simple def without any liveness.
381 // If the previous value was a simple mapping, add liveness for it now.
382 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
383 SlotIndex Def = OldVNI->def;
384 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), OldVNI));
385 // No longer a simple mapping. Switch to a complex, non-forced mapping.
386 InsP.first->second = ValueForcePair();
389 // This is a complex mapping, add liveness for VNI
390 SlotIndex Def = VNI->def;
391 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI));
396 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
397 assert(ParentVNI && "Mapping NULL value");
398 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
399 VNInfo *VNI = VFP.getPointer();
401 // ParentVNI was either unmapped or already complex mapped. Either way, just
402 // set the force bit.
408 // This was previously a single mapping. Make sure the old def is represented
409 // by a trivial live range.
410 SlotIndex Def = VNI->def;
411 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
412 LI->addSegment(LiveInterval::Segment(Def, Def.getDeadSlot(), VNI));
413 // Mark as complex mapped, forced.
414 VFP = ValueForcePair(nullptr, true);
417 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
420 MachineBasicBlock &MBB,
421 MachineBasicBlock::iterator I) {
422 MachineInstr *CopyMI = nullptr;
424 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
426 // We may be trying to avoid interference that ends at a deleted instruction,
427 // so always begin RegIdx 0 early and all others late.
428 bool Late = RegIdx != 0;
430 // Attempt cheap-as-a-copy rematerialization.
431 LiveRangeEdit::Remat RM(ParentVNI);
432 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
433 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late);
436 // Can't remat, just insert a copy from parent.
437 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
438 .addReg(Edit->getReg());
439 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
444 // Define the value in Reg.
445 return defValue(RegIdx, ParentVNI, Def);
448 /// Create a new virtual register and live interval.
449 unsigned SplitEditor::openIntv() {
450 // Create the complement as index 0.
452 Edit->createEmptyInterval();
454 // Create the open interval.
455 OpenIdx = Edit->size();
456 Edit->createEmptyInterval();
460 void SplitEditor::selectIntv(unsigned Idx) {
461 assert(Idx != 0 && "Cannot select the complement interval");
462 assert(Idx < Edit->size() && "Can only select previously opened interval");
463 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
467 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
468 assert(OpenIdx && "openIntv not called before enterIntvBefore");
469 DEBUG(dbgs() << " enterIntvBefore " << Idx);
470 Idx = Idx.getBaseIndex();
471 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
473 DEBUG(dbgs() << ": not live\n");
476 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
477 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
478 assert(MI && "enterIntvBefore called with invalid index");
480 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
484 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
485 assert(OpenIdx && "openIntv not called before enterIntvAfter");
486 DEBUG(dbgs() << " enterIntvAfter " << Idx);
487 Idx = Idx.getBoundaryIndex();
488 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
490 DEBUG(dbgs() << ": not live\n");
493 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
494 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
495 assert(MI && "enterIntvAfter called with invalid index");
497 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
498 std::next(MachineBasicBlock::iterator(MI)));
502 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
503 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
504 SlotIndex End = LIS.getMBBEndIdx(&MBB);
505 SlotIndex Last = End.getPrevSlot();
506 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
507 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
509 DEBUG(dbgs() << ": not live\n");
512 DEBUG(dbgs() << ": valno " << ParentVNI->id);
513 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
514 SA.getLastSplitPointIter(&MBB));
515 RegAssign.insert(VNI->def, End, OpenIdx);
520 /// useIntv - indicate that all instructions in MBB should use OpenLI.
521 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
522 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
525 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
526 assert(OpenIdx && "openIntv not called before useIntv");
527 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
528 RegAssign.insert(Start, End, OpenIdx);
532 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
533 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
534 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
536 // The interval must be live beyond the instruction at Idx.
537 SlotIndex Boundary = Idx.getBoundaryIndex();
538 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Boundary);
540 DEBUG(dbgs() << ": not live\n");
541 return Boundary.getNextSlot();
543 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
544 MachineInstr *MI = LIS.getInstructionFromIndex(Boundary);
545 assert(MI && "No instruction at index");
547 // In spill mode, make live ranges as short as possible by inserting the copy
548 // before MI. This is only possible if that instruction doesn't redefine the
549 // value. The inserted COPY is not a kill, and we don't need to recompute
550 // the source live range. The spiller also won't try to hoist this copy.
551 if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
552 MI->readsVirtualRegister(Edit->getReg())) {
553 forceRecompute(0, ParentVNI);
554 defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
558 VNInfo *VNI = defFromParent(0, ParentVNI, Boundary, *MI->getParent(),
559 std::next(MachineBasicBlock::iterator(MI)));
563 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
564 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
565 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
567 // The interval must be live into the instruction at Idx.
568 Idx = Idx.getBaseIndex();
569 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
571 DEBUG(dbgs() << ": not live\n");
572 return Idx.getNextSlot();
574 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
576 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
577 assert(MI && "No instruction at index");
578 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
582 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
583 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
584 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
585 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
587 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
589 DEBUG(dbgs() << ": not live\n");
593 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
594 MBB.SkipPHIsAndLabels(MBB.begin()));
595 RegAssign.insert(Start, VNI->def, OpenIdx);
600 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
601 assert(OpenIdx && "openIntv not called before overlapIntv");
602 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
603 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
604 "Parent changes value in extended range");
605 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
606 "Range cannot span basic blocks");
608 // The complement interval will be extended as needed by LRCalc.extend().
610 forceRecompute(0, ParentVNI);
611 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
612 RegAssign.insert(Start, End, OpenIdx);
616 //===----------------------------------------------------------------------===//
618 //===----------------------------------------------------------------------===//
620 void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
621 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
622 DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
623 RegAssignMap::iterator AssignI;
624 AssignI.setMap(RegAssign);
626 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
627 VNInfo *VNI = Copies[i];
628 SlotIndex Def = VNI->def;
629 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
630 assert(MI && "No instruction for back-copy");
632 MachineBasicBlock *MBB = MI->getParent();
633 MachineBasicBlock::iterator MBBI(MI);
635 do AtBegin = MBBI == MBB->begin();
636 while (!AtBegin && (--MBBI)->isDebugValue());
638 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
639 LI->removeValNo(VNI);
640 LIS.RemoveMachineInstrFromMaps(MI);
641 MI->eraseFromParent();
643 // Adjust RegAssign if a register assignment is killed at VNI->def. We
644 // want to avoid calculating the live range of the source register if
646 AssignI.find(Def.getPrevSlot());
647 if (!AssignI.valid() || AssignI.start() >= Def)
649 // If MI doesn't kill the assigned register, just leave it.
650 if (AssignI.stop() != Def)
652 unsigned RegIdx = AssignI.value();
653 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
654 DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
655 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
657 SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
658 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
659 AssignI.setStop(Kill);
665 SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
666 MachineBasicBlock *DefMBB) {
669 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
671 const MachineLoopInfo &Loops = SA.Loops;
672 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
673 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
675 // Best candidate so far.
676 MachineBasicBlock *BestMBB = MBB;
677 unsigned BestDepth = UINT_MAX;
680 const MachineLoop *Loop = Loops.getLoopFor(MBB);
682 // MBB isn't in a loop, it doesn't get any better. All dominators have a
683 // higher frequency by definition.
685 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
686 << MBB->getNumber() << " at depth 0\n");
690 // We'll never be able to exit the DefLoop.
691 if (Loop == DefLoop) {
692 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
693 << MBB->getNumber() << " in the same loop\n");
697 // Least busy dominator seen so far.
698 unsigned Depth = Loop->getLoopDepth();
699 if (Depth < BestDepth) {
702 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
703 << MBB->getNumber() << " at depth " << Depth << '\n');
706 // Leave loop by going to the immediate dominator of the loop header.
707 // This is a bigger stride than simply walking up the dominator tree.
708 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
710 // Too far up the dominator tree?
711 if (!IDom || !MDT.dominates(DefDomNode, IDom))
714 MBB = IDom->getBlock();
718 void SplitEditor::hoistCopiesForSize() {
719 // Get the complement interval, always RegIdx 0.
720 LiveInterval *LI = &LIS.getInterval(Edit->get(0));
721 LiveInterval *Parent = &Edit->getParent();
723 // Track the nearest common dominator for all back-copies for each ParentVNI,
724 // indexed by ParentVNI->id.
725 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
726 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
728 // Find the nearest common dominator for parent values with multiple
729 // back-copies. If a single back-copy dominates, put it in DomPair.second.
730 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
735 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
736 assert(ParentVNI && "Parent not live at complement def");
738 // Don't hoist remats. The complement is probably going to disappear
739 // completely anyway.
740 if (Edit->didRematerialize(ParentVNI))
743 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
744 DomPair &Dom = NearestDom[ParentVNI->id];
746 // Keep directly defined parent values. This is either a PHI or an
747 // instruction in the complement range. All other copies of ParentVNI
748 // should be eliminated.
749 if (VNI->def == ParentVNI->def) {
750 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
751 Dom = DomPair(ValMBB, VNI->def);
754 // Skip the singly mapped values. There is nothing to gain from hoisting a
756 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
757 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
762 // First time we see ParentVNI. VNI dominates itself.
763 Dom = DomPair(ValMBB, VNI->def);
764 } else if (Dom.first == ValMBB) {
765 // Two defs in the same block. Pick the earlier def.
766 if (!Dom.second.isValid() || VNI->def < Dom.second)
767 Dom.second = VNI->def;
769 // Different basic blocks. Check if one dominates.
770 MachineBasicBlock *Near =
771 MDT.findNearestCommonDominator(Dom.first, ValMBB);
773 // Def ValMBB dominates.
774 Dom = DomPair(ValMBB, VNI->def);
775 else if (Near != Dom.first)
776 // None dominate. Hoist to common dominator, need new def.
777 Dom = DomPair(Near, SlotIndex());
780 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
781 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
782 << " hoist to BB#" << Dom.first->getNumber() << ' '
783 << Dom.second << '\n');
786 // Insert the hoisted copies.
787 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
788 DomPair &Dom = NearestDom[i];
789 if (!Dom.first || Dom.second.isValid())
791 // This value needs a hoisted copy inserted at the end of Dom.first.
792 VNInfo *ParentVNI = Parent->getValNumInfo(i);
793 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
794 // Get a less loopy dominator than Dom.first.
795 Dom.first = findShallowDominator(Dom.first, DefMBB);
796 SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
798 defFromParent(0, ParentVNI, Last, *Dom.first,
799 SA.getLastSplitPointIter(Dom.first))->def;
802 // Remove redundant back-copies that are now known to be dominated by another
803 // def with the same value.
804 SmallVector<VNInfo*, 8> BackCopies;
805 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
810 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
811 const DomPair &Dom = NearestDom[ParentVNI->id];
812 if (!Dom.first || Dom.second == VNI->def)
814 BackCopies.push_back(VNI);
815 forceRecompute(0, ParentVNI);
817 removeBackCopies(BackCopies);
821 /// transferValues - Transfer all possible values to the new live ranges.
822 /// Values that were rematerialized are left alone, they need LRCalc.extend().
823 bool SplitEditor::transferValues() {
824 bool Skipped = false;
825 RegAssignMap::const_iterator AssignI = RegAssign.begin();
826 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
827 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
828 DEBUG(dbgs() << " blit " << *ParentI << ':');
829 VNInfo *ParentVNI = ParentI->valno;
830 // RegAssign has holes where RegIdx 0 should be used.
831 SlotIndex Start = ParentI->start;
832 AssignI.advanceTo(Start);
835 SlotIndex End = ParentI->end;
836 if (!AssignI.valid()) {
838 } else if (AssignI.start() <= Start) {
839 RegIdx = AssignI.value();
840 if (AssignI.stop() < End) {
841 End = AssignI.stop();
846 End = std::min(End, AssignI.start());
849 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
850 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
851 LiveRange &LR = LIS.getInterval(Edit->get(RegIdx));
853 // Check for a simply defined value that can be blitted directly.
854 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
855 if (VNInfo *VNI = VFP.getPointer()) {
856 DEBUG(dbgs() << ':' << VNI->id);
857 LR.addSegment(LiveInterval::Segment(Start, End, VNI));
862 // Skip values with forced recomputation.
864 DEBUG(dbgs() << "(recalc)");
870 LiveRangeCalc &LRC = getLRCalc(RegIdx);
872 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
873 // so the live range is accurate. Add live-in blocks in [Start;End) to the
875 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
876 SlotIndex BlockStart, BlockEnd;
877 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
879 // The first block may be live-in, or it may have its own def.
880 if (Start != BlockStart) {
881 VNInfo *VNI = LR.extendInBlock(BlockStart, std::min(BlockEnd, End));
882 assert(VNI && "Missing def for complex mapped value");
883 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
884 // MBB has its own def. Is it also live-out?
886 LRC.setLiveOutValue(MBB, VNI);
888 // Skip to the next block for live-in.
890 BlockStart = BlockEnd;
893 // Handle the live-in blocks covered by [Start;End).
894 assert(Start <= BlockStart && "Expected live-in block");
895 while (BlockStart < End) {
896 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
897 BlockEnd = LIS.getMBBEndIdx(MBB);
898 if (BlockStart == ParentVNI->def) {
899 // This block has the def of a parent PHI, so it isn't live-in.
900 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
901 VNInfo *VNI = LR.extendInBlock(BlockStart, std::min(BlockEnd, End));
902 assert(VNI && "Missing def for complex mapped parent PHI");
904 LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
906 // This block needs a live-in value. The last block covered may not
909 LRC.addLiveInBlock(LR, MDT[MBB], End);
911 // Live-through, and we don't know the value.
912 LRC.addLiveInBlock(LR, MDT[MBB]);
913 LRC.setLiveOutValue(MBB, nullptr);
916 BlockStart = BlockEnd;
920 } while (Start != ParentI->end);
921 DEBUG(dbgs() << '\n');
924 LRCalc[0].calculateValues();
926 LRCalc[1].calculateValues();
931 void SplitEditor::extendPHIKillRanges() {
932 // Extend live ranges to be live-out for successor PHI values.
933 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
934 E = Edit->getParent().vni_end(); I != E; ++I) {
935 const VNInfo *PHIVNI = *I;
936 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
938 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
939 LiveRange &LR = LIS.getInterval(Edit->get(RegIdx));
940 LiveRangeCalc &LRC = getLRCalc(RegIdx);
941 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
942 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
943 PE = MBB->pred_end(); PI != PE; ++PI) {
944 SlotIndex End = LIS.getMBBEndIdx(*PI);
945 SlotIndex LastUse = End.getPrevSlot();
946 // The predecessor may not have a live-out value. That is OK, like an
947 // undef PHI operand.
948 if (Edit->getParent().liveAt(LastUse)) {
949 assert(RegAssign.lookup(LastUse) == RegIdx &&
950 "Different register assignment in phi predecessor");
957 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
958 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
959 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
960 RE = MRI.reg_end(); RI != RE;) {
961 MachineOperand &MO = *RI;
962 MachineInstr *MI = MO.getParent();
964 // LiveDebugVariables should have handled all DBG_VALUE instructions.
965 if (MI->isDebugValue()) {
966 DEBUG(dbgs() << "Zapping " << *MI);
971 // <undef> operands don't really read the register, so it doesn't matter
972 // which register we choose. When the use operand is tied to a def, we must
973 // use the same register as the def, so just do that always.
974 SlotIndex Idx = LIS.getInstructionIndex(MI);
975 if (MO.isDef() || MO.isUndef())
976 Idx = Idx.getRegSlot(MO.isEarlyClobber());
978 // Rewrite to the mapped register at Idx.
979 unsigned RegIdx = RegAssign.lookup(Idx);
980 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
982 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
983 << Idx << ':' << RegIdx << '\t' << *MI);
985 // Extend liveness to Idx if the instruction reads reg.
986 if (!ExtendRanges || MO.isUndef())
989 // Skip instructions that don't read Reg.
991 if (!MO.getSubReg() && !MO.isEarlyClobber())
993 // We may wan't to extend a live range for a partial redef, or for a use
994 // tied to an early clobber.
995 Idx = Idx.getPrevSlot();
996 if (!Edit->getParent().liveAt(Idx))
999 Idx = Idx.getRegSlot(true);
1001 getLRCalc(RegIdx).extend(*LI, Idx.getNextSlot());
1005 void SplitEditor::deleteRematVictims() {
1006 SmallVector<MachineInstr*, 8> Dead;
1007 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
1008 LiveInterval *LI = &LIS.getInterval(*I);
1009 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
1010 LII != LIE; ++LII) {
1011 // Dead defs end at the dead slot.
1012 if (LII->end != LII->valno->def.getDeadSlot())
1014 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
1015 assert(MI && "Missing instruction for dead def");
1016 MI->addRegisterDead(LI->reg, &TRI);
1018 if (!MI->allDefsAreDead())
1021 DEBUG(dbgs() << "All defs dead: " << *MI);
1029 Edit->eliminateDeadDefs(Dead);
1032 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1035 // At this point, the live intervals in Edit contain VNInfos corresponding to
1036 // the inserted copies.
1038 // Add the original defs from the parent interval.
1039 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
1040 E = Edit->getParent().vni_end(); I != E; ++I) {
1041 const VNInfo *ParentVNI = *I;
1042 if (ParentVNI->isUnused())
1044 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1045 defValue(RegIdx, ParentVNI, ParentVNI->def);
1047 // Force rematted values to be recomputed everywhere.
1048 // The new live ranges may be truncated.
1049 if (Edit->didRematerialize(ParentVNI))
1050 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1051 forceRecompute(i, ParentVNI);
1054 // Hoist back-copies to the complement interval when in spill mode.
1055 switch (SpillMode) {
1057 // Leave all back-copies as is.
1060 hoistCopiesForSize();
1063 llvm_unreachable("Spill mode 'speed' not implemented yet");
1066 // Transfer the simply mapped values, check if any are skipped.
1067 bool Skipped = transferValues();
1069 extendPHIKillRanges();
1073 // Rewrite virtual registers, possibly extending ranges.
1074 rewriteAssigned(Skipped);
1076 // Delete defs that were rematted everywhere.
1078 deleteRematVictims();
1080 // Get rid of unused values and set phi-kill flags.
1081 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) {
1082 LiveInterval &LI = LIS.getInterval(*I);
1083 LI.RenumberValues();
1086 // Provide a reverse mapping from original indices to Edit ranges.
1089 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1090 LRMap->push_back(i);
1093 // Now check if any registers were separated into multiple components.
1094 ConnectedVNInfoEqClasses ConEQ(LIS);
1095 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1096 // Don't use iterators, they are invalidated by create() below.
1097 LiveInterval *li = &LIS.getInterval(Edit->get(i));
1098 unsigned NumComp = ConEQ.Classify(li);
1101 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
1102 SmallVector<LiveInterval*, 8> dups;
1104 for (unsigned j = 1; j != NumComp; ++j)
1105 dups.push_back(&Edit->createEmptyInterval());
1106 ConEQ.Distribute(&dups[0], MRI);
1107 // The new intervals all map back to i.
1109 LRMap->resize(Edit->size(), i);
1112 // Calculate spill weight and allocation hints for new intervals.
1113 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops, MBFI);
1115 assert(!LRMap || LRMap->size() == Edit->size());
1119 //===----------------------------------------------------------------------===//
1120 // Single Block Splitting
1121 //===----------------------------------------------------------------------===//
1123 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1124 bool SingleInstrs) const {
1125 // Always split for multiple instructions.
1126 if (!BI.isOneInstr())
1128 // Don't split for single instructions unless explicitly requested.
1131 // Splitting a live-through range always makes progress.
1132 if (BI.LiveIn && BI.LiveOut)
1134 // No point in isolating a copy. It has no register class constraints.
1135 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1137 // Finally, don't isolate an end point that was created by earlier splits.
1138 return isOriginalEndpoint(BI.FirstInstr);
1141 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1143 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1144 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1146 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1147 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1149 // The last use is after the last valid split point.
1150 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1151 useIntv(SegStart, SegStop);
1152 overlapIntv(SegStop, BI.LastInstr);
1157 //===----------------------------------------------------------------------===//
1158 // Global Live Range Splitting Support
1159 //===----------------------------------------------------------------------===//
1161 // These methods support a method of global live range splitting that uses a
1162 // global algorithm to decide intervals for CFG edges. They will insert split
1163 // points and color intervals in basic blocks while avoiding interference.
1165 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1166 // are on the stack.
1168 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1169 unsigned IntvIn, SlotIndex LeaveBefore,
1170 unsigned IntvOut, SlotIndex EnterAfter){
1171 SlotIndex Start, Stop;
1172 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1174 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1175 << ") intf " << LeaveBefore << '-' << EnterAfter
1176 << ", live-through " << IntvIn << " -> " << IntvOut);
1178 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1180 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1181 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1182 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1184 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1187 DEBUG(dbgs() << ", spill on entry.\n");
1189 // <<<<<<<<< Possible LeaveBefore interference.
1190 // |-----------| Live through.
1191 // -____________ Spill on entry.
1194 SlotIndex Idx = leaveIntvAtTop(*MBB);
1195 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1201 DEBUG(dbgs() << ", reload on exit.\n");
1203 // >>>>>>> Possible EnterAfter interference.
1204 // |-----------| Live through.
1205 // ___________-- Reload on exit.
1207 selectIntv(IntvOut);
1208 SlotIndex Idx = enterIntvAtEnd(*MBB);
1209 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1214 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1215 DEBUG(dbgs() << ", straight through.\n");
1217 // |-----------| Live through.
1218 // ------------- Straight through, same intv, no interference.
1220 selectIntv(IntvOut);
1221 useIntv(Start, Stop);
1225 // We cannot legally insert splits after LSP.
1226 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1227 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1229 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1230 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1231 DEBUG(dbgs() << ", switch avoiding interference.\n");
1233 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1234 // |-----------| Live through.
1235 // ------======= Switch intervals between interference.
1237 selectIntv(IntvOut);
1239 if (LeaveBefore && LeaveBefore < LSP) {
1240 Idx = enterIntvBefore(LeaveBefore);
1243 Idx = enterIntvAtEnd(*MBB);
1246 useIntv(Start, Idx);
1247 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1248 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1252 DEBUG(dbgs() << ", create local intv for interference.\n");
1254 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1255 // |-----------| Live through.
1256 // ==---------== Switch intervals before/after interference.
1258 assert(LeaveBefore <= EnterAfter && "Missed case");
1260 selectIntv(IntvOut);
1261 SlotIndex Idx = enterIntvAfter(EnterAfter);
1263 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1266 Idx = leaveIntvBefore(LeaveBefore);
1267 useIntv(Start, Idx);
1268 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1272 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1273 unsigned IntvIn, SlotIndex LeaveBefore) {
1274 SlotIndex Start, Stop;
1275 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1277 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1278 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1279 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1280 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1282 assert(IntvIn && "Must have register in");
1283 assert(BI.LiveIn && "Must be live-in");
1284 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1286 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1287 DEBUG(dbgs() << " before interference.\n");
1289 // <<< Interference after kill.
1290 // |---o---x | Killed in block.
1291 // ========= Use IntvIn everywhere.
1294 useIntv(Start, BI.LastInstr);
1298 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1300 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1302 // <<< Possible interference after last use.
1303 // |---o---o---| Live-out on stack.
1304 // =========____ Leave IntvIn after last use.
1306 // < Interference after last use.
1307 // |---o---o--o| Live-out on stack, late last use.
1308 // ============ Copy to stack after LSP, overlap IntvIn.
1309 // \_____ Stack interval is live-out.
1311 if (BI.LastInstr < LSP) {
1312 DEBUG(dbgs() << ", spill after last use before interference.\n");
1314 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1315 useIntv(Start, Idx);
1316 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1318 DEBUG(dbgs() << ", spill before last split point.\n");
1320 SlotIndex Idx = leaveIntvBefore(LSP);
1321 overlapIntv(Idx, BI.LastInstr);
1322 useIntv(Start, Idx);
1323 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1328 // The interference is overlapping somewhere we wanted to use IntvIn. That
1329 // means we need to create a local interval that can be allocated a
1330 // different register.
1331 unsigned LocalIntv = openIntv();
1333 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1335 if (!BI.LiveOut || BI.LastInstr < LSP) {
1337 // <<<<<<< Interference overlapping uses.
1338 // |---o---o---| Live-out on stack.
1339 // =====----____ Leave IntvIn before interference, then spill.
1341 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1342 SlotIndex From = enterIntvBefore(LeaveBefore);
1345 useIntv(Start, From);
1346 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1350 // <<<<<<< Interference overlapping uses.
1351 // |---o---o--o| Live-out on stack, late last use.
1352 // =====------- Copy to stack before LSP, overlap LocalIntv.
1353 // \_____ Stack interval is live-out.
1355 SlotIndex To = leaveIntvBefore(LSP);
1356 overlapIntv(To, BI.LastInstr);
1357 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1360 useIntv(Start, From);
1361 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1364 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1365 unsigned IntvOut, SlotIndex EnterAfter) {
1366 SlotIndex Start, Stop;
1367 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1369 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1370 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1371 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1372 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1374 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1376 assert(IntvOut && "Must have register out");
1377 assert(BI.LiveOut && "Must be live-out");
1378 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1380 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1381 DEBUG(dbgs() << " after interference.\n");
1383 // >>>> Interference before def.
1384 // | o---o---| Defined in block.
1385 // ========= Use IntvOut everywhere.
1387 selectIntv(IntvOut);
1388 useIntv(BI.FirstInstr, Stop);
1392 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1393 DEBUG(dbgs() << ", reload after interference.\n");
1395 // >>>> Interference before def.
1396 // |---o---o---| Live-through, stack-in.
1397 // ____========= Enter IntvOut before first use.
1399 selectIntv(IntvOut);
1400 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1402 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1406 // The interference is overlapping somewhere we wanted to use IntvOut. That
1407 // means we need to create a local interval that can be allocated a
1408 // different register.
1409 DEBUG(dbgs() << ", interference overlaps uses.\n");
1411 // >>>>>>> Interference overlapping uses.
1412 // |---o---o---| Live-through, stack-in.
1413 // ____---====== Create local interval for interference range.
1415 selectIntv(IntvOut);
1416 SlotIndex Idx = enterIntvAfter(EnterAfter);
1418 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1421 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));