1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 STATISTIC(NumFinished, "Number of splits finished");
32 STATISTIC(NumSimple, "Number of splits that were simple");
33 STATISTIC(NumCopies, "Number of copies inserted for splitting");
34 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
35 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42 const LiveIntervals &lis,
43 const MachineLoopInfo &mli)
44 : MF(vrm.getMachineFunction()),
48 TII(*MF.getTarget().getInstrInfo()),
50 LastSplitPoint(MF.getNumBlockIDs()) {}
52 void SplitAnalysis::clear() {
55 ThroughBlocks.clear();
57 DidRepairRange = false;
60 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 // Compute split points on the first call. The pair is independent of the
66 // current live interval.
67 if (!LSP.first.isValid()) {
68 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getMBBEndIdx(MBB);
72 LSP.first = LIS.getInstructionIndex(FirstTerm);
74 // If there is a landing pad successor, also find the call instruction.
77 // There may not be a call instruction (?) in which case we ignore LPad.
78 LSP.second = LSP.first;
79 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
82 if (I->getDesc().isCall()) {
83 LSP.second = LIS.getInstructionIndex(I);
89 // If CurLI is live into a landing pad successor, move the last split point
90 // back to the call that may throw.
91 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
97 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98 void SplitAnalysis::analyzeUses() {
99 assert(UseSlots.empty() && "Call clear first");
101 // First get all the defs from the interval values. This provides the correct
102 // slots for early clobbers.
103 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104 E = CurLI->vni_end(); I != E; ++I)
105 if (!(*I)->isPHIDef() && !(*I)->isUnused())
106 UseSlots.push_back((*I)->def);
108 // Get use slots form the use-def chain.
109 const MachineRegisterInfo &MRI = MF.getRegInfo();
110 for (MachineRegisterInfo::use_nodbg_iterator
111 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
113 if (!I.getOperand().isUndef())
114 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
116 array_pod_sort(UseSlots.begin(), UseSlots.end());
118 // Remove duplicates, keeping the smaller slot for each instruction.
119 // That is what we want for early clobbers.
120 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121 SlotIndex::isSameInstr),
124 // Compute per-live block info.
125 if (!calcLiveBlockInfo()) {
126 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127 // I am looking at you, RegisterCoalescer!
128 DidRepairRange = true;
130 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131 const_cast<LiveIntervals&>(LIS)
132 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
134 ThroughBlocks.clear();
135 bool fixed = calcLiveBlockInfo();
137 assert(fixed && "Couldn't fix broken live interval");
140 DEBUG(dbgs() << "Analyze counted "
141 << UseSlots.size() << " instrs in "
142 << UseBlocks.size() << " blocks, through "
143 << NumThroughBlocks << " blocks.\n");
146 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147 /// where CurLI is live.
148 bool SplitAnalysis::calcLiveBlockInfo() {
149 ThroughBlocks.resize(MF.getNumBlockIDs());
150 NumThroughBlocks = NumGapBlocks = 0;
154 LiveInterval::const_iterator LVI = CurLI->begin();
155 LiveInterval::const_iterator LVE = CurLI->end();
157 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158 UseI = UseSlots.begin();
159 UseE = UseSlots.end();
161 // Loop over basic blocks where CurLI is live.
162 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
166 SlotIndex Start, Stop;
167 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
169 // If the block contains no uses, the range must be live through. At one
170 // point, RegisterCoalescer could create dangling ranges that ended
172 if (UseI == UseE || *UseI >= Stop) {
174 ThroughBlocks.set(BI.MBB->getNumber());
175 // The range shouldn't end mid-block if there are no uses. This shouldn't
180 // This block has uses. Find the first and last uses in the block.
181 BI.FirstInstr = *UseI;
182 assert(BI.FirstInstr >= Start);
184 while (UseI != UseE && *UseI < Stop);
185 BI.LastInstr = UseI[-1];
186 assert(BI.LastInstr < Stop);
188 // LVI is the first live segment overlapping MBB.
189 BI.LiveIn = LVI->start <= Start;
191 // When not live in, the first use should be a def.
193 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
194 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
195 BI.FirstDef = BI.FirstInstr;
198 // Look for gaps in the live range.
200 while (LVI->end < Stop) {
201 SlotIndex LastStop = LVI->end;
202 if (++LVI == LVE || LVI->start >= Stop) {
204 BI.LastInstr = LastStop;
208 if (LastStop < LVI->start) {
209 // There is a gap in the live range. Create duplicate entries for the
210 // live-in snippet and the live-out snippet.
213 // Push the Live-in part.
215 UseBlocks.push_back(BI);
216 UseBlocks.back().LastInstr = LastStop;
218 // Set up BI for the live-out part.
221 BI.FirstInstr = BI.FirstDef = LVI->start;
224 // A LiveRange that starts in the middle of the block must be a def.
225 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
227 BI.FirstDef = LVI->start;
230 UseBlocks.push_back(BI);
232 // LVI is now at LVE or LVI->end >= Stop.
237 // Live segment ends exactly at Stop. Move to the next segment.
238 if (LVI->end == Stop && ++LVI == LVE)
241 // Pick the next basic block.
242 if (LVI->start < Stop)
245 MFI = LIS.getMBBFromIndex(LVI->start);
248 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
252 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
255 LiveInterval *li = const_cast<LiveInterval*>(cli);
256 LiveInterval::iterator LVI = li->begin();
257 LiveInterval::iterator LVE = li->end();
260 // Loop over basic blocks where li is live.
261 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
262 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
265 LVI = li->advanceTo(LVI, Stop);
270 Stop = LIS.getMBBEndIdx(MFI);
271 } while (Stop <= LVI->start);
275 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
276 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
277 const LiveInterval &Orig = LIS.getInterval(OrigReg);
278 assert(!Orig.empty() && "Splitting empty interval?");
279 LiveInterval::const_iterator I = Orig.find(Idx);
281 // Range containing Idx should begin at Idx.
282 if (I != Orig.end() && I->start <= Idx)
283 return I->start == Idx;
285 // Range does not contain Idx, previous must end at Idx.
286 return I != Orig.begin() && (--I)->end == Idx;
289 void SplitAnalysis::analyze(const LiveInterval *li) {
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
300 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
301 SplitEditor::SplitEditor(SplitAnalysis &sa,
304 MachineDominatorTree &mdt)
305 : SA(sa), LIS(lis), VRM(vrm),
306 MRI(vrm.getMachineFunction().getRegInfo()),
308 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
309 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
315 void SplitEditor::reset(LiveRangeEdit &lre) {
321 // We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
324 // We don't need an AliasAnalysis since we will only be performing
325 // cheap-as-a-copy remats anyway.
326 Edit->anyRematerializable(LIS, TII, 0);
329 void SplitEditor::dump() const {
330 if (RegAssign.empty()) {
331 dbgs() << " empty\n";
335 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
336 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
340 VNInfo *SplitEditor::defValue(unsigned RegIdx,
341 const VNInfo *ParentVNI,
343 assert(ParentVNI && "Mapping NULL value");
344 assert(Idx.isValid() && "Invalid SlotIndex");
345 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
346 LiveInterval *LI = Edit->get(RegIdx);
348 // Create a new value.
349 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
351 // Use insert for lookup, so we can add missing values with a second lookup.
352 std::pair<ValueMap::iterator, bool> InsP =
353 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
355 // This was the first time (RegIdx, ParentVNI) was mapped.
356 // Keep it as a simple def without any liveness.
360 // If the previous value was a simple mapping, add liveness for it now.
361 if (VNInfo *OldVNI = InsP.first->second) {
362 SlotIndex Def = OldVNI->def;
363 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
364 // No longer a simple mapping.
365 InsP.first->second = 0;
368 // This is a complex mapping, add liveness for VNI
369 SlotIndex Def = VNI->def;
370 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
375 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
376 assert(ParentVNI && "Mapping NULL value");
377 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
379 // ParentVNI was either unmapped or already complex mapped. Either way.
383 // This was previously a single mapping. Make sure the old def is represented
384 // by a trivial live range.
385 SlotIndex Def = VNI->def;
386 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
390 // extendRange - Extend the live range to reach Idx.
391 // Potentially create phi-def values.
392 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
393 assert(Idx.isValid() && "Invalid SlotIndex");
394 MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
395 assert(IdxMBB && "No MBB at Idx");
396 LiveInterval *LI = Edit->get(RegIdx);
398 // Is there a def in the same MBB we can extend?
399 if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
402 // Now for the fun part. We know that ParentVNI potentially has multiple defs,
403 // and we may need to create even more phi-defs to preserve VNInfo SSA form.
404 // Perform a search for all predecessor blocks where we know the dominating
406 VNInfo *VNI = findReachingDefs(LI, IdxMBB, Idx.getNextSlot());
408 // When there were multiple different values, we may need new PHIs.
412 // Poor man's SSA update for the single-value case.
413 LiveOutPair LOP(VNI, MDT[LIS.getMBBFromIndex(VNI->def)]);
414 for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
415 E = LiveInBlocks.end(); I != E; ++I) {
416 MachineBasicBlock *MBB = I->DomNode->getBlock();
417 SlotIndex Start = LIS.getMBBStartIdx(MBB);
418 if (I->Kill.isValid())
419 LI->addRange(LiveRange(Start, I->Kill, VNI));
421 LiveOutCache[MBB] = LOP;
422 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
427 /// findReachingDefs - Search the CFG for known live-out values.
428 /// Add required live-in blocks to LiveInBlocks.
429 VNInfo *SplitEditor::findReachingDefs(LiveInterval *LI,
430 MachineBasicBlock *KillMBB,
432 // Initialize the live-out cache the first time it is needed.
433 if (LiveOutSeen.empty()) {
434 unsigned N = VRM.getMachineFunction().getNumBlockIDs();
435 LiveOutSeen.resize(N);
436 LiveOutCache.resize(N);
439 // Blocks where LI should be live-in.
440 SmallVector<MachineBasicBlock*, 16> WorkList(1, KillMBB);
442 // Remember if we have seen more than one value.
443 bool UniqueVNI = true;
446 // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
447 for (unsigned i = 0; i != WorkList.size(); ++i) {
448 MachineBasicBlock *MBB = WorkList[i];
449 assert(!MBB->pred_empty() && "Value live-in to entry block?");
450 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
451 PE = MBB->pred_end(); PI != PE; ++PI) {
452 MachineBasicBlock *Pred = *PI;
453 LiveOutPair &LOP = LiveOutCache[Pred];
455 // Is this a known live-out block?
456 if (LiveOutSeen.test(Pred->getNumber())) {
457 if (VNInfo *VNI = LOP.first) {
458 if (TheVNI && TheVNI != VNI)
465 // First time. LOP is garbage and must be cleared below.
466 LiveOutSeen.set(Pred->getNumber());
468 // Does Pred provide a live-out value?
469 SlotIndex Start, Last;
470 tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
471 Last = Last.getPrevSlot();
472 VNInfo *VNI = LI->extendInBlock(Start, Last);
475 LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
476 if (TheVNI && TheVNI != VNI)
483 // No, we need a live-in value for Pred as well
485 WorkList.push_back(Pred);
487 // Loopback to KillMBB, so value is really live through.
492 // Transfer WorkList to LiveInBlocks in reverse order.
493 // This ordering works best with updateSSA().
494 LiveInBlocks.clear();
495 LiveInBlocks.reserve(WorkList.size());
496 while(!WorkList.empty())
497 LiveInBlocks.push_back(MDT[WorkList.pop_back_val()]);
499 // The kill block may not be live-through.
500 assert(LiveInBlocks.back().DomNode->getBlock() == KillMBB);
501 LiveInBlocks.back().Kill = Kill;
503 return UniqueVNI ? TheVNI : 0;
506 void SplitEditor::updateSSA() {
507 // This is essentially the same iterative algorithm that SSAUpdater uses,
508 // except we already have a dominator tree, so we don't have to recompute it.
512 // Propagate live-out values down the dominator tree, inserting phi-defs
514 for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
515 E = LiveInBlocks.end(); I != E; ++I) {
516 MachineDomTreeNode *Node = I->DomNode;
517 // Skip block if the live-in value has already been determined.
520 MachineBasicBlock *MBB = Node->getBlock();
521 MachineDomTreeNode *IDom = Node->getIDom();
522 LiveOutPair IDomValue;
524 // We need a live-in value to a block with no immediate dominator?
525 // This is probably an unreachable block that has survived somehow.
526 bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
528 // IDom dominates all of our predecessors, but it may not be their
529 // immediate dominator. Check if any of them have live-out values that are
530 // properly dominated by IDom. If so, we need a phi-def here.
532 IDomValue = LiveOutCache[IDom->getBlock()];
533 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
534 PE = MBB->pred_end(); PI != PE; ++PI) {
535 LiveOutPair Value = LiveOutCache[*PI];
536 if (!Value.first || Value.first == IDomValue.first)
538 // This predecessor is carrying something other than IDomValue.
539 // It could be because IDomValue hasn't propagated yet, or it could be
540 // because MBB is in the dominance frontier of that value.
541 if (MDT.dominates(IDom, Value.second)) {
548 // The value may be live-through even if Kill is set, as can happen when
549 // we are called from extendRange. In that case LiveOutSeen is true, and
550 // LiveOutCache indicates a foreign or missing value.
551 LiveOutPair &LOP = LiveOutCache[MBB];
553 // Create a phi-def if required.
556 SlotIndex Start = LIS.getMBBStartIdx(MBB);
557 unsigned RegIdx = RegAssign.lookup(Start);
558 LiveInterval *LI = Edit->get(RegIdx);
559 VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
560 VNI->setIsPHIDef(true);
562 // This block is done, we know the final value.
564 if (I->Kill.isValid())
565 LI->addRange(LiveRange(Start, I->Kill, VNI));
567 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
568 LOP = LiveOutPair(VNI, Node);
570 } else if (IDomValue.first) {
571 // No phi-def here. Remember incoming value.
572 I->Value = IDomValue.first;
573 if (I->Kill.isValid())
575 // Propagate IDomValue if needed:
576 // MBB is live-out and doesn't define its own value.
577 if (LOP.second != Node && LOP.first != IDomValue.first) {
585 // The values in LiveInBlocks are now accurate. No more phi-defs are needed
586 // for these blocks, so we can color the live ranges.
587 for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
588 E = LiveInBlocks.end(); I != E; ++I) {
591 assert(I->Value && "No live-in value found");
592 MachineBasicBlock *MBB = I->DomNode->getBlock();
593 SlotIndex Start = LIS.getMBBStartIdx(MBB);
594 unsigned RegIdx = RegAssign.lookup(Start);
595 LiveInterval *LI = Edit->get(RegIdx);
596 LI->addRange(LiveRange(Start, I->Kill.isValid() ?
597 I->Kill : LIS.getMBBEndIdx(MBB), I->Value));
601 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
604 MachineBasicBlock &MBB,
605 MachineBasicBlock::iterator I) {
606 MachineInstr *CopyMI = 0;
608 LiveInterval *LI = Edit->get(RegIdx);
610 // We may be trying to avoid interference that ends at a deleted instruction,
611 // so always begin RegIdx 0 early and all others late.
612 bool Late = RegIdx != 0;
614 // Attempt cheap-as-a-copy rematerialization.
615 LiveRangeEdit::Remat RM(ParentVNI);
616 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
617 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
620 // Can't remat, just insert a copy from parent.
621 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
622 .addReg(Edit->getReg());
623 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
628 // Define the value in Reg.
629 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
630 VNI->setCopy(CopyMI);
634 /// Create a new virtual register and live interval.
635 unsigned SplitEditor::openIntv() {
636 // Create the complement as index 0.
638 Edit->create(LIS, VRM);
640 // Create the open interval.
641 OpenIdx = Edit->size();
642 Edit->create(LIS, VRM);
646 void SplitEditor::selectIntv(unsigned Idx) {
647 assert(Idx != 0 && "Cannot select the complement interval");
648 assert(Idx < Edit->size() && "Can only select previously opened interval");
649 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
653 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
654 assert(OpenIdx && "openIntv not called before enterIntvBefore");
655 DEBUG(dbgs() << " enterIntvBefore " << Idx);
656 Idx = Idx.getBaseIndex();
657 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
659 DEBUG(dbgs() << ": not live\n");
662 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
663 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
664 assert(MI && "enterIntvBefore called with invalid index");
666 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
670 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
671 assert(OpenIdx && "openIntv not called before enterIntvAfter");
672 DEBUG(dbgs() << " enterIntvAfter " << Idx);
673 Idx = Idx.getBoundaryIndex();
674 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
676 DEBUG(dbgs() << ": not live\n");
679 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
680 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
681 assert(MI && "enterIntvAfter called with invalid index");
683 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
684 llvm::next(MachineBasicBlock::iterator(MI)));
688 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
689 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
690 SlotIndex End = LIS.getMBBEndIdx(&MBB);
691 SlotIndex Last = End.getPrevSlot();
692 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
693 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
695 DEBUG(dbgs() << ": not live\n");
698 DEBUG(dbgs() << ": valno " << ParentVNI->id);
699 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
700 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
701 RegAssign.insert(VNI->def, End, OpenIdx);
706 /// useIntv - indicate that all instructions in MBB should use OpenLI.
707 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
708 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
711 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
712 assert(OpenIdx && "openIntv not called before useIntv");
713 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
714 RegAssign.insert(Start, End, OpenIdx);
718 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
719 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
720 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
722 // The interval must be live beyond the instruction at Idx.
723 Idx = Idx.getBoundaryIndex();
724 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
726 DEBUG(dbgs() << ": not live\n");
727 return Idx.getNextSlot();
729 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
731 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
732 assert(MI && "No instruction at index");
733 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
734 llvm::next(MachineBasicBlock::iterator(MI)));
738 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
739 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
740 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
742 // The interval must be live into the instruction at Idx.
743 Idx = Idx.getBaseIndex();
744 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
746 DEBUG(dbgs() << ": not live\n");
747 return Idx.getNextSlot();
749 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
751 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
752 assert(MI && "No instruction at index");
753 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
757 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
758 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
759 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
760 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
762 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
764 DEBUG(dbgs() << ": not live\n");
768 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
769 MBB.SkipPHIsAndLabels(MBB.begin()));
770 RegAssign.insert(Start, VNI->def, OpenIdx);
775 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
776 assert(OpenIdx && "openIntv not called before overlapIntv");
777 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
778 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
779 "Parent changes value in extended range");
780 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
781 "Range cannot span basic blocks");
783 // The complement interval will be extended as needed by extendRange().
785 markComplexMapped(0, ParentVNI);
786 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
787 RegAssign.insert(Start, End, OpenIdx);
791 /// transferValues - Transfer all possible values to the new live ranges.
792 /// Values that were rematerialized are left alone, they need extendRange().
793 bool SplitEditor::transferValues() {
794 bool Skipped = false;
795 LiveInBlocks.clear();
796 RegAssignMap::const_iterator AssignI = RegAssign.begin();
797 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
798 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
799 DEBUG(dbgs() << " blit " << *ParentI << ':');
800 VNInfo *ParentVNI = ParentI->valno;
801 // RegAssign has holes where RegIdx 0 should be used.
802 SlotIndex Start = ParentI->start;
803 AssignI.advanceTo(Start);
806 SlotIndex End = ParentI->end;
807 if (!AssignI.valid()) {
809 } else if (AssignI.start() <= Start) {
810 RegIdx = AssignI.value();
811 if (AssignI.stop() < End) {
812 End = AssignI.stop();
817 End = std::min(End, AssignI.start());
820 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
821 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
822 LiveInterval *LI = Edit->get(RegIdx);
824 // Check for a simply defined value that can be blitted directly.
825 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
826 DEBUG(dbgs() << ':' << VNI->id);
827 LI->addRange(LiveRange(Start, End, VNI));
832 // Skip rematerialized values, we need to use extendRange() and
833 // extendPHIKillRanges() to completely recompute the live ranges.
834 if (Edit->didRematerialize(ParentVNI)) {
835 DEBUG(dbgs() << "(remat)");
841 // Initialize the live-out cache the first time it is needed.
842 if (LiveOutSeen.empty()) {
843 unsigned N = VRM.getMachineFunction().getNumBlockIDs();
844 LiveOutSeen.resize(N);
845 LiveOutCache.resize(N);
848 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
849 // so the live range is accurate. Add live-in blocks in [Start;End) to the
851 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
852 SlotIndex BlockStart, BlockEnd;
853 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
855 // The first block may be live-in, or it may have its own def.
856 if (Start != BlockStart) {
857 VNInfo *VNI = LI->extendInBlock(BlockStart,
858 std::min(BlockEnd, End).getPrevSlot());
859 assert(VNI && "Missing def for complex mapped value");
860 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
861 // MBB has its own def. Is it also live-out?
862 if (BlockEnd <= End) {
863 LiveOutSeen.set(MBB->getNumber());
864 LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
866 // Skip to the next block for live-in.
868 BlockStart = BlockEnd;
871 // Handle the live-in blocks covered by [Start;End).
872 assert(Start <= BlockStart && "Expected live-in block");
873 while (BlockStart < End) {
874 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
875 BlockEnd = LIS.getMBBEndIdx(MBB);
876 if (BlockStart == ParentVNI->def) {
877 // This block has the def of a parent PHI, so it isn't live-in.
878 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
879 VNInfo *VNI = LI->extendInBlock(BlockStart,
880 std::min(BlockEnd, End).getPrevSlot());
881 assert(VNI && "Missing def for complex mapped parent PHI");
882 if (End >= BlockEnd) {
884 LiveOutSeen.set(MBB->getNumber());
885 LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
888 // This block needs a live-in value.
889 LiveInBlocks.push_back(MDT[MBB]);
890 // The last block covered may not be live-out.
892 LiveInBlocks.back().Kill = End;
894 // Live-out, but we need updateSSA to tell us the value.
895 LiveOutSeen.set(MBB->getNumber());
896 LiveOutCache[MBB] = LiveOutPair((VNInfo*)0,
897 (MachineDomTreeNode*)0);
900 BlockStart = BlockEnd;
904 } while (Start != ParentI->end);
905 DEBUG(dbgs() << '\n');
908 if (!LiveInBlocks.empty())
914 void SplitEditor::extendPHIKillRanges() {
915 // Extend live ranges to be live-out for successor PHI values.
916 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
917 E = Edit->getParent().vni_end(); I != E; ++I) {
918 const VNInfo *PHIVNI = *I;
919 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
921 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
922 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
923 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
924 PE = MBB->pred_end(); PI != PE; ++PI) {
925 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
926 // The predecessor may not have a live-out value. That is OK, like an
927 // undef PHI operand.
928 if (Edit->getParent().liveAt(End)) {
929 assert(RegAssign.lookup(End) == RegIdx &&
930 "Different register assignment in phi predecessor");
931 extendRange(RegIdx, End);
937 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
938 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
939 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
940 RE = MRI.reg_end(); RI != RE;) {
941 MachineOperand &MO = RI.getOperand();
942 MachineInstr *MI = MO.getParent();
944 // LiveDebugVariables should have handled all DBG_VALUE instructions.
945 if (MI->isDebugValue()) {
946 DEBUG(dbgs() << "Zapping " << *MI);
951 // <undef> operands don't really read the register, so it doesn't matter
952 // which register we choose. When the use operand is tied to a def, we must
953 // use the same register as the def, so just do that always.
954 SlotIndex Idx = LIS.getInstructionIndex(MI);
955 if (MO.isDef() || MO.isUndef())
956 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
958 // Rewrite to the mapped register at Idx.
959 unsigned RegIdx = RegAssign.lookup(Idx);
960 MO.setReg(Edit->get(RegIdx)->reg);
961 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
962 << Idx << ':' << RegIdx << '\t' << *MI);
964 // Extend liveness to Idx if the instruction reads reg.
965 if (!ExtendRanges || MO.isUndef())
968 // Skip instructions that don't read Reg.
970 if (!MO.getSubReg() && !MO.isEarlyClobber())
972 // We may wan't to extend a live range for a partial redef, or for a use
973 // tied to an early clobber.
974 Idx = Idx.getPrevSlot();
975 if (!Edit->getParent().liveAt(Idx))
978 Idx = Idx.getUseIndex();
980 extendRange(RegIdx, Idx);
984 void SplitEditor::deleteRematVictims() {
985 SmallVector<MachineInstr*, 8> Dead;
986 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
987 LiveInterval *LI = *I;
988 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
990 // Dead defs end at the store slot.
991 if (LII->end != LII->valno->def.getNextSlot())
993 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
994 assert(MI && "Missing instruction for dead def");
995 MI->addRegisterDead(LI->reg, &TRI);
997 if (!MI->allDefsAreDead())
1000 DEBUG(dbgs() << "All defs dead: " << *MI);
1008 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
1011 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1014 // At this point, the live intervals in Edit contain VNInfos corresponding to
1015 // the inserted copies.
1017 // Add the original defs from the parent interval.
1018 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
1019 E = Edit->getParent().vni_end(); I != E; ++I) {
1020 const VNInfo *ParentVNI = *I;
1021 if (ParentVNI->isUnused())
1023 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1024 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
1025 VNI->setIsPHIDef(ParentVNI->isPHIDef());
1026 VNI->setCopy(ParentVNI->getCopy());
1028 // Mark rematted values as complex everywhere to force liveness computation.
1029 // The new live ranges may be truncated.
1030 if (Edit->didRematerialize(ParentVNI))
1031 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1032 markComplexMapped(i, ParentVNI);
1035 // Transfer the simply mapped values, check if any are skipped.
1036 bool Skipped = transferValues();
1038 extendPHIKillRanges();
1042 // Rewrite virtual registers, possibly extending ranges.
1043 rewriteAssigned(Skipped);
1045 // Delete defs that were rematted everywhere.
1047 deleteRematVictims();
1049 // Get rid of unused values and set phi-kill flags.
1050 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
1051 (*I)->RenumberValues(LIS);
1053 // Provide a reverse mapping from original indices to Edit ranges.
1056 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1057 LRMap->push_back(i);
1060 // Now check if any registers were separated into multiple components.
1061 ConnectedVNInfoEqClasses ConEQ(LIS);
1062 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1063 // Don't use iterators, they are invalidated by create() below.
1064 LiveInterval *li = Edit->get(i);
1065 unsigned NumComp = ConEQ.Classify(li);
1068 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
1069 SmallVector<LiveInterval*, 8> dups;
1071 for (unsigned j = 1; j != NumComp; ++j)
1072 dups.push_back(&Edit->create(LIS, VRM));
1073 ConEQ.Distribute(&dups[0], MRI);
1074 // The new intervals all map back to i.
1076 LRMap->resize(Edit->size(), i);
1079 // Calculate spill weight and allocation hints for new intervals.
1080 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
1082 assert(!LRMap || LRMap->size() == Edit->size());
1086 //===----------------------------------------------------------------------===//
1087 // Single Block Splitting
1088 //===----------------------------------------------------------------------===//
1090 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1091 bool SingleInstrs) const {
1092 // Always split for multiple instructions.
1093 if (!BI.isOneInstr())
1095 // Don't split for single instructions unless explicitly requested.
1098 // Splitting a live-through range always makes progress.
1099 if (BI.LiveIn && BI.LiveOut)
1101 // No point in isolating a copy. It has no register class constraints.
1102 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1104 // Finally, don't isolate an end point that was created by earlier splits.
1105 return isOriginalEndpoint(BI.FirstInstr);
1108 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1110 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1111 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1113 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1114 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1116 // The last use is after the last valid split point.
1117 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1118 useIntv(SegStart, SegStop);
1119 overlapIntv(SegStop, BI.LastInstr);
1124 //===----------------------------------------------------------------------===//
1125 // Global Live Range Splitting Support
1126 //===----------------------------------------------------------------------===//
1128 // These methods support a method of global live range splitting that uses a
1129 // global algorithm to decide intervals for CFG edges. They will insert split
1130 // points and color intervals in basic blocks while avoiding interference.
1132 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1133 // are on the stack.
1135 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1136 unsigned IntvIn, SlotIndex LeaveBefore,
1137 unsigned IntvOut, SlotIndex EnterAfter){
1138 SlotIndex Start, Stop;
1139 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1141 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1142 << ") intf " << LeaveBefore << '-' << EnterAfter
1143 << ", live-through " << IntvIn << " -> " << IntvOut);
1145 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1147 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1148 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1149 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1151 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1154 DEBUG(dbgs() << ", spill on entry.\n");
1156 // <<<<<<<<< Possible LeaveBefore interference.
1157 // |-----------| Live through.
1158 // -____________ Spill on entry.
1161 SlotIndex Idx = leaveIntvAtTop(*MBB);
1162 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1168 DEBUG(dbgs() << ", reload on exit.\n");
1170 // >>>>>>> Possible EnterAfter interference.
1171 // |-----------| Live through.
1172 // ___________-- Reload on exit.
1174 selectIntv(IntvOut);
1175 SlotIndex Idx = enterIntvAtEnd(*MBB);
1176 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1181 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1182 DEBUG(dbgs() << ", straight through.\n");
1184 // |-----------| Live through.
1185 // ------------- Straight through, same intv, no interference.
1187 selectIntv(IntvOut);
1188 useIntv(Start, Stop);
1192 // We cannot legally insert splits after LSP.
1193 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1194 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1196 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1197 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1198 DEBUG(dbgs() << ", switch avoiding interference.\n");
1200 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1201 // |-----------| Live through.
1202 // ------======= Switch intervals between interference.
1204 selectIntv(IntvOut);
1206 if (LeaveBefore && LeaveBefore < LSP) {
1207 Idx = enterIntvBefore(LeaveBefore);
1210 Idx = enterIntvAtEnd(*MBB);
1213 useIntv(Start, Idx);
1214 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1215 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1219 DEBUG(dbgs() << ", create local intv for interference.\n");
1221 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1222 // |-----------| Live through.
1223 // ==---------== Switch intervals before/after interference.
1225 assert(LeaveBefore <= EnterAfter && "Missed case");
1227 selectIntv(IntvOut);
1228 SlotIndex Idx = enterIntvAfter(EnterAfter);
1230 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1233 Idx = leaveIntvBefore(LeaveBefore);
1234 useIntv(Start, Idx);
1235 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1239 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1240 unsigned IntvIn, SlotIndex LeaveBefore) {
1241 SlotIndex Start, Stop;
1242 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1244 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1245 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1246 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1247 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1249 assert(IntvIn && "Must have register in");
1250 assert(BI.LiveIn && "Must be live-in");
1251 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1253 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1254 DEBUG(dbgs() << " before interference.\n");
1256 // <<< Interference after kill.
1257 // |---o---x | Killed in block.
1258 // ========= Use IntvIn everywhere.
1261 useIntv(Start, BI.LastInstr);
1265 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1267 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1269 // <<< Possible interference after last use.
1270 // |---o---o---| Live-out on stack.
1271 // =========____ Leave IntvIn after last use.
1273 // < Interference after last use.
1274 // |---o---o--o| Live-out on stack, late last use.
1275 // ============ Copy to stack after LSP, overlap IntvIn.
1276 // \_____ Stack interval is live-out.
1278 if (BI.LastInstr < LSP) {
1279 DEBUG(dbgs() << ", spill after last use before interference.\n");
1281 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1282 useIntv(Start, Idx);
1283 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1285 DEBUG(dbgs() << ", spill before last split point.\n");
1287 SlotIndex Idx = leaveIntvBefore(LSP);
1288 overlapIntv(Idx, BI.LastInstr);
1289 useIntv(Start, Idx);
1290 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1295 // The interference is overlapping somewhere we wanted to use IntvIn. That
1296 // means we need to create a local interval that can be allocated a
1297 // different register.
1298 unsigned LocalIntv = openIntv();
1300 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1302 if (!BI.LiveOut || BI.LastInstr < LSP) {
1304 // <<<<<<< Interference overlapping uses.
1305 // |---o---o---| Live-out on stack.
1306 // =====----____ Leave IntvIn before interference, then spill.
1308 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1309 SlotIndex From = enterIntvBefore(LeaveBefore);
1312 useIntv(Start, From);
1313 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1317 // <<<<<<< Interference overlapping uses.
1318 // |---o---o--o| Live-out on stack, late last use.
1319 // =====------- Copy to stack before LSP, overlap LocalIntv.
1320 // \_____ Stack interval is live-out.
1322 SlotIndex To = leaveIntvBefore(LSP);
1323 overlapIntv(To, BI.LastInstr);
1324 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1327 useIntv(Start, From);
1328 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1331 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1332 unsigned IntvOut, SlotIndex EnterAfter) {
1333 SlotIndex Start, Stop;
1334 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1336 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1337 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1338 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1339 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1341 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1343 assert(IntvOut && "Must have register out");
1344 assert(BI.LiveOut && "Must be live-out");
1345 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1347 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1348 DEBUG(dbgs() << " after interference.\n");
1350 // >>>> Interference before def.
1351 // | o---o---| Defined in block.
1352 // ========= Use IntvOut everywhere.
1354 selectIntv(IntvOut);
1355 useIntv(BI.FirstInstr, Stop);
1359 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1360 DEBUG(dbgs() << ", reload after interference.\n");
1362 // >>>> Interference before def.
1363 // |---o---o---| Live-through, stack-in.
1364 // ____========= Enter IntvOut before first use.
1366 selectIntv(IntvOut);
1367 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1369 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1373 // The interference is overlapping somewhere we wanted to use IntvOut. That
1374 // means we need to create a local interval that can be allocated a
1375 // different register.
1376 DEBUG(dbgs() << ", interference overlaps uses.\n");
1378 // >>>>>>> Interference overlapping uses.
1379 // |---o---o---| Live-through, stack-in.
1380 // ____---====== Create local interval for interference range.
1382 selectIntv(IntvOut);
1383 SlotIndex Idx = enterIntvAfter(EnterAfter);
1385 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1388 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));