1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/CalcSpillWeights.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
34 AllowSplit("spiller-splits-edges",
35 cl::desc("Allow critical edge splitting during spilling"));
37 STATISTIC(NumFinished, "Number of splits finished");
38 STATISTIC(NumSimple, "Number of splits that were simple");
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
45 const LiveIntervals &lis,
46 const MachineLoopInfo &mli)
47 : MF(vrm.getMachineFunction()),
51 TII(*MF.getTarget().getInstrInfo()),
54 void SplitAnalysis::clear() {
62 bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
63 MachineBasicBlock *T, *F;
64 SmallVector<MachineOperand, 4> Cond;
65 return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
68 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
69 void SplitAnalysis::analyzeUses() {
70 const MachineRegisterInfo &MRI = MF.getRegInfo();
71 for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
72 E = MRI.reg_end(); I != E; ++I) {
73 MachineOperand &MO = I.getOperand();
74 if (MO.isUse() && MO.isUndef())
76 MachineInstr *MI = MO.getParent();
77 if (MI->isDebugValue() || !UsingInstrs.insert(MI))
79 UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
80 MachineBasicBlock *MBB = MI->getParent();
83 array_pod_sort(UseSlots.begin(), UseSlots.end());
85 DEBUG(dbgs() << " counted "
86 << UsingInstrs.size() << " instrs, "
87 << UsingBlocks.size() << " blocks.\n");
90 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
91 /// where CurLI is live.
92 void SplitAnalysis::calcLiveBlockInfo() {
96 LiveInterval::const_iterator LVI = CurLI->begin();
97 LiveInterval::const_iterator LVE = CurLI->end();
99 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
100 UseI = UseSlots.begin();
101 UseE = UseSlots.end();
103 // Loop over basic blocks where CurLI is live.
104 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
108 SlotIndex Start, Stop;
109 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
111 // The last split point is the latest possible insertion point that dominates
112 // all successor blocks. If interference reaches LastSplitPoint, it is not
113 // possible to insert a split or reload that makes CurLI live in the
115 MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
116 if (LSP == BI.MBB->end())
117 BI.LastSplitPoint = Stop;
119 BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
121 // LVI is the first live segment overlapping MBB.
122 BI.LiveIn = LVI->start <= Start;
126 // Find the first and last uses in the block.
127 BI.Uses = hasUses(MFI);
128 if (BI.Uses && UseI != UseE) {
130 assert(BI.FirstUse >= Start);
132 while (UseI != UseE && *UseI < Stop);
133 BI.LastUse = UseI[-1];
134 assert(BI.LastUse < Stop);
137 // Look for gaps in the live range.
140 while (LVI->end < Stop) {
141 SlotIndex LastStop = LVI->end;
142 if (++LVI == LVE || LVI->start >= Stop) {
147 if (LastStop < LVI->start) {
154 // Don't set LiveThrough when the block has a gap.
155 BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
156 LiveBlocks.push_back(BI);
158 // LVI is now at LVE or LVI->end >= Stop.
162 // Live segment ends exactly at Stop. Move to the next segment.
163 if (LVI->end == Stop && ++LVI == LVE)
166 // Pick the next basic block.
167 if (LVI->start < Stop)
170 MFI = LIS.getMBBFromIndex(LVI->start);
174 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
175 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
176 const LiveInterval &Orig = LIS.getInterval(OrigReg);
177 assert(!Orig.empty() && "Splitting empty interval?");
178 LiveInterval::const_iterator I = Orig.find(Idx);
180 // Range containing Idx should begin at Idx.
181 if (I != Orig.end() && I->start <= Idx)
182 return I->start == Idx;
184 // Range does not contain Idx, previous must end at Idx.
185 return I != Orig.begin() && (--I)->end == Idx;
188 void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
189 for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
190 unsigned count = UsingBlocks.lookup(*I);
191 OS << " BB#" << (*I)->getNumber();
193 OS << '(' << count << ')';
197 void SplitAnalysis::analyze(const LiveInterval *li) {
204 //===----------------------------------------------------------------------===//
206 //===----------------------------------------------------------------------===//
208 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
209 SplitEditor::SplitEditor(SplitAnalysis &sa,
212 MachineDominatorTree &mdt)
213 : SA(sa), LIS(lis), VRM(vrm),
214 MRI(vrm.getMachineFunction().getRegInfo()),
216 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
217 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
223 void SplitEditor::reset(LiveRangeEdit &lre) {
228 LiveOutCache.clear();
230 // We don't need an AliasAnalysis since we will only be performing
231 // cheap-as-a-copy remats anyway.
232 Edit->anyRematerializable(LIS, TII, 0);
235 void SplitEditor::dump() const {
236 if (RegAssign.empty()) {
237 dbgs() << " empty\n";
241 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
242 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
246 VNInfo *SplitEditor::defValue(unsigned RegIdx,
247 const VNInfo *ParentVNI,
249 assert(ParentVNI && "Mapping NULL value");
250 assert(Idx.isValid() && "Invalid SlotIndex");
251 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
252 LiveInterval *LI = Edit->get(RegIdx);
254 // Create a new value.
255 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
257 // Preserve the PHIDef bit.
258 if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
259 VNI->setIsPHIDef(true);
261 // Use insert for lookup, so we can add missing values with a second lookup.
262 std::pair<ValueMap::iterator, bool> InsP =
263 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
265 // This was the first time (RegIdx, ParentVNI) was mapped.
266 // Keep it as a simple def without any liveness.
270 // If the previous value was a simple mapping, add liveness for it now.
271 if (VNInfo *OldVNI = InsP.first->second) {
272 SlotIndex Def = OldVNI->def;
273 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
274 // No longer a simple mapping.
275 InsP.first->second = 0;
278 // This is a complex mapping, add liveness for VNI
279 SlotIndex Def = VNI->def;
280 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
285 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
286 assert(ParentVNI && "Mapping NULL value");
287 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
289 // ParentVNI was either unmapped or already complex mapped. Either way.
293 // This was previously a single mapping. Make sure the old def is represented
294 // by a trivial live range.
295 SlotIndex Def = VNI->def;
296 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
300 // extendRange - Extend the live range to reach Idx.
301 // Potentially create phi-def values.
302 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
303 assert(Idx.isValid() && "Invalid SlotIndex");
304 MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
305 assert(IdxMBB && "No MBB at Idx");
306 LiveInterval *LI = Edit->get(RegIdx);
308 // Is there a def in the same MBB we can extend?
309 if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
312 // Now for the fun part. We know that ParentVNI potentially has multiple defs,
313 // and we may need to create even more phi-defs to preserve VNInfo SSA form.
314 // Perform a search for all predecessor blocks where we know the dominating
315 // VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
316 DEBUG(dbgs() << "\n Reaching defs for BB#" << IdxMBB->getNumber()
317 << " at " << Idx << " in " << *LI << '\n');
319 // Blocks where LI should be live-in.
320 SmallVector<MachineDomTreeNode*, 16> LiveIn;
321 LiveIn.push_back(MDT[IdxMBB]);
323 // Remember if we have seen more than one value.
324 bool UniqueVNI = true;
327 // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
328 for (unsigned i = 0; i != LiveIn.size(); ++i) {
329 MachineBasicBlock *MBB = LiveIn[i]->getBlock();
330 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
331 PE = MBB->pred_end(); PI != PE; ++PI) {
332 MachineBasicBlock *Pred = *PI;
333 // Is this a known live-out block?
334 std::pair<LiveOutMap::iterator,bool> LOIP =
335 LiveOutCache.insert(std::make_pair(Pred, LiveOutPair()));
336 // Yes, we have been here before.
338 if (VNInfo *VNI = LOIP.first->second.first) {
339 if (IdxVNI && IdxVNI != VNI)
345 // Does Pred provide a live-out value?
346 SlotIndex Start, Last;
347 tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
348 Last = Last.getPrevSlot();
349 if (VNInfo *VNI = LI->extendInBlock(Start, Last)) {
350 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(VNI->def);
351 LiveOutPair &LOP = LOIP.first->second;
353 LOP.second = MDT[DefMBB];
354 if (IdxVNI && IdxVNI != VNI)
359 // No, we need a live-in value for Pred as well
361 LiveIn.push_back(MDT[Pred]);
363 UniqueVNI = false; // Loopback to IdxMBB, ask updateSSA() for help.
367 // We may need to add phi-def values to preserve the SSA form.
369 LiveOutPair LOP(IdxVNI, MDT[LIS.getMBBFromIndex(IdxVNI->def)]);
370 // Update LiveOutCache, but skip IdxMBB at LiveIn[0].
371 for (unsigned i = 1, e = LiveIn.size(); i != e; ++i)
372 LiveOutCache[LiveIn[i]->getBlock()] = LOP;
374 IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
377 // Check the LiveOutCache invariants.
378 for (LiveOutMap::iterator I = LiveOutCache.begin(), E = LiveOutCache.end();
380 assert(I->first && "Null MBB entry in cache");
381 assert(I->second.first && "Null VNInfo in cache");
382 assert(I->second.second && "Null DomTreeNode in cache");
383 if (I->second.second->getBlock() == I->first)
385 for (MachineBasicBlock::pred_iterator PI = I->first->pred_begin(),
386 PE = I->first->pred_end(); PI != PE; ++PI)
387 assert(LiveOutCache.lookup(*PI) == I->second && "Bad invariant");
391 // Since we went through the trouble of a full BFS visiting all reaching defs,
392 // the values in LiveIn are now accurate. No more phi-defs are needed
393 // for these blocks, so we can color the live ranges.
394 for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
395 MachineBasicBlock *MBB = LiveIn[i]->getBlock();
396 SlotIndex Start = LIS.getMBBStartIdx(MBB);
397 VNInfo *VNI = LiveOutCache.lookup(MBB).first;
399 // Anything in LiveIn other than IdxMBB is live-through.
400 // In IdxMBB, we should stop at Idx unless the same value is live-out.
401 if (MBB == IdxMBB && IdxVNI != VNI)
402 LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
404 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
408 VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
409 SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
411 const MachineBasicBlock *IdxMBB) {
412 // This is essentially the same iterative algorithm that SSAUpdater uses,
413 // except we already have a dominator tree, so we don't have to recompute it.
414 LiveInterval *LI = Edit->get(RegIdx);
419 DEBUG(dbgs() << " Iterating over " << LiveIn.size() << " blocks.\n");
420 // Propagate live-out values down the dominator tree, inserting phi-defs
421 // when necessary. Since LiveIn was created by a BFS, going backwards makes
422 // it more likely for us to visit immediate dominators before their
424 for (unsigned i = LiveIn.size(); i; --i) {
425 MachineDomTreeNode *Node = LiveIn[i-1];
426 MachineBasicBlock *MBB = Node->getBlock();
427 MachineDomTreeNode *IDom = Node->getIDom();
428 LiveOutPair IDomValue;
429 // We need a live-in value to a block with no immediate dominator?
430 // This is probably an unreachable block that has survived somehow.
431 bool needPHI = !IDom;
433 // Get the IDom live-out value.
435 LiveOutMap::iterator I = LiveOutCache.find(IDom->getBlock());
436 if (I != LiveOutCache.end())
437 IDomValue = I->second;
439 // If IDom is outside our set of live-out blocks, there must be new
440 // defs, and we need a phi-def here.
444 // IDom dominates all of our predecessors, but it may not be the immediate
445 // dominator. Check if any of them have live-out values that are properly
446 // dominated by IDom. If so, we need a phi-def here.
448 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
449 PE = MBB->pred_end(); PI != PE; ++PI) {
450 LiveOutPair Value = LiveOutCache[*PI];
451 if (!Value.first || Value.first == IDomValue.first)
453 // This predecessor is carrying something other than IDomValue.
454 // It could be because IDomValue hasn't propagated yet, or it could be
455 // because MBB is in the dominance frontier of that value.
456 if (MDT.dominates(IDom, Value.second)) {
463 // Create a phi-def if required.
466 SlotIndex Start = LIS.getMBBStartIdx(MBB);
467 VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
468 VNI->setIsPHIDef(true);
469 DEBUG(dbgs() << " - BB#" << MBB->getNumber()
470 << " phi-def #" << VNI->id << " at " << Start << '\n');
471 // We no longer need LI to be live-in.
472 LiveIn.erase(LiveIn.begin()+(i-1));
473 // Blocks in LiveIn are either IdxMBB, or have a value live-through.
476 // Check if we need to update live-out info.
477 LiveOutMap::iterator I = LiveOutCache.find(MBB);
478 if (I == LiveOutCache.end() || I->second.second == Node) {
479 // We already have a live-out defined in MBB, so this must be IdxMBB.
480 assert(MBB == IdxMBB && "Adding phi-def to known live-out");
481 LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
483 // This phi-def is also live-out, so color the whole block.
484 LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
485 I->second = LiveOutPair(VNI, Node);
487 } else if (IDomValue.first) {
488 // No phi-def here. Remember incoming value for IdxMBB.
490 IdxVNI = IDomValue.first;
491 // Propagate IDomValue if needed:
492 // MBB is live-out and doesn't define its own value.
493 LiveOutMap::iterator I = LiveOutCache.find(MBB);
494 if (I != LiveOutCache.end() && I->second.second != Node &&
495 I->second.first != IDomValue.first) {
497 I->second = IDomValue;
498 DEBUG(dbgs() << " - BB#" << MBB->getNumber()
499 << " idom valno #" << IDomValue.first->id
500 << " from BB#" << IDom->getBlock()->getNumber() << '\n');
504 DEBUG(dbgs() << " - made " << Changes << " changes.\n");
507 assert(IdxVNI && "Didn't find value for Idx");
511 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
514 MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator I) {
516 MachineInstr *CopyMI = 0;
518 LiveInterval *LI = Edit->get(RegIdx);
520 // Attempt cheap-as-a-copy rematerialization.
521 LiveRangeEdit::Remat RM(ParentVNI);
522 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
523 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
525 // Can't remat, just insert a copy from parent.
526 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
527 .addReg(Edit->getReg());
528 Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
531 // Define the value in Reg.
532 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
533 VNI->setCopy(CopyMI);
537 /// Create a new virtual register and live interval.
538 void SplitEditor::openIntv() {
539 assert(!OpenIdx && "Previous LI not closed before openIntv");
541 // Create the complement as index 0.
543 Edit->create(MRI, LIS, VRM);
545 // Create the open interval.
546 OpenIdx = Edit->size();
547 Edit->create(MRI, LIS, VRM);
550 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
551 assert(OpenIdx && "openIntv not called before enterIntvBefore");
552 DEBUG(dbgs() << " enterIntvBefore " << Idx);
553 Idx = Idx.getBaseIndex();
554 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
556 DEBUG(dbgs() << ": not live\n");
559 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
560 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
561 assert(MI && "enterIntvBefore called with invalid index");
563 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
567 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
568 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
569 SlotIndex End = LIS.getMBBEndIdx(&MBB);
570 SlotIndex Last = End.getPrevSlot();
571 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
572 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
574 DEBUG(dbgs() << ": not live\n");
577 DEBUG(dbgs() << ": valno " << ParentVNI->id);
578 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
579 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
580 RegAssign.insert(VNI->def, End, OpenIdx);
585 /// useIntv - indicate that all instructions in MBB should use OpenLI.
586 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
587 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
590 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
591 assert(OpenIdx && "openIntv not called before useIntv");
592 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
593 RegAssign.insert(Start, End, OpenIdx);
597 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
598 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
599 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
601 // The interval must be live beyond the instruction at Idx.
602 Idx = Idx.getBoundaryIndex();
603 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
605 DEBUG(dbgs() << ": not live\n");
606 return Idx.getNextSlot();
608 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
610 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
611 assert(MI && "No instruction at index");
612 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
613 llvm::next(MachineBasicBlock::iterator(MI)));
617 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
618 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
619 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
621 // The interval must be live into the instruction at Idx.
622 Idx = Idx.getBoundaryIndex();
623 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
625 DEBUG(dbgs() << ": not live\n");
626 return Idx.getNextSlot();
628 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
630 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
631 assert(MI && "No instruction at index");
632 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
636 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
637 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
638 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
639 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
641 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
643 DEBUG(dbgs() << ": not live\n");
647 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
648 MBB.SkipPHIsAndLabels(MBB.begin()));
649 RegAssign.insert(Start, VNI->def, OpenIdx);
654 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
655 assert(OpenIdx && "openIntv not called before overlapIntv");
656 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
657 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
658 "Parent changes value in extended range");
659 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
660 "Range cannot span basic blocks");
662 // The complement interval will be extended as needed by extendRange().
663 markComplexMapped(0, ParentVNI);
664 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
665 RegAssign.insert(Start, End, OpenIdx);
669 /// closeIntv - Indicate that we are done editing the currently open
670 /// LiveInterval, and ranges can be trimmed.
671 void SplitEditor::closeIntv() {
672 assert(OpenIdx && "openIntv not called before closeIntv");
676 /// transferSimpleValues - Transfer all simply defined values to the new live
678 /// Values that were rematerialized or that have multiple defs are left alone.
679 bool SplitEditor::transferSimpleValues() {
680 bool Skipped = false;
681 RegAssignMap::const_iterator AssignI = RegAssign.begin();
682 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
683 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
684 DEBUG(dbgs() << " blit " << *ParentI << ':');
685 VNInfo *ParentVNI = ParentI->valno;
686 // RegAssign has holes where RegIdx 0 should be used.
687 SlotIndex Start = ParentI->start;
688 AssignI.advanceTo(Start);
691 SlotIndex End = ParentI->end;
692 if (!AssignI.valid()) {
694 } else if (AssignI.start() <= Start) {
695 RegIdx = AssignI.value();
696 if (AssignI.stop() < End) {
697 End = AssignI.stop();
702 End = std::min(End, AssignI.start());
704 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
705 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
706 DEBUG(dbgs() << ':' << VNI->id);
707 Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
711 } while (Start != ParentI->end);
712 DEBUG(dbgs() << '\n');
717 void SplitEditor::extendPHIKillRanges() {
718 // Extend live ranges to be live-out for successor PHI values.
719 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
720 E = Edit->getParent().vni_end(); I != E; ++I) {
721 const VNInfo *PHIVNI = *I;
722 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
724 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
725 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
726 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
727 PE = MBB->pred_end(); PI != PE; ++PI) {
728 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
729 // The predecessor may not have a live-out value. That is OK, like an
730 // undef PHI operand.
731 if (Edit->getParent().liveAt(End)) {
732 assert(RegAssign.lookup(End) == RegIdx &&
733 "Different register assignment in phi predecessor");
734 extendRange(RegIdx, End);
740 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
741 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
742 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
743 RE = MRI.reg_end(); RI != RE;) {
744 MachineOperand &MO = RI.getOperand();
745 MachineInstr *MI = MO.getParent();
747 // LiveDebugVariables should have handled all DBG_VALUE instructions.
748 if (MI->isDebugValue()) {
749 DEBUG(dbgs() << "Zapping " << *MI);
754 // <undef> operands don't really read the register, so just assign them to
756 if (MO.isUse() && MO.isUndef()) {
757 MO.setReg(Edit->get(0)->reg);
761 SlotIndex Idx = LIS.getInstructionIndex(MI);
762 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
764 // Rewrite to the mapped register at Idx.
765 unsigned RegIdx = RegAssign.lookup(Idx);
766 MO.setReg(Edit->get(RegIdx)->reg);
767 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
768 << Idx << ':' << RegIdx << '\t' << *MI);
770 // Extend liveness to Idx.
772 extendRange(RegIdx, Idx);
776 /// rewriteSplit - Rewrite uses of Intvs[0] according to the ConEQ mapping.
777 void SplitEditor::rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
778 const ConnectedVNInfoEqClasses &ConEq) {
779 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Intvs[0]->reg),
780 RE = MRI.reg_end(); RI != RE;) {
781 MachineOperand &MO = RI.getOperand();
782 MachineInstr *MI = MO.getParent();
784 if (MO.isUse() && MO.isUndef())
786 // DBG_VALUE instructions should have been eliminated earlier.
787 SlotIndex Idx = LIS.getInstructionIndex(MI);
788 Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
789 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
791 const VNInfo *VNI = Intvs[0]->getVNInfoAt(Idx);
792 assert(VNI && "Interval not live at use.");
793 MO.setReg(Intvs[ConEq.getEqClass(VNI)]->reg);
794 DEBUG(dbgs() << VNI->id << '\t' << *MI);
798 void SplitEditor::finish() {
799 assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
802 // At this point, the live intervals in Edit contain VNInfos corresponding to
803 // the inserted copies.
805 // Add the original defs from the parent interval.
806 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
807 E = Edit->getParent().vni_end(); I != E; ++I) {
808 const VNInfo *ParentVNI = *I;
809 if (ParentVNI->isUnused())
811 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
812 defValue(RegIdx, ParentVNI, ParentVNI->def);
813 // Mark rematted values as complex everywhere to force liveness computation.
814 // The new live ranges may be truncated.
815 if (Edit->didRematerialize(ParentVNI))
816 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
817 markComplexMapped(i, ParentVNI);
821 // Every new interval must have a def by now, otherwise the split is bogus.
822 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
823 assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
826 // Transfer the simply mapped values, check if any are complex.
827 bool Complex = transferSimpleValues();
829 extendPHIKillRanges();
833 // Rewrite virtual registers, possibly extending ranges.
834 rewriteAssigned(Complex);
836 // FIXME: Delete defs that were rematted everywhere.
838 // Get rid of unused values and set phi-kill flags.
839 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
840 (*I)->RenumberValues(LIS);
842 // Now check if any registers were separated into multiple components.
843 ConnectedVNInfoEqClasses ConEQ(LIS);
844 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
845 // Don't use iterators, they are invalidated by create() below.
846 LiveInterval *li = Edit->get(i);
847 unsigned NumComp = ConEQ.Classify(li);
850 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
851 SmallVector<LiveInterval*, 8> dups;
853 for (unsigned i = 1; i != NumComp; ++i)
854 dups.push_back(&Edit->create(MRI, LIS, VRM));
855 rewriteComponents(dups, ConEQ);
856 ConEQ.Distribute(&dups[0]);
859 // Calculate spill weight and allocation hints for new intervals.
860 VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
861 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
862 LiveInterval &li = **I;
863 vrai.CalculateRegClass(li.reg);
864 vrai.CalculateWeightAndHint(li);
865 DEBUG(dbgs() << " new interval " << MRI.getRegClass(li.reg)->getName()
866 << ":" << li << '\n');
871 //===----------------------------------------------------------------------===//
872 // Single Block Splitting
873 //===----------------------------------------------------------------------===//
875 /// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
876 /// may be an advantage to split CurLI for the duration of the block.
877 bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
878 // If CurLI is local to one block, there is no point to splitting it.
879 if (LiveBlocks.size() <= 1)
881 // Add blocks with multiple uses.
882 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
883 const BlockInfo &BI = LiveBlocks[i];
886 unsigned Instrs = UsingBlocks.lookup(BI.MBB);
889 if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
891 Blocks.insert(BI.MBB);
893 return !Blocks.empty();
896 /// splitSingleBlocks - Split CurLI into a separate live interval inside each
897 /// basic block in Blocks.
898 void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
899 DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
901 for (unsigned i = 0, e = SA.LiveBlocks.size(); i != e; ++i) {
902 const SplitAnalysis::BlockInfo &BI = SA.LiveBlocks[i];
903 if (!BI.Uses || !Blocks.count(BI.MBB))
907 SlotIndex SegStart = enterIntvBefore(BI.FirstUse);
908 if (!BI.LiveOut || BI.LastUse < BI.LastSplitPoint) {
909 useIntv(SegStart, leaveIntvAfter(BI.LastUse));
911 // The last use is after the last valid split point.
912 SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
913 useIntv(SegStart, SegStop);
914 overlapIntv(SegStop, BI.LastUse);