1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
32 STATISTIC(NumFinished, "Number of splits finished");
33 STATISTIC(NumSimple, "Number of splits that were simple");
34 STATISTIC(NumCopies, "Number of copies inserted for splitting");
35 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
36 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
38 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
43 const LiveIntervals &lis,
44 const MachineLoopInfo &mli)
45 : MF(vrm.getMachineFunction()),
49 TII(*MF.getTarget().getInstrInfo()),
51 LastSplitPoint(MF.getNumBlockIDs()) {}
53 void SplitAnalysis::clear() {
56 ThroughBlocks.clear();
58 DidRepairRange = false;
61 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
62 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
63 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
64 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
66 // Compute split points on the first call. The pair is independent of the
67 // current live interval.
68 if (!LSP.first.isValid()) {
69 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
70 if (FirstTerm == MBB->end())
71 LSP.first = LIS.getMBBEndIdx(MBB);
73 LSP.first = LIS.getInstructionIndex(FirstTerm);
75 // If there is a landing pad successor, also find the call instruction.
78 // There may not be a call instruction (?) in which case we ignore LPad.
79 LSP.second = LSP.first;
80 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
83 if (I->getDesc().isCall()) {
84 LSP.second = LIS.getInstructionIndex(I);
90 // If CurLI is live into a landing pad successor, move the last split point
91 // back to the call that may throw.
92 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
98 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
99 void SplitAnalysis::analyzeUses() {
100 assert(UseSlots.empty() && "Call clear first");
102 // First get all the defs from the interval values. This provides the correct
103 // slots for early clobbers.
104 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
105 E = CurLI->vni_end(); I != E; ++I)
106 if (!(*I)->isPHIDef() && !(*I)->isUnused())
107 UseSlots.push_back((*I)->def);
109 // Get use slots form the use-def chain.
110 const MachineRegisterInfo &MRI = MF.getRegInfo();
111 for (MachineRegisterInfo::use_nodbg_iterator
112 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
114 if (!I.getOperand().isUndef())
115 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
117 array_pod_sort(UseSlots.begin(), UseSlots.end());
119 // Remove duplicates, keeping the smaller slot for each instruction.
120 // That is what we want for early clobbers.
121 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
122 SlotIndex::isSameInstr),
125 // Compute per-live block info.
126 if (!calcLiveBlockInfo()) {
127 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
128 // I am looking at you, RegisterCoalescer!
129 DidRepairRange = true;
131 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
132 const_cast<LiveIntervals&>(LIS)
133 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
135 ThroughBlocks.clear();
136 bool fixed = calcLiveBlockInfo();
138 assert(fixed && "Couldn't fix broken live interval");
141 DEBUG(dbgs() << "Analyze counted "
142 << UseSlots.size() << " instrs in "
143 << UseBlocks.size() << " blocks, through "
144 << NumThroughBlocks << " blocks.\n");
147 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
148 /// where CurLI is live.
149 bool SplitAnalysis::calcLiveBlockInfo() {
150 ThroughBlocks.resize(MF.getNumBlockIDs());
151 NumThroughBlocks = NumGapBlocks = 0;
155 LiveInterval::const_iterator LVI = CurLI->begin();
156 LiveInterval::const_iterator LVE = CurLI->end();
158 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
159 UseI = UseSlots.begin();
160 UseE = UseSlots.end();
162 // Loop over basic blocks where CurLI is live.
163 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
167 SlotIndex Start, Stop;
168 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
170 // If the block contains no uses, the range must be live through. At one
171 // point, RegisterCoalescer could create dangling ranges that ended
173 if (UseI == UseE || *UseI >= Stop) {
175 ThroughBlocks.set(BI.MBB->getNumber());
176 // The range shouldn't end mid-block if there are no uses. This shouldn't
181 // This block has uses. Find the first and last uses in the block.
182 BI.FirstInstr = *UseI;
183 assert(BI.FirstInstr >= Start);
185 while (UseI != UseE && *UseI < Stop);
186 BI.LastInstr = UseI[-1];
187 assert(BI.LastInstr < Stop);
189 // LVI is the first live segment overlapping MBB.
190 BI.LiveIn = LVI->start <= Start;
192 // When not live in, the first use should be a def.
194 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
195 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
196 BI.FirstDef = BI.FirstInstr;
199 // Look for gaps in the live range.
201 while (LVI->end < Stop) {
202 SlotIndex LastStop = LVI->end;
203 if (++LVI == LVE || LVI->start >= Stop) {
205 BI.LastInstr = LastStop;
209 if (LastStop < LVI->start) {
210 // There is a gap in the live range. Create duplicate entries for the
211 // live-in snippet and the live-out snippet.
214 // Push the Live-in part.
216 UseBlocks.push_back(BI);
217 UseBlocks.back().LastInstr = LastStop;
219 // Set up BI for the live-out part.
222 BI.FirstInstr = BI.FirstDef = LVI->start;
225 // A LiveRange that starts in the middle of the block must be a def.
226 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
228 BI.FirstDef = LVI->start;
231 UseBlocks.push_back(BI);
233 // LVI is now at LVE or LVI->end >= Stop.
238 // Live segment ends exactly at Stop. Move to the next segment.
239 if (LVI->end == Stop && ++LVI == LVE)
242 // Pick the next basic block.
243 if (LVI->start < Stop)
246 MFI = LIS.getMBBFromIndex(LVI->start);
249 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
253 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
256 LiveInterval *li = const_cast<LiveInterval*>(cli);
257 LiveInterval::iterator LVI = li->begin();
258 LiveInterval::iterator LVE = li->end();
261 // Loop over basic blocks where li is live.
262 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
263 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
266 LVI = li->advanceTo(LVI, Stop);
271 Stop = LIS.getMBBEndIdx(MFI);
272 } while (Stop <= LVI->start);
276 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
277 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
278 const LiveInterval &Orig = LIS.getInterval(OrigReg);
279 assert(!Orig.empty() && "Splitting empty interval?");
280 LiveInterval::const_iterator I = Orig.find(Idx);
282 // Range containing Idx should begin at Idx.
283 if (I != Orig.end() && I->start <= Idx)
284 return I->start == Idx;
286 // Range does not contain Idx, previous must end at Idx.
287 return I != Orig.begin() && (--I)->end == Idx;
290 void SplitAnalysis::analyze(const LiveInterval *li) {
297 //===----------------------------------------------------------------------===//
299 //===----------------------------------------------------------------------===//
301 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
302 SplitEditor::SplitEditor(SplitAnalysis &sa,
305 MachineDominatorTree &mdt)
306 : SA(sa), LIS(lis), VRM(vrm),
307 MRI(vrm.getMachineFunction().getRegInfo()),
309 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
310 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
313 SpillMode(SM_Partition),
317 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
324 // Reset the LiveRangeCalc instances needed for this spill mode.
325 LRCalc[0].reset(&VRM.getMachineFunction());
327 LRCalc[1].reset(&VRM.getMachineFunction());
329 // We don't need an AliasAnalysis since we will only be performing
330 // cheap-as-a-copy remats anyway.
331 Edit->anyRematerializable(LIS, TII, 0);
334 void SplitEditor::dump() const {
335 if (RegAssign.empty()) {
336 dbgs() << " empty\n";
340 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
341 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
345 VNInfo *SplitEditor::defValue(unsigned RegIdx,
346 const VNInfo *ParentVNI,
348 assert(ParentVNI && "Mapping NULL value");
349 assert(Idx.isValid() && "Invalid SlotIndex");
350 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
351 LiveInterval *LI = Edit->get(RegIdx);
353 // Create a new value.
354 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
356 // Use insert for lookup, so we can add missing values with a second lookup.
357 std::pair<ValueMap::iterator, bool> InsP =
358 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
359 ValueForcePair(VNI, false)));
361 // This was the first time (RegIdx, ParentVNI) was mapped.
362 // Keep it as a simple def without any liveness.
366 // If the previous value was a simple mapping, add liveness for it now.
367 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
368 SlotIndex Def = OldVNI->def;
369 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
370 // No longer a simple mapping. Switch to a complex, non-forced mapping.
371 InsP.first->second = ValueForcePair();
374 // This is a complex mapping, add liveness for VNI
375 SlotIndex Def = VNI->def;
376 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
381 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
382 assert(ParentVNI && "Mapping NULL value");
383 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
384 VNInfo *VNI = VFP.getPointer();
386 // ParentVNI was either unmapped or already complex mapped. Either way, just
387 // set the force bit.
393 // This was previously a single mapping. Make sure the old def is represented
394 // by a trivial live range.
395 SlotIndex Def = VNI->def;
396 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
397 // Mark as complex mapped, forced.
398 VFP = ValueForcePair(0, true);
401 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
404 MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator I) {
406 MachineInstr *CopyMI = 0;
408 LiveInterval *LI = Edit->get(RegIdx);
410 // We may be trying to avoid interference that ends at a deleted instruction,
411 // so always begin RegIdx 0 early and all others late.
412 bool Late = RegIdx != 0;
414 // Attempt cheap-as-a-copy rematerialization.
415 LiveRangeEdit::Remat RM(ParentVNI);
416 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
417 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
420 // Can't remat, just insert a copy from parent.
421 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
422 .addReg(Edit->getReg());
423 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
428 // Define the value in Reg.
429 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
430 VNI->setCopy(CopyMI);
434 /// Create a new virtual register and live interval.
435 unsigned SplitEditor::openIntv() {
436 // Create the complement as index 0.
438 Edit->create(LIS, VRM);
440 // Create the open interval.
441 OpenIdx = Edit->size();
442 Edit->create(LIS, VRM);
446 void SplitEditor::selectIntv(unsigned Idx) {
447 assert(Idx != 0 && "Cannot select the complement interval");
448 assert(Idx < Edit->size() && "Can only select previously opened interval");
449 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
453 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
454 assert(OpenIdx && "openIntv not called before enterIntvBefore");
455 DEBUG(dbgs() << " enterIntvBefore " << Idx);
456 Idx = Idx.getBaseIndex();
457 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
459 DEBUG(dbgs() << ": not live\n");
462 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
463 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
464 assert(MI && "enterIntvBefore called with invalid index");
466 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
470 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
471 assert(OpenIdx && "openIntv not called before enterIntvAfter");
472 DEBUG(dbgs() << " enterIntvAfter " << Idx);
473 Idx = Idx.getBoundaryIndex();
474 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
476 DEBUG(dbgs() << ": not live\n");
479 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
480 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
481 assert(MI && "enterIntvAfter called with invalid index");
483 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
484 llvm::next(MachineBasicBlock::iterator(MI)));
488 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
489 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
490 SlotIndex End = LIS.getMBBEndIdx(&MBB);
491 SlotIndex Last = End.getPrevSlot();
492 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
493 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
495 DEBUG(dbgs() << ": not live\n");
498 DEBUG(dbgs() << ": valno " << ParentVNI->id);
499 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
500 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
501 RegAssign.insert(VNI->def, End, OpenIdx);
506 /// useIntv - indicate that all instructions in MBB should use OpenLI.
507 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
508 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
511 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
512 assert(OpenIdx && "openIntv not called before useIntv");
513 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
514 RegAssign.insert(Start, End, OpenIdx);
518 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
519 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
520 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
522 // The interval must be live beyond the instruction at Idx.
523 Idx = Idx.getBoundaryIndex();
524 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
526 DEBUG(dbgs() << ": not live\n");
527 return Idx.getNextSlot();
529 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
531 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
532 assert(MI && "No instruction at index");
533 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
534 llvm::next(MachineBasicBlock::iterator(MI)));
538 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
539 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
540 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
542 // The interval must be live into the instruction at Idx.
543 Idx = Idx.getBaseIndex();
544 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
546 DEBUG(dbgs() << ": not live\n");
547 return Idx.getNextSlot();
549 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
551 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
552 assert(MI && "No instruction at index");
553 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
557 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
558 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
559 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
560 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
562 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
564 DEBUG(dbgs() << ": not live\n");
568 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
569 MBB.SkipPHIsAndLabels(MBB.begin()));
570 RegAssign.insert(Start, VNI->def, OpenIdx);
575 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
576 assert(OpenIdx && "openIntv not called before overlapIntv");
577 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
578 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
579 "Parent changes value in extended range");
580 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
581 "Range cannot span basic blocks");
583 // The complement interval will be extended as needed by LRCalc.extend().
585 forceRecompute(0, ParentVNI);
586 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
587 RegAssign.insert(Start, End, OpenIdx);
591 //===----------------------------------------------------------------------===//
593 //===----------------------------------------------------------------------===//
595 void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
596 LiveInterval *LI = Edit->get(0);
597 DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
598 RegAssignMap::iterator AssignI;
599 AssignI.setMap(RegAssign);
601 for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
602 VNInfo *VNI = Copies[i];
603 SlotIndex Def = VNI->def;
604 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
605 assert(MI && "No instruction for back-copy");
607 MachineBasicBlock *MBB = MI->getParent();
608 MachineBasicBlock::iterator MBBI(MI);
610 do AtBegin = MBBI == MBB->begin();
611 while (!AtBegin && (--MBBI)->isDebugValue());
613 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
614 LI->removeValNo(VNI);
615 LIS.RemoveMachineInstrFromMaps(MI);
616 MI->eraseFromParent();
618 // Adjust RegAssign if a register assignment is killed at VNI->def. We
619 // want to avoid calculating the live range of the source register if
621 AssignI.find(VNI->def.getPrevSlot());
622 if (!AssignI.valid() || AssignI.start() >= Def)
624 // If MI doesn't kill the assigned register, just leave it.
625 if (AssignI.stop() != Def)
627 unsigned RegIdx = AssignI.value();
628 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
629 DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
630 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
632 SlotIndex Kill = LIS.getInstructionIndex(MBBI).getDefIndex();
633 DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
634 AssignI.setStop(Kill);
640 SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
641 MachineBasicBlock *DefMBB) {
644 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
646 const MachineLoopInfo &Loops = SA.Loops;
647 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
648 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
650 // Best candidate so far.
651 MachineBasicBlock *BestMBB = MBB;
652 unsigned BestDepth = UINT_MAX;
655 const MachineLoop *Loop = Loops.getLoopFor(MBB);
657 // MBB isn't in a loop, it doesn't get any better. All dominators have a
658 // higher frequency by definition.
660 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
661 << MBB->getNumber() << " at depth 0\n");
665 // We'll never be able to exit the DefLoop.
666 if (Loop == DefLoop) {
667 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
668 << MBB->getNumber() << " in the same loop\n");
672 // Least busy dominator seen so far.
673 unsigned Depth = Loop->getLoopDepth();
674 if (Depth < BestDepth) {
677 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
678 << MBB->getNumber() << " at depth " << Depth << '\n');
681 // Leave loop by going to the immediate dominator of the loop header.
682 // This is a bigger stride than simply walking up the dominator tree.
683 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
685 // Too far up the dominator tree?
686 if (!IDom || !MDT.dominates(DefDomNode, IDom))
689 MBB = IDom->getBlock();
693 void SplitEditor::hoistCopiesForSize() {
694 // Get the complement interval, always RegIdx 0.
695 LiveInterval *LI = Edit->get(0);
696 LiveInterval *Parent = &Edit->getParent();
698 // Track the nearest common dominator for all back-copies for each ParentVNI,
699 // indexed by ParentVNI->id.
700 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
701 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
703 // Find the nearest common dominator for parent values with multiple
704 // back-copies. If a single back-copy dominates, put it in DomPair.second.
705 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
708 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
709 assert(ParentVNI && "Parent not live at complement def");
711 // Don't hoist remats. The complement is probably going to disappear
712 // completely anyway.
713 if (Edit->didRematerialize(ParentVNI))
716 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
717 DomPair &Dom = NearestDom[ParentVNI->id];
719 // Keep directly defined parent values. This is either a PHI or an
720 // instruction in the complement range. All other copies of ParentVNI
721 // should be eliminated.
722 if (VNI->def == ParentVNI->def) {
723 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
724 Dom = DomPair(ValMBB, VNI->def);
727 // Skip the singly mapped values. There is nothing to gain from hoisting a
729 if (Values.lookup(std::make_pair(0, ParentVNI->id)).getPointer()) {
730 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
735 // First time we see ParentVNI. VNI dominates itself.
736 Dom = DomPair(ValMBB, VNI->def);
737 } else if (Dom.first == ValMBB) {
738 // Two defs in the same block. Pick the earlier def.
739 if (!Dom.second.isValid() || VNI->def < Dom.second)
740 Dom.second = VNI->def;
742 // Different basic blocks. Check if one dominates.
743 MachineBasicBlock *Near =
744 MDT.findNearestCommonDominator(Dom.first, ValMBB);
746 // Def ValMBB dominates.
747 Dom = DomPair(ValMBB, VNI->def);
748 else if (Near != Dom.first)
749 // None dominate. Hoist to common dominator, need new def.
750 Dom = DomPair(Near, SlotIndex());
753 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
754 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
755 << " hoist to BB#" << Dom.first->getNumber() << ' '
756 << Dom.second << '\n');
759 // Insert the hoisted copies.
760 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
761 DomPair &Dom = NearestDom[i];
762 if (!Dom.first || Dom.second.isValid())
764 // This value needs a hoisted copy inserted at the end of Dom.first.
765 VNInfo *ParentVNI = Parent->getValNumInfo(i);
766 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
767 // Get a less loopy dominator than Dom.first.
768 Dom.first = findShallowDominator(Dom.first, DefMBB);
769 SlotIndex Last = LIS.getMBBEndIdx(Dom.first).getPrevSlot();
771 defFromParent(0, ParentVNI, Last, *Dom.first,
772 LIS.getLastSplitPoint(Edit->getParent(), Dom.first))->def;
775 // Remove redundant back-copies that are now known to be dominated by another
776 // def with the same value.
777 SmallVector<VNInfo*, 8> BackCopies;
778 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
781 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
782 const DomPair &Dom = NearestDom[ParentVNI->id];
783 if (!Dom.first || Dom.second == VNI->def)
785 BackCopies.push_back(VNI);
786 forceRecompute(0, ParentVNI);
788 removeBackCopies(BackCopies);
792 /// transferValues - Transfer all possible values to the new live ranges.
793 /// Values that were rematerialized are left alone, they need LRCalc.extend().
794 bool SplitEditor::transferValues() {
795 bool Skipped = false;
796 RegAssignMap::const_iterator AssignI = RegAssign.begin();
797 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
798 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
799 DEBUG(dbgs() << " blit " << *ParentI << ':');
800 VNInfo *ParentVNI = ParentI->valno;
801 // RegAssign has holes where RegIdx 0 should be used.
802 SlotIndex Start = ParentI->start;
803 AssignI.advanceTo(Start);
806 SlotIndex End = ParentI->end;
807 if (!AssignI.valid()) {
809 } else if (AssignI.start() <= Start) {
810 RegIdx = AssignI.value();
811 if (AssignI.stop() < End) {
812 End = AssignI.stop();
817 End = std::min(End, AssignI.start());
820 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
821 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
822 LiveInterval *LI = Edit->get(RegIdx);
824 // Check for a simply defined value that can be blitted directly.
825 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id));
826 if (VNInfo *VNI = VFP.getPointer()) {
827 DEBUG(dbgs() << ':' << VNI->id);
828 LI->addRange(LiveRange(Start, End, VNI));
833 // Skip values with forced recomputation.
835 DEBUG(dbgs() << "(recalc)");
841 LiveRangeCalc &LRC = getLRCalc(RegIdx);
843 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
844 // so the live range is accurate. Add live-in blocks in [Start;End) to the
846 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
847 SlotIndex BlockStart, BlockEnd;
848 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
850 // The first block may be live-in, or it may have its own def.
851 if (Start != BlockStart) {
852 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
853 assert(VNI && "Missing def for complex mapped value");
854 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
855 // MBB has its own def. Is it also live-out?
857 LRC.setLiveOutValue(MBB, VNI);
859 // Skip to the next block for live-in.
861 BlockStart = BlockEnd;
864 // Handle the live-in blocks covered by [Start;End).
865 assert(Start <= BlockStart && "Expected live-in block");
866 while (BlockStart < End) {
867 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
868 BlockEnd = LIS.getMBBEndIdx(MBB);
869 if (BlockStart == ParentVNI->def) {
870 // This block has the def of a parent PHI, so it isn't live-in.
871 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
872 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
873 assert(VNI && "Missing def for complex mapped parent PHI");
875 LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
877 // This block needs a live-in value. The last block covered may not
880 LRC.addLiveInBlock(LI, MDT[MBB], End);
882 // Live-through, and we don't know the value.
883 LRC.addLiveInBlock(LI, MDT[MBB]);
884 LRC.setLiveOutValue(MBB, 0);
887 BlockStart = BlockEnd;
891 } while (Start != ParentI->end);
892 DEBUG(dbgs() << '\n');
895 LRCalc[0].calculateValues(LIS.getSlotIndexes(), &MDT,
896 &LIS.getVNInfoAllocator());
898 LRCalc[1].calculateValues(LIS.getSlotIndexes(), &MDT,
899 &LIS.getVNInfoAllocator());
904 void SplitEditor::extendPHIKillRanges() {
905 // Extend live ranges to be live-out for successor PHI values.
906 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
907 E = Edit->getParent().vni_end(); I != E; ++I) {
908 const VNInfo *PHIVNI = *I;
909 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
911 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
912 LiveInterval *LI = Edit->get(RegIdx);
913 LiveRangeCalc &LRC = getLRCalc(RegIdx);
914 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
915 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
916 PE = MBB->pred_end(); PI != PE; ++PI) {
917 SlotIndex End = LIS.getMBBEndIdx(*PI);
918 SlotIndex LastUse = End.getPrevSlot();
919 // The predecessor may not have a live-out value. That is OK, like an
920 // undef PHI operand.
921 if (Edit->getParent().liveAt(LastUse)) {
922 assert(RegAssign.lookup(LastUse) == RegIdx &&
923 "Different register assignment in phi predecessor");
925 LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
931 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
932 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
933 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
934 RE = MRI.reg_end(); RI != RE;) {
935 MachineOperand &MO = RI.getOperand();
936 MachineInstr *MI = MO.getParent();
938 // LiveDebugVariables should have handled all DBG_VALUE instructions.
939 if (MI->isDebugValue()) {
940 DEBUG(dbgs() << "Zapping " << *MI);
945 // <undef> operands don't really read the register, so it doesn't matter
946 // which register we choose. When the use operand is tied to a def, we must
947 // use the same register as the def, so just do that always.
948 SlotIndex Idx = LIS.getInstructionIndex(MI);
949 if (MO.isDef() || MO.isUndef())
950 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
952 // Rewrite to the mapped register at Idx.
953 unsigned RegIdx = RegAssign.lookup(Idx);
954 LiveInterval *LI = Edit->get(RegIdx);
956 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
957 << Idx << ':' << RegIdx << '\t' << *MI);
959 // Extend liveness to Idx if the instruction reads reg.
960 if (!ExtendRanges || MO.isUndef())
963 // Skip instructions that don't read Reg.
965 if (!MO.getSubReg() && !MO.isEarlyClobber())
967 // We may wan't to extend a live range for a partial redef, or for a use
968 // tied to an early clobber.
969 Idx = Idx.getPrevSlot();
970 if (!Edit->getParent().liveAt(Idx))
973 Idx = Idx.getUseIndex();
975 getLRCalc(RegIdx).extend(LI, Idx.getNextSlot(), LIS.getSlotIndexes(),
976 &MDT, &LIS.getVNInfoAllocator());
980 void SplitEditor::deleteRematVictims() {
981 SmallVector<MachineInstr*, 8> Dead;
982 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
983 LiveInterval *LI = *I;
984 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
986 // Dead defs end at the store slot.
987 if (LII->end != LII->valno->def.getNextSlot())
989 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
990 assert(MI && "Missing instruction for dead def");
991 MI->addRegisterDead(LI->reg, &TRI);
993 if (!MI->allDefsAreDead())
996 DEBUG(dbgs() << "All defs dead: " << *MI);
1004 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
1007 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1010 // At this point, the live intervals in Edit contain VNInfos corresponding to
1011 // the inserted copies.
1013 // Add the original defs from the parent interval.
1014 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
1015 E = Edit->getParent().vni_end(); I != E; ++I) {
1016 const VNInfo *ParentVNI = *I;
1017 if (ParentVNI->isUnused())
1019 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1020 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
1021 VNI->setIsPHIDef(ParentVNI->isPHIDef());
1022 VNI->setCopy(ParentVNI->getCopy());
1024 // Force rematted values to be recomputed everywhere.
1025 // The new live ranges may be truncated.
1026 if (Edit->didRematerialize(ParentVNI))
1027 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1028 forceRecompute(i, ParentVNI);
1031 // Hoist back-copies to the complement interval when in spill mode.
1032 switch (SpillMode) {
1034 // Leave all back-copies as is.
1037 hoistCopiesForSize();
1040 llvm_unreachable("Spill mode 'speed' not implemented yet");
1044 // Transfer the simply mapped values, check if any are skipped.
1045 bool Skipped = transferValues();
1047 extendPHIKillRanges();
1051 // Rewrite virtual registers, possibly extending ranges.
1052 rewriteAssigned(Skipped);
1054 // Delete defs that were rematted everywhere.
1056 deleteRematVictims();
1058 // Get rid of unused values and set phi-kill flags.
1059 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
1060 (*I)->RenumberValues(LIS);
1062 // Provide a reverse mapping from original indices to Edit ranges.
1065 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1066 LRMap->push_back(i);
1069 // Now check if any registers were separated into multiple components.
1070 ConnectedVNInfoEqClasses ConEQ(LIS);
1071 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1072 // Don't use iterators, they are invalidated by create() below.
1073 LiveInterval *li = Edit->get(i);
1074 unsigned NumComp = ConEQ.Classify(li);
1077 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
1078 SmallVector<LiveInterval*, 8> dups;
1080 for (unsigned j = 1; j != NumComp; ++j)
1081 dups.push_back(&Edit->create(LIS, VRM));
1082 ConEQ.Distribute(&dups[0], MRI);
1083 // The new intervals all map back to i.
1085 LRMap->resize(Edit->size(), i);
1088 // Calculate spill weight and allocation hints for new intervals.
1089 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
1091 assert(!LRMap || LRMap->size() == Edit->size());
1095 //===----------------------------------------------------------------------===//
1096 // Single Block Splitting
1097 //===----------------------------------------------------------------------===//
1099 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1100 bool SingleInstrs) const {
1101 // Always split for multiple instructions.
1102 if (!BI.isOneInstr())
1104 // Don't split for single instructions unless explicitly requested.
1107 // Splitting a live-through range always makes progress.
1108 if (BI.LiveIn && BI.LiveOut)
1110 // No point in isolating a copy. It has no register class constraints.
1111 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
1113 // Finally, don't isolate an end point that was created by earlier splits.
1114 return isOriginalEndpoint(BI.FirstInstr);
1117 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1119 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1120 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
1122 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1123 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
1125 // The last use is after the last valid split point.
1126 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1127 useIntv(SegStart, SegStop);
1128 overlapIntv(SegStop, BI.LastInstr);
1133 //===----------------------------------------------------------------------===//
1134 // Global Live Range Splitting Support
1135 //===----------------------------------------------------------------------===//
1137 // These methods support a method of global live range splitting that uses a
1138 // global algorithm to decide intervals for CFG edges. They will insert split
1139 // points and color intervals in basic blocks while avoiding interference.
1141 // Note that splitSingleBlock is also useful for blocks where both CFG edges
1142 // are on the stack.
1144 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1145 unsigned IntvIn, SlotIndex LeaveBefore,
1146 unsigned IntvOut, SlotIndex EnterAfter){
1147 SlotIndex Start, Stop;
1148 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1150 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1151 << ") intf " << LeaveBefore << '-' << EnterAfter
1152 << ", live-through " << IntvIn << " -> " << IntvOut);
1154 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1156 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1157 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1158 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1160 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1163 DEBUG(dbgs() << ", spill on entry.\n");
1165 // <<<<<<<<< Possible LeaveBefore interference.
1166 // |-----------| Live through.
1167 // -____________ Spill on entry.
1170 SlotIndex Idx = leaveIntvAtTop(*MBB);
1171 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1177 DEBUG(dbgs() << ", reload on exit.\n");
1179 // >>>>>>> Possible EnterAfter interference.
1180 // |-----------| Live through.
1181 // ___________-- Reload on exit.
1183 selectIntv(IntvOut);
1184 SlotIndex Idx = enterIntvAtEnd(*MBB);
1185 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1190 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1191 DEBUG(dbgs() << ", straight through.\n");
1193 // |-----------| Live through.
1194 // ------------- Straight through, same intv, no interference.
1196 selectIntv(IntvOut);
1197 useIntv(Start, Stop);
1201 // We cannot legally insert splits after LSP.
1202 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1203 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1205 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1206 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1207 DEBUG(dbgs() << ", switch avoiding interference.\n");
1209 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1210 // |-----------| Live through.
1211 // ------======= Switch intervals between interference.
1213 selectIntv(IntvOut);
1215 if (LeaveBefore && LeaveBefore < LSP) {
1216 Idx = enterIntvBefore(LeaveBefore);
1219 Idx = enterIntvAtEnd(*MBB);
1222 useIntv(Start, Idx);
1223 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1224 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1228 DEBUG(dbgs() << ", create local intv for interference.\n");
1230 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1231 // |-----------| Live through.
1232 // ==---------== Switch intervals before/after interference.
1234 assert(LeaveBefore <= EnterAfter && "Missed case");
1236 selectIntv(IntvOut);
1237 SlotIndex Idx = enterIntvAfter(EnterAfter);
1239 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1242 Idx = leaveIntvBefore(LeaveBefore);
1243 useIntv(Start, Idx);
1244 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1248 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1249 unsigned IntvIn, SlotIndex LeaveBefore) {
1250 SlotIndex Start, Stop;
1251 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1253 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1254 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1255 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1256 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1258 assert(IntvIn && "Must have register in");
1259 assert(BI.LiveIn && "Must be live-in");
1260 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1262 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1263 DEBUG(dbgs() << " before interference.\n");
1265 // <<< Interference after kill.
1266 // |---o---x | Killed in block.
1267 // ========= Use IntvIn everywhere.
1270 useIntv(Start, BI.LastInstr);
1274 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1276 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1278 // <<< Possible interference after last use.
1279 // |---o---o---| Live-out on stack.
1280 // =========____ Leave IntvIn after last use.
1282 // < Interference after last use.
1283 // |---o---o--o| Live-out on stack, late last use.
1284 // ============ Copy to stack after LSP, overlap IntvIn.
1285 // \_____ Stack interval is live-out.
1287 if (BI.LastInstr < LSP) {
1288 DEBUG(dbgs() << ", spill after last use before interference.\n");
1290 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1291 useIntv(Start, Idx);
1292 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1294 DEBUG(dbgs() << ", spill before last split point.\n");
1296 SlotIndex Idx = leaveIntvBefore(LSP);
1297 overlapIntv(Idx, BI.LastInstr);
1298 useIntv(Start, Idx);
1299 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1304 // The interference is overlapping somewhere we wanted to use IntvIn. That
1305 // means we need to create a local interval that can be allocated a
1306 // different register.
1307 unsigned LocalIntv = openIntv();
1309 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1311 if (!BI.LiveOut || BI.LastInstr < LSP) {
1313 // <<<<<<< Interference overlapping uses.
1314 // |---o---o---| Live-out on stack.
1315 // =====----____ Leave IntvIn before interference, then spill.
1317 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1318 SlotIndex From = enterIntvBefore(LeaveBefore);
1321 useIntv(Start, From);
1322 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1326 // <<<<<<< Interference overlapping uses.
1327 // |---o---o--o| Live-out on stack, late last use.
1328 // =====------- Copy to stack before LSP, overlap LocalIntv.
1329 // \_____ Stack interval is live-out.
1331 SlotIndex To = leaveIntvBefore(LSP);
1332 overlapIntv(To, BI.LastInstr);
1333 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1336 useIntv(Start, From);
1337 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1340 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1341 unsigned IntvOut, SlotIndex EnterAfter) {
1342 SlotIndex Start, Stop;
1343 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1345 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1346 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1347 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1348 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1350 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1352 assert(IntvOut && "Must have register out");
1353 assert(BI.LiveOut && "Must be live-out");
1354 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1356 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1357 DEBUG(dbgs() << " after interference.\n");
1359 // >>>> Interference before def.
1360 // | o---o---| Defined in block.
1361 // ========= Use IntvOut everywhere.
1363 selectIntv(IntvOut);
1364 useIntv(BI.FirstInstr, Stop);
1368 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1369 DEBUG(dbgs() << ", reload after interference.\n");
1371 // >>>> Interference before def.
1372 // |---o---o---| Live-through, stack-in.
1373 // ____========= Enter IntvOut before first use.
1375 selectIntv(IntvOut);
1376 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1378 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1382 // The interference is overlapping somewhere we wanted to use IntvOut. That
1383 // means we need to create a local interval that can be allocated a
1384 // different register.
1385 DEBUG(dbgs() << ", interference overlaps uses.\n");
1387 // >>>>>>> Interference overlapping uses.
1388 // |---o---o---| Live-through, stack-in.
1389 // ____---====== Create local interval for interference range.
1391 selectIntv(IntvOut);
1392 SlotIndex Idx = enterIntvAfter(EnterAfter);
1394 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1397 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));