1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 STATISTIC(NumFinished, "Number of splits finished");
32 STATISTIC(NumSimple, "Number of splits that were simple");
33 STATISTIC(NumCopies, "Number of copies inserted for splitting");
34 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
35 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42 const LiveIntervals &lis,
43 const MachineLoopInfo &mli)
44 : MF(vrm.getMachineFunction()),
48 TII(*MF.getTarget().getInstrInfo()),
50 LastSplitPoint(MF.getNumBlockIDs()) {}
52 void SplitAnalysis::clear() {
55 ThroughBlocks.clear();
57 DidRepairRange = false;
60 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 // Compute split points on the first call. The pair is independent of the
66 // current live interval.
67 if (!LSP.first.isValid()) {
68 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getMBBEndIdx(MBB);
72 LSP.first = LIS.getInstructionIndex(FirstTerm);
74 // If there is a landing pad successor, also find the call instruction.
77 // There may not be a call instruction (?) in which case we ignore LPad.
78 LSP.second = LSP.first;
79 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
82 if (I->getDesc().isCall()) {
83 LSP.second = LIS.getInstructionIndex(I);
89 // If CurLI is live into a landing pad successor, move the last split point
90 // back to the call that may throw.
91 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
97 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98 void SplitAnalysis::analyzeUses() {
99 assert(UseSlots.empty() && "Call clear first");
101 // First get all the defs from the interval values. This provides the correct
102 // slots for early clobbers.
103 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104 E = CurLI->vni_end(); I != E; ++I)
105 if (!(*I)->isPHIDef() && !(*I)->isUnused())
106 UseSlots.push_back((*I)->def);
108 // Get use slots form the use-def chain.
109 const MachineRegisterInfo &MRI = MF.getRegInfo();
110 for (MachineRegisterInfo::use_nodbg_iterator
111 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
113 if (!I.getOperand().isUndef())
114 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
116 array_pod_sort(UseSlots.begin(), UseSlots.end());
118 // Remove duplicates, keeping the smaller slot for each instruction.
119 // That is what we want for early clobbers.
120 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121 SlotIndex::isSameInstr),
124 // Compute per-live block info.
125 if (!calcLiveBlockInfo()) {
126 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127 // I am looking at you, RegisterCoalescer!
128 DidRepairRange = true;
130 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131 const_cast<LiveIntervals&>(LIS)
132 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
134 ThroughBlocks.clear();
135 bool fixed = calcLiveBlockInfo();
137 assert(fixed && "Couldn't fix broken live interval");
140 DEBUG(dbgs() << "Analyze counted "
141 << UseSlots.size() << " instrs in "
142 << UseBlocks.size() << " blocks, through "
143 << NumThroughBlocks << " blocks.\n");
146 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147 /// where CurLI is live.
148 bool SplitAnalysis::calcLiveBlockInfo() {
149 ThroughBlocks.resize(MF.getNumBlockIDs());
150 NumThroughBlocks = NumGapBlocks = 0;
154 LiveInterval::const_iterator LVI = CurLI->begin();
155 LiveInterval::const_iterator LVE = CurLI->end();
157 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158 UseI = UseSlots.begin();
159 UseE = UseSlots.end();
161 // Loop over basic blocks where CurLI is live.
162 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
166 SlotIndex Start, Stop;
167 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
169 // If the block contains no uses, the range must be live through. At one
170 // point, RegisterCoalescer could create dangling ranges that ended
172 if (UseI == UseE || *UseI >= Stop) {
174 ThroughBlocks.set(BI.MBB->getNumber());
175 // The range shouldn't end mid-block if there are no uses. This shouldn't
180 // This block has uses. Find the first and last uses in the block.
181 BI.FirstInstr = *UseI;
182 assert(BI.FirstInstr >= Start);
184 while (UseI != UseE && *UseI < Stop);
185 BI.LastInstr = UseI[-1];
186 assert(BI.LastInstr < Stop);
188 // LVI is the first live segment overlapping MBB.
189 BI.LiveIn = LVI->start <= Start;
191 // When not live in, the first use should be a def.
193 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
194 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
195 BI.FirstDef = BI.FirstInstr;
198 // Look for gaps in the live range.
200 while (LVI->end < Stop) {
201 SlotIndex LastStop = LVI->end;
202 if (++LVI == LVE || LVI->start >= Stop) {
204 BI.LastInstr = LastStop;
208 if (LastStop < LVI->start) {
209 // There is a gap in the live range. Create duplicate entries for the
210 // live-in snippet and the live-out snippet.
213 // Push the Live-in part.
215 UseBlocks.push_back(BI);
216 UseBlocks.back().LastInstr = LastStop;
218 // Set up BI for the live-out part.
221 BI.FirstInstr = BI.FirstDef = LVI->start;
224 // A LiveRange that starts in the middle of the block must be a def.
225 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
227 BI.FirstDef = LVI->start;
230 UseBlocks.push_back(BI);
232 // LVI is now at LVE or LVI->end >= Stop.
237 // Live segment ends exactly at Stop. Move to the next segment.
238 if (LVI->end == Stop && ++LVI == LVE)
241 // Pick the next basic block.
242 if (LVI->start < Stop)
245 MFI = LIS.getMBBFromIndex(LVI->start);
248 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
252 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
255 LiveInterval *li = const_cast<LiveInterval*>(cli);
256 LiveInterval::iterator LVI = li->begin();
257 LiveInterval::iterator LVE = li->end();
260 // Loop over basic blocks where li is live.
261 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
262 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
265 LVI = li->advanceTo(LVI, Stop);
270 Stop = LIS.getMBBEndIdx(MFI);
271 } while (Stop <= LVI->start);
275 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
276 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
277 const LiveInterval &Orig = LIS.getInterval(OrigReg);
278 assert(!Orig.empty() && "Splitting empty interval?");
279 LiveInterval::const_iterator I = Orig.find(Idx);
281 // Range containing Idx should begin at Idx.
282 if (I != Orig.end() && I->start <= Idx)
283 return I->start == Idx;
285 // Range does not contain Idx, previous must end at Idx.
286 return I != Orig.begin() && (--I)->end == Idx;
289 void SplitAnalysis::analyze(const LiveInterval *li) {
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
300 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
301 SplitEditor::SplitEditor(SplitAnalysis &sa,
304 MachineDominatorTree &mdt)
305 : SA(sa), LIS(lis), VRM(vrm),
306 MRI(vrm.getMachineFunction().getRegInfo()),
308 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
309 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
312 SpillMode(SM_Partition),
316 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
323 // Reset the LiveRangeCalc instances needed for this spill mode.
324 LRCalc[0].reset(&VRM.getMachineFunction());
326 LRCalc[1].reset(&VRM.getMachineFunction());
328 // We don't need an AliasAnalysis since we will only be performing
329 // cheap-as-a-copy remats anyway.
330 Edit->anyRematerializable(LIS, TII, 0);
333 void SplitEditor::dump() const {
334 if (RegAssign.empty()) {
335 dbgs() << " empty\n";
339 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
340 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
344 VNInfo *SplitEditor::defValue(unsigned RegIdx,
345 const VNInfo *ParentVNI,
347 assert(ParentVNI && "Mapping NULL value");
348 assert(Idx.isValid() && "Invalid SlotIndex");
349 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
350 LiveInterval *LI = Edit->get(RegIdx);
352 // Create a new value.
353 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
355 // Use insert for lookup, so we can add missing values with a second lookup.
356 std::pair<ValueMap::iterator, bool> InsP =
357 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
359 // This was the first time (RegIdx, ParentVNI) was mapped.
360 // Keep it as a simple def without any liveness.
364 // If the previous value was a simple mapping, add liveness for it now.
365 if (VNInfo *OldVNI = InsP.first->second) {
366 SlotIndex Def = OldVNI->def;
367 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
368 // No longer a simple mapping.
369 InsP.first->second = 0;
372 // This is a complex mapping, add liveness for VNI
373 SlotIndex Def = VNI->def;
374 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
379 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
380 assert(ParentVNI && "Mapping NULL value");
381 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
383 // ParentVNI was either unmapped or already complex mapped. Either way.
387 // This was previously a single mapping. Make sure the old def is represented
388 // by a trivial live range.
389 SlotIndex Def = VNI->def;
390 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
394 // extendRange - Extend the live range to reach Idx.
395 // Potentially create phi-def values.
396 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
397 getLRCalc(RegIdx).extend(Edit->get(RegIdx), Idx.getNextSlot(),
398 LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
401 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
404 MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator I) {
406 MachineInstr *CopyMI = 0;
408 LiveInterval *LI = Edit->get(RegIdx);
410 // We may be trying to avoid interference that ends at a deleted instruction,
411 // so always begin RegIdx 0 early and all others late.
412 bool Late = RegIdx != 0;
414 // Attempt cheap-as-a-copy rematerialization.
415 LiveRangeEdit::Remat RM(ParentVNI);
416 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
417 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
420 // Can't remat, just insert a copy from parent.
421 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
422 .addReg(Edit->getReg());
423 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
428 // Define the value in Reg.
429 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
430 VNI->setCopy(CopyMI);
434 /// Create a new virtual register and live interval.
435 unsigned SplitEditor::openIntv() {
436 // Create the complement as index 0.
438 Edit->create(LIS, VRM);
440 // Create the open interval.
441 OpenIdx = Edit->size();
442 Edit->create(LIS, VRM);
446 void SplitEditor::selectIntv(unsigned Idx) {
447 assert(Idx != 0 && "Cannot select the complement interval");
448 assert(Idx < Edit->size() && "Can only select previously opened interval");
449 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
453 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
454 assert(OpenIdx && "openIntv not called before enterIntvBefore");
455 DEBUG(dbgs() << " enterIntvBefore " << Idx);
456 Idx = Idx.getBaseIndex();
457 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
459 DEBUG(dbgs() << ": not live\n");
462 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
463 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
464 assert(MI && "enterIntvBefore called with invalid index");
466 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
470 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
471 assert(OpenIdx && "openIntv not called before enterIntvAfter");
472 DEBUG(dbgs() << " enterIntvAfter " << Idx);
473 Idx = Idx.getBoundaryIndex();
474 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
476 DEBUG(dbgs() << ": not live\n");
479 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
480 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
481 assert(MI && "enterIntvAfter called with invalid index");
483 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
484 llvm::next(MachineBasicBlock::iterator(MI)));
488 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
489 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
490 SlotIndex End = LIS.getMBBEndIdx(&MBB);
491 SlotIndex Last = End.getPrevSlot();
492 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
493 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
495 DEBUG(dbgs() << ": not live\n");
498 DEBUG(dbgs() << ": valno " << ParentVNI->id);
499 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
500 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
501 RegAssign.insert(VNI->def, End, OpenIdx);
506 /// useIntv - indicate that all instructions in MBB should use OpenLI.
507 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
508 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
511 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
512 assert(OpenIdx && "openIntv not called before useIntv");
513 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
514 RegAssign.insert(Start, End, OpenIdx);
518 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
519 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
520 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
522 // The interval must be live beyond the instruction at Idx.
523 Idx = Idx.getBoundaryIndex();
524 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
526 DEBUG(dbgs() << ": not live\n");
527 return Idx.getNextSlot();
529 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
531 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
532 assert(MI && "No instruction at index");
533 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
534 llvm::next(MachineBasicBlock::iterator(MI)));
538 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
539 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
540 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
542 // The interval must be live into the instruction at Idx.
543 Idx = Idx.getBaseIndex();
544 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
546 DEBUG(dbgs() << ": not live\n");
547 return Idx.getNextSlot();
549 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
551 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
552 assert(MI && "No instruction at index");
553 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
557 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
558 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
559 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
560 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
562 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
564 DEBUG(dbgs() << ": not live\n");
568 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
569 MBB.SkipPHIsAndLabels(MBB.begin()));
570 RegAssign.insert(Start, VNI->def, OpenIdx);
575 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
576 assert(OpenIdx && "openIntv not called before overlapIntv");
577 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
578 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
579 "Parent changes value in extended range");
580 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
581 "Range cannot span basic blocks");
583 // The complement interval will be extended as needed by extendRange().
585 markComplexMapped(0, ParentVNI);
586 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
587 RegAssign.insert(Start, End, OpenIdx);
591 /// transferValues - Transfer all possible values to the new live ranges.
592 /// Values that were rematerialized are left alone, they need extendRange().
593 bool SplitEditor::transferValues() {
594 bool Skipped = false;
595 RegAssignMap::const_iterator AssignI = RegAssign.begin();
596 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
597 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
598 DEBUG(dbgs() << " blit " << *ParentI << ':');
599 VNInfo *ParentVNI = ParentI->valno;
600 // RegAssign has holes where RegIdx 0 should be used.
601 SlotIndex Start = ParentI->start;
602 AssignI.advanceTo(Start);
605 SlotIndex End = ParentI->end;
606 if (!AssignI.valid()) {
608 } else if (AssignI.start() <= Start) {
609 RegIdx = AssignI.value();
610 if (AssignI.stop() < End) {
611 End = AssignI.stop();
616 End = std::min(End, AssignI.start());
619 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
620 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
621 LiveInterval *LI = Edit->get(RegIdx);
623 // Check for a simply defined value that can be blitted directly.
624 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
625 DEBUG(dbgs() << ':' << VNI->id);
626 LI->addRange(LiveRange(Start, End, VNI));
631 // Skip rematerialized values, we need to use extendRange() and
632 // extendPHIKillRanges() to completely recompute the live ranges.
633 if (Edit->didRematerialize(ParentVNI)) {
634 DEBUG(dbgs() << "(remat)");
640 LiveRangeCalc &LRC = getLRCalc(RegIdx);
642 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
643 // so the live range is accurate. Add live-in blocks in [Start;End) to the
645 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
646 SlotIndex BlockStart, BlockEnd;
647 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
649 // The first block may be live-in, or it may have its own def.
650 if (Start != BlockStart) {
651 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
652 assert(VNI && "Missing def for complex mapped value");
653 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
654 // MBB has its own def. Is it also live-out?
656 LRC.setLiveOutValue(MBB, VNI);
658 // Skip to the next block for live-in.
660 BlockStart = BlockEnd;
663 // Handle the live-in blocks covered by [Start;End).
664 assert(Start <= BlockStart && "Expected live-in block");
665 while (BlockStart < End) {
666 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
667 BlockEnd = LIS.getMBBEndIdx(MBB);
668 if (BlockStart == ParentVNI->def) {
669 // This block has the def of a parent PHI, so it isn't live-in.
670 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
671 VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
672 assert(VNI && "Missing def for complex mapped parent PHI");
674 LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
676 // This block needs a live-in value. The last block covered may not
679 LRC.addLiveInBlock(LI, MDT[MBB], End);
681 // Live-through, and we don't know the value.
682 LRC.addLiveInBlock(LI, MDT[MBB]);
683 LRC.setLiveOutValue(MBB, 0);
686 BlockStart = BlockEnd;
690 } while (Start != ParentI->end);
691 DEBUG(dbgs() << '\n');
694 LRCalc[0].calculateValues(LIS.getSlotIndexes(), &MDT,
695 &LIS.getVNInfoAllocator());
697 LRCalc[1].calculateValues(LIS.getSlotIndexes(), &MDT,
698 &LIS.getVNInfoAllocator());
703 void SplitEditor::extendPHIKillRanges() {
704 // Extend live ranges to be live-out for successor PHI values.
705 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
706 E = Edit->getParent().vni_end(); I != E; ++I) {
707 const VNInfo *PHIVNI = *I;
708 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
710 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
711 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
712 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
713 PE = MBB->pred_end(); PI != PE; ++PI) {
714 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
715 // The predecessor may not have a live-out value. That is OK, like an
716 // undef PHI operand.
717 if (Edit->getParent().liveAt(End)) {
718 assert(RegAssign.lookup(End) == RegIdx &&
719 "Different register assignment in phi predecessor");
720 extendRange(RegIdx, End);
726 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
727 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
728 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
729 RE = MRI.reg_end(); RI != RE;) {
730 MachineOperand &MO = RI.getOperand();
731 MachineInstr *MI = MO.getParent();
733 // LiveDebugVariables should have handled all DBG_VALUE instructions.
734 if (MI->isDebugValue()) {
735 DEBUG(dbgs() << "Zapping " << *MI);
740 // <undef> operands don't really read the register, so it doesn't matter
741 // which register we choose. When the use operand is tied to a def, we must
742 // use the same register as the def, so just do that always.
743 SlotIndex Idx = LIS.getInstructionIndex(MI);
744 if (MO.isDef() || MO.isUndef())
745 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
747 // Rewrite to the mapped register at Idx.
748 unsigned RegIdx = RegAssign.lookup(Idx);
749 MO.setReg(Edit->get(RegIdx)->reg);
750 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
751 << Idx << ':' << RegIdx << '\t' << *MI);
753 // Extend liveness to Idx if the instruction reads reg.
754 if (!ExtendRanges || MO.isUndef())
757 // Skip instructions that don't read Reg.
759 if (!MO.getSubReg() && !MO.isEarlyClobber())
761 // We may wan't to extend a live range for a partial redef, or for a use
762 // tied to an early clobber.
763 Idx = Idx.getPrevSlot();
764 if (!Edit->getParent().liveAt(Idx))
767 Idx = Idx.getUseIndex();
769 extendRange(RegIdx, Idx);
773 void SplitEditor::deleteRematVictims() {
774 SmallVector<MachineInstr*, 8> Dead;
775 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
776 LiveInterval *LI = *I;
777 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
779 // Dead defs end at the store slot.
780 if (LII->end != LII->valno->def.getNextSlot())
782 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
783 assert(MI && "Missing instruction for dead def");
784 MI->addRegisterDead(LI->reg, &TRI);
786 if (!MI->allDefsAreDead())
789 DEBUG(dbgs() << "All defs dead: " << *MI);
797 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
800 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
803 // At this point, the live intervals in Edit contain VNInfos corresponding to
804 // the inserted copies.
806 // Add the original defs from the parent interval.
807 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
808 E = Edit->getParent().vni_end(); I != E; ++I) {
809 const VNInfo *ParentVNI = *I;
810 if (ParentVNI->isUnused())
812 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
813 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
814 VNI->setIsPHIDef(ParentVNI->isPHIDef());
815 VNI->setCopy(ParentVNI->getCopy());
817 // Mark rematted values as complex everywhere to force liveness computation.
818 // The new live ranges may be truncated.
819 if (Edit->didRematerialize(ParentVNI))
820 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
821 markComplexMapped(i, ParentVNI);
824 // Transfer the simply mapped values, check if any are skipped.
825 bool Skipped = transferValues();
827 extendPHIKillRanges();
831 // Rewrite virtual registers, possibly extending ranges.
832 rewriteAssigned(Skipped);
834 // Delete defs that were rematted everywhere.
836 deleteRematVictims();
838 // Get rid of unused values and set phi-kill flags.
839 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
840 (*I)->RenumberValues(LIS);
842 // Provide a reverse mapping from original indices to Edit ranges.
845 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
849 // Now check if any registers were separated into multiple components.
850 ConnectedVNInfoEqClasses ConEQ(LIS);
851 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
852 // Don't use iterators, they are invalidated by create() below.
853 LiveInterval *li = Edit->get(i);
854 unsigned NumComp = ConEQ.Classify(li);
857 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
858 SmallVector<LiveInterval*, 8> dups;
860 for (unsigned j = 1; j != NumComp; ++j)
861 dups.push_back(&Edit->create(LIS, VRM));
862 ConEQ.Distribute(&dups[0], MRI);
863 // The new intervals all map back to i.
865 LRMap->resize(Edit->size(), i);
868 // Calculate spill weight and allocation hints for new intervals.
869 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
871 assert(!LRMap || LRMap->size() == Edit->size());
875 //===----------------------------------------------------------------------===//
876 // Single Block Splitting
877 //===----------------------------------------------------------------------===//
879 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
880 bool SingleInstrs) const {
881 // Always split for multiple instructions.
882 if (!BI.isOneInstr())
884 // Don't split for single instructions unless explicitly requested.
887 // Splitting a live-through range always makes progress.
888 if (BI.LiveIn && BI.LiveOut)
890 // No point in isolating a copy. It has no register class constraints.
891 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
893 // Finally, don't isolate an end point that was created by earlier splits.
894 return isOriginalEndpoint(BI.FirstInstr);
897 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
899 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
900 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
902 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
903 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
905 // The last use is after the last valid split point.
906 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
907 useIntv(SegStart, SegStop);
908 overlapIntv(SegStop, BI.LastInstr);
913 //===----------------------------------------------------------------------===//
914 // Global Live Range Splitting Support
915 //===----------------------------------------------------------------------===//
917 // These methods support a method of global live range splitting that uses a
918 // global algorithm to decide intervals for CFG edges. They will insert split
919 // points and color intervals in basic blocks while avoiding interference.
921 // Note that splitSingleBlock is also useful for blocks where both CFG edges
924 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
925 unsigned IntvIn, SlotIndex LeaveBefore,
926 unsigned IntvOut, SlotIndex EnterAfter){
927 SlotIndex Start, Stop;
928 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
930 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
931 << ") intf " << LeaveBefore << '-' << EnterAfter
932 << ", live-through " << IntvIn << " -> " << IntvOut);
934 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
936 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
937 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
938 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
940 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
943 DEBUG(dbgs() << ", spill on entry.\n");
945 // <<<<<<<<< Possible LeaveBefore interference.
946 // |-----------| Live through.
947 // -____________ Spill on entry.
950 SlotIndex Idx = leaveIntvAtTop(*MBB);
951 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
957 DEBUG(dbgs() << ", reload on exit.\n");
959 // >>>>>>> Possible EnterAfter interference.
960 // |-----------| Live through.
961 // ___________-- Reload on exit.
964 SlotIndex Idx = enterIntvAtEnd(*MBB);
965 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
970 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
971 DEBUG(dbgs() << ", straight through.\n");
973 // |-----------| Live through.
974 // ------------- Straight through, same intv, no interference.
977 useIntv(Start, Stop);
981 // We cannot legally insert splits after LSP.
982 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
983 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
985 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
986 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
987 DEBUG(dbgs() << ", switch avoiding interference.\n");
989 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
990 // |-----------| Live through.
991 // ------======= Switch intervals between interference.
995 if (LeaveBefore && LeaveBefore < LSP) {
996 Idx = enterIntvBefore(LeaveBefore);
999 Idx = enterIntvAtEnd(*MBB);
1002 useIntv(Start, Idx);
1003 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1004 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1008 DEBUG(dbgs() << ", create local intv for interference.\n");
1010 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1011 // |-----------| Live through.
1012 // ==---------== Switch intervals before/after interference.
1014 assert(LeaveBefore <= EnterAfter && "Missed case");
1016 selectIntv(IntvOut);
1017 SlotIndex Idx = enterIntvAfter(EnterAfter);
1019 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1022 Idx = leaveIntvBefore(LeaveBefore);
1023 useIntv(Start, Idx);
1024 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1028 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1029 unsigned IntvIn, SlotIndex LeaveBefore) {
1030 SlotIndex Start, Stop;
1031 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1033 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1034 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1035 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1036 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1038 assert(IntvIn && "Must have register in");
1039 assert(BI.LiveIn && "Must be live-in");
1040 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1042 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1043 DEBUG(dbgs() << " before interference.\n");
1045 // <<< Interference after kill.
1046 // |---o---x | Killed in block.
1047 // ========= Use IntvIn everywhere.
1050 useIntv(Start, BI.LastInstr);
1054 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1056 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1058 // <<< Possible interference after last use.
1059 // |---o---o---| Live-out on stack.
1060 // =========____ Leave IntvIn after last use.
1062 // < Interference after last use.
1063 // |---o---o--o| Live-out on stack, late last use.
1064 // ============ Copy to stack after LSP, overlap IntvIn.
1065 // \_____ Stack interval is live-out.
1067 if (BI.LastInstr < LSP) {
1068 DEBUG(dbgs() << ", spill after last use before interference.\n");
1070 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1071 useIntv(Start, Idx);
1072 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1074 DEBUG(dbgs() << ", spill before last split point.\n");
1076 SlotIndex Idx = leaveIntvBefore(LSP);
1077 overlapIntv(Idx, BI.LastInstr);
1078 useIntv(Start, Idx);
1079 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1084 // The interference is overlapping somewhere we wanted to use IntvIn. That
1085 // means we need to create a local interval that can be allocated a
1086 // different register.
1087 unsigned LocalIntv = openIntv();
1089 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1091 if (!BI.LiveOut || BI.LastInstr < LSP) {
1093 // <<<<<<< Interference overlapping uses.
1094 // |---o---o---| Live-out on stack.
1095 // =====----____ Leave IntvIn before interference, then spill.
1097 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1098 SlotIndex From = enterIntvBefore(LeaveBefore);
1101 useIntv(Start, From);
1102 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1106 // <<<<<<< Interference overlapping uses.
1107 // |---o---o--o| Live-out on stack, late last use.
1108 // =====------- Copy to stack before LSP, overlap LocalIntv.
1109 // \_____ Stack interval is live-out.
1111 SlotIndex To = leaveIntvBefore(LSP);
1112 overlapIntv(To, BI.LastInstr);
1113 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1116 useIntv(Start, From);
1117 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1120 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1121 unsigned IntvOut, SlotIndex EnterAfter) {
1122 SlotIndex Start, Stop;
1123 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1125 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1126 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1127 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1128 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1130 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1132 assert(IntvOut && "Must have register out");
1133 assert(BI.LiveOut && "Must be live-out");
1134 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1136 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1137 DEBUG(dbgs() << " after interference.\n");
1139 // >>>> Interference before def.
1140 // | o---o---| Defined in block.
1141 // ========= Use IntvOut everywhere.
1143 selectIntv(IntvOut);
1144 useIntv(BI.FirstInstr, Stop);
1148 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1149 DEBUG(dbgs() << ", reload after interference.\n");
1151 // >>>> Interference before def.
1152 // |---o---o---| Live-through, stack-in.
1153 // ____========= Enter IntvOut before first use.
1155 selectIntv(IntvOut);
1156 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1158 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1162 // The interference is overlapping somewhere we wanted to use IntvOut. That
1163 // means we need to create a local interval that can be allocated a
1164 // different register.
1165 DEBUG(dbgs() << ", interference overlaps uses.\n");
1167 // >>>>>>> Interference overlapping uses.
1168 // |---o---o---| Live-through, stack-in.
1169 // ____---====== Create local interval for interference range.
1171 selectIntv(IntvOut);
1172 SlotIndex Idx = enterIntvAfter(EnterAfter);
1174 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1177 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));