1 //===---------------------------- StackMaps.cpp ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "stackmaps"
12 #include "llvm/CodeGen/StackMaps.h"
14 #include "llvm/CodeGen/AsmPrinter.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/IR/DataLayout.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCObjectFileInfo.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetOpcodes.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
32 PatchPointOpers::PatchPointOpers(const MachineInstr *MI)
34 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
35 !MI->getOperand(0).isImplicit()),
36 IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg)
39 unsigned CheckStartIdx = 0, e = MI->getNumOperands();
40 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
41 MI->getOperand(CheckStartIdx).isDef() &&
42 !MI->getOperand(CheckStartIdx).isImplicit())
45 assert(getMetaIdx() == CheckStartIdx &&
46 "Unexpected additonal definition in Patchpoint intrinsic.");
50 unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
52 StartIdx = getVarIdx();
54 // Find the next scratch register (implicit def and early clobber)
55 unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
56 while (ScratchIdx < e &&
57 !(MI->getOperand(ScratchIdx).isReg() &&
58 MI->getOperand(ScratchIdx).isDef() &&
59 MI->getOperand(ScratchIdx).isImplicit() &&
60 MI->getOperand(ScratchIdx).isEarlyClobber()))
63 assert(ScratchIdx != e && "No scratch register available");
67 MachineInstr::const_mop_iterator
68 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
69 MachineInstr::const_mop_iterator MOE,
70 LocationVec &Locs, LiveOutVec &LiveOuts) const {
72 switch (MOI->getImm()) {
73 default: llvm_unreachable("Unrecognized operand type.");
74 case StackMaps::DirectMemRefOp: {
75 unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits();
76 assert((Size % 8) == 0 && "Need pointer size in bytes.");
78 unsigned Reg = (++MOI)->getReg();
79 int64_t Imm = (++MOI)->getImm();
80 Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm));
83 case StackMaps::IndirectMemRefOp: {
84 int64_t Size = (++MOI)->getImm();
85 assert(Size > 0 && "Need a valid size for indirect memory locations.");
86 unsigned Reg = (++MOI)->getReg();
87 int64_t Imm = (++MOI)->getImm();
88 Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm));
91 case StackMaps::ConstantOp: {
93 assert(MOI->isImm() && "Expected constant operand.");
94 int64_t Imm = MOI->getImm();
95 Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm));
102 // The physical register number will ultimately be encoded as a DWARF regno.
103 // The stack map also records the size of a spill slot that can hold the
104 // register content. (The runtime can track the actual size of the data type
107 // Skip implicit registers (this includes our scratch registers)
108 if (MOI->isImplicit())
111 assert(TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) &&
112 "Virtreg operands should have been rewritten before now.");
113 const TargetRegisterClass *RC =
114 AP.TM.getRegisterInfo()->getMinimalPhysRegClass(MOI->getReg());
115 assert(!MOI->getSubReg() && "Physical subreg still around.");
117 Location(Location::Register, RC->getSize(), MOI->getReg(), 0));
121 if (MOI->isRegLiveOut())
122 LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
127 /// Go up the super-register chain until we hit a valid dwarf register number.
128 static unsigned short getDwarfRegNum(unsigned Reg, const MCRegisterInfo &MCRI,
129 const TargetRegisterInfo *TRI) {
130 int RegNo = MCRI.getDwarfRegNum(Reg, false);
131 for (MCSuperRegIterator SR(Reg, TRI);
132 SR.isValid() && RegNo < 0; ++SR)
133 RegNo = TRI->getDwarfRegNum(*SR, false);
135 assert(RegNo >= 0 && "Invalid Dwarf register number.");
136 return (unsigned short) RegNo;
139 /// Create a live-out register record for the given register Reg.
140 StackMaps::LiveOutReg
141 StackMaps::createLiveOutReg(unsigned Reg, const MCRegisterInfo &MCRI,
142 const TargetRegisterInfo *TRI) const {
143 unsigned RegNo = getDwarfRegNum(Reg, MCRI, TRI);
144 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
145 return LiveOutReg(Reg, RegNo, Size);
148 /// Parse the register live-out mask and return a vector of live-out registers
149 /// that need to be recorded in the stackmap.
150 StackMaps::LiveOutVec
151 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
152 assert(Mask && "No register mask specified");
153 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
154 MCContext &OutContext = AP.OutStreamer.getContext();
155 const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo();
158 // Create a LiveOutReg for each bit that is set in the register mask.
159 for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
160 if ((Mask[Reg / 32] >> Reg % 32) & 1)
161 LiveOuts.push_back(createLiveOutReg(Reg, MCRI, TRI));
163 // We don't need to keep track of a register if its super-register is already
164 // in the list. Merge entries that refer to the same dwarf register and use
165 // the maximum size that needs to be spilled.
166 std::sort(LiveOuts.begin(), LiveOuts.end());
167 for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end();
169 for (LiveOutVec::iterator II = next(I); II != E; ++II) {
170 if (I->RegNo != II->RegNo) {
171 // Skip all the now invalid entries.
175 I->Size = std::max(I->Size, II->Size);
176 if (TRI->isSuperRegister(I->Reg, II->Reg))
181 LiveOuts.erase(std::remove_if(LiveOuts.begin(), LiveOuts.end(),
182 LiveOutReg::IsInvalid), LiveOuts.end());
186 void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
187 MachineInstr::const_mop_iterator MOI,
188 MachineInstr::const_mop_iterator MOE,
191 MCContext &OutContext = AP.OutStreamer.getContext();
192 MCSymbol *MILabel = OutContext.CreateTempSymbol();
193 AP.OutStreamer.EmitLabel(MILabel);
195 LocationVec Locations;
199 assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
200 parseOperand(MI.operands_begin(), llvm::next(MI.operands_begin()),
201 Locations, LiveOuts);
206 MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
209 // Move large constants into the constant pool.
210 for (LocationVec::iterator I = Locations.begin(), E = Locations.end();
212 if (I->LocType == Location::Constant && (I->Offset & ~0xFFFFFFFFULL)) {
213 I->LocType = Location::ConstantIndex;
214 I->Offset = ConstPool.getConstantIndex(I->Offset);
218 const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
219 MCSymbolRefExpr::Create(MILabel, OutContext),
220 MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext),
223 CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, Locations, LiveOuts));
226 void StackMaps::recordStackMap(const MachineInstr &MI) {
227 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
229 int64_t ID = MI.getOperand(0).getImm();
230 recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2),
234 void StackMaps::recordPatchPoint(const MachineInstr &MI) {
235 assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
237 PatchPointOpers opers(&MI);
238 int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
240 MachineInstr::const_mop_iterator MOI =
241 llvm::next(MI.operands_begin(), opers.getStackMapStartIdx());
242 recordStackMapOpers(MI, ID, MOI, MI.operands_end(),
243 opers.isAnyReg() && opers.hasDef());
247 LocationVec &Locations = CSInfos.back().Locations;
248 if (opers.isAnyReg()) {
249 unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm();
250 for (unsigned i = 0, e = (opers.hasDef() ? NArgs+1 : NArgs); i != e; ++i)
251 assert(Locations[i].LocType == Location::Register &&
252 "anyreg arg must be in reg.");
257 /// serializeToStackMapSection conceptually populates the following fields:
259 /// uint32 : Reserved (header)
260 /// uint32 : NumConstants
261 /// int64 : Constants[NumConstants]
262 /// uint32 : NumRecords
263 /// StkMapRecord[NumRecords] {
264 /// uint64 : PatchPoint ID
265 /// uint32 : Instruction Offset
266 /// uint16 : Reserved (record flags)
267 /// uint16 : NumLocations
268 /// Location[NumLocations] {
269 /// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
270 /// uint8 : Size in Bytes
271 /// uint16 : Dwarf RegNum
274 /// uint16 : NumLiveOuts
275 /// LiveOuts[NumLiveOuts]
276 /// uint16 : Dwarf RegNum
278 /// uint8 : Size in Bytes
281 /// Location Encoding, Type, Value:
282 /// 0x1, Register, Reg (value in register)
283 /// 0x2, Direct, Reg + Offset (frame index)
284 /// 0x3, Indirect, [Reg + Offset] (spilled value)
285 /// 0x4, Constant, Offset (small constant)
286 /// 0x5, ConstIndex, Constants[Offset] (large constant)
288 void StackMaps::serializeToStackMapSection() {
289 // Bail out if there's no stack map data.
293 MCContext &OutContext = AP.OutStreamer.getContext();
294 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
296 // Create the section.
297 const MCSection *StackMapSection =
298 OutContext.getObjectFileInfo()->getStackMapSection();
299 AP.OutStreamer.SwitchSection(StackMapSection);
301 // Emit a dummy symbol to force section inclusion.
302 AP.OutStreamer.EmitLabel(
303 OutContext.GetOrCreateSymbol(Twine("__LLVM_StackMaps")));
306 const char *WSMP = "Stack Maps: ";
308 const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo();
310 DEBUG(dbgs() << "********** Stack Map Output **********\n");
313 AP.OutStreamer.EmitIntValue(0, 4);
316 AP.OutStreamer.EmitIntValue(ConstPool.getNumConstants(), 4);
318 // Constant pool entries.
319 for (unsigned i = 0; i < ConstPool.getNumConstants(); ++i)
320 AP.OutStreamer.EmitIntValue(ConstPool.getConstant(i), 8);
322 DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << "\n");
323 AP.OutStreamer.EmitIntValue(CSInfos.size(), 4);
325 for (CallsiteInfoList::const_iterator CSII = CSInfos.begin(),
326 CSIE = CSInfos.end();
327 CSII != CSIE; ++CSII) {
329 uint64_t CallsiteID = CSII->ID;
330 const LocationVec &CSLocs = CSII->Locations;
331 const LiveOutVec &LiveOuts = CSII->LiveOuts;
333 DEBUG(dbgs() << WSMP << "callsite " << CallsiteID << "\n");
335 // Verify stack map entry. It's better to communicate a problem to the
336 // runtime than crash in case of in-process compilation. Currently, we do
337 // simple overflow checks, but we may eventually communicate other
338 // compilation errors this way.
339 if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
340 AP.OutStreamer.EmitIntValue(UINT64_MAX, 8); // Invalid ID.
341 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
342 AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
343 AP.OutStreamer.EmitIntValue(0, 2); // 0 locations.
344 AP.OutStreamer.EmitIntValue(0, 2); // 0 live-out registers.
348 AP.OutStreamer.EmitIntValue(CallsiteID, 8);
349 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
351 // Reserved for flags.
352 AP.OutStreamer.EmitIntValue(0, 2);
354 DEBUG(dbgs() << WSMP << " has " << CSLocs.size() << " locations\n");
356 AP.OutStreamer.EmitIntValue(CSLocs.size(), 2);
358 unsigned operIdx = 0;
359 for (LocationVec::const_iterator LocI = CSLocs.begin(), LocE = CSLocs.end();
360 LocI != LocE; ++LocI, ++operIdx) {
361 const Location &Loc = *LocI;
363 int Offset = Loc.Offset;
365 RegNo = MCRI.getDwarfRegNum(Loc.Reg, false);
366 for (MCSuperRegIterator SR(Loc.Reg, TRI);
367 SR.isValid() && (int)RegNo < 0; ++SR) {
368 RegNo = TRI->getDwarfRegNum(*SR, false);
370 // If this is a register location, put the subregister byte offset in
371 // the location offset.
372 if (Loc.LocType == Location::Register) {
373 assert(!Loc.Offset && "Register location should have zero offset");
374 unsigned LLVMRegNo = MCRI.getLLVMRegNum(RegNo, false);
375 unsigned SubRegIdx = MCRI.getSubRegIndex(LLVMRegNo, Loc.Reg);
377 Offset = MCRI.getSubRegIdxOffset(SubRegIdx);
381 assert(Loc.LocType != Location::Register &&
382 "Missing location register");
386 dbgs() << WSMP << " Loc " << operIdx << ": ";
387 switch (Loc.LocType) {
388 case Location::Unprocessed:
389 dbgs() << "<Unprocessed operand>";
391 case Location::Register:
392 dbgs() << "Register " << MCRI.getName(Loc.Reg);
394 case Location::Direct:
395 dbgs() << "Direct " << MCRI.getName(Loc.Reg);
397 dbgs() << " + " << Loc.Offset;
399 case Location::Indirect:
400 dbgs() << "Indirect " << MCRI.getName(Loc.Reg)
401 << " + " << Loc.Offset;
403 case Location::Constant:
404 dbgs() << "Constant " << Loc.Offset;
406 case Location::ConstantIndex:
407 dbgs() << "Constant Index " << Loc.Offset;
410 dbgs() << " [encoding: .byte " << Loc.LocType
411 << ", .byte " << Loc.Size
412 << ", .short " << RegNo
413 << ", .int " << Offset << "]\n";
416 AP.OutStreamer.EmitIntValue(Loc.LocType, 1);
417 AP.OutStreamer.EmitIntValue(Loc.Size, 1);
418 AP.OutStreamer.EmitIntValue(RegNo, 2);
419 AP.OutStreamer.EmitIntValue(Offset, 4);
422 DEBUG(dbgs() << WSMP << " has " << LiveOuts.size()
423 << " live-out registers\n");
425 AP.OutStreamer.EmitIntValue(LiveOuts.size(), 2);
428 for (LiveOutVec::const_iterator LI = LiveOuts.begin(), LE = LiveOuts.end();
429 LI != LE; ++LI, ++operIdx) {
430 DEBUG(dbgs() << WSMP << " LO " << operIdx << ": "
431 << MCRI.getName(LI->Reg)
432 << " [encoding: .short " << LI->RegNo
433 << ", .byte 0, .byte " << LI->Size << "]\n");
435 AP.OutStreamer.EmitIntValue(LI->RegNo, 2);
436 AP.OutStreamer.EmitIntValue(0, 1);
437 AP.OutStreamer.EmitIntValue(LI->Size, 1);
441 AP.OutStreamer.AddBlankLine();